From 04d83f948510f17f8f2ab320b2386f4b5fbd0bd4 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Wed, 3 Feb 2016 03:15:22 +0000 Subject: MIPS: traps: Make sure secondary cores have a sane ebase register We shouldn't trust that the secondary cores will have a sane ebase register (either from the bootloader or during the hardware design phase) so use the ebase address as calculated by the boot CPU. Signed-off-by: Markos Chandras Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin Cc: Maciej W. Rozycki Cc: James Hogan Cc: Petri Gynther Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12328/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/traps.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/mips/kernel/traps.c') diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 82c2fcf7e585..bd4893feffa6 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2116,6 +2116,13 @@ void per_cpu_trap_init(bool is_boot_cpu) * o read IntCtl.IPFDC to determine the fast debug channel interrupt */ if (cpu_has_mips_r2_r6) { + /* + * We shouldn't trust a secondary core has a sane EBASE register + * so use the one calculated by the boot CPU. + */ + if (!is_boot_cpu) + write_c0_ebase(ebase); + cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; -- cgit