From 442e14a2c55e55f208bf87e3686396b4ff17ebf6 Mon Sep 17 00:00:00 2001 From: "Steven J. Hill" Date: Fri, 17 Jan 2014 15:03:50 -0600 Subject: MIPS: Add 1074K CPU support explicitly. The 1074K is a multiprocessing coherent processing system (CPS) based on modified 74K cores. This patch makes the 1074K an actual unique CPU type, instead of a 74K derivative, which it is not. Signed-off-by: Steven J. Hill Reviewed-by: Leonid Yegoshin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6389/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 2 +- arch/mips/kernel/idle.c | 1 + arch/mips/kernel/perf_event_mipsxx.c | 6 ++++++ arch/mips/kernel/spram.c | 1 + arch/mips/kernel/traps.c | 1 + 5 files changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 530f832de02c..ac09248b7468 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -806,7 +806,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "MIPS 1004Kc"; break; case PRID_IMP_1074K: - c->cputype = CPU_74K; + c->cputype = CPU_1074K; __cpu_name[cpu] = "MIPS 1074Kc"; break; case PRID_IMP_INTERAPTIV_UP: diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 3553243bf9d6..c1fd0bc7a315 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -184,6 +184,7 @@ void __init check_wait(void) case CPU_24K: case CPU_34K: case CPU_1004K: + case CPU_1074K: case CPU_INTERAPTIV: case CPU_PROAPTIV: cpu_wait = r4k_wait; diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 24cdf64789c3..17594b81a5d2 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -1442,6 +1442,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) #endif break; case CPU_74K: + case CPU_1074K: if (IS_BOTH_COUNTERS_74K_EVENT(base_id)) raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; else @@ -1584,6 +1585,11 @@ init_hw_perf_events(void) mipspmu.general_event_map = &mipsxxcore_event_map; mipspmu.cache_event_map = &mipsxxcore_cache_map; break; + case CPU_1074K: + mipspmu.name = "mips/1074K"; + mipspmu.general_event_map = &mipsxxcore_event_map; + mipspmu.cache_event_map = &mipsxxcore_cache_map; + break; case CPU_LOONGSON1: mipspmu.name = "mips/loongson1"; mipspmu.general_event_map = &mipsxxcore_event_map; diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index b242e2c10ea0..707d957e6a66 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c @@ -205,6 +205,7 @@ void spram_config(void) case CPU_34K: case CPU_74K: case CPU_1004K: + case CPU_1074K: case CPU_INTERAPTIV: case CPU_PROAPTIV: config0 = read_c0_config(); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e0b499694d18..b0c7f80e05e5 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1337,6 +1337,7 @@ static inline void parity_protection_init(void) case CPU_34K: case CPU_74K: case CPU_1004K: + case CPU_1074K: case CPU_INTERAPTIV: case CPU_PROAPTIV: { -- cgit From 72e20142b2bf4cf1c3071e6cf49d01f55f2e1e53 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Wed, 15 Jan 2014 10:31:50 +0000 Subject: MIPS: Move GIC IPI functions out of smp-cmp.c The GIC IPI functions aren't necessarily specific to the "CMP framework" SMP implementation, and will be used elsewhere in a subsequent commit. This patch adds cleaned up GIC IPI functions to a separate file which is compiled when a new CONFIG_MIPS_GIC_IPI Kconfig symbol is selected, and selects that symbol for CONFIG_MIPS_CMP. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6359/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/Makefile | 1 + arch/mips/kernel/smp-cmp.c | 52 ++------------------------------------------- arch/mips/kernel/smp-gic.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 50 deletions(-) create mode 100644 arch/mips/kernel/smp-gic.c (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 26c6175e1379..786a51ddbb78 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o obj-$(CONFIG_MIPS_MT_SMTC) += smtc.o smtc-asm.o smtc-proc.o obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o obj-$(CONFIG_MIPS_CMP) += smp-cmp.o +obj-$(CONFIG_MIPS_GIC_IPI) += smp-gic.o obj-$(CONFIG_CPU_MIPSR2) += spram.o obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index 1b925d8a610c..594660ed19dc 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -39,54 +39,6 @@ #include #include -static void ipi_call_function(unsigned int cpu) -{ - pr_debug("CPU%d: %s cpu %d status %08x\n", - smp_processor_id(), __func__, cpu, read_c0_status()); - - gic_send_ipi(plat_ipi_call_int_xlate(cpu)); -} - - -static void ipi_resched(unsigned int cpu) -{ - pr_debug("CPU%d: %s cpu %d status %08x\n", - smp_processor_id(), __func__, cpu, read_c0_status()); - - gic_send_ipi(plat_ipi_resched_int_xlate(cpu)); -} - -/* - * FIXME: This isn't restricted to CMP - * The SMVP kernel could use GIC interrupts if available - */ -void cmp_send_ipi_single(int cpu, unsigned int action) -{ - unsigned long flags; - - local_irq_save(flags); - - switch (action) { - case SMP_CALL_FUNCTION: - ipi_call_function(cpu); - break; - - case SMP_RESCHEDULE_YOURSELF: - ipi_resched(cpu); - break; - } - - local_irq_restore(flags); -} - -static void cmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) -{ - unsigned int i; - - for_each_cpu(i, mask) - cmp_send_ipi_single(i, action); -} - static void cmp_init_secondary(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -210,8 +162,8 @@ void __init cmp_prepare_cpus(unsigned int max_cpus) } struct plat_smp_ops cmp_smp_ops = { - .send_ipi_single = cmp_send_ipi_single, - .send_ipi_mask = cmp_send_ipi_mask, + .send_ipi_single = gic_send_ipi_single, + .send_ipi_mask = gic_send_ipi_mask, .init_secondary = cmp_init_secondary, .smp_finish = cmp_smp_finish, .cpus_done = cmp_cpus_done, diff --git a/arch/mips/kernel/smp-gic.c b/arch/mips/kernel/smp-gic.c new file mode 100644 index 000000000000..3bb1f92ab525 --- /dev/null +++ b/arch/mips/kernel/smp-gic.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * Based on smp-cmp.c: + * Copyright (C) 2007 MIPS Technologies, Inc. + * Author: Chris Dearman (chris@mips.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include +#include + +void gic_send_ipi_single(int cpu, unsigned int action) +{ + unsigned long flags; + unsigned int intr; + + pr_debug("CPU%d: %s cpu %d action %u status %08x\n", + smp_processor_id(), __func__, cpu, action, read_c0_status()); + + local_irq_save(flags); + + switch (action) { + case SMP_CALL_FUNCTION: + intr = plat_ipi_call_int_xlate(cpu); + break; + + case SMP_RESCHEDULE_YOURSELF: + intr = plat_ipi_resched_int_xlate(cpu); + break; + + default: + BUG(); + } + + gic_send_ipi(intr); + local_irq_restore(flags); +} + +void gic_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu(i, mask) + gic_send_ipi_single(i, action); +} -- cgit From 9f98f3dd0c518d9de02aebe0c25712b17ab3358d Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Wed, 15 Jan 2014 10:31:51 +0000 Subject: MIPS: Add generic CM probe & access code The kernel currently only probes for a MIPS Coherence Manager in the Malta interrupt code in order to detect & enable the GIC. However CM is not Malta-specific, so this should really be more generic. This patch introduces some non-Malta-specific code which probes for a CM and performs some basic initialisation. A new header, with temporarily duplicated register definitions, is introduced in order to: 1) Allow the new definitions to be correct with regards to the CM documentation, as many of those in gcmpregs.h aren't. 2) Allow switching away from the REG() macro used via a few layers of nested macros in order to access registers in gcmpregs.h. This patch instead introduced accessor functions akin to the {read,write}_c0_* functions used for cop0 registers. 3) Allow users of the CM to be migrated one by one. 4) Switch from the name 'GCMP' to 'CM' since the Coherence Manager is what this code is actually dealing with. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6360/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/Makefile | 2 + arch/mips/kernel/mips-cm.c | 121 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+) create mode 100644 arch/mips/kernel/mips-cm.c (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 786a51ddbb78..be56cd8d213b 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -103,6 +103,8 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o +obj-$(CONFIG_MIPS_CM) += mips-cm.o + # # DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not # safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c new file mode 100644 index 000000000000..f76f7a08412d --- /dev/null +++ b/arch/mips/kernel/mips-cm.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include +#include + +void __iomem *mips_cm_base; +void __iomem *mips_cm_l2sync_base; + +phys_t __mips_cm_phys_base(void) +{ + u32 config3 = read_c0_config3(); + u32 cmgcr; + + /* Check the CMGCRBase register is implemented */ + if (!(config3 & MIPS_CONF3_CMGCR)) + return 0; + + /* Read the address from CMGCRBase */ + cmgcr = read_c0_cmgcrbase(); + return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32); +} + +phys_t mips_cm_phys_base(void) + __attribute__((weak, alias("__mips_cm_phys_base"))); + +phys_t __mips_cm_l2sync_phys_base(void) +{ + u32 base_reg; + + /* + * If the L2-only sync region is already enabled then leave it at it's + * current location. + */ + base_reg = read_gcr_l2_only_sync_base(); + if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK) + return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK; + + /* Default to following the CM */ + return mips_cm_phys_base() + MIPS_CM_GCR_SIZE; +} + +phys_t mips_cm_l2sync_phys_base(void) + __attribute__((weak, alias("__mips_cm_l2sync_phys_base"))); + +static void mips_cm_probe_l2sync(void) +{ + unsigned major_rev; + phys_t addr; + + /* L2-only sync was introduced with CM major revision 6 */ + major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >> + CM_GCR_REV_MAJOR_SHF; + if (major_rev < 6) + return; + + /* Find a location for the L2 sync region */ + addr = mips_cm_l2sync_phys_base(); + BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK) != addr); + if (!addr) + return; + + /* Set the region base address & enable it */ + write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK); + + /* Map the region */ + mips_cm_l2sync_base = ioremap_nocache(addr, MIPS_CM_L2SYNC_SIZE); +} + +int mips_cm_probe(void) +{ + phys_t addr; + u32 base_reg; + + addr = mips_cm_phys_base(); + BUG_ON((addr & CM_GCR_BASE_GCRBASE_MSK) != addr); + if (!addr) + return -ENODEV; + + mips_cm_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE); + if (!mips_cm_base) + return -ENXIO; + + /* sanity check that we're looking at a CM */ + base_reg = read_gcr_base(); + if ((base_reg & CM_GCR_BASE_GCRBASE_MSK) != addr) { + pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n", + (unsigned long)addr); + mips_cm_base = NULL; + return -ENODEV; + } + + /* set default target to memory */ + base_reg &= ~CM_GCR_BASE_CMDEFTGT_MSK; + base_reg |= CM_GCR_BASE_CMDEFTGT_MEM; + write_gcr_base(base_reg); + + /* disable CM regions */ + write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK); + write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); + write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK); + write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); + write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR_MSK); + write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); + write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK); + write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); + + /* probe for an L2-only sync region */ + mips_cm_probe_l2sync(); + + return 0; +} -- cgit From 9c38cf44712af95a5ec3937d63faaea9b43eab9a Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Wed, 15 Jan 2014 10:31:52 +0000 Subject: MIPS: Add CPC probe, access functions This patch introduces code to probe for a MIPS Cluster Power Controller & accessor functions to allow for easy register access. This support code will be used by a subsequent patch. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6361/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/Makefile | 1 + arch/mips/kernel/mips-cpc.c | 52 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 arch/mips/kernel/mips-cpc.c (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index be56cd8d213b..a6a87173e17a 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -104,6 +104,7 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o obj-$(CONFIG_MIPS_CM) += mips-cm.o +obj-$(CONFIG_MIPS_CPC) += mips-cpc.o # # DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c new file mode 100644 index 000000000000..c9dc67402969 --- /dev/null +++ b/arch/mips/kernel/mips-cpc.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include +#include + +void __iomem *mips_cpc_base; + +phys_t __weak mips_cpc_phys_base(void) +{ + u32 cpc_base; + + if (!mips_cm_present()) + return 0; + + if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK)) + return 0; + + /* If the CPC is already enabled, leave it so */ + cpc_base = read_gcr_cpc_base(); + if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK) + return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK; + + /* Otherwise, give it the default address & enable it */ + cpc_base = mips_cpc_default_phys_base(); + write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK); + return cpc_base; +} + +int mips_cpc_probe(void) +{ + phys_t addr; + + addr = mips_cpc_phys_base(); + if (!addr) + return -ENODEV; + + mips_cpc_base = ioremap_nocache(addr, 0x8000); + if (!mips_cpc_base) + return -ENXIO; + + return 0; +} -- cgit From 0ee958e102b62b418c2fb46c3439d4262067a5fc Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Wed, 15 Jan 2014 10:31:53 +0000 Subject: MIPS: Coherent Processing System SMP implementation This patch introduces a new SMP implementation for systems implementing the MIPS Coherent Processing System architecture. The kernel will make use of the Coherence Manager, Cluster Power Controller & Global Interrupt Controller in order to detect, bring up & make use of other cores in the system. SMTC is not supported, so only a single TC per VPE in the system is used. That is, this option enables an SMVP style setup but across multiple cores. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6362/ Patchwork: https://patchwork.linux-mips.org/patch/6611/ Patchwork: https://patchwork.linux-mips.org/patch/6651/ Patchwork: https://patchwork.linux-mips.org/patch/6652/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/Makefile | 1 + arch/mips/kernel/asm-offsets.c | 13 ++ arch/mips/kernel/cps-vec.S | 191 +++++++++++++++++++++++ arch/mips/kernel/cpu-probe.c | 2 + arch/mips/kernel/smp-cps.c | 335 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 542 insertions(+) create mode 100644 arch/mips/kernel/cps-vec.S create mode 100644 arch/mips/kernel/smp-cps.c (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index a6a87173e17a..277dab301cea 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o obj-$(CONFIG_MIPS_MT_SMTC) += smtc.o smtc-asm.o smtc-proc.o obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o obj-$(CONFIG_MIPS_CMP) += smp-cmp.o +obj-$(CONFIG_MIPS_CPS) += smp-cps.o cps-vec.o obj-$(CONFIG_MIPS_GIC_IPI) += smp-gic.o obj-$(CONFIG_CPU_MIPSR2) += spram.o diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 0c2e853c3db4..8a2a45d4b147 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -16,6 +16,7 @@ #include #include #include +#include #include @@ -397,3 +398,15 @@ void output_kvm_defines(void) OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]); BLANK(); } + +#ifdef CONFIG_MIPS_CPS +void output_cps_defines(void) +{ + COMMENT(" MIPS CPS offsets. "); + OFFSET(BOOTCFG_CORE, boot_config, core); + OFFSET(BOOTCFG_VPE, boot_config, vpe); + OFFSET(BOOTCFG_PC, boot_config, pc); + OFFSET(BOOTCFG_SP, boot_config, sp); + OFFSET(BOOTCFG_GP, boot_config, gp); +} +#endif diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S new file mode 100644 index 000000000000..f7a46db4b161 --- /dev/null +++ b/arch/mips/kernel/cps-vec.S @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include + +#define GCR_CL_COHERENCE_OFS 0x2008 + +.section .text.cps-vec +.balign 0x1000 +.set noreorder + +LEAF(mips_cps_core_entry) + /* + * These first 8 bytes will be patched by cps_smp_setup to load the + * base address of the CM GCRs into register v1. + */ + .quad 0 + + /* Check whether we're here due to an NMI */ + mfc0 k0, CP0_STATUS + and k0, k0, ST0_NMI + beqz k0, not_nmi + nop + + /* This is an NMI */ + la k0, nmi_handler + jr k0 + nop + +not_nmi: + /* Setup Cause */ + li t0, CAUSEF_IV + mtc0 t0, CP0_CAUSE + + /* Setup Status */ + li t0, ST0_CU1 | ST0_CU0 + mtc0 t0, CP0_STATUS + + /* + * Clear the bits used to index the caches. Note that the architecture + * dictates that writing to any of TagLo or TagHi selects 0 or 2 should + * be valid for all MIPS32 CPUs, even those for which said writes are + * unnecessary. + */ + mtc0 zero, CP0_TAGLO, 0 + mtc0 zero, CP0_TAGHI, 0 + mtc0 zero, CP0_TAGLO, 2 + mtc0 zero, CP0_TAGHI, 2 + ehb + + /* Primary cache configuration is indicated by Config1 */ + mfc0 v0, CP0_CONFIG, 1 + + /* Detect I-cache line size */ + _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ + beqz t0, icache_done + li t1, 2 + sllv t0, t1, t0 + + /* Detect I-cache size */ + _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ + xori t2, t1, 0x7 + beqz t2, 1f + li t3, 32 + addi t1, t1, 1 + sllv t1, t3, t1 +1: /* At this point t1 == I-cache sets per way */ + _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ + addi t2, t2, 1 + mul t1, t1, t0 + mul t1, t1, t2 + + li a0, KSEG0 + add a1, a0, t1 +1: cache Index_Store_Tag_I, 0(a0) + add a0, a0, t0 + bne a0, a1, 1b + nop +icache_done: + + /* Detect D-cache line size */ + _EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ + beqz t0, dcache_done + li t1, 2 + sllv t0, t1, t0 + + /* Detect D-cache size */ + _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ + xori t2, t1, 0x7 + beqz t2, 1f + li t3, 32 + addi t1, t1, 1 + sllv t1, t3, t1 +1: /* At this point t1 == D-cache sets per way */ + _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ + addi t2, t2, 1 + mul t1, t1, t0 + mul t1, t1, t2 + + li a0, KSEG0 + addu a1, a0, t1 + subu a1, a1, t0 +1: cache Index_Store_Tag_D, 0(a0) + bne a0, a1, 1b + add a0, a0, t0 +dcache_done: + + /* Set Kseg0 cacheable, coherent, write-back, write-allocate */ + mfc0 t0, CP0_CONFIG + ori t0, 0x7 + xori t0, 0x2 + mtc0 t0, CP0_CONFIG + ehb + + /* Enter the coherent domain */ + li t0, 0xff + sw t0, GCR_CL_COHERENCE_OFS(v1) + ehb + + /* Jump to kseg0 */ + la t0, 1f + jr t0 + nop + +1: /* We're up, cached & coherent */ + + /* + * TODO: We should check the VPE number we intended to boot here, and + * if non-zero we should start that VPE and stop this one. For + * the moment this doesn't matter since CPUs are brought up + * sequentially and in order, but once hotplug is implemented + * this will need revisiting. + */ + + /* Off we go! */ + la t0, mips_cps_bootcfg + lw t1, BOOTCFG_PC(t0) + lw gp, BOOTCFG_GP(t0) + lw sp, BOOTCFG_SP(t0) + jr t1 + nop + END(mips_cps_core_entry) + +.org 0x200 +LEAF(excep_tlbfill) + b . + nop + END(excep_tlbfill) + +.org 0x280 +LEAF(excep_xtlbfill) + b . + nop + END(excep_xtlbfill) + +.org 0x300 +LEAF(excep_cache) + b . + nop + END(excep_cache) + +.org 0x380 +LEAF(excep_genex) + b . + nop + END(excep_genex) + +.org 0x400 +LEAF(excep_intex) + b . + nop + END(excep_intex) + +.org 0x480 +LEAF(excep_ejtag) + la k0, ejtag_debug_handler + jr k0 + nop + END(excep_ejtag) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index ac09248b7468..c1ee8b4d2144 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -398,8 +398,10 @@ static void decode_configs(struct cpuinfo_mips *c) mips_probe_watch_registers(c); +#ifndef CONFIG_MIPS_CPS if (cpu_has_mips_r2) c->core = read_c0_ebase() & 0x3ff; +#endif } #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c new file mode 100644 index 000000000000..536eec0d21b6 --- /dev/null +++ b/arch/mips/kernel/smp-cps.c @@ -0,0 +1,335 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static DECLARE_BITMAP(core_power, NR_CPUS); + +struct boot_config mips_cps_bootcfg; + +static void init_core(void) +{ + unsigned int nvpes, t; + u32 mvpconf0, vpeconf0, vpecontrol, tcstatus, tcbind, status; + + if (!cpu_has_mipsmt) + return; + + /* Enter VPE configuration state */ + dvpe(); + set_c0_mvpcontrol(MVPCONTROL_VPC); + + /* Retrieve the count of VPEs in this core */ + mvpconf0 = read_c0_mvpconf0(); + nvpes = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; + smp_num_siblings = nvpes; + + for (t = 1; t < nvpes; t++) { + /* Use a 1:1 mapping of TC index to VPE index */ + settc(t); + + /* Bind 1 TC to this VPE */ + tcbind = read_tc_c0_tcbind(); + tcbind &= ~TCBIND_CURVPE; + tcbind |= t << TCBIND_CURVPE_SHIFT; + write_tc_c0_tcbind(tcbind); + + /* Set exclusive TC, non-active, master */ + vpeconf0 = read_vpe_c0_vpeconf0(); + vpeconf0 &= ~(VPECONF0_XTC | VPECONF0_VPA); + vpeconf0 |= t << VPECONF0_XTC_SHIFT; + vpeconf0 |= VPECONF0_MVP; + write_vpe_c0_vpeconf0(vpeconf0); + + /* Declare TC non-active, non-allocatable & interrupt exempt */ + tcstatus = read_tc_c0_tcstatus(); + tcstatus &= ~(TCSTATUS_A | TCSTATUS_DA); + tcstatus |= TCSTATUS_IXMT; + write_tc_c0_tcstatus(tcstatus); + + /* Halt the TC */ + write_tc_c0_tchalt(TCHALT_H); + + /* Allow only 1 TC to execute */ + vpecontrol = read_vpe_c0_vpecontrol(); + vpecontrol &= ~VPECONTROL_TE; + write_vpe_c0_vpecontrol(vpecontrol); + + /* Copy (most of) Status from VPE 0 */ + status = read_c0_status(); + status &= ~(ST0_IM | ST0_IE | ST0_KSU); + status |= ST0_CU0; + write_vpe_c0_status(status); + + /* Copy Config from VPE 0 */ + write_vpe_c0_config(read_c0_config()); + write_vpe_c0_config7(read_c0_config7()); + + /* Ensure no software interrupts are pending */ + write_vpe_c0_cause(0); + + /* Sync Count */ + write_vpe_c0_count(read_c0_count()); + } + + /* Leave VPE configuration state */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); +} + +static void __init cps_smp_setup(void) +{ + unsigned int ncores, nvpes, core_vpes; + int c, v; + u32 core_cfg, *entry_code; + + /* Detect & record VPE topology */ + ncores = mips_cm_numcores(); + pr_info("VPE topology "); + for (c = nvpes = 0; c < ncores; c++) { + if (cpu_has_mipsmt && config_enabled(CONFIG_MIPS_MT_SMP)) { + write_gcr_cl_other(c << CM_GCR_Cx_OTHER_CORENUM_SHF); + core_cfg = read_gcr_co_config(); + core_vpes = ((core_cfg & CM_GCR_Cx_CONFIG_PVPE_MSK) >> + CM_GCR_Cx_CONFIG_PVPE_SHF) + 1; + } else { + core_vpes = 1; + } + + pr_cont("%c%u", c ? ',' : '{', core_vpes); + + for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { + cpu_data[nvpes + v].core = c; +#ifdef CONFIG_MIPS_MT_SMP + cpu_data[nvpes + v].vpe_id = v; +#endif + } + + nvpes += core_vpes; + } + pr_cont("} total %u\n", nvpes); + + /* Indicate present CPUs (CPU being synonymous with VPE) */ + for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { + set_cpu_possible(v, true); + set_cpu_present(v, true); + __cpu_number_map[v] = v; + __cpu_logical_map[v] = v; + } + + /* Core 0 is powered up (we're running on it) */ + bitmap_set(core_power, 0, 1); + + /* Disable MT - we only want to run 1 TC per VPE */ + if (cpu_has_mipsmt) + dmt(); + + /* Initialise core 0 */ + init_core(); + + /* Patch the start of mips_cps_core_entry to provide the CM base */ + entry_code = (u32 *)&mips_cps_core_entry; + UASM_i_LA(&entry_code, 3, (long)mips_cm_base); + + /* Make core 0 coherent with everything */ + write_gcr_cl_coherence(0xff); +} + +static void __init cps_prepare_cpus(unsigned int max_cpus) +{ + mips_mt_set_cpuoptions(); +} + +static void boot_core(struct boot_config *cfg) +{ + u32 access; + + /* Select the appropriate core */ + write_gcr_cl_other(cfg->core << CM_GCR_Cx_OTHER_CORENUM_SHF); + + /* Set its reset vector */ + write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); + + /* Ensure its coherency is disabled */ + write_gcr_co_coherence(0); + + /* Ensure the core can access the GCRs */ + access = read_gcr_access(); + access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + cfg->core); + write_gcr_access(access); + + /* Copy cfg */ + mips_cps_bootcfg = *cfg; + + if (mips_cpc_present()) { + /* Select the appropriate core */ + write_cpc_cl_other(cfg->core << CPC_Cx_OTHER_CORENUM_SHF); + + /* Reset the core */ + write_cpc_co_cmd(CPC_Cx_CMD_RESET); + } else { + /* Take the core out of reset */ + write_gcr_co_reset_release(0); + } + + /* The core is now powered up */ + bitmap_set(core_power, cfg->core, 1); +} + +static void boot_vpe(void *info) +{ + struct boot_config *cfg = info; + u32 tcstatus, vpeconf0; + + /* Enter VPE configuration state */ + dvpe(); + set_c0_mvpcontrol(MVPCONTROL_VPC); + + settc(cfg->vpe); + + /* Set the TC restart PC */ + write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); + + /* Activate the TC, allow interrupts */ + tcstatus = read_tc_c0_tcstatus(); + tcstatus &= ~TCSTATUS_IXMT; + tcstatus |= TCSTATUS_A; + write_tc_c0_tcstatus(tcstatus); + + /* Clear the TC halt bit */ + write_tc_c0_tchalt(0); + + /* Activate the VPE */ + vpeconf0 = read_vpe_c0_vpeconf0(); + vpeconf0 |= VPECONF0_VPA; + write_vpe_c0_vpeconf0(vpeconf0); + + /* Set the stack & global pointer registers */ + write_tc_gpr_sp(cfg->sp); + write_tc_gpr_gp(cfg->gp); + + /* Leave VPE configuration state */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + + /* Enable other VPEs to execute */ + evpe(EVPE_ENABLE); +} + +static void cps_boot_secondary(int cpu, struct task_struct *idle) +{ + struct boot_config cfg; + unsigned int remote; + int err; + + cfg.core = cpu_data[cpu].core; + cfg.vpe = cpu_vpe_id(&cpu_data[cpu]); + cfg.pc = (unsigned long)&smp_bootstrap; + cfg.sp = __KSTK_TOS(idle); + cfg.gp = (unsigned long)task_thread_info(idle); + + if (!test_bit(cfg.core, core_power)) { + /* Boot a VPE on a powered down core */ + boot_core(&cfg); + return; + } + + if (cfg.core != current_cpu_data.core) { + /* Boot a VPE on another powered up core */ + for (remote = 0; remote < NR_CPUS; remote++) { + if (cpu_data[remote].core != cfg.core) + continue; + if (cpu_online(remote)) + break; + } + BUG_ON(remote >= NR_CPUS); + + err = smp_call_function_single(remote, boot_vpe, &cfg, 1); + if (err) + panic("Failed to call remote CPU\n"); + return; + } + + BUG_ON(!cpu_has_mipsmt); + + /* Boot a VPE on this core */ + boot_vpe(&cfg); +} + +static void cps_init_secondary(void) +{ + /* Disable MT - we only want to run 1 TC per VPE */ + if (cpu_has_mipsmt) + dmt(); + + /* TODO: revisit this assumption once hotplug is implemented */ + if (cpu_vpe_id(¤t_cpu_data) == 0) + init_core(); + + change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | + STATUSF_IP6 | STATUSF_IP7); +} + +static void cps_smp_finish(void) +{ + write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); + +#ifdef CONFIG_MIPS_MT_FPAFF + /* If we have an FPU, enroll ourselves in the FPU-full mask */ + if (cpu_has_fpu) + cpu_set(smp_processor_id(), mt_fpu_cpumask); +#endif /* CONFIG_MIPS_MT_FPAFF */ + + local_irq_enable(); +} + +static void cps_cpus_done(void) +{ +} + +static struct plat_smp_ops cps_smp_ops = { + .smp_setup = cps_smp_setup, + .prepare_cpus = cps_prepare_cpus, + .boot_secondary = cps_boot_secondary, + .init_secondary = cps_init_secondary, + .smp_finish = cps_smp_finish, + .send_ipi_single = gic_send_ipi_single, + .send_ipi_mask = gic_send_ipi_mask, + .cpus_done = cps_cpus_done, +}; + +int register_cps_smp_ops(void) +{ + if (!mips_cm_present()) { + pr_warn("MIPS CPS SMP unable to proceed without a CM\n"); + return -ENODEV; + } + + /* check we have a GIC - we need one for IPIs */ + if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) { + pr_warn("MIPS CPS SMP unable to proceed without a GIC\n"); + return -ENODEV; + } + + register_smp_ops(&cps_smp_ops); + return 0; +} -- cgit From 9d9812706f17c296f0ce3c932276f3757163cfa1 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Wed, 15 Jan 2014 10:31:57 +0000 Subject: MIPS: Remove gcmpregs.h This header was used only by Malta but is used no longer. Remove it. It was also included unnecessarily in irq-gic.c, so that include is also removed. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6366/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/irq-gic.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index 5b5ddb231f26..8520dad6d4e3 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include -- cgit From 6e34574603f633fa67cf1037aa6374292469c74f Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Wed, 22 Jan 2014 14:39:59 +0000 Subject: MIPS: asm: syscall: Define syscall_get_arch This effectively renames __syscall_get_arch to syscall_get_arch and implements a compatible interface for the seccomp API. The seccomp code (kernel/seccomp.c) expects a syscall_get_arch function to be defined for every architecture, so we drop the leading underscores from the existing function. This also makes use of the 'task' argument to determine the type the process instead of assuming the process has the same characteristics as the kernel it's running on. Signed-off-by: Markos Chandras Reviewed-by: Paul Burton Reviewed-by: James Hogan Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6398/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 7da9b76db4d9..fe5af5440472 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -677,7 +677,7 @@ asmlinkage void syscall_trace_enter(struct pt_regs *regs) if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) trace_sys_enter(regs, regs->regs[2]); - audit_syscall_entry(__syscall_get_arch(), + audit_syscall_entry(syscall_get_arch(current, regs), regs->regs[2], regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); -- cgit From 1225eb825208b529fd4c01d07faf9db48e68cd33 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Wed, 22 Jan 2014 14:40:01 +0000 Subject: MIPS: ptrace: Move away from secure_computing_strict MIPS now has the infrastructure for dynamic seccomp-bpf filtering Signed-off-by: Markos Chandras Reviewed-by: James Hogan Reviewed-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6400/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index fe5af5440472..7f9bcaac467e 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -662,13 +662,14 @@ long arch_ptrace(struct task_struct *child, long request, * Notification of system call entry/exit * - triggered by current->work.syscall_trace */ -asmlinkage void syscall_trace_enter(struct pt_regs *regs) +asmlinkage long syscall_trace_enter(struct pt_regs *regs) { + long syscall = regs->regs[2]; long ret = 0; user_exit(); - /* do the secure computing check first */ - secure_computing_strict(regs->regs[2]); + if (secure_computing(syscall) == -1) + return -1; if (test_thread_flag(TIF_SYSCALL_TRACE) && tracehook_report_syscall_entry(regs)) @@ -678,9 +679,10 @@ asmlinkage void syscall_trace_enter(struct pt_regs *regs) trace_sys_enter(regs, regs->regs[2]); audit_syscall_entry(syscall_get_arch(current, regs), - regs->regs[2], + syscall, regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); + return syscall; } /* -- cgit From 9d37c405ed7e4bb10798c37ef4e642b682425c4e Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Wed, 22 Jan 2014 14:40:02 +0000 Subject: MIPS: kernel: scalls: Skip the syscall if denied by the seccomp filter Signed-off-by: Markos Chandras Reviewed-by: Paul Burton Reviewed-by: James Hogan Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6399/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/scall32-o32.S | 4 +++- arch/mips/kernel/scall64-64.S | 4 +++- arch/mips/kernel/scall64-n32.S | 4 +++- arch/mips/kernel/scall64-o32.S | 4 +++- 4 files changed, 12 insertions(+), 4 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index a5b14f48e1af..1789a801802e 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -120,6 +120,8 @@ syscall_trace_entry: move a0, sp jal syscall_trace_enter + bltz v0, 2f # seccomp failed? Skip syscall + move t0, s0 RESTORE_STATIC lw a0, PT_R4(sp) # Restore argument registers @@ -138,7 +140,7 @@ syscall_trace_entry: sw t1, PT_R0(sp) # save it for syscall restarting 1: sw v0, PT_R2(sp) # result - j syscall_exit +2: j syscall_exit /* ------------------------------------------------------------------------ */ diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index b56e254beb15..7f5d88be6b9e 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -82,6 +82,8 @@ syscall_trace_entry: move a0, sp jal syscall_trace_enter + bltz v0, 2f # seccomp failed? Skip syscall + move t0, s0 RESTORE_STATIC ld a0, PT_R4(sp) # Restore argument registers @@ -102,7 +104,7 @@ syscall_trace_entry: sd t1, PT_R0(sp) # save it for syscall restarting 1: sd v0, PT_R2(sp) # result - j syscall_exit +2: j syscall_exit illegal_syscall: /* This also isn't a 64-bit syscall, throw an error. */ diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index f7e5b72cf481..b6e15861bd1b 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -74,6 +74,8 @@ n32_syscall_trace_entry: move a0, sp jal syscall_trace_enter + bltz v0, 2f # seccomp failed? Skip syscall + move t0, s0 RESTORE_STATIC ld a0, PT_R4(sp) # Restore argument registers @@ -94,7 +96,7 @@ n32_syscall_trace_entry: sd t1, PT_R0(sp) # save it for syscall restarting 1: sd v0, PT_R2(sp) # result - j syscall_exit +2: j syscall_exit not_n32_scall: /* This is not an n32 compatibility syscall, pass it on to diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 6788727d91af..67dc022f6826 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -114,6 +114,8 @@ trace_a_syscall: move a0, sp jal syscall_trace_enter + bltz v0, 2f # seccomp failed? Skip syscall + move t0, s0 RESTORE_STATIC ld a0, PT_R4(sp) # Restore argument registers @@ -136,7 +138,7 @@ trace_a_syscall: sd t1, PT_R0(sp) # save it for syscall restarting 1: sd v0, PT_R2(sp) # result - j syscall_exit +2: j syscall_exit /* ------------------------------------------------------------------------ */ -- cgit From 4c21b8fd8f146a22e1eaf92833a32e51f560e82a Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Wed, 22 Jan 2014 14:40:03 +0000 Subject: MIPS: seccomp: Handle indirect system calls (o32) When userland uses syscall() to perform an indirect system call the actually system call that needs to be checked by the filter is on the first argument. The kernel code needs to handle this case by looking at the original syscall number in v0 and if it's NR_syscall, then it needs to examine the first argument to identify the real system call that will be executed. Similarly, we need to 'virtually' shift the syscall() arguments so the syscall_get_arguments() function can fetch the correct arguments for the indirect system call. Signed-off-by: Markos Chandras Reviewed-by: James Hogan Reviewed-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6404/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 3 +-- arch/mips/kernel/scall32-o32.S | 11 ++++++++++- arch/mips/kernel/scall64-64.S | 1 + arch/mips/kernel/scall64-n32.S | 1 + arch/mips/kernel/scall64-o32.S | 13 ++++++++++++- 5 files changed, 25 insertions(+), 4 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 7f9bcaac467e..a17a7023d7c9 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -662,9 +662,8 @@ long arch_ptrace(struct task_struct *child, long request, * Notification of system call entry/exit * - triggered by current->work.syscall_trace */ -asmlinkage long syscall_trace_enter(struct pt_regs *regs) +asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall) { - long syscall = regs->regs[2]; long ret = 0; user_exit(); diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index 1789a801802e..ffe89139e0f9 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -118,7 +118,16 @@ syscall_trace_entry: SAVE_STATIC move s0, t2 move a0, sp - jal syscall_trace_enter + + /* + * syscall number is in v0 unless we called syscall(__NR_###) + * where the real syscall number is in a0 + */ + addiu a1, v0, __NR_O32_Linux + bnez v0, 1f /* __NR_syscall at offset 0 */ + lw a1, PT_R4(sp) + +1: jal syscall_trace_enter bltz v0, 2f # seccomp failed? Skip syscall diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 7f5d88be6b9e..dd99c3285aea 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -80,6 +80,7 @@ syscall_trace_entry: SAVE_STATIC move s0, t2 move a0, sp + daddiu a1, v0, __NR_64_Linux jal syscall_trace_enter bltz v0, 2f # seccomp failed? Skip syscall diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index b6e15861bd1b..f68d2f4f0090 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -72,6 +72,7 @@ n32_syscall_trace_entry: SAVE_STATIC move s0, t2 move a0, sp + daddiu a1, v0, __NR_N32_Linux jal syscall_trace_enter bltz v0, 2f # seccomp failed? Skip syscall diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 67dc022f6826..70f6acecd928 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -112,7 +112,18 @@ trace_a_syscall: move s0, t2 # Save syscall pointer move a0, sp - jal syscall_trace_enter + /* + * syscall number is in v0 unless we called syscall(__NR_###) + * where the real syscall number is in a0 + * note: NR_syscall is the first O32 syscall but the macro is + * only defined when compiling with -mabi=32 (CONFIG_32BIT) + * therefore __NR_O32_Linux is used (4000) + */ + addiu a1, v0, __NR_O32_Linux + bnez v0, 1f /* __NR_syscall at offset 0 */ + lw a1, PT_R4(sp) + +1: jal syscall_trace_enter bltz v0, 2f # seccomp failed? Skip syscall -- cgit From bbd426f542cb61f2322e15dab4507f2661090c06 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Thu, 13 Feb 2014 11:26:41 +0000 Subject: MIPS: Simplify FP context access This patch replaces the fpureg_t typedef with a "union fpureg" enabling easier access to 32 & 64 bit values. This allows the access macros used in cp1emu.c to be simplified somewhat. It will also make it easier to expand the width of the FP registers as will be done in a future patch in order to support the 128 bit registers introduced with MSA. No behavioural change is intended by this patch. Signed-off-by: Paul Burton Reviewed-by: Qais Yousef Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6532/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 39 +++++++++++++++++---------------------- arch/mips/kernel/ptrace32.c | 25 ++++++++----------------- 2 files changed, 25 insertions(+), 39 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index a17a7023d7c9..7d97709e715f 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -120,9 +120,10 @@ int ptrace_getfpregs(struct task_struct *child, __u32 __user *data) return -EIO; if (tsk_used_math(child)) { - fpureg_t *fregs = get_fpu_regs(child); + union fpureg *fregs = get_fpu_regs(child); for (i = 0; i < 32; i++) - __put_user(fregs[i], i + (__u64 __user *) data); + __put_user(get_fpr64(&fregs[i], 0), + i + (__u64 __user *)data); } else { for (i = 0; i < 32; i++) __put_user((__u64) -1, i + (__u64 __user *) data); @@ -158,7 +159,8 @@ int ptrace_getfpregs(struct task_struct *child, __u32 __user *data) int ptrace_setfpregs(struct task_struct *child, __u32 __user *data) { - fpureg_t *fregs; + union fpureg *fregs; + u64 fpr_val; int i; if (!access_ok(VERIFY_READ, data, 33 * 8)) @@ -166,8 +168,10 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data) fregs = get_fpu_regs(child); - for (i = 0; i < 32; i++) - __get_user(fregs[i], i + (__u64 __user *) data); + for (i = 0; i < 32; i++) { + __get_user(fpr_val, i + (__u64 __user *)data); + set_fpr64(&fregs[i], 0, fpr_val); + } __get_user(child->thread.fpu.fcr31, data + 64); @@ -408,7 +412,7 @@ long arch_ptrace(struct task_struct *child, long request, /* Read the word at location addr in the USER area. */ case PTRACE_PEEKUSR: { struct pt_regs *regs; - fpureg_t *fregs; + union fpureg *fregs; unsigned long tmp = 0; regs = task_pt_regs(child); @@ -433,14 +437,12 @@ long arch_ptrace(struct task_struct *child, long request, * order bits of the values stored in the even * registers - unless we're using r2k_switch.S. */ - if (addr & 1) - tmp = fregs[(addr & ~1) - 32] >> 32; - else - tmp = fregs[addr - 32]; + tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE], + addr & 1); break; } #endif - tmp = fregs[addr - FPR_BASE]; + tmp = get_fpr32(&fregs[addr - FPR_BASE], 0); break; case PC: tmp = regs->cp0_epc; @@ -548,7 +550,7 @@ long arch_ptrace(struct task_struct *child, long request, regs->regs[addr] = data; break; case FPR_BASE ... FPR_BASE + 31: { - fpureg_t *fregs = get_fpu_regs(child); + union fpureg *fregs = get_fpu_regs(child); if (!tsk_used_math(child)) { /* FP not yet used */ @@ -563,19 +565,12 @@ long arch_ptrace(struct task_struct *child, long request, * order bits of the values stored in the even * registers - unless we're using r2k_switch.S. */ - if (addr & 1) { - fregs[(addr & ~1) - FPR_BASE] &= - 0xffffffff; - fregs[(addr & ~1) - FPR_BASE] |= - ((u64)data) << 32; - } else { - fregs[addr - FPR_BASE] &= ~0xffffffffLL; - fregs[addr - FPR_BASE] |= data; - } + set_fpr32(&fregs[(addr & ~1) - FPR_BASE], + addr & 1, data); break; } #endif - fregs[addr - FPR_BASE] = data; + set_fpr64(&fregs[addr - FPR_BASE], 0, data); break; } case PC: diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c index b8aa2dd5b00b..c394d8f74265 100644 --- a/arch/mips/kernel/ptrace32.c +++ b/arch/mips/kernel/ptrace32.c @@ -80,7 +80,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, /* Read the word at location addr in the USER area. */ case PTRACE_PEEKUSR: { struct pt_regs *regs; - fpureg_t *fregs; + union fpureg *fregs; unsigned int tmp; regs = task_pt_regs(child); @@ -103,13 +103,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, * order bits of the values stored in the even * registers - unless we're using r2k_switch.S. */ - if (addr & 1) - tmp = fregs[(addr & ~1) - 32] >> 32; - else - tmp = fregs[addr - 32]; + tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE], + addr & 1); break; } - tmp = fregs[addr - FPR_BASE]; + tmp = get_fpr32(&fregs[addr - FPR_BASE], 0); break; case PC: tmp = regs->cp0_epc; @@ -233,7 +231,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, regs->regs[addr] = data; break; case FPR_BASE ... FPR_BASE + 31: { - fpureg_t *fregs = get_fpu_regs(child); + union fpureg *fregs = get_fpu_regs(child); if (!tsk_used_math(child)) { /* FP not yet used */ @@ -247,18 +245,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, * order bits of the values stored in the even * registers - unless we're using r2k_switch.S. */ - if (addr & 1) { - fregs[(addr & ~1) - FPR_BASE] &= - 0xffffffff; - fregs[(addr & ~1) - FPR_BASE] |= - ((u64)data) << 32; - } else { - fregs[addr - FPR_BASE] &= ~0xffffffffLL; - fregs[addr - FPR_BASE] |= data; - } + set_fpr32(&fregs[(addr & ~1) - FPR_BASE], + addr & 1, data); break; } - fregs[addr - FPR_BASE] = data; + set_fpr64(&fregs[addr - FPR_BASE], 0, data); break; } case PC: -- cgit From b2ead528288545859dbd7004e07bc23204cf92a8 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 27 Jan 2014 15:23:02 +0000 Subject: MIPS: Move & rename fpu_emulator_{save,restore}_context These functions aren't directly related to the FPU emulator at all, they simply copy between a thread's saved context & a sigcontext. Thus move them to the appropriate signal files & rename them accordingly. This makes it clearer that the functions don't require the FPU emulator in any way. Signed-off-by: Paul Burton Reviewed-by: Qais Yousef Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6422/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/signal.c | 45 ++++++++++++++++++++++++++++++++++++++------- arch/mips/kernel/signal32.c | 43 ++++++++++++++++++++++++++++++++++++++----- 2 files changed, 76 insertions(+), 12 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 5199563c4403..b7e4614d41b5 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -46,9 +46,6 @@ static int (*restore_fp_context)(struct sigcontext __user *sc); extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); -extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); -extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); - struct sigframe { u32 sf_ass[4]; /* argument save space for o32 */ u32 sf_pad[2]; /* Was: signal trampoline */ @@ -63,6 +60,40 @@ struct rt_sigframe { struct ucontext rs_uc; }; +/* + * Thread saved context copy to/from a signal context presumed to be on the + * user stack, and therefore accessed with appropriate macros from uaccess.h. + */ +static int copy_fp_to_sigcontext(struct sigcontext __user *sc) +{ + int i; + int err = 0; + + for (i = 0; i < 32; i++) { + err |= + __put_user(get_fpr64(¤t->thread.fpu.fpr[i], 0), + &sc->sc_fpregs[i]); + } + err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); + + return err; +} + +static int copy_fp_from_sigcontext(struct sigcontext __user *sc) +{ + int i; + int err = 0; + u64 fpr_val; + + for (i = 0; i < 32; i++) { + err |= __get_user(fpr_val, &sc->sc_fpregs[i]); + set_fpr64(¤t->thread.fpu.fpr[i], 0, fpr_val); + } + err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); + + return err; +} + /* * Helper routines */ @@ -595,14 +626,14 @@ static int smp_save_fp_context(struct sigcontext __user *sc) { return raw_cpu_has_fpu ? _save_fp_context(sc) - : fpu_emulator_save_context(sc); + : copy_fp_to_sigcontext(sc); } static int smp_restore_fp_context(struct sigcontext __user *sc) { return raw_cpu_has_fpu ? _restore_fp_context(sc) - : fpu_emulator_restore_context(sc); + : copy_fp_from_sigcontext(sc); } #endif @@ -617,8 +648,8 @@ static int signal_setup(void) save_fp_context = _save_fp_context; restore_fp_context = _restore_fp_context; } else { - save_fp_context = fpu_emulator_save_context; - restore_fp_context = fpu_emulator_restore_context; + save_fp_context = copy_fp_from_sigcontext; + restore_fp_context = copy_fp_to_sigcontext; } #endif diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 3d60f7750fa8..dc09206d8c7b 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -42,9 +42,6 @@ static int (*restore_fp_context32)(struct sigcontext32 __user *sc); extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); -extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); -extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); - /* * Including would give use the 64-bit syscall numbers ... */ @@ -77,6 +74,42 @@ struct rt_sigframe32 { struct ucontext32 rs_uc; }; +/* + * Thread saved context copy to/from a signal context presumed to be on the + * user stack, and therefore accessed with appropriate macros from uaccess.h. + */ +static int copy_fp_to_sigcontext32(struct sigcontext32 __user *sc) +{ + int i; + int err = 0; + int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1; + + for (i = 0; i < 32; i += inc) { + err |= + __put_user(get_fpr64(¤t->thread.fpu.fpr[i], 0), + &sc->sc_fpregs[i]); + } + err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); + + return err; +} + +static int copy_fp_from_sigcontext32(struct sigcontext32 __user *sc) +{ + int i; + int err = 0; + int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1; + u64 fpr_val; + + for (i = 0; i < 32; i += inc) { + err |= __get_user(fpr_val, &sc->sc_fpregs[i]); + set_fpr64(¤t->thread.fpu.fpr[i], 0, fpr_val); + } + err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); + + return err; +} + /* * sigcontext handlers */ @@ -566,8 +599,8 @@ static int signal32_init(void) save_fp_context32 = _save_fp_context32; restore_fp_context32 = _restore_fp_context32; } else { - save_fp_context32 = fpu_emulator_save_context32; - restore_fp_context32 = fpu_emulator_restore_context32; + save_fp_context32 = copy_fp_to_sigcontext32; + restore_fp_context32 = copy_fp_from_sigcontext32; } return 0; -- cgit From ff3aa5f296392b4bdc46ce975e6403bc7d27b191 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 27 Jan 2014 15:23:03 +0000 Subject: MIPS: Don't require FPU on sigcontext setup/restore When a task which has used the FPU at some point in its past takes a signal the kernel would previously always require the task to take ownership of the FPU whilst setting up or restoring from the sigcontext. That means that if the task has not used the FPU within this timeslice then the kernel would enable the FPU, restore the task's FP context into FPU registers and then save them into the sigcontext. This seems inefficient, and if the signal handler doesn't use FP then enabling the FPU & the extra memory accesses are entirely wasted work. This patch modifies the sigcontext setup & restore code to copy directly between the tasks saved FP context & the sigcontext for any tasks which have used FP in the past but are not currently the FPU owner (ie. have not used FP in this timeslice). Signed-off-by: Paul Burton Reviewed-by: Qais Yousef Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6423/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/signal.c | 22 ++++++++++++++-------- arch/mips/kernel/signal32.c | 22 ++++++++++++++-------- 2 files changed, 28 insertions(+), 16 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index b7e4614d41b5..e0178e117f68 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -102,10 +102,13 @@ static int protected_save_fp_context(struct sigcontext __user *sc) int err; while (1) { lock_fpu_owner(); - err = own_fpu_inatomic(1); - if (!err) - err = save_fp_context(sc); /* this might fail */ - unlock_fpu_owner(); + if (is_fpu_owner()) { + err = save_fp_context(sc); + unlock_fpu_owner(); + } else { + unlock_fpu_owner(); + err = copy_fp_to_sigcontext(sc); + } if (likely(!err)) break; /* touch the sigcontext and try again */ @@ -123,10 +126,13 @@ static int protected_restore_fp_context(struct sigcontext __user *sc) int err, tmp __maybe_unused; while (1) { lock_fpu_owner(); - err = own_fpu_inatomic(0); - if (!err) - err = restore_fp_context(sc); /* this might fail */ - unlock_fpu_owner(); + if (is_fpu_owner()) { + err = restore_fp_context(sc); + unlock_fpu_owner(); + } else { + unlock_fpu_owner(); + err = copy_fp_from_sigcontext(sc); + } if (likely(!err)) break; /* touch the sigcontext and try again */ diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index dc09206d8c7b..aec58211faaa 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -118,10 +118,13 @@ static int protected_save_fp_context32(struct sigcontext32 __user *sc) int err; while (1) { lock_fpu_owner(); - err = own_fpu_inatomic(1); - if (!err) - err = save_fp_context32(sc); /* this might fail */ - unlock_fpu_owner(); + if (is_fpu_owner()) { + err = save_fp_context32(sc); + unlock_fpu_owner(); + } else { + unlock_fpu_owner(); + err = copy_fp_to_sigcontext32(sc); + } if (likely(!err)) break; /* touch the sigcontext and try again */ @@ -139,10 +142,13 @@ static int protected_restore_fp_context32(struct sigcontext32 __user *sc) int err, tmp __maybe_unused; while (1) { lock_fpu_owner(); - err = own_fpu_inatomic(0); - if (!err) - err = restore_fp_context32(sc); /* this might fail */ - unlock_fpu_owner(); + if (is_fpu_owner()) { + err = restore_fp_context32(sc); + unlock_fpu_owner(); + } else { + unlock_fpu_owner(); + err = copy_fp_from_sigcontext32(sc); + } if (likely(!err)) break; /* touch the sigcontext and try again */ -- cgit From 6bbfd65e28c9d72eb140373c7796ce269616f2c0 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 27 Jan 2014 15:23:04 +0000 Subject: MIPS: Replace hardcoded 32 with NUM_FPU_REGS in ptrace NUM_FPU_REGS just makes it clearer what's going on, rather than the magic hard coded 32. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6424/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/signal.c | 4 ++-- arch/mips/kernel/signal32.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index e0178e117f68..0f97c7dc54e6 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -69,7 +69,7 @@ static int copy_fp_to_sigcontext(struct sigcontext __user *sc) int i; int err = 0; - for (i = 0; i < 32; i++) { + for (i = 0; i < NUM_FPU_REGS; i++) { err |= __put_user(get_fpr64(¤t->thread.fpu.fpr[i], 0), &sc->sc_fpregs[i]); @@ -85,7 +85,7 @@ static int copy_fp_from_sigcontext(struct sigcontext __user *sc) int err = 0; u64 fpr_val; - for (i = 0; i < 32; i++) { + for (i = 0; i < NUM_FPU_REGS; i++) { err |= __get_user(fpr_val, &sc->sc_fpregs[i]); set_fpr64(¤t->thread.fpu.fpr[i], 0, fpr_val); } diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index aec58211faaa..bae2e6ee2109 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -84,7 +84,7 @@ static int copy_fp_to_sigcontext32(struct sigcontext32 __user *sc) int err = 0; int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1; - for (i = 0; i < 32; i += inc) { + for (i = 0; i < NUM_FPU_REGS; i += inc) { err |= __put_user(get_fpr64(¤t->thread.fpu.fpr[i], 0), &sc->sc_fpregs[i]); @@ -101,7 +101,7 @@ static int copy_fp_from_sigcontext32(struct sigcontext32 __user *sc) int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1; u64 fpr_val; - for (i = 0; i < 32; i += inc) { + for (i = 0; i < NUM_FPU_REGS; i += inc) { err |= __get_user(fpr_val, &sc->sc_fpregs[i]); set_fpr64(¤t->thread.fpu.fpr[i], 0, fpr_val); } -- cgit From 6cec7c4ad79f8fd66574044adfa284b20ee7c4fd Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 27 Jan 2014 15:23:06 +0000 Subject: MIPS: Don't assume 64-bit FP registers for dump_{,task_}fpu This code assumed that saved FP registers are 64 bits wide, an assumption which will no longer be true once MSA is introduced. This patch modifies the code to copy the lower 64 bits of each register in turn, which is safe for any FP register width >= 64 bits. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6425/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/process.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 6ae540e133b2..2f01f3d48d75 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -157,7 +157,13 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, /* Fill in the fpu structure for a core dump.. */ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r) { - memcpy(r, ¤t->thread.fpu, sizeof(current->thread.fpu)); + int i; + + for (i = 0; i < NUM_FPU_REGS; i++) + memcpy(&r[i], ¤t->thread.fpu.fpr[i], sizeof(*r)); + + memcpy(&r[NUM_FPU_REGS], ¤t->thread.fpu.fcr31, + sizeof(current->thread.fpu.fcr31)); return 1; } @@ -192,7 +198,13 @@ int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs) int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpr) { - memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu)); + int i; + + for (i = 0; i < NUM_FPU_REGS; i++) + memcpy(&fpr[i], &t->thread.fpu.fpr[i], sizeof(*fpr)); + + memcpy(&fpr[NUM_FPU_REGS], &t->thread.fpu.fcr31, + sizeof(t->thread.fpu.fcr31)); return 1; } -- cgit From 72b22bbad1e7cff4645c0f05b4d573ac301d5157 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 27 Jan 2014 15:23:07 +0000 Subject: MIPS: Don't assume 64-bit FP registers for FP regset When we want to access 64-bit FP register values we can only treat consecutive registers as being consecutive in memory when the width of an FP register equals 64 bits. This assumption will not remain true once MSA support is introduced, so provide a code path which copies each 64 bit FP register value in turn when the width of an FP register differs from 64 bits. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6427/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 46 ++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 6 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 7d97709e715f..4137a49eae26 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -304,10 +304,27 @@ static int fpr_get(struct task_struct *target, unsigned int pos, unsigned int count, void *kbuf, void __user *ubuf) { - return user_regset_copyout(&pos, &count, &kbuf, &ubuf, - &target->thread.fpu, - 0, sizeof(elf_fpregset_t)); + unsigned i; + int err; + u64 fpr_val; + /* XXX fcr31 */ + + if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t)) + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &target->thread.fpu, + 0, sizeof(elf_fpregset_t)); + + for (i = 0; i < NUM_FPU_REGS; i++) { + fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0); + err = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &fpr_val, i * sizeof(elf_fpreg_t), + (i + 1) * sizeof(elf_fpreg_t)); + if (err) + return err; + } + + return 0; } static int fpr_set(struct task_struct *target, @@ -315,10 +332,27 @@ static int fpr_set(struct task_struct *target, unsigned int pos, unsigned int count, const void *kbuf, const void __user *ubuf) { - return user_regset_copyin(&pos, &count, &kbuf, &ubuf, - &target->thread.fpu, - 0, sizeof(elf_fpregset_t)); + unsigned i; + int err; + u64 fpr_val; + /* XXX fcr31 */ + + if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t)) + return user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &target->thread.fpu, + 0, sizeof(elf_fpregset_t)); + + for (i = 0; i < NUM_FPU_REGS; i++) { + err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &fpr_val, i * sizeof(elf_fpreg_t), + (i + 1) * sizeof(elf_fpreg_t)); + if (err) + return err; + set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val); + } + + return 0; } enum mips_regset { -- cgit From 02987633df7ba2f62967791dda816eb191d1add3 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 27 Jan 2014 15:23:08 +0000 Subject: MIPS: Don't assume 64-bit FP registers for context switch When saving or restoring scalar FP context we want to access the least significant 64 bits of each FP register. When the FP registers are 64 bits wide that is trivially the start of the registers value in memory. However when the FP registers are wider this equivalence will no longer be true for big endian systems. Define a new set of offset macros for the least significant 64 bits of each saved FP register within thread context, and make use of them when saving and restoring scalar FP context. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6428/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/asm-offsets.c | 66 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 8a2a45d4b147..7ff80622c8d9 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -169,6 +169,72 @@ void output_thread_fpu_defines(void) OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]); OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]); + /* the least significant 64 bits of each FP register */ + OFFSET(THREAD_FPR0_LS64, task_struct, + thread.fpu.fpr[0].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR1_LS64, task_struct, + thread.fpu.fpr[1].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR2_LS64, task_struct, + thread.fpu.fpr[2].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR3_LS64, task_struct, + thread.fpu.fpr[3].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR4_LS64, task_struct, + thread.fpu.fpr[4].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR5_LS64, task_struct, + thread.fpu.fpr[5].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR6_LS64, task_struct, + thread.fpu.fpr[6].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR7_LS64, task_struct, + thread.fpu.fpr[7].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR8_LS64, task_struct, + thread.fpu.fpr[8].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR9_LS64, task_struct, + thread.fpu.fpr[9].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR10_LS64, task_struct, + thread.fpu.fpr[10].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR11_LS64, task_struct, + thread.fpu.fpr[11].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR12_LS64, task_struct, + thread.fpu.fpr[12].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR13_LS64, task_struct, + thread.fpu.fpr[13].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR14_LS64, task_struct, + thread.fpu.fpr[14].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR15_LS64, task_struct, + thread.fpu.fpr[15].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR16_LS64, task_struct, + thread.fpu.fpr[16].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR17_LS64, task_struct, + thread.fpu.fpr[17].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR18_LS64, task_struct, + thread.fpu.fpr[18].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR19_LS64, task_struct, + thread.fpu.fpr[19].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR20_LS64, task_struct, + thread.fpu.fpr[20].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR21_LS64, task_struct, + thread.fpu.fpr[21].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR22_LS64, task_struct, + thread.fpu.fpr[22].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR23_LS64, task_struct, + thread.fpu.fpr[23].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR24_LS64, task_struct, + thread.fpu.fpr[24].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR25_LS64, task_struct, + thread.fpu.fpr[25].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR26_LS64, task_struct, + thread.fpu.fpr[26].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR27_LS64, task_struct, + thread.fpu.fpr[27].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR28_LS64, task_struct, + thread.fpu.fpr[28].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR29_LS64, task_struct, + thread.fpu.fpr[29].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR30_LS64, task_struct, + thread.fpu.fpr[30].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FPR31_LS64, task_struct, + thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]); + OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31); BLANK(); } -- cgit From a5e9a69e2cb64c15246291fdc0e27134b9cdce37 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 27 Jan 2014 15:23:10 +0000 Subject: MIPS: Detect the MSA ASE This patch adds support for probing the MSAP bit within the Config3 register in order to detect the presence of the MSA ASE. Presence of the ASE will be indicated in /proc/cpuinfo. The value of the MSA implementation register will be displayed at boot to aid debugging and verification of a correct setup, as is done for the FPU. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6430/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 22 ++++++++++++++++++++++ arch/mips/kernel/proc.c | 1 + 2 files changed, 23 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index c1ee8b4d2144..420d2fc595d0 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -126,6 +127,20 @@ static inline int __cpu_has_fpu(void) return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE); } +static inline unsigned long cpu_get_msa_id(void) +{ + unsigned long status, conf5, msa_id; + + status = read_c0_status(); + __enable_fpu(FPU_64BIT); + conf5 = read_c0_config5(); + enable_msa(); + msa_id = read_msa_ir(); + write_c0_config5(conf5); + write_c0_status(status); + return msa_id; +} + static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) { #ifdef __NEED_VMBITS_PROBE @@ -301,6 +316,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->ases |= MIPS_ASE_VZ; if (config3 & MIPS_CONF3_SC) c->options |= MIPS_CPU_SEGMENTS; + if (config3 & MIPS_CONF3_MSA) + c->ases |= MIPS_ASE_MSA; return config3 & MIPS_CONF_M; } @@ -1178,6 +1195,9 @@ void cpu_probe(void) else c->srsets = 1; + if (cpu_has_msa) + c->msa_id = cpu_get_msa_id(); + cpu_probe_vmbits(c); #ifdef CONFIG_64BIT @@ -1194,4 +1214,6 @@ void cpu_report(void) smp_processor_id(), c->processor_id, cpu_name_string()); if (c->options & MIPS_CPU_FPU) printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); + if (cpu_has_msa) + pr_info("MSA revision is: %08x\n", c->msa_id); } diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 00d20974b3e7..ca1d48e5d53f 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -95,6 +95,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (cpu_has_mipsmt) seq_printf(m, "%s", " mt"); if (cpu_has_mmips) seq_printf(m, "%s", " micromips"); if (cpu_has_vz) seq_printf(m, "%s", " vz"); + if (cpu_has_msa) seq_printf(m, "%s", " msa"); seq_printf(m, "\n"); if (cpu_has_mmips) { -- cgit From 1db1af84d6df99a8e5d6ddea8c7b5c1327c9a620 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 27 Jan 2014 15:23:11 +0000 Subject: MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/genex.S | 1 + arch/mips/kernel/process.c | 7 ++- arch/mips/kernel/r4k_switch.S | 58 +++++++++++++++++------- arch/mips/kernel/traps.c | 101 +++++++++++++++++++++++++++++++++++++++--- 4 files changed, 143 insertions(+), 24 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index d84f6a509502..278a49bd93b6 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -477,6 +477,7 @@ NESTED(nmi_handler, PT_SIZE, sp) BUILD_HANDLER tr tr sti silent /* #13 */ BUILD_HANDLER fpe fpe fpe silent /* #15 */ BUILD_HANDLER ftlb ftlb none silent /* #16 */ + BUILD_HANDLER msa msa sti silent /* #21 */ BUILD_HANDLER mdmx mdmx sti silent /* #22 */ #ifdef CONFIG_HARDWARE_WATCHPOINTS /* diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 2f01f3d48d75..60e39dc7f1eb 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -65,6 +66,8 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) clear_used_math(); clear_fpu_owner(); init_dsp(); + clear_thread_flag(TIF_MSA_CTX_LIVE); + disable_msa(); regs->cp0_epc = pc; regs->regs[29] = sp; } @@ -89,7 +92,9 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, preempt_disable(); - if (is_fpu_owner()) + if (is_msa_enabled()) + save_msa(p); + else if (is_fpu_owner()) save_fp(p); if (cpu_has_dsp) diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index cc78dd9a17c7..f938ecd22af0 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -28,19 +28,9 @@ */ #define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS) -/* - * FPU context is saved iff the process has used it's FPU in the current - * time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user - * space STATUS register should be 0, so that a process *always* starts its - * userland with FPU disabled after each context switch. - * - * FPU will be enabled as soon as the process accesses FPU again, through - * do_cpu() trap. - */ - /* * task_struct *resume(task_struct *prev, task_struct *next, - * struct thread_info *next_ti, int usedfpu) + * struct thread_info *next_ti, s32 fp_save) */ .align 5 LEAF(resume) @@ -50,23 +40,37 @@ LONG_S ra, THREAD_REG31(a0) /* - * check if we need to save FPU registers + * Check whether we need to save any FP context. FP context is saved + * iff the process has used the context with the scalar FPU or the MSA + * ASE in the current time slice, as indicated by _TIF_USEDFPU and + * _TIF_USEDMSA respectively. switch_to will have set fp_save + * accordingly to an FP_SAVE_ enum value. */ + beqz a3, 2f - beqz a3, 1f - - PTR_L t3, TASK_THREAD_INFO(a0) /* - * clear saved user stack CU1 bit + * We do. Clear the saved CU1 bit for prev, such that next time it is + * scheduled it will start in userland with the FPU disabled. If the + * task uses the FPU then it will be enabled again via the do_cpu trap. + * This allows us to lazily restore the FP context. */ + PTR_L t3, TASK_THREAD_INFO(a0) LONG_L t0, ST_OFF(t3) li t1, ~ST0_CU1 and t0, t0, t1 LONG_S t0, ST_OFF(t3) + /* Check whether we're saving scalar or vector context. */ + bgtz a3, 1f + + /* Save 128b MSA vector context. */ + msa_save_all a0 + b 2f + +1: /* Save 32b/64b scalar FP context. */ fpu_save_double a0 t0 t1 # c0_status passed in t0 # clobbers t1 -1: +2: #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) PTR_LA t8, __stack_chk_guard @@ -141,6 +145,26 @@ LEAF(_restore_fp) jr ra END(_restore_fp) +#ifdef CONFIG_CPU_HAS_MSA + +/* + * Save a thread's MSA vector context. + */ +LEAF(_save_msa) + msa_save_all a0 + jr ra + END(_save_msa) + +/* + * Restore a thread's MSA vector context. + */ +LEAF(_restore_msa) + msa_restore_all a0 + jr ra + END(_restore_msa) + +#endif + /* * Load the FPU with signalling NANS. This bit pattern we're using has * the property that no matter whether considered as single or as double diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index b0c7f80e05e5..4f27cbfad1e5 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include #include @@ -79,6 +80,7 @@ extern asmlinkage void handle_ov(void); extern asmlinkage void handle_tr(void); extern asmlinkage void handle_fpe(void); extern asmlinkage void handle_ftlb(void); +extern asmlinkage void handle_msa(void); extern asmlinkage void handle_mdmx(void); extern asmlinkage void handle_watch(void); extern asmlinkage void handle_mt(void); @@ -1074,6 +1076,76 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action, return NOTIFY_OK; } +static int enable_restore_fp_context(int msa) +{ + int err, was_fpu_owner; + + if (!used_math()) { + /* First time FP context user. */ + err = init_fpu(); + if (msa && !err) + enable_msa(); + if (!err) + set_used_math(); + return err; + } + + /* + * This task has formerly used the FP context. + * + * If this thread has no live MSA vector context then we can simply + * restore the scalar FP context. If it has live MSA vector context + * (that is, it has or may have used MSA since last performing a + * function call) then we'll need to restore the vector context. This + * applies even if we're currently only executing a scalar FP + * instruction. This is because if we were to later execute an MSA + * instruction then we'd either have to: + * + * - Restore the vector context & clobber any registers modified by + * scalar FP instructions between now & then. + * + * or + * + * - Not restore the vector context & lose the most significant bits + * of all vector registers. + * + * Neither of those options is acceptable. We cannot restore the least + * significant bits of the registers now & only restore the most + * significant bits later because the most significant bits of any + * vector registers whose aliased FP register is modified now will have + * been zeroed. We'd have no way to know that when restoring the vector + * context & thus may load an outdated value for the most significant + * bits of a vector register. + */ + if (!msa && !thread_msa_context_live()) + return own_fpu(1); + + /* + * This task is using or has previously used MSA. Thus we require + * that Status.FR == 1. + */ + was_fpu_owner = is_fpu_owner(); + err = own_fpu(0); + if (err) + return err; + + enable_msa(); + write_msa_csr(current->thread.fpu.msacsr); + set_thread_flag(TIF_USEDMSA); + + /* + * If this is the first time that the task is using MSA and it has + * previously used scalar FP in this time slice then we already nave + * FP context which we shouldn't clobber. + */ + if (!test_and_set_thread_flag(TIF_MSA_CTX_LIVE) && was_fpu_owner) + return 0; + + /* We need to restore the vector context. */ + restore_msa(current); + return 0; +} + asmlinkage void do_cpu(struct pt_regs *regs) { enum ctx_state prev_state; @@ -1153,12 +1225,7 @@ asmlinkage void do_cpu(struct pt_regs *regs) /* Fall through. */ case 1: - if (used_math()) /* Using the FPU again. */ - err = own_fpu(1); - else { /* First time FPU user. */ - err = init_fpu(); - set_used_math(); - } + err = enable_restore_fp_context(0); if (!raw_cpu_has_fpu || err) { int sig; @@ -1183,6 +1250,27 @@ out: exception_exit(prev_state); } +asmlinkage void do_msa(struct pt_regs *regs) +{ + enum ctx_state prev_state; + int err; + + prev_state = exception_enter(); + + if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { + force_sig(SIGILL, current); + goto out; + } + + die_if_kernel("do_msa invoked from kernel context!", regs); + + err = enable_restore_fp_context(1); + if (err) + force_sig(SIGILL, current); +out: + exception_exit(prev_state); +} + asmlinkage void do_mdmx(struct pt_regs *regs) { enum ctx_state prev_state; @@ -2041,6 +2129,7 @@ void __init trap_init(void) set_except_vector(15, handle_fpe); set_except_vector(16, handle_ftlb); + set_except_vector(21, handle_msa); set_except_vector(22, handle_mdmx); if (cpu_has_mcheck) -- cgit From 2bcb3fbc3fc593d2ec1efbdeb3e71b9475afe320 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 27 Jan 2014 15:23:12 +0000 Subject: MIPS: Dumb MSA FP exception handler This patch adds a simple handler for MSA FP exceptions which delivers a SIGFPE to the running task. In the future it should probably be extended to re-execute the instruction with the MSACSR.NX bit set in order to generate results for any elements which did not cause an exception before delivering the SIGFPE signal. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6432/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/genex.S | 1 + arch/mips/kernel/traps.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 278a49bd93b6..7365cd6be702 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -475,6 +475,7 @@ NESTED(nmi_handler, PT_SIZE, sp) BUILD_HANDLER cpu cpu sti silent /* #11 */ BUILD_HANDLER ov ov sti silent /* #12 */ BUILD_HANDLER tr tr sti silent /* #13 */ + BUILD_HANDLER msa_fpe msa_fpe sti silent /* #14 */ BUILD_HANDLER fpe fpe fpe silent /* #15 */ BUILD_HANDLER ftlb ftlb none silent /* #16 */ BUILD_HANDLER msa msa sti silent /* #21 */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 4f27cbfad1e5..7ac4d8f44cf0 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -78,6 +78,7 @@ extern asmlinkage void handle_ri_rdhwr(void); extern asmlinkage void handle_cpu(void); extern asmlinkage void handle_ov(void); extern asmlinkage void handle_tr(void); +extern asmlinkage void handle_msa_fpe(void); extern asmlinkage void handle_fpe(void); extern asmlinkage void handle_ftlb(void); extern asmlinkage void handle_msa(void); @@ -1250,6 +1251,16 @@ out: exception_exit(prev_state); } +asmlinkage void do_msa_fpe(struct pt_regs *regs) +{ + enum ctx_state prev_state; + + prev_state = exception_enter(); + die_if_kernel("do_msa_fpe invoked from kernel context!", regs); + force_sig(SIGFPE, current); + exception_exit(prev_state); +} + asmlinkage void do_msa(struct pt_regs *regs) { enum ctx_state prev_state; @@ -2106,6 +2117,7 @@ void __init trap_init(void) set_except_vector(11, handle_cpu); set_except_vector(12, handle_ov); set_except_vector(13, handle_tr); + set_except_vector(14, handle_msa_fpe); if (current_cpu_type() == CPU_R6000 || current_cpu_type() == CPU_R6000A) { -- cgit From a8ad136789b4256fa372d59daaddb91b72aa0753 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 28 Jan 2014 14:28:43 +0000 Subject: MIPS: Warn if vector register partitioning is implemented No current systems implementing MSA include support for vector register partitioning which makes it somewhat difficult to implement support for it in the kernel. Thus for the moment the kernel includes no such support. However if the kernel were to be run on a system which implemented register partitioning then it would not function correctly, mishandling MSA disabled exceptions. Print a warning if run on a system with vector register partitioning implemented to indicate this problem should it occur. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6494/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 420d2fc595d0..dec20f580cea 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1195,8 +1195,11 @@ void cpu_probe(void) else c->srsets = 1; - if (cpu_has_msa) + if (cpu_has_msa) { c->msa_id = cpu_get_msa_id(); + WARN(c->msa_id & MSA_IR_WRPF, + "Vector register partitioning unimplemented!"); + } cpu_probe_vmbits(c); -- cgit From eec43a224cf198c7e3538fca16f689e4d17d4471 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Thu, 13 Feb 2014 11:27:42 +0000 Subject: MIPS: Save/restore MSA context around signals This patch extends sigcontext in order to hold the most significant 64 bits of each vector register in addition to the MSA control & status register. The least significant 64 bits are already saved as the scalar FP context. This makes things a little awkward since the least & most significant 64 bits of each vector register are not contiguous in memory. Thus the copy_u & insert instructions are used to transfer the values of the most significant 64 bits via GP registers. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6533/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/asm-offsets.c | 3 + arch/mips/kernel/r4k_fpu.S | 213 +++++++++++++++++++++++++++++++++++++++++ arch/mips/kernel/signal.c | 73 ++++++++++++-- arch/mips/kernel/signal32.c | 74 ++++++++++++-- 4 files changed, 347 insertions(+), 16 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 7ff80622c8d9..0ea75c244b48 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -295,6 +295,7 @@ void output_sc_defines(void) OFFSET(SC_LO2, sigcontext, sc_lo2); OFFSET(SC_HI3, sigcontext, sc_hi3); OFFSET(SC_LO3, sigcontext, sc_lo3); + OFFSET(SC_MSAREGS, sigcontext, sc_msaregs); BLANK(); } #endif @@ -309,6 +310,7 @@ void output_sc_defines(void) OFFSET(SC_MDLO, sigcontext, sc_mdlo); OFFSET(SC_PC, sigcontext, sc_pc); OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr); + OFFSET(SC_MSAREGS, sigcontext, sc_msaregs); BLANK(); } #endif @@ -320,6 +322,7 @@ void output_sc32_defines(void) OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs); OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr); OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir); + OFFSET(SC32_MSAREGS, sigcontext32, sc_msaregs); BLANK(); } #endif diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S index 253b2fb52026..752b50a69264 100644 --- a/arch/mips/kernel/r4k_fpu.S +++ b/arch/mips/kernel/r4k_fpu.S @@ -13,6 +13,7 @@ * Copyright (C) 1999, 2001 Silicon Graphics, Inc. */ #include +#include #include #include #include @@ -245,6 +246,218 @@ LEAF(_restore_fp_context32) END(_restore_fp_context32) #endif +#ifdef CONFIG_CPU_HAS_MSA + + .macro save_sc_msareg wr, off, sc, tmp +#ifdef CONFIG_64BIT + copy_u_d \tmp, \wr, 1 + EX sd \tmp, (\off+(\wr*8))(\sc) +#elif defined(CONFIG_CPU_LITTLE_ENDIAN) + copy_u_w \tmp, \wr, 2 + EX sw \tmp, (\off+(\wr*8)+0)(\sc) + copy_u_w \tmp, \wr, 3 + EX sw \tmp, (\off+(\wr*8)+4)(\sc) +#else /* CONFIG_CPU_BIG_ENDIAN */ + copy_u_w \tmp, \wr, 2 + EX sw \tmp, (\off+(\wr*8)+4)(\sc) + copy_u_w \tmp, \wr, 3 + EX sw \tmp, (\off+(\wr*8)+0)(\sc) +#endif + .endm + +/* + * int _save_msa_context(struct sigcontext *sc) + * + * Save the upper 64 bits of each vector register along with the MSA_CSR + * register into sc. Returns zero on success, else non-zero. + */ +LEAF(_save_msa_context) + save_sc_msareg 0, SC_MSAREGS, a0, t0 + save_sc_msareg 1, SC_MSAREGS, a0, t0 + save_sc_msareg 2, SC_MSAREGS, a0, t0 + save_sc_msareg 3, SC_MSAREGS, a0, t0 + save_sc_msareg 4, SC_MSAREGS, a0, t0 + save_sc_msareg 5, SC_MSAREGS, a0, t0 + save_sc_msareg 6, SC_MSAREGS, a0, t0 + save_sc_msareg 7, SC_MSAREGS, a0, t0 + save_sc_msareg 8, SC_MSAREGS, a0, t0 + save_sc_msareg 9, SC_MSAREGS, a0, t0 + save_sc_msareg 10, SC_MSAREGS, a0, t0 + save_sc_msareg 11, SC_MSAREGS, a0, t0 + save_sc_msareg 12, SC_MSAREGS, a0, t0 + save_sc_msareg 13, SC_MSAREGS, a0, t0 + save_sc_msareg 14, SC_MSAREGS, a0, t0 + save_sc_msareg 15, SC_MSAREGS, a0, t0 + save_sc_msareg 16, SC_MSAREGS, a0, t0 + save_sc_msareg 17, SC_MSAREGS, a0, t0 + save_sc_msareg 18, SC_MSAREGS, a0, t0 + save_sc_msareg 19, SC_MSAREGS, a0, t0 + save_sc_msareg 20, SC_MSAREGS, a0, t0 + save_sc_msareg 21, SC_MSAREGS, a0, t0 + save_sc_msareg 22, SC_MSAREGS, a0, t0 + save_sc_msareg 23, SC_MSAREGS, a0, t0 + save_sc_msareg 24, SC_MSAREGS, a0, t0 + save_sc_msareg 25, SC_MSAREGS, a0, t0 + save_sc_msareg 26, SC_MSAREGS, a0, t0 + save_sc_msareg 27, SC_MSAREGS, a0, t0 + save_sc_msareg 28, SC_MSAREGS, a0, t0 + save_sc_msareg 29, SC_MSAREGS, a0, t0 + save_sc_msareg 30, SC_MSAREGS, a0, t0 + save_sc_msareg 31, SC_MSAREGS, a0, t0 + jr ra + li v0, 0 + END(_save_msa_context) + +#ifdef CONFIG_MIPS32_COMPAT + +/* + * int _save_msa_context32(struct sigcontext32 *sc) + * + * Save the upper 64 bits of each vector register along with the MSA_CSR + * register into sc. Returns zero on success, else non-zero. + */ +LEAF(_save_msa_context32) + save_sc_msareg 0, SC32_MSAREGS, a0, t0 + save_sc_msareg 1, SC32_MSAREGS, a0, t0 + save_sc_msareg 2, SC32_MSAREGS, a0, t0 + save_sc_msareg 3, SC32_MSAREGS, a0, t0 + save_sc_msareg 4, SC32_MSAREGS, a0, t0 + save_sc_msareg 5, SC32_MSAREGS, a0, t0 + save_sc_msareg 6, SC32_MSAREGS, a0, t0 + save_sc_msareg 7, SC32_MSAREGS, a0, t0 + save_sc_msareg 8, SC32_MSAREGS, a0, t0 + save_sc_msareg 9, SC32_MSAREGS, a0, t0 + save_sc_msareg 10, SC32_MSAREGS, a0, t0 + save_sc_msareg 11, SC32_MSAREGS, a0, t0 + save_sc_msareg 12, SC32_MSAREGS, a0, t0 + save_sc_msareg 13, SC32_MSAREGS, a0, t0 + save_sc_msareg 14, SC32_MSAREGS, a0, t0 + save_sc_msareg 15, SC32_MSAREGS, a0, t0 + save_sc_msareg 16, SC32_MSAREGS, a0, t0 + save_sc_msareg 17, SC32_MSAREGS, a0, t0 + save_sc_msareg 18, SC32_MSAREGS, a0, t0 + save_sc_msareg 19, SC32_MSAREGS, a0, t0 + save_sc_msareg 20, SC32_MSAREGS, a0, t0 + save_sc_msareg 21, SC32_MSAREGS, a0, t0 + save_sc_msareg 22, SC32_MSAREGS, a0, t0 + save_sc_msareg 23, SC32_MSAREGS, a0, t0 + save_sc_msareg 24, SC32_MSAREGS, a0, t0 + save_sc_msareg 25, SC32_MSAREGS, a0, t0 + save_sc_msareg 26, SC32_MSAREGS, a0, t0 + save_sc_msareg 27, SC32_MSAREGS, a0, t0 + save_sc_msareg 28, SC32_MSAREGS, a0, t0 + save_sc_msareg 29, SC32_MSAREGS, a0, t0 + save_sc_msareg 30, SC32_MSAREGS, a0, t0 + save_sc_msareg 31, SC32_MSAREGS, a0, t0 + jr ra + li v0, 0 + END(_save_msa_context32) + +#endif /* CONFIG_MIPS32_COMPAT */ + + .macro restore_sc_msareg wr, off, sc, tmp +#ifdef CONFIG_64BIT + EX ld \tmp, (\off+(\wr*8))(\sc) + insert_d \wr, 1, \tmp +#elif defined(CONFIG_CPU_LITTLE_ENDIAN) + EX lw \tmp, (\off+(\wr*8)+0)(\sc) + insert_w \wr, 2, \tmp + EX lw \tmp, (\off+(\wr*8)+4)(\sc) + insert_w \wr, 3, \tmp +#else /* CONFIG_CPU_BIG_ENDIAN */ + EX lw \tmp, (\off+(\wr*8)+4)(\sc) + insert_w \wr, 2, \tmp + EX lw \tmp, (\off+(\wr*8)+0)(\sc) + insert_w \wr, 3, \tmp +#endif + .endm + +/* + * int _restore_msa_context(struct sigcontext *sc) + */ +LEAF(_restore_msa_context) + restore_sc_msareg 0, SC_MSAREGS, a0, t0 + restore_sc_msareg 1, SC_MSAREGS, a0, t0 + restore_sc_msareg 2, SC_MSAREGS, a0, t0 + restore_sc_msareg 3, SC_MSAREGS, a0, t0 + restore_sc_msareg 4, SC_MSAREGS, a0, t0 + restore_sc_msareg 5, SC_MSAREGS, a0, t0 + restore_sc_msareg 6, SC_MSAREGS, a0, t0 + restore_sc_msareg 7, SC_MSAREGS, a0, t0 + restore_sc_msareg 8, SC_MSAREGS, a0, t0 + restore_sc_msareg 9, SC_MSAREGS, a0, t0 + restore_sc_msareg 10, SC_MSAREGS, a0, t0 + restore_sc_msareg 11, SC_MSAREGS, a0, t0 + restore_sc_msareg 12, SC_MSAREGS, a0, t0 + restore_sc_msareg 13, SC_MSAREGS, a0, t0 + restore_sc_msareg 14, SC_MSAREGS, a0, t0 + restore_sc_msareg 15, SC_MSAREGS, a0, t0 + restore_sc_msareg 16, SC_MSAREGS, a0, t0 + restore_sc_msareg 17, SC_MSAREGS, a0, t0 + restore_sc_msareg 18, SC_MSAREGS, a0, t0 + restore_sc_msareg 19, SC_MSAREGS, a0, t0 + restore_sc_msareg 20, SC_MSAREGS, a0, t0 + restore_sc_msareg 21, SC_MSAREGS, a0, t0 + restore_sc_msareg 22, SC_MSAREGS, a0, t0 + restore_sc_msareg 23, SC_MSAREGS, a0, t0 + restore_sc_msareg 24, SC_MSAREGS, a0, t0 + restore_sc_msareg 25, SC_MSAREGS, a0, t0 + restore_sc_msareg 26, SC_MSAREGS, a0, t0 + restore_sc_msareg 27, SC_MSAREGS, a0, t0 + restore_sc_msareg 28, SC_MSAREGS, a0, t0 + restore_sc_msareg 29, SC_MSAREGS, a0, t0 + restore_sc_msareg 30, SC_MSAREGS, a0, t0 + restore_sc_msareg 31, SC_MSAREGS, a0, t0 + jr ra + li v0, 0 + END(_restore_msa_context) + +#ifdef CONFIG_MIPS32_COMPAT + +/* + * int _restore_msa_context32(struct sigcontext32 *sc) + */ +LEAF(_restore_msa_context32) + restore_sc_msareg 0, SC32_MSAREGS, a0, t0 + restore_sc_msareg 1, SC32_MSAREGS, a0, t0 + restore_sc_msareg 2, SC32_MSAREGS, a0, t0 + restore_sc_msareg 3, SC32_MSAREGS, a0, t0 + restore_sc_msareg 4, SC32_MSAREGS, a0, t0 + restore_sc_msareg 5, SC32_MSAREGS, a0, t0 + restore_sc_msareg 6, SC32_MSAREGS, a0, t0 + restore_sc_msareg 7, SC32_MSAREGS, a0, t0 + restore_sc_msareg 8, SC32_MSAREGS, a0, t0 + restore_sc_msareg 9, SC32_MSAREGS, a0, t0 + restore_sc_msareg 10, SC32_MSAREGS, a0, t0 + restore_sc_msareg 11, SC32_MSAREGS, a0, t0 + restore_sc_msareg 12, SC32_MSAREGS, a0, t0 + restore_sc_msareg 13, SC32_MSAREGS, a0, t0 + restore_sc_msareg 14, SC32_MSAREGS, a0, t0 + restore_sc_msareg 15, SC32_MSAREGS, a0, t0 + restore_sc_msareg 16, SC32_MSAREGS, a0, t0 + restore_sc_msareg 17, SC32_MSAREGS, a0, t0 + restore_sc_msareg 18, SC32_MSAREGS, a0, t0 + restore_sc_msareg 19, SC32_MSAREGS, a0, t0 + restore_sc_msareg 20, SC32_MSAREGS, a0, t0 + restore_sc_msareg 21, SC32_MSAREGS, a0, t0 + restore_sc_msareg 22, SC32_MSAREGS, a0, t0 + restore_sc_msareg 23, SC32_MSAREGS, a0, t0 + restore_sc_msareg 24, SC32_MSAREGS, a0, t0 + restore_sc_msareg 25, SC32_MSAREGS, a0, t0 + restore_sc_msareg 26, SC32_MSAREGS, a0, t0 + restore_sc_msareg 27, SC32_MSAREGS, a0, t0 + restore_sc_msareg 28, SC32_MSAREGS, a0, t0 + restore_sc_msareg 29, SC32_MSAREGS, a0, t0 + restore_sc_msareg 30, SC32_MSAREGS, a0, t0 + restore_sc_msareg 31, SC32_MSAREGS, a0, t0 + jr ra + li v0, 0 + END(_restore_msa_context32) + +#endif /* CONFIG_MIPS32_COMPAT */ + +#endif /* CONFIG_CPU_HAS_MSA */ + .set reorder .type fault@function diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 0f97c7dc54e6..fd61700409bc 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -46,6 +47,9 @@ static int (*restore_fp_context)(struct sigcontext __user *sc); extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); +extern asmlinkage int _save_msa_context(struct sigcontext __user *sc); +extern asmlinkage int _restore_msa_context(struct sigcontext __user *sc); + struct sigframe { u32 sf_ass[4]; /* argument save space for o32 */ u32 sf_pad[2]; /* Was: signal trampoline */ @@ -94,20 +98,60 @@ static int copy_fp_from_sigcontext(struct sigcontext __user *sc) return err; } +/* + * These functions will save only the upper 64 bits of the vector registers, + * since the lower 64 bits have already been saved as the scalar FP context. + */ +static int copy_msa_to_sigcontext(struct sigcontext __user *sc) +{ + int i; + int err = 0; + + for (i = 0; i < NUM_FPU_REGS; i++) { + err |= + __put_user(get_fpr64(¤t->thread.fpu.fpr[i], 1), + &sc->sc_msaregs[i]); + } + err |= __put_user(current->thread.fpu.msacsr, &sc->sc_msa_csr); + + return err; +} + +static int copy_msa_from_sigcontext(struct sigcontext __user *sc) +{ + int i; + int err = 0; + u64 val; + + for (i = 0; i < NUM_FPU_REGS; i++) { + err |= __get_user(val, &sc->sc_msaregs[i]); + set_fpr64(¤t->thread.fpu.fpr[i], 1, val); + } + err |= __get_user(current->thread.fpu.msacsr, &sc->sc_msa_csr); + + return err; +} + /* * Helper routines */ -static int protected_save_fp_context(struct sigcontext __user *sc) +static int protected_save_fp_context(struct sigcontext __user *sc, + unsigned used_math) { int err; + bool save_msa = cpu_has_msa && (used_math & USEDMATH_MSA); while (1) { lock_fpu_owner(); if (is_fpu_owner()) { err = save_fp_context(sc); + if (save_msa && !err) + err = _save_msa_context(sc); unlock_fpu_owner(); } else { unlock_fpu_owner(); err = copy_fp_to_sigcontext(sc); + if (save_msa && !err) + err = copy_msa_to_sigcontext(sc); } if (likely(!err)) break; @@ -121,17 +165,28 @@ static int protected_save_fp_context(struct sigcontext __user *sc) return err; } -static int protected_restore_fp_context(struct sigcontext __user *sc) +static int protected_restore_fp_context(struct sigcontext __user *sc, + unsigned used_math) { int err, tmp __maybe_unused; + bool restore_msa = cpu_has_msa && (used_math & USEDMATH_MSA); while (1) { lock_fpu_owner(); if (is_fpu_owner()) { err = restore_fp_context(sc); + if (restore_msa && !err) { + enable_msa(); + err = _restore_msa_context(sc); + } else { + /* signal handler may have used MSA */ + disable_msa(); + } unlock_fpu_owner(); } else { unlock_fpu_owner(); err = copy_fp_from_sigcontext(sc); + if (!err && (used_math & USEDMATH_MSA)) + err = copy_msa_from_sigcontext(sc); } if (likely(!err)) break; @@ -172,7 +227,8 @@ int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp); } - used_math = !!used_math(); + used_math = used_math() ? USEDMATH_FP : 0; + used_math |= thread_msa_context_live() ? USEDMATH_MSA : 0; err |= __put_user(used_math, &sc->sc_used_math); if (used_math) { @@ -180,7 +236,7 @@ int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ - err |= protected_save_fp_context(sc); + err |= protected_save_fp_context(sc, used_math); } return err; } @@ -205,14 +261,14 @@ int fpcsr_pending(unsigned int __user *fpcsr) } static int -check_and_restore_fp_context(struct sigcontext __user *sc) +check_and_restore_fp_context(struct sigcontext __user *sc, unsigned used_math) { int err, sig; err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; - err |= protected_restore_fp_context(sc); + err |= protected_restore_fp_context(sc, used_math); return err ?: sig; } @@ -252,9 +308,10 @@ int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) if (used_math) { /* restore fpu context if we have used it before */ if (!err) - err = check_and_restore_fp_context(sc); + err = check_and_restore_fp_context(sc, used_math); } else { - /* signal handler may have used FPU. Give it up. */ + /* signal handler may have used FPU or MSA. Disable them. */ + disable_msa(); lose_fpu(0); } diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index bae2e6ee2109..299f956e4db3 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -42,6 +43,9 @@ static int (*restore_fp_context32)(struct sigcontext32 __user *sc); extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); +extern asmlinkage int _save_msa_context32(struct sigcontext32 __user *sc); +extern asmlinkage int _restore_msa_context32(struct sigcontext32 __user *sc); + /* * Including would give use the 64-bit syscall numbers ... */ @@ -110,20 +114,60 @@ static int copy_fp_from_sigcontext32(struct sigcontext32 __user *sc) return err; } +/* + * These functions will save only the upper 64 bits of the vector registers, + * since the lower 64 bits have already been saved as the scalar FP context. + */ +static int copy_msa_to_sigcontext32(struct sigcontext32 __user *sc) +{ + int i; + int err = 0; + + for (i = 0; i < NUM_FPU_REGS; i++) { + err |= + __put_user(get_fpr64(¤t->thread.fpu.fpr[i], 1), + &sc->sc_msaregs[i]); + } + err |= __put_user(current->thread.fpu.msacsr, &sc->sc_msa_csr); + + return err; +} + +static int copy_msa_from_sigcontext32(struct sigcontext32 __user *sc) +{ + int i; + int err = 0; + u64 val; + + for (i = 0; i < NUM_FPU_REGS; i++) { + err |= __get_user(val, &sc->sc_msaregs[i]); + set_fpr64(¤t->thread.fpu.fpr[i], 1, val); + } + err |= __get_user(current->thread.fpu.msacsr, &sc->sc_msa_csr); + + return err; +} + /* * sigcontext handlers */ -static int protected_save_fp_context32(struct sigcontext32 __user *sc) +static int protected_save_fp_context32(struct sigcontext32 __user *sc, + unsigned used_math) { int err; + bool save_msa = cpu_has_msa && (used_math & USEDMATH_MSA); while (1) { lock_fpu_owner(); if (is_fpu_owner()) { err = save_fp_context32(sc); + if (save_msa && !err) + err = _save_msa_context32(sc); unlock_fpu_owner(); } else { unlock_fpu_owner(); err = copy_fp_to_sigcontext32(sc); + if (save_msa && !err) + err = copy_msa_to_sigcontext32(sc); } if (likely(!err)) break; @@ -137,17 +181,28 @@ static int protected_save_fp_context32(struct sigcontext32 __user *sc) return err; } -static int protected_restore_fp_context32(struct sigcontext32 __user *sc) +static int protected_restore_fp_context32(struct sigcontext32 __user *sc, + unsigned used_math) { int err, tmp __maybe_unused; + bool restore_msa = cpu_has_msa && (used_math & USEDMATH_MSA); while (1) { lock_fpu_owner(); if (is_fpu_owner()) { err = restore_fp_context32(sc); + if (restore_msa && !err) { + enable_msa(); + err = _restore_msa_context32(sc); + } else { + /* signal handler may have used MSA */ + disable_msa(); + } unlock_fpu_owner(); } else { unlock_fpu_owner(); err = copy_fp_from_sigcontext32(sc); + if (restore_msa && !err) + err = copy_msa_from_sigcontext32(sc); } if (likely(!err)) break; @@ -186,7 +241,8 @@ static int setup_sigcontext32(struct pt_regs *regs, err |= __put_user(mflo3(), &sc->sc_lo3); } - used_math = !!used_math(); + used_math = used_math() ? USEDMATH_FP : 0; + used_math |= thread_msa_context_live() ? USEDMATH_MSA : 0; err |= __put_user(used_math, &sc->sc_used_math); if (used_math) { @@ -194,20 +250,21 @@ static int setup_sigcontext32(struct pt_regs *regs, * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ - err |= protected_save_fp_context32(sc); + err |= protected_save_fp_context32(sc, used_math); } return err; } static int -check_and_restore_fp_context32(struct sigcontext32 __user *sc) +check_and_restore_fp_context32(struct sigcontext32 __user *sc, + unsigned used_math) { int err, sig; err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; - err |= protected_restore_fp_context32(sc); + err |= protected_restore_fp_context32(sc, used_math); return err ?: sig; } @@ -244,9 +301,10 @@ static int restore_sigcontext32(struct pt_regs *regs, if (used_math) { /* restore fpu context if we have used it before */ if (!err) - err = check_and_restore_fp_context32(sc); + err = check_and_restore_fp_context32(sc, used_math); } else { - /* signal handler may have used FPU. Give it up. */ + /* signal handler may have used FPU or MSA. Disable them. */ + disable_msa(); lose_fpu(0); } -- cgit From aced4cbd6e3da7dd71f19d0378d27aa74f76e70b Mon Sep 17 00:00:00 2001 From: James Hogan Date: Wed, 22 Jan 2014 16:19:38 +0000 Subject: MIPS: Add cases for CPU_P5600 Add a CPU_P5600 case to various switch statements, doing the same thing as for CPU_PROAPTIV. Signed-off-by: James Hogan Reviewed-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6408/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/idle.c | 1 + arch/mips/kernel/spram.c | 1 + arch/mips/kernel/traps.c | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index c1fd0bc7a315..04ea1c7a3d31 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -187,6 +187,7 @@ void __init check_wait(void) case CPU_1074K: case CPU_INTERAPTIV: case CPU_PROAPTIV: + case CPU_P5600: cpu_wait = r4k_wait; if (read_c0_config7() & MIPS_CONF7_WII) cpu_wait = r4k_wait_irqoff; diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index 707d957e6a66..f9a693a6aaa7 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c @@ -208,6 +208,7 @@ void spram_config(void) case CPU_1074K: case CPU_INTERAPTIV: case CPU_PROAPTIV: + case CPU_P5600: config0 = read_c0_config(); /* FIXME: addresses are Malta specific */ if (config0 & (1<<24)) { diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 7ac4d8f44cf0..ee1f2fc584ea 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1439,6 +1439,7 @@ static inline void parity_protection_init(void) case CPU_1074K: case CPU_INTERAPTIV: case CPU_PROAPTIV: + case CPU_P5600: { #define ERRCTL_PE 0x80000000 #define ERRCTL_L2P 0x00800000 -- cgit From 829dcc0a956a2317631873d946b5a5c2b0bf53ee Mon Sep 17 00:00:00 2001 From: James Hogan Date: Wed, 22 Jan 2014 16:19:39 +0000 Subject: MIPS: Add MIPS P5600 probe support Add a case in cpu_probe_mips for the MIPS P5600 processor ID, which sets the CPU type to the new CPU_P5600. Signed-off-by: James Hogan Reviewed-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6409/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index dec20f580cea..0b9bbcb64afd 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -844,6 +844,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_PROAPTIV; __cpu_name[cpu] = "MIPS proAptiv (multi)"; break; + case PRID_IMP_P5600: + c->cputype = CPU_P5600; + __cpu_name[cpu] = "MIPS P5600"; + break; } decode_configs(c); -- cgit From d83b0e82ad055920fb7f05f85b9466d97b7182db Mon Sep 17 00:00:00 2001 From: James Hogan Date: Wed, 22 Jan 2014 16:19:40 +0000 Subject: MIPS: Allow FTLB to be turned on for CPU_P5600 Allow FTLB to be turned on or off for CPU_P5600 as well as CPU_PROAPTIV. The existing if statement is converted into a switch to allow for future expansion. Signed-off-by: James Hogan Reviewed-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6411/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 0b9bbcb64afd..ee5de360636d 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -181,11 +181,12 @@ static char unknown_isa[] = KERN_ERR \ static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) { unsigned int config6; - /* - * Config6 is implementation dependent and it's currently only - * used by proAptiv - */ - if (c->cputype == CPU_PROAPTIV) { + + /* It's implementation dependent how the FTLB can be enabled */ + switch (c->cputype) { + case CPU_PROAPTIV: + case CPU_P5600: + /* proAptiv & related cores use Config6 to enable the FTLB */ config6 = read_c0_config6(); if (enable) /* Enable FTLB */ @@ -194,6 +195,7 @@ static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) /* Disable FTLB */ write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); back_to_back_c0_hazard(); + break; } } -- cgit From 86bdb2779d67773edcfddfca4d6a4ae055e21964 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Wed, 4 Dec 2013 14:35:28 +0000 Subject: MIPS: kernel: scall32-o32: Use EVA wrappers to fetch syscall arguments Arguments 4-8 are stored on user's stack, so use the EVA instructions to fetch them if EVA is enabled. Signed-off-by: Markos Chandras --- arch/mips/kernel/scall32-o32.S | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index ffe89139e0f9..fdc70b400442 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -6,6 +6,7 @@ * Copyright (C) 1995-99, 2000- 02, 06 Ralf Baechle * Copyright (C) 2001 MIPS Technologies, Inc. * Copyright (C) 2004 Thiemo Seufer + * Copyright (C) 2014 Imagination Technologies Ltd. */ #include #include @@ -74,10 +75,10 @@ NESTED(handle_sys, PT_SIZE, sp) .set noreorder .set nomacro -1: lw t5, 16(t0) # argument #5 from usp -4: lw t6, 20(t0) # argument #6 from usp -3: lw t7, 24(t0) # argument #7 from usp -2: lw t8, 28(t0) # argument #8 from usp +1: user_lw(t5, 16(t0)) # argument #5 from usp +4: user_lw(t6, 20(t0)) # argument #6 from usp +3: user_lw(t7, 24(t0)) # argument #7 from usp +2: user_lw(t8, 28(t0)) # argument #8 from usp sw t5, 16(sp) # argument #5 to ksp sw t6, 20(sp) # argument #6 to ksp -- cgit From b08a9c95f80f2f760f62d70fcd5a869c425d17b6 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Wed, 4 Dec 2013 16:20:08 +0000 Subject: MIPS: kernel: traps: Whitespace clean up Signed-off-by: Markos Chandras --- arch/mips/kernel/traps.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ee1f2fc584ea..1a76d114e84b 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -10,6 +10,7 @@ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2014, Imagination Technologies Ltd. */ #include #include @@ -873,17 +874,19 @@ asmlinkage void do_bp(struct pt_regs *regs) if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) || (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))) goto out_sigsegv; - opcode = (instr[0] << 16) | instr[1]; + opcode = (instr[0] << 16) | instr[1]; } else { - /* MIPS16e mode */ - if (__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc))) + /* MIPS16e mode */ + if (__get_user(instr[0], + (u16 __user *)msk_isa16_mode(epc))) goto out_sigsegv; - bcode = (instr[0] >> 6) & 0x3f; - do_trap_or_bp(regs, bcode, "Break"); - goto out; + bcode = (instr[0] >> 6) & 0x3f; + do_trap_or_bp(regs, bcode, "Break"); + goto out; } } else { - if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) + if (__get_user(opcode, + (unsigned int __user *) exception_epc(regs))) goto out_sigsegv; } -- cgit From 078dde5e21dba9f4186ebfc2aef06341fd20efb4 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Wed, 4 Dec 2013 16:39:34 +0000 Subject: MIPS: traps: Set correct address limit for breakpoints and traps When a breakpoint or trap happens when operating in kernel mode but on users behalf (eg syscall) it is necessary to change the address limit to KERNEL_DS so any address checking can be bypassed and print the correct stack trace. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras --- arch/mips/kernel/traps.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 1a76d114e84b..074e857ced28 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -865,6 +865,11 @@ asmlinkage void do_bp(struct pt_regs *regs) enum ctx_state prev_state; unsigned long epc; u16 instr[2]; + mm_segment_t seg; + + seg = get_fs(); + if (!user_mode(regs)) + set_fs(KERNEL_DS); prev_state = exception_enter(); if (get_isa16_mode(regs->cp0_epc)) { @@ -924,6 +929,7 @@ asmlinkage void do_bp(struct pt_regs *regs) do_trap_or_bp(regs, bcode, "Break"); out: + set_fs(seg); exception_exit(prev_state); return; @@ -937,8 +943,13 @@ asmlinkage void do_tr(struct pt_regs *regs) u32 opcode, tcode = 0; enum ctx_state prev_state; u16 instr[2]; + mm_segment_t seg; unsigned long epc = msk_isa16_mode(exception_epc(regs)); + seg = get_fs(); + if (!user_mode(regs)) + set_fs(get_ds()); + prev_state = exception_enter(); if (get_isa16_mode(regs->cp0_epc)) { if (__get_user(instr[0], (u16 __user *)(epc + 0)) || @@ -959,6 +970,7 @@ asmlinkage void do_tr(struct pt_regs *regs) do_trap_or_bp(regs, tcode, "Trap"); out: + set_fs(seg); exception_exit(prev_state); return; -- cgit From 4968db4b9c4528b097ab4e549c4e0d0420dd1efc Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Mon, 9 Dec 2013 15:28:10 +0000 Subject: MIPS: lib: strnlen_user: Add EVA support In non-EVA mode, a strlen_user* alias is used for the strlen_kernel* symbols since the code is identical. In EVA mode, a new strlen_user* symbol is used which uses the EVA specific instructions to load values from userspace. Signed-off-by: Markos Chandras --- arch/mips/kernel/mips_ksyms.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c index 6e58e97fcd39..a322db072c3c 100644 --- a/arch/mips/kernel/mips_ksyms.c +++ b/arch/mips/kernel/mips_ksyms.c @@ -22,6 +22,8 @@ extern long __strncpy_from_user_asm(char *__to, const char *__from, long __len); extern long __strlen_user_nocheck_asm(const char *s); extern long __strlen_user_asm(const char *s); +extern long __strnlen_kernel_nocheck_asm(const char *s); +extern long __strnlen_kernel_asm(const char *s); extern long __strnlen_user_nocheck_asm(const char *s); extern long __strnlen_user_asm(const char *s); @@ -48,6 +50,8 @@ EXPORT_SYMBOL(__strncpy_from_user_nocheck_asm); EXPORT_SYMBOL(__strncpy_from_user_asm); EXPORT_SYMBOL(__strlen_user_nocheck_asm); EXPORT_SYMBOL(__strlen_user_asm); +EXPORT_SYMBOL(__strnlen_kernel_nocheck_asm); +EXPORT_SYMBOL(__strnlen_kernel_asm); EXPORT_SYMBOL(__strnlen_user_nocheck_asm); EXPORT_SYMBOL(__strnlen_user_asm); -- cgit From 053970542f049d3e30dc4be6eb19e92ff1f70f00 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Thu, 2 Jan 2014 16:04:38 +0000 Subject: MIPS: lib: strlen_user: Add EVA support In non-EVA mode, strlen_user* aliases are used for the strlen_kernel* symbols since the code is identical. In EVA mode, new strlen_user* symbols are used which use the EVA specific instructions to load values from userspace. Signed-off-by: Markos Chandras --- arch/mips/kernel/mips_ksyms.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c index a322db072c3c..742ed7d790a0 100644 --- a/arch/mips/kernel/mips_ksyms.c +++ b/arch/mips/kernel/mips_ksyms.c @@ -20,6 +20,8 @@ extern long __strncpy_from_user_nocheck_asm(char *__to, const char *__from, long __len); extern long __strncpy_from_user_asm(char *__to, const char *__from, long __len); +extern long __strlen_kernel_nocheck_asm(const char *s); +extern long __strlen_kernel_asm(const char *s); extern long __strlen_user_nocheck_asm(const char *s); extern long __strlen_user_asm(const char *s); extern long __strnlen_kernel_nocheck_asm(const char *s); @@ -48,6 +50,8 @@ EXPORT_SYMBOL(__copy_user_inatomic); EXPORT_SYMBOL(__bzero); EXPORT_SYMBOL(__strncpy_from_user_nocheck_asm); EXPORT_SYMBOL(__strncpy_from_user_asm); +EXPORT_SYMBOL(__strlen_kernel_nocheck_asm); +EXPORT_SYMBOL(__strlen_kernel_asm); EXPORT_SYMBOL(__strlen_user_nocheck_asm); EXPORT_SYMBOL(__strlen_user_asm); EXPORT_SYMBOL(__strnlen_kernel_nocheck_asm); -- cgit From b3c3025b2c5536c2b243f4947cffe58628758020 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Thu, 2 Jan 2014 16:40:20 +0000 Subject: MIPS: lib: strncpy_user: Add EVA support In non-EVA mode, strncpy_from_user* aliases are used for the strncpy_from_kernel* symbols since the code is identical. In EVA mode, new strcpy_from_user* symbols are used which use the EVA specific instructions to load values from userspace. Signed-off-by: Markos Chandras --- arch/mips/kernel/mips_ksyms.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c index 742ed7d790a0..675bd0578d3f 100644 --- a/arch/mips/kernel/mips_ksyms.c +++ b/arch/mips/kernel/mips_ksyms.c @@ -16,6 +16,10 @@ #include extern void *__bzero(void *__s, size_t __count); +extern long __strncpy_from_kernel_nocheck_asm(char *__to, + const char *__from, long __len); +extern long __strncpy_from_kernel_asm(char *__to, const char *__from, + long __len); extern long __strncpy_from_user_nocheck_asm(char *__to, const char *__from, long __len); extern long __strncpy_from_user_asm(char *__to, const char *__from, @@ -48,6 +52,8 @@ EXPORT_SYMBOL(copy_page); EXPORT_SYMBOL(__copy_user); EXPORT_SYMBOL(__copy_user_inatomic); EXPORT_SYMBOL(__bzero); +EXPORT_SYMBOL(__strncpy_from_kernel_nocheck_asm); +EXPORT_SYMBOL(__strncpy_from_kernel_asm); EXPORT_SYMBOL(__strncpy_from_user_nocheck_asm); EXPORT_SYMBOL(__strncpy_from_user_asm); EXPORT_SYMBOL(__strlen_kernel_nocheck_asm); -- cgit From cd26cb41ece49ce0dd0f43d88f4d3386ca42a825 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Tue, 7 Jan 2014 16:20:22 +0000 Subject: MIPS: lib: memcpy: Add EVA support Add copy_{to,from,in}_user when the CPU operates in EVA mode. This is necessary so the EVA specific instructions can be used to perform the virtual to physical translation for user space addresses. We will use the non-EVA functions to read from kernel if needed. Signed-off-by: Markos Chandras --- arch/mips/kernel/mips_ksyms.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c index 675bd0578d3f..13e60f676b8b 100644 --- a/arch/mips/kernel/mips_ksyms.c +++ b/arch/mips/kernel/mips_ksyms.c @@ -51,6 +51,12 @@ EXPORT_SYMBOL(copy_page); */ EXPORT_SYMBOL(__copy_user); EXPORT_SYMBOL(__copy_user_inatomic); +#ifdef CONFIG_EVA +EXPORT_SYMBOL(__copy_from_user_eva); +EXPORT_SYMBOL(__copy_in_user_eva); +EXPORT_SYMBOL(__copy_to_user_eva); +EXPORT_SYMBOL(__copy_user_inatomic_eva); +#endif EXPORT_SYMBOL(__bzero); EXPORT_SYMBOL(__strncpy_from_kernel_nocheck_asm); EXPORT_SYMBOL(__strncpy_from_kernel_asm); -- cgit From 9d8e573683ca85e2bd3cade8b5c42e195e6390ad Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Thu, 19 Dec 2013 16:41:05 +0000 Subject: MIPS: kernel: unaligned: Add EVA instruction wrappers Use the load/store instruction wrappers from asm/asm.h to perform such operations when operating in EVA mode. Signed-off-by: Markos Chandras --- arch/mips/kernel/unaligned.c | 49 ++++++++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 24 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index c369a5d35527..5ec8f00b51b5 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -7,6 +7,7 @@ * * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2014 Imagination Technologies Ltd. * * This file contains exception handler for address error exception with the * special capability to execute faulting instructions in software. The @@ -110,8 +111,8 @@ extern void show_registers(struct pt_regs *regs); #ifdef __BIG_ENDIAN #define LoadHW(addr, value, res) \ __asm__ __volatile__ (".set\tnoat\n" \ - "1:\tlb\t%0, 0(%2)\n" \ - "2:\tlbu\t$1, 1(%2)\n\t" \ + "1:\t"user_lb("%0", "0(%2)")"\n" \ + "2:\t"user_lbu("$1", "1(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ @@ -130,8 +131,8 @@ extern void show_registers(struct pt_regs *regs); #define LoadW(addr, value, res) \ __asm__ __volatile__ ( \ - "1:\tlwl\t%0, (%2)\n" \ - "2:\tlwr\t%0, 3(%2)\n\t" \ + "1:\t"user_lwl("%0", "(%2)")"\n" \ + "2:\t"user_lwr("%0", "3(%2)")"\n\t" \ "li\t%1, 0\n" \ "3:\n\t" \ ".insn\n\t" \ @@ -149,8 +150,8 @@ extern void show_registers(struct pt_regs *regs); #define LoadHWU(addr, value, res) \ __asm__ __volatile__ ( \ ".set\tnoat\n" \ - "1:\tlbu\t%0, 0(%2)\n" \ - "2:\tlbu\t$1, 1(%2)\n\t" \ + "1:\t"user_lbu("%0", "0(%2)")"\n" \ + "2:\t"user_lbu("$1", "1(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ @@ -170,8 +171,8 @@ extern void show_registers(struct pt_regs *regs); #define LoadWU(addr, value, res) \ __asm__ __volatile__ ( \ - "1:\tlwl\t%0, (%2)\n" \ - "2:\tlwr\t%0, 3(%2)\n\t" \ + "1:\t"user_lwl("%0", "(%2)")"\n" \ + "2:\t"user_lwr("%0", "3(%2)")"\n\t" \ "dsll\t%0, %0, 32\n\t" \ "dsrl\t%0, %0, 32\n\t" \ "li\t%1, 0\n" \ @@ -209,9 +210,9 @@ extern void show_registers(struct pt_regs *regs); #define StoreHW(addr, value, res) \ __asm__ __volatile__ ( \ ".set\tnoat\n" \ - "1:\tsb\t%1, 1(%2)\n\t" \ + "1:\t"user_sb("%1", "1(%2)")"\n" \ "srl\t$1, %1, 0x8\n" \ - "2:\tsb\t$1, 0(%2)\n\t" \ + "2:\t"user_sb("$1", "0(%2)")"\n" \ ".set\tat\n\t" \ "li\t%0, 0\n" \ "3:\n\t" \ @@ -229,8 +230,8 @@ extern void show_registers(struct pt_regs *regs); #define StoreW(addr, value, res) \ __asm__ __volatile__ ( \ - "1:\tswl\t%1,(%2)\n" \ - "2:\tswr\t%1, 3(%2)\n\t" \ + "1:\t"user_swl("%1", "(%2)")"\n" \ + "2:\t"user_swr("%1", "3(%2)")"\n\t" \ "li\t%0, 0\n" \ "3:\n\t" \ ".insn\n\t" \ @@ -267,8 +268,8 @@ extern void show_registers(struct pt_regs *regs); #ifdef __LITTLE_ENDIAN #define LoadHW(addr, value, res) \ __asm__ __volatile__ (".set\tnoat\n" \ - "1:\tlb\t%0, 1(%2)\n" \ - "2:\tlbu\t$1, 0(%2)\n\t" \ + "1:\t"user_lb("%0", "1(%2)")"\n" \ + "2:\t"user_lbu("$1", "0(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ @@ -287,8 +288,8 @@ extern void show_registers(struct pt_regs *regs); #define LoadW(addr, value, res) \ __asm__ __volatile__ ( \ - "1:\tlwl\t%0, 3(%2)\n" \ - "2:\tlwr\t%0, (%2)\n\t" \ + "1:\t"user_lwl("%0", "3(%2)")"\n" \ + "2:\t"user_lwr("%0", "(%2)")"\n\t" \ "li\t%1, 0\n" \ "3:\n\t" \ ".insn\n\t" \ @@ -306,8 +307,8 @@ extern void show_registers(struct pt_regs *regs); #define LoadHWU(addr, value, res) \ __asm__ __volatile__ ( \ ".set\tnoat\n" \ - "1:\tlbu\t%0, 1(%2)\n" \ - "2:\tlbu\t$1, 0(%2)\n\t" \ + "1:\t"user_lbu("%0", "1(%2)")"\n" \ + "2:\t"user_lbu("$1", "0(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ @@ -327,8 +328,8 @@ extern void show_registers(struct pt_regs *regs); #define LoadWU(addr, value, res) \ __asm__ __volatile__ ( \ - "1:\tlwl\t%0, 3(%2)\n" \ - "2:\tlwr\t%0, (%2)\n\t" \ + "1:\t"user_lwl("%0", "3(%2)")"\n" \ + "2:\t"user_lwr("%0", "(%2)")"\n\t" \ "dsll\t%0, %0, 32\n\t" \ "dsrl\t%0, %0, 32\n\t" \ "li\t%1, 0\n" \ @@ -366,9 +367,9 @@ extern void show_registers(struct pt_regs *regs); #define StoreHW(addr, value, res) \ __asm__ __volatile__ ( \ ".set\tnoat\n" \ - "1:\tsb\t%1, 0(%2)\n\t" \ + "1:\t"user_sb("%1", "0(%2)")"\n" \ "srl\t$1,%1, 0x8\n" \ - "2:\tsb\t$1, 1(%2)\n\t" \ + "2:\t"user_sb("$1", "1(%2)")"\n" \ ".set\tat\n\t" \ "li\t%0, 0\n" \ "3:\n\t" \ @@ -386,8 +387,8 @@ extern void show_registers(struct pt_regs *regs); #define StoreW(addr, value, res) \ __asm__ __volatile__ ( \ - "1:\tswl\t%1, 3(%2)\n" \ - "2:\tswr\t%1, (%2)\n\t" \ + "1:\t"user_swl("%1", "3(%2)")"\n" \ + "2:\t"user_swr("%1", "(%2)")"\n\t" \ "li\t%0, 0\n" \ "3:\n\t" \ ".insn\n\t" \ -- cgit From c1771216ab48bb077cee30e6d197a5a55f707101 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Thu, 12 Dec 2013 16:15:15 +0000 Subject: MIPS: kernel: unaligned: Handle unaligned accesses for EVA Handle unaligned accesses when we access userspace memory EVA mode. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras --- arch/mips/kernel/unaligned.c | 86 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 5ec8f00b51b5..2b3517214d6d 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -431,7 +431,9 @@ static void emulate_load_store_insn(struct pt_regs *regs, unsigned long origpc; unsigned long orig31; void __user *fault_addr = NULL; - +#ifdef CONFIG_EVA + mm_segment_t seg; +#endif origpc = (unsigned long)pc; orig31 = regs->regs[31]; @@ -476,6 +478,88 @@ static void emulate_load_store_insn(struct pt_regs *regs, * The remaining opcodes are the ones that are really of * interest. */ +#ifdef CONFIG_EVA + case spec3_op: + /* + * we can land here only from kernel accessing user memory, + * so we need to "switch" the address limit to user space, so + * address check can work properly. + */ + seg = get_fs(); + set_fs(USER_DS); + switch (insn.spec3_format.func) { + case lhe_op: + if (!access_ok(VERIFY_READ, addr, 2)) { + set_fs(seg); + goto sigbus; + } + LoadHW(addr, value, res); + if (res) { + set_fs(seg); + goto fault; + } + compute_return_epc(regs); + regs->regs[insn.spec3_format.rt] = value; + break; + case lwe_op: + if (!access_ok(VERIFY_READ, addr, 4)) { + set_fs(seg); + goto sigbus; + } + LoadW(addr, value, res); + if (res) { + set_fs(seg); + goto fault; + } + compute_return_epc(regs); + regs->regs[insn.spec3_format.rt] = value; + break; + case lhue_op: + if (!access_ok(VERIFY_READ, addr, 2)) { + set_fs(seg); + goto sigbus; + } + LoadHWU(addr, value, res); + if (res) { + set_fs(seg); + goto fault; + } + compute_return_epc(regs); + regs->regs[insn.spec3_format.rt] = value; + break; + case she_op: + if (!access_ok(VERIFY_WRITE, addr, 2)) { + set_fs(seg); + goto sigbus; + } + compute_return_epc(regs); + value = regs->regs[insn.spec3_format.rt]; + StoreHW(addr, value, res); + if (res) { + set_fs(seg); + goto fault; + } + break; + case swe_op: + if (!access_ok(VERIFY_WRITE, addr, 4)) { + set_fs(seg); + goto sigbus; + } + compute_return_epc(regs); + value = regs->regs[insn.spec3_format.rt]; + StoreW(addr, value, res); + if (res) { + set_fs(seg); + goto fault; + } + break; + default: + set_fs(seg); + goto sigill; + } + set_fs(seg); + break; +#endif case lh_op: if (!access_ok(VERIFY_READ, addr, 2)) goto sigbus; -- cgit From ac85227f7637cfb0d811519b8253c454d0d0a159 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Thu, 12 Dec 2013 16:21:00 +0000 Subject: MIPS: checksum: Split the 'copy_user' symbol The 'copy_user' symbol can be used to copy from or to userland so we will use two different symbols for these operations. This makes no difference in the existing code, but when the core is operating in EVA mode, different instructions need to be used to read and write to userland address space. The old function has also been renamed to 'copy_kernel' to denote that it is suitable for copy data to and from kernel space. Signed-off-by: Markos Chandras --- arch/mips/kernel/mips_ksyms.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c index 13e60f676b8b..2607c3a4ff7e 100644 --- a/arch/mips/kernel/mips_ksyms.c +++ b/arch/mips/kernel/mips_ksyms.c @@ -73,7 +73,9 @@ EXPORT_SYMBOL(__strnlen_user_asm); EXPORT_SYMBOL(csum_partial); EXPORT_SYMBOL(csum_partial_copy_nocheck); -EXPORT_SYMBOL(__csum_partial_copy_user); +EXPORT_SYMBOL(__csum_partial_copy_kernel); +EXPORT_SYMBOL(__csum_partial_copy_to_user); +EXPORT_SYMBOL(__csum_partial_copy_from_user); EXPORT_SYMBOL(invalid_pte_table); #ifdef CONFIG_FUNCTION_TRACER -- cgit From ca750649e08ce37bd3873e1026dc245811adf7a8 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Thu, 12 Dec 2013 16:57:19 +0000 Subject: MIPS: kernel: signal: Prevent save/restore FPU context in user memory EVA does not have FPU specific instructions for reading or writing FPU registers from userspace memory. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras --- arch/mips/kernel/signal.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index fd61700409bc..33133d3df3e5 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -6,6 +6,7 @@ * Copyright (C) 1991, 1992 Linus Torvalds * Copyright (C) 1994 - 2000 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2014, Imagination Technologies Ltd. */ #include #include @@ -140,6 +141,7 @@ static int protected_save_fp_context(struct sigcontext __user *sc, { int err; bool save_msa = cpu_has_msa && (used_math & USEDMATH_MSA); +#ifndef CONFIG_EVA while (1) { lock_fpu_owner(); if (is_fpu_owner()) { @@ -162,6 +164,17 @@ static int protected_save_fp_context(struct sigcontext __user *sc, if (err) break; /* really bad sigcontext */ } +#else + /* + * EVA does not have FPU EVA instructions so saving fpu context directly + * does not work. + */ + disable_msa(); + lose_fpu(1); + err = save_fp_context(sc); /* this might fail */ + if (save_msa && !err) + err = copy_msa_to_sigcontext(sc); +#endif return err; } @@ -170,6 +183,7 @@ static int protected_restore_fp_context(struct sigcontext __user *sc, { int err, tmp __maybe_unused; bool restore_msa = cpu_has_msa && (used_math & USEDMATH_MSA); +#ifndef CONFIG_EVA while (1) { lock_fpu_owner(); if (is_fpu_owner()) { @@ -197,6 +211,17 @@ static int protected_restore_fp_context(struct sigcontext __user *sc, if (err) break; /* really bad sigcontext */ } +#else + /* + * EVA does not have FPU EVA instructions so restoring fpu context + * directly does not work. + */ + enable_msa(); + lose_fpu(0); + err = restore_fp_context(sc); /* this might fail */ + if (restore_msa && !err) + err = copy_msa_from_sigcontext(sc); +#endif return err; } @@ -685,6 +710,7 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused, } #ifdef CONFIG_SMP +#ifndef CONFIG_EVA static int smp_save_fp_context(struct sigcontext __user *sc) { return raw_cpu_has_fpu @@ -698,10 +724,12 @@ static int smp_restore_fp_context(struct sigcontext __user *sc) ? _restore_fp_context(sc) : copy_fp_from_sigcontext(sc); } +#endif /* CONFIG_EVA */ #endif static int signal_setup(void) { +#ifndef CONFIG_EVA #ifdef CONFIG_SMP /* For now just do the cpu_has_fpu check when the functions are invoked */ save_fp_context = smp_save_fp_context; @@ -714,6 +742,10 @@ static int signal_setup(void) save_fp_context = copy_fp_from_sigcontext; restore_fp_context = copy_fp_to_sigcontext; } +#endif /* CONFIG_SMP */ +#else + save_fp_context = copy_fp_from_sigcontext;; + restore_fp_context = copy_fp_to_sigcontext; #endif return 0; -- cgit From 6ebda44f366478d1eea180d93154e7d97b591f50 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Mon, 16 Dec 2013 12:06:55 +0000 Subject: MIPS: kernel: {ftrace,kgdb}: Set correct address limit for cache flushes When flushing the icache, make sure the address limit is correct so the appropriate 'cache' instruction will be used. This has no impact on cores operating in non-eva mode. However, when EVA is enabled, we ensure that 'cache' will be used instead of 'cachee'. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras --- arch/mips/kernel/ftrace.c | 4 ++++ arch/mips/kernel/kgdb.c | 18 +++++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index 185ba258361b..ddcc3500248d 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -90,6 +90,7 @@ static inline void ftrace_dyn_arch_init_insns(void) static int ftrace_modify_code(unsigned long ip, unsigned int new_code) { int faulted; + mm_segment_t old_fs; /* *(unsigned int *)ip = new_code; */ safe_store_code(new_code, ip, faulted); @@ -97,7 +98,10 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code) if (unlikely(faulted)) return -EFAULT; + old_fs = get_fs(); + set_fs(get_ds()); flush_icache_range(ip, ip + 8); + set_fs(old_fs); return 0; } diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c index fcaac2f132f0..7afcc2f22c0d 100644 --- a/arch/mips/kernel/kgdb.c +++ b/arch/mips/kernel/kgdb.c @@ -32,6 +32,7 @@ #include #include #include +#include static struct hard_trap_info { unsigned char tt; /* Trap type code for MIPS R3xxx and R4xxx */ @@ -208,7 +209,14 @@ void arch_kgdb_breakpoint(void) static void kgdb_call_nmi_hook(void *ignored) { + mm_segment_t old_fs; + + old_fs = get_fs(); + set_fs(get_ds()); + kgdb_nmicallback(raw_smp_processor_id(), NULL); + + set_fs(old_fs); } void kgdb_roundup_cpus(unsigned long flags) @@ -282,6 +290,7 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd, struct die_args *args = (struct die_args *)ptr; struct pt_regs *regs = args->regs; int trap = (regs->cp0_cause & 0x7c) >> 2; + mm_segment_t old_fs; #ifdef CONFIG_KPROBES /* @@ -296,11 +305,17 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd, if (user_mode(regs)) return NOTIFY_DONE; + /* Kernel mode. Set correct address limit */ + old_fs = get_fs(); + set_fs(get_ds()); + if (atomic_read(&kgdb_active) != -1) kgdb_nmicallback(smp_processor_id(), regs); - if (kgdb_handle_exception(trap, compute_signal(trap), cmd, regs)) + if (kgdb_handle_exception(trap, compute_signal(trap), cmd, regs)) { + set_fs(old_fs); return NOTIFY_DONE; + } if (atomic_read(&kgdb_setting_breakpoint)) if ((trap == 9) && (regs->cp0_epc == (unsigned long)breakinst)) @@ -310,6 +325,7 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd, local_irq_enable(); __flush_cache_all(); + set_fs(old_fs); return NOTIFY_STOP; } -- cgit From 49016748ec45408ad89d10308ac903a2202ff305 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Thu, 9 Jan 2014 16:04:51 +0000 Subject: MIPS: kernel: cpu-probe: Enable EVA option on supported cores Signed-off-by: Markos Chandras --- arch/mips/kernel/cpu-probe.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index ee5de360636d..e225b0d369e8 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -386,6 +386,9 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c) config5 &= ~MIPS_CONF5_UFR; write_c0_config5(config5); + if (config5 & MIPS_CONF5_EVA) + c->options |= MIPS_CPU_EVA; + return config5 & MIPS_CONF_M; } -- cgit From 91119686f33928e2ced93eaedf4191cedbd0e827 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Mon, 27 Jan 2014 15:10:40 +0000 Subject: MIPS: kernel: proc: Add EVA to the list of CPU features Signed-off-by: Markos Chandras --- arch/mips/kernel/proc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index ca1d48e5d53f..f0df7fde37c5 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -96,6 +96,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (cpu_has_mmips) seq_printf(m, "%s", " micromips"); if (cpu_has_vz) seq_printf(m, "%s", " vz"); if (cpu_has_msa) seq_printf(m, "%s", " msa"); + if (cpu_has_eva) seq_printf(m, "%s", " eva"); seq_printf(m, "\n"); if (cpu_has_mmips) { -- cgit From d0ba3544a5ca185f69688fa0b51b187d3e78e31a Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Tue, 21 Jan 2014 09:52:23 +0000 Subject: MIPS: malta: Add support for SMP EVA Allow secondary cores to program their segment control registers during smp bootstrap code. This enables EVA on Malta SMP configurations Signed-off-by: Markos Chandras --- arch/mips/kernel/head.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index 7b6a5b3e3acf..e712dcf18b2d 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -175,8 +175,8 @@ NESTED(smp_bootstrap, 16, sp) DMT 10 # dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */ jal mips_ihb #endif /* CONFIG_MIPS_MT_SMTC */ - setup_c0_status_sec smp_slave_setup + setup_c0_status_sec #ifdef CONFIG_MIPS_MT_SMTC andi t2, t2, VPECONTROL_TE beqz t2, 2f -- cgit From f36c4720fca325579faddc880d4e178e4ccbda88 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Tue, 4 Mar 2014 13:34:43 +0000 Subject: MIPS: Add support for the M5150 processor The M5150 core is a 32-bit MIPS RISC which implements the MIPS Architecture Release-5 in a 5-stage pipeline. In addition, it includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6596/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/idle.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 04ea1c7a3d31..9f904eda5de5 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -188,6 +188,7 @@ void __init check_wait(void) case CPU_INTERAPTIV: case CPU_PROAPTIV: case CPU_P5600: + case CPU_M5150: cpu_wait = r4k_wait; if (read_c0_config7() & MIPS_CONF7_WII) cpu_wait = r4k_wait_irqoff; -- cgit From 9943ed921bbf4de59ed1986cb316e720a244f757 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Tue, 4 Mar 2014 13:34:44 +0000 Subject: MIPS: cpu-probe: Add support for probing M5150 cores Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6597/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index e225b0d369e8..f4229544df10 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -853,6 +853,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_P5600; __cpu_name[cpu] = "MIPS P5600"; break; + case PRID_IMP_M5150: + c->cputype = CPU_M5150; + __cpu_name[cpu] = "MIPS M5150"; + break; } decode_configs(c); -- cgit From 6b0b84295c4a82c89de64b80923e9d975e9249ed Mon Sep 17 00:00:00 2001 From: Deng-Cheng Zhu Date: Mon, 10 Feb 2014 09:48:52 -0800 Subject: MIPS: perf: Rename 74K event/cache maps in preparation for Aptiv support 74K/proAptiv share the same event/cache maps. So it's better to change the names of the existing mipsxx74Kcore_[event|cache]_map. Signed-off-by: Deng-Cheng Zhu Reviewed-by: Markos Chandras Reviewed-by: James Hogan Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6526/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/perf_event_mipsxx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 17594b81a5d2..d5294cc7a6ac 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -815,7 +815,7 @@ static const struct mips_perf_event mipsxxcore_event_map }; /* 74K core has different branch event code. */ -static const struct mips_perf_event mipsxx74Kcore_event_map +static const struct mips_perf_event mipsxxcore_event_map2 [PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, @@ -931,7 +931,7 @@ static const struct mips_perf_event mipsxxcore_cache_map }; /* 74K core has completely different cache event map. */ -static const struct mips_perf_event mipsxx74Kcore_cache_map +static const struct mips_perf_event mipsxxcore_cache_map2 [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] = { @@ -1577,8 +1577,8 @@ init_hw_perf_events(void) break; case CPU_74K: mipspmu.name = "mips/74K"; - mipspmu.general_event_map = &mipsxx74Kcore_event_map; - mipspmu.cache_event_map = &mipsxx74Kcore_cache_map; + mipspmu.general_event_map = &mipsxxcore_event_map2; + mipspmu.cache_event_map = &mipsxxcore_cache_map2; break; case CPU_1004K: mipspmu.name = "mips/1004K"; -- cgit From c52068bd2f5d733a6edaab5108a9975dcb333494 Mon Sep 17 00:00:00 2001 From: Deng-Cheng Zhu Date: Mon, 10 Feb 2014 09:48:53 -0800 Subject: MIPS: perf: Add proAptiv support Choose event/cache maps and handle raw event mapping for proAptiv. Update code comments. Signed-off-by: Deng-Cheng Zhu Reviewed-by: Markos Chandras Reviewed-by: James Hogan Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6527/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/perf_event_mipsxx.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index d5294cc7a6ac..fc4cf07358cb 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -814,7 +814,7 @@ static const struct mips_perf_event mipsxxcore_event_map [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, }; -/* 74K core has different branch event code. */ +/* 74K/proAptiv core has different branch event code. */ static const struct mips_perf_event mipsxxcore_event_map2 [PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, @@ -930,7 +930,7 @@ static const struct mips_perf_event mipsxxcore_cache_map }, }; -/* 74K core has completely different cache event map. */ +/* 74K/proAptiv core has completely different cache event map. */ static const struct mips_perf_event mipsxxcore_cache_map2 [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] @@ -978,6 +978,11 @@ static const struct mips_perf_event mipsxxcore_cache_map2 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, }, }, +/* + * 74K core does not have specific DTLB events. proAptiv core has + * "speculative" DTLB events which are numbered 0x63 (even/odd) and + * not included here. One can use raw events if really needed. + */ [C(ITLB)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, @@ -1378,6 +1383,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev) #define IS_BOTH_COUNTERS_74K_EVENT(b) \ ((b) == 0 || (b) == 1) +/* proAptiv */ +#define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b) \ + ((b) == 0 || (b) == 1) + /* 1004K */ #define IS_BOTH_COUNTERS_1004K_EVENT(b) \ ((b) == 0 || (b) == 1 || (b) == 11) @@ -1450,6 +1459,16 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) raw_id > 127 ? CNTR_ODD : CNTR_EVEN; #ifdef CONFIG_MIPS_MT_SMP raw_event.range = P; +#endif + break; + case CPU_PROAPTIV: + if (IS_BOTH_COUNTERS_PROAPTIV_EVENT(base_id)) + raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; + else + raw_event.cntr_mask = + raw_id > 127 ? CNTR_ODD : CNTR_EVEN; +#ifdef CONFIG_MIPS_MT_SMP + raw_event.range = P; #endif break; case CPU_1004K: @@ -1580,6 +1599,11 @@ init_hw_perf_events(void) mipspmu.general_event_map = &mipsxxcore_event_map2; mipspmu.cache_event_map = &mipsxxcore_cache_map2; break; + case CPU_PROAPTIV: + mipspmu.name = "mips/proAptiv"; + mipspmu.general_event_map = &mipsxxcore_event_map2; + mipspmu.cache_event_map = &mipsxxcore_cache_map2; + break; case CPU_1004K: mipspmu.name = "mips/1004K"; mipspmu.general_event_map = &mipsxxcore_event_map; -- cgit From 9597e432455023bfbebfdd9a2e6064508a4b129e Mon Sep 17 00:00:00 2001 From: Deng-Cheng Zhu Date: Mon, 10 Feb 2014 09:48:54 -0800 Subject: MIPS: perf: Add interAptiv support Choose event/cache maps and handle raw event mapping for interAptiv. Update code comments. Signed-off-by: Deng-Cheng Zhu Reviewed-by: Markos Chandras Reviewed-by: James Hogan Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6528/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/perf_event_mipsxx.c | 38 ++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index fc4cf07358cb..4f2d9dece7ab 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -805,7 +805,7 @@ static void reset_counters(void *arg) } } -/* 24K/34K/1004K cores can share the same event map. */ +/* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */ static const struct mips_perf_event mipsxxcore_event_map [PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, @@ -849,7 +849,7 @@ static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */ }; -/* 24K/34K/1004K cores can share the same cache event map. */ +/* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */ static const struct mips_perf_event mipsxxcore_cache_map [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] @@ -1400,6 +1400,20 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev) #define IS_RANGE_V_1004K_EVENT(r) ((r) == 47) #endif +/* interAptiv */ +#define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b) \ + ((b) == 0 || (b) == 1 || (b) == 11) +#ifdef CONFIG_MIPS_MT_SMP +/* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */ +#define IS_RANGE_P_INTERAPTIV_EVENT(r, b) \ + ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ + (b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 || \ + (r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 && \ + (b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 || \ + ((b) >= 64 && (b) <= 67)) +#define IS_RANGE_V_INTERAPTIV_EVENT(r) ((r) == 47 || (r) == 175) +#endif + /* BMIPS5000 */ #define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b) \ ((b) == 0 || (b) == 1) @@ -1484,6 +1498,21 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) raw_event.range = V; else raw_event.range = T; +#endif + break; + case CPU_INTERAPTIV: + if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id)) + raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; + else + raw_event.cntr_mask = + raw_id > 127 ? CNTR_ODD : CNTR_EVEN; +#ifdef CONFIG_MIPS_MT_SMP + if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id)) + raw_event.range = P; + else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id))) + raw_event.range = V; + else + raw_event.range = T; #endif break; case CPU_BMIPS5000: @@ -1614,6 +1643,11 @@ init_hw_perf_events(void) mipspmu.general_event_map = &mipsxxcore_event_map; mipspmu.cache_event_map = &mipsxxcore_cache_map; break; + case CPU_INTERAPTIV: + mipspmu.name = "mips/interAptiv"; + mipspmu.general_event_map = &mipsxxcore_event_map; + mipspmu.cache_event_map = &mipsxxcore_cache_map; + break; case CPU_LOONGSON1: mipspmu.name = "mips/loongson1"; mipspmu.general_event_map = &mipsxxcore_event_map; -- cgit From 26859198195503823735641ff79a246299606da8 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Sun, 16 Feb 2014 16:01:18 +0800 Subject: MIPS: Loongson: Rename PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2 Loongson-1 is a 32-bit MIPS CPU and Loongson-2/3 are 64-bit MIPS CPUs, and both Loongson-2/3 has the same PRID IMP filed (0x6300). As a result, renaming PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2 to PRID_IMP_LOONGSON_32 and PRID_IMP_LOONGSON_64 will make more sense. Signed-off-by: Huacai Chen Tested-by: Alex Smith Reviewed-by: Alex Smith Cc: John Crispin Cc: Steven J. Hill Cc: Aurelien Jarno Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang Cc: Zhangjin Wu Patchwork: https://patchwork.linux-mips.org/patch/6552/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f4229544df10..34df5afa2d6f 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -734,7 +734,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) MIPS_CPU_LLSC; c->tlbsize = 64; break; - case PRID_IMP_LOONGSON2: + case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ c->cputype = CPU_LOONGSON2; __cpu_name[cpu] = "ICT Loongson-2"; @@ -753,7 +753,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) MIPS_CPU_32FPR; c->tlbsize = 64; break; - case PRID_IMP_LOONGSON1: + case PRID_IMP_LOONGSON_32: /* Loongson-1 */ decode_configs(c); c->cputype = CPU_LOONGSON1; -- cgit From d7b12056bc9cbd7f0c0ae5bc52f2b049d48c4314 Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Sun, 26 Dec 2010 04:42:37 +0800 Subject: MIPS: Use current_cpu_type() instead of c->cputype If current_cpu_type() is pre-defined in cpu-feature-overrides.h, This may save about 10k for the compressed kernel image(vmlinuz). Signed-off-by: Wu Zhangjin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1901/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/spram.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index f9a693a6aaa7..67f2495def1c 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c @@ -197,10 +197,9 @@ static void probe_spram(char *type, } void spram_config(void) { - struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config0; - switch (c->cputype) { + switch (current_cpu_type()) { case CPU_24K: case CPU_34K: case CPU_74K: -- cgit From 3351047f01fe012abbb585b400d1c51b57ed011d Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 19 Nov 2013 17:30:35 +0000 Subject: MIPS: Simplify PTRACE_PEEKUSR for FPC_EIR All architecturally defined bits in the FPU implementation register are read only & unchanging. It contains some implementation-defined bits but the architecture manual states "This bits are explicitly not intended to be used for mode control functions" which seems to provide justification for viewing the register as a whole as unchanging. This being the case we can simply re-use the value we read at boot rather than having to re-read it later, and avoid the complexity which that read entails. Signed-off-by: Paul Burton Reviewed-by: Qais Yousef Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6144/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 40 +++------------------------------------- arch/mips/kernel/ptrace32.c | 42 +++--------------------------------------- 2 files changed, 6 insertions(+), 76 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 4137a49eae26..94144bad5727 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -501,44 +501,10 @@ long arch_ptrace(struct task_struct *child, long request, case FPC_CSR: tmp = child->thread.fpu.fcr31; break; - case FPC_EIR: { /* implementation / version register */ - unsigned int flags; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long irqflags; - unsigned int mtflags; -#endif /* CONFIG_MIPS_MT_SMTC */ - - preempt_disable(); - if (!cpu_has_fpu) { - preempt_enable(); - break; - } - -#ifdef CONFIG_MIPS_MT_SMTC - /* Read-modify-write of Status must be atomic */ - local_irq_save(irqflags); - mtflags = dmt(); -#endif /* CONFIG_MIPS_MT_SMTC */ - if (cpu_has_mipsmt) { - unsigned int vpflags = dvpe(); - flags = read_c0_status(); - __enable_fpu(FPU_AS_IS); - __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); - write_c0_status(flags); - evpe(vpflags); - } else { - flags = read_c0_status(); - __enable_fpu(FPU_AS_IS); - __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); - write_c0_status(flags); - } -#ifdef CONFIG_MIPS_MT_SMTC - emt(mtflags); - local_irq_restore(irqflags); -#endif /* CONFIG_MIPS_MT_SMTC */ - preempt_enable(); + case FPC_EIR: + /* implementation / version register */ + tmp = current_cpu_data.fpu_id; break; - } case DSP_BASE ... DSP_BASE + 5: { dspreg_t *dregs; diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c index c394d8f74265..b40c3ca60ee5 100644 --- a/arch/mips/kernel/ptrace32.c +++ b/arch/mips/kernel/ptrace32.c @@ -127,46 +127,10 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, case FPC_CSR: tmp = child->thread.fpu.fcr31; break; - case FPC_EIR: { /* implementation / version register */ - unsigned int flags; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned int irqflags; - unsigned int mtflags; -#endif /* CONFIG_MIPS_MT_SMTC */ - - preempt_disable(); - if (!cpu_has_fpu) { - preempt_enable(); - tmp = 0; - break; - } - -#ifdef CONFIG_MIPS_MT_SMTC - /* Read-modify-write of Status must be atomic */ - local_irq_save(irqflags); - mtflags = dmt(); -#endif /* CONFIG_MIPS_MT_SMTC */ - - if (cpu_has_mipsmt) { - unsigned int vpflags = dvpe(); - flags = read_c0_status(); - __enable_fpu(FPU_AS_IS); - __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); - write_c0_status(flags); - evpe(vpflags); - } else { - flags = read_c0_status(); - __enable_fpu(FPU_AS_IS); - __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); - write_c0_status(flags); - } -#ifdef CONFIG_MIPS_MT_SMTC - emt(mtflags); - local_irq_restore(irqflags); -#endif /* CONFIG_MIPS_MT_SMTC */ - preempt_enable(); + case FPC_EIR: + /* implementation / version register */ + tmp = current_cpu_data.fpu_id; break; - } case DSP_BASE ... DSP_BASE + 5: { dspreg_t *dregs; -- cgit From dab75dd956522ce19403c108f659ea9b339f2559 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 19 Nov 2013 17:30:36 +0000 Subject: MIPS: Simplify ptrace_getfpregs FPU IR retrieval All architecturally defined bits in the FPU implementation register are read only & unchanging. It contains some implementation-defined bits but the architecture manual states "This bits are explicitly not intended to be used for mode control functions" which seems to provide justification for viewing the register as a whole as unchanging. This being the case we can simply re-use the value we read at boot rather than having to re-read it later, and avoid the complexity which that read entails. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6147/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/ptrace.c | 25 +------------------------ 1 file changed, 1 insertion(+), 24 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 94144bad5727..7271e5a83081 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -114,7 +114,6 @@ int ptrace_setregs(struct task_struct *child, __s64 __user *data) int ptrace_getfpregs(struct task_struct *child, __u32 __user *data) { int i; - unsigned int tmp; if (!access_ok(VERIFY_WRITE, data, 33 * 8)) return -EIO; @@ -130,29 +129,7 @@ int ptrace_getfpregs(struct task_struct *child, __u32 __user *data) } __put_user(child->thread.fpu.fcr31, data + 64); - - preempt_disable(); - if (cpu_has_fpu) { - unsigned int flags; - - if (cpu_has_mipsmt) { - unsigned int vpflags = dvpe(); - flags = read_c0_status(); - __enable_fpu(FPU_AS_IS); - __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); - write_c0_status(flags); - evpe(vpflags); - } else { - flags = read_c0_status(); - __enable_fpu(FPU_AS_IS); - __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); - write_c0_status(flags); - } - } else { - tmp = 0; - } - preempt_enable(); - __put_user(tmp, data + 65); + __put_user(current_cpu_data.fpu_id, data + 65); return 0; } -- cgit From d6d3c9afaab47418ab2d7f874fb8aeac1f067104 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 16 Oct 2013 17:10:07 +0200 Subject: MIPS: MT: proc: Add support for printing VPE and TC ids And there are more CPUs or configurations that want to provide special per-CPU information in /proc/cpuinfo. So I think there needs to be a hook mechanism, such as a notifier. This is a first cut only; I need to think about what sort of looking the notifier needs to have. But I'd appreciate testing on MT hardware! Signed-off-by: Ralf Baechle Cc: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6066/ --- arch/mips/kernel/proc.c | 23 +++++++++++++++++++++++ arch/mips/kernel/smp-mt.c | 22 ++++++++++++++++++++++ arch/mips/kernel/smtc-proc.c | 23 +++++++++++++++++++++++ 3 files changed, 68 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index f0df7fde37c5..e40971b51d2f 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -17,8 +17,24 @@ unsigned int vced_count, vcei_count; +/* + * * No lock; only written during early bootup by CPU 0. + * */ +static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain); + +int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb) +{ + return raw_notifier_chain_register(&proc_cpuinfo_chain, nb); +} + +int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v) +{ + return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v); +} + static int show_cpuinfo(struct seq_file *m, void *v) { + struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args; unsigned long n = (unsigned long) v - 1; unsigned int version = cpu_data[n].processor_id; unsigned int fp_vers = cpu_data[n].fpu_id; @@ -120,6 +136,13 @@ static int show_cpuinfo(struct seq_file *m, void *v) cpu_has_vce ? "%u" : "not available"); seq_printf(m, fmt, 'D', vced_count); seq_printf(m, fmt, 'I', vcei_count); + + proc_cpuinfo_notifier_args.m = m; + proc_cpuinfo_notifier_args.n = n; + + raw_notifier_call_chain(&proc_cpuinfo_chain, 0, + &proc_cpuinfo_notifier_args); + seq_printf(m, "\n"); return 0; diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 0fb8cefc9114..3378c452e5d7 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -313,3 +313,25 @@ struct plat_smp_ops vsmp_smp_ops = { .smp_setup = vsmp_smp_setup, .prepare_cpus = vsmp_prepare_cpus, }; + +static int proc_cpuinfo_chain_call(struct notifier_block *nfb, + unsigned long action_unused, void *data) +{ + struct proc_cpuinfo_notifier_args *pcn = data; + struct seq_file *m = pcn->m; + unsigned long n = pcn->n; + + if (!cpu_has_mipsmt) + return NOTIFY_OK; + + seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id); + + return NOTIFY_OK; +} + +static int __init proc_cpuinfo_notifier_init(void) +{ + return proc_cpuinfo_notifier(proc_cpuinfo_chain_call, 0); +} + +subsys_initcall(proc_cpuinfo_notifier_init); diff --git a/arch/mips/kernel/smtc-proc.c b/arch/mips/kernel/smtc-proc.c index c10aa84c9fa9..38635a996cbf 100644 --- a/arch/mips/kernel/smtc-proc.c +++ b/arch/mips/kernel/smtc-proc.c @@ -77,3 +77,26 @@ void init_smtc_stats(void) proc_create("smtc", 0444, NULL, &smtc_proc_fops); } + +static int proc_cpuinfo_chain_call(struct notifier_block *nfb, + unsigned long action_unused, void *data) +{ + struct proc_cpuinfo_notifier_args *pcn = data; + struct seq_file *m = pcn->m; + unsigned long n = pcn->n; + + if (!cpu_has_mipsmt) + return NOTIFY_OK; + + seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id); + seq_printf(m, "TC\t\t\t: %d\n", cpu_data[n].tc_id); + + return NOTIFY_OK; +} + +static int __init proc_cpuinfo_notifier_init(void) +{ + return proc_cpuinfo_notifier(proc_cpuinfo_chain_call, 0); +} + +subsys_initcall(proc_cpuinfo_notifier_init); -- cgit From c579d310b9b22b4b9fedcdd720c8ac58c901e1e9 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Fri, 21 Mar 2014 18:44:00 +0800 Subject: MIPS: Loongson: Add basic Loongson-3 CPU support Basic Loongson-3 CPU support include CPU probing and TLB/cache initializing. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan Tested-by: Alex Smith Reviewed-by: Alex Smith Cc: John Crispin Cc: Steven J. Hill Cc: Aurelien Jarno Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang Cc: Zhangjin Wu Patchwork: https://patchwork.linux-mips.org/patch/6630 Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 34df5afa2d6f..bd712c91f48b 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -735,16 +735,22 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->tlbsize = 64; break; case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ - c->cputype = CPU_LOONGSON2; - __cpu_name[cpu] = "ICT Loongson-2"; - switch (c->processor_id & PRID_REV_MASK) { case PRID_REV_LOONGSON2E: + c->cputype = CPU_LOONGSON2; + __cpu_name[cpu] = "ICT Loongson-2"; set_elf_platform(cpu, "loongson2e"); break; case PRID_REV_LOONGSON2F: + c->cputype = CPU_LOONGSON2; + __cpu_name[cpu] = "ICT Loongson-2"; set_elf_platform(cpu, "loongson2f"); break; + case PRID_REV_LOONGSON3A: + c->cputype = CPU_LOONGSON3; + __cpu_name[cpu] = "ICT Loongson-3"; + set_elf_platform(cpu, "loongson3a"); + break; } set_isa(c, MIPS_CPU_ISA_III); -- cgit From 30ee615bb86ba640c9ec7f85fb95c1b0e31c41be Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Thu, 27 Mar 2014 10:57:30 +0000 Subject: MIPS: Fix core number detection for MT cores In cores which implement the MT ASE, the CPUNum in the EBase register is a concatenation of the core number & the VPE ID within that core. In order to retrieve the correct core number CPUNum must be shifted appropriately to remove the VPE ID bits. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6666/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index bd712c91f48b..6e8fb85ce7c3 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -421,8 +422,11 @@ static void decode_configs(struct cpuinfo_mips *c) mips_probe_watch_registers(c); #ifndef CONFIG_MIPS_CPS - if (cpu_has_mips_r2) + if (cpu_has_mips_r2) { c->core = read_c0_ebase() & 0x3ff; + if (cpu_has_mipsmt) + c->core >>= fls(core_nvpes()) - 1; + } #endif } -- cgit From a809d46066d5171ed446d59a51cd1e57d99fcfc3 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 30 Mar 2014 13:20:10 +0200 Subject: MIPS: Fix gigaton of warning building with microMIPS. With binutils 2.24 the attempt to switch with microMIPS mode to MIPS III mode through .set mips3 results in *lots* of warnings like {standard input}: Assembler messages: {standard input}:397: Warning: the 64-bit MIPS architecture does not support the `smartmips' extension during a kernel build. Fixed by using .set arch=r4000 instead. This breaks support for building the kernel with binutils 2.13 which was supported for 32 bit kernels only anyway and 2.14 which was a bad vintage for MIPS anyway. Signed-off-by: Ralf Baechle --- arch/mips/kernel/bmips_vec.S | 2 +- arch/mips/kernel/genex.S | 6 +++--- arch/mips/kernel/idle.c | 6 +++--- arch/mips/kernel/r4k_fpu.S | 2 +- arch/mips/kernel/r4k_switch.S | 2 +- arch/mips/kernel/syscall.c | 4 ++-- 6 files changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S index a5bf73d22fcc..290c23b51678 100644 --- a/arch/mips/kernel/bmips_vec.S +++ b/arch/mips/kernel/bmips_vec.S @@ -122,7 +122,7 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp) jr k0 RESTORE_ALL - .set mips3 + .set arch=r4000 eret /*********************************************************************** diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 7365cd6be702..a9ce3408be25 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -67,7 +67,7 @@ NESTED(except_vec3_generic, 0, sp) */ NESTED(except_vec3_r4000, 0, sp) .set push - .set mips3 + .set arch=r4000 .set noat mfc0 k1, CP0_CAUSE li k0, 31<<2 @@ -139,7 +139,7 @@ LEAF(__r4k_wait) nop nop #endif - .set mips3 + .set arch=r4000 wait /* end of rollback region (the region size must be power of two) */ 1: @@ -577,7 +577,7 @@ isrdhwr: ori k1, _THREAD_MASK xori k1, _THREAD_MASK LONG_L v1, TI_TP_VALUE(k1) - .set mips3 + .set arch=r4000 eret .set mips0 #endif diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 9f904eda5de5..837ff27950bc 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -64,7 +64,7 @@ void r4k_wait_irqoff(void) if (!need_resched()) __asm__( " .set push \n" - " .set mips3 \n" + " .set arch=r4000 \n" " wait \n" " .set pop \n"); local_irq_enable(); @@ -82,7 +82,7 @@ static void rm7k_wait_irqoff(void) if (!need_resched()) __asm__( " .set push \n" - " .set mips3 \n" + " .set arch=r4000 \n" " .set noat \n" " mfc0 $1, $12 \n" " sync \n" @@ -103,7 +103,7 @@ static void au1k_wait(void) unsigned long c0status = read_c0_status() | 1; /* irqs on */ __asm__( - " .set mips3 \n" + " .set arch=r4000 \n" " cache 0x14, 0(%0) \n" " cache 0x14, 32(%0) \n" " sync \n" diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S index 752b50a69264..0cfa7a56a153 100644 --- a/arch/mips/kernel/r4k_fpu.S +++ b/arch/mips/kernel/r4k_fpu.S @@ -31,7 +31,7 @@ .endm .set noreorder - .set mips3 + .set arch=r4000 LEAF(_save_fp_context) cfc1 t1, fcr31 diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index f938ecd22af0..abacac7c33ef 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -294,7 +294,7 @@ LEAF(_init_fpu) 1: .set pop #endif /* CONFIG_CPU_MIPS32_R2 */ #else - .set mips3 + .set arch=r4000 dmtc1 t1, $f0 dmtc1 t1, $f2 dmtc1 t1, $f4 diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index b79d13f95bf0..4a4f9dda5658 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -110,7 +110,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__ ( - " .set mips3 \n" + " .set arch=r4000 \n" " li %[err], 0 \n" "1: ll %[old], (%[addr]) \n" " move %[tmp], %[new] \n" @@ -135,7 +135,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__ ( - " .set mips3 \n" + " .set arch=r4000 \n" " li %[err], 0 \n" "1: ll %[old], (%[addr]) \n" " move %[tmp], %[new] \n" -- cgit From f0cff5c86f7d3be0084eedbf449c3f47638e76f2 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 24 Mar 2014 10:19:28 +0000 Subject: MIPS: smp-cmp: Remove incorrect core number probe This probing is already done by decode_configs as part of cpu_probe, and furthermore the implementation here was incorrect for any MT core with a number of VPEs other than 2. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6650/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp-cmp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index 594660ed19dc..3ef55fb7ac03 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -41,7 +41,7 @@ static void cmp_init_secondary(void) { - struct cpuinfo_mips *c = ¤t_cpu_data; + struct cpuinfo_mips *c __maybe_unused = ¤t_cpu_data; /* Assume GIC is present */ change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 | @@ -49,7 +49,6 @@ static void cmp_init_secondary(void) /* Enable per-cpu interrupts: platform specific */ - c->core = (read_c0_ebase() >> 1) & 0x1ff; #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) if (cpu_has_mipsmt) c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & -- cgit From 0c2cb004b262987f7ab84d0c40b7bff74ed5d17b Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 24 Mar 2014 10:19:31 +0000 Subject: MIPS: smp-mt: Use common GIC IPI implementation Rather than duplicating the GIC IPI send function, share the one already used by CONFIG_MIPS_CPS & CONFIG_MIPS_CMP. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Cc: Paul Burton Patchwork: https://patchwork.linux-mips.org/patch/6653/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp-mt.c | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 3378c452e5d7..f8e13149604d 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -113,27 +113,6 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0) write_tc_c0_tchalt(TCHALT_H); } -#ifdef CONFIG_IRQ_GIC -static void mp_send_ipi_single(int cpu, unsigned int action) -{ - unsigned long flags; - - local_irq_save(flags); - - switch (action) { - case SMP_CALL_FUNCTION: - gic_send_ipi(plat_ipi_call_int_xlate(cpu)); - break; - - case SMP_RESCHEDULE_YOURSELF: - gic_send_ipi(plat_ipi_resched_int_xlate(cpu)); - break; - } - - local_irq_restore(flags); -} -#endif - static void vsmp_send_ipi_single(int cpu, unsigned int action) { int i; @@ -142,7 +121,7 @@ static void vsmp_send_ipi_single(int cpu, unsigned int action) #ifdef CONFIG_IRQ_GIC if (gic_present) { - mp_send_ipi_single(cpu, action); + gic_send_ipi_single(cpu, action); return; } #endif -- cgit