From 7eca5b1460f3f1ad3891252743c36f309df53d53 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Tue, 27 Jan 2015 21:45:49 +0000 Subject: MIPS: Remove redundant IPTI==IPPCI logic The situation where the timer interrupt is on the same line as the performance counter interrupt is handled in per_cpu_trap_init() by setting cp0_perfcount_irq to -1, so there is no need to duplicate the logic conditional upon cp0_perfcount_irq >= 0 in perf (init_hw_perf_events()) and oprofile (mipsxx_init()). Signed-off-by: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9125/ Signed-off-by: Ralf Baechle --- arch/mips/oprofile/op_model_mipsxx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/mips/oprofile') diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index faf0d4ad0cc2..24729f023d93 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -435,8 +435,7 @@ static int __init mipsxx_init(void) if (get_c0_perfcount_int) perfcount_irq = get_c0_perfcount_int(); - else if ((cp0_perfcount_irq >= 0) && - (cp0_compare_irq != cp0_perfcount_irq)) + else if (cp0_perfcount_irq >= 0) perfcount_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; else perfcount_irq = -1; -- cgit