From 51e396078412ef91f222b9834f09308746ac7049 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sun, 14 Apr 2013 09:55:29 +0200 Subject: MIPS: ralink: add memory definition for MT7620 Populate struct soc_info with the data that describes our RAM window. Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/5183/ --- arch/mips/ralink/mt7620.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/mips/ralink/mt7620.c') diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index af19ae740162..0018b1a661f6 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -211,4 +211,24 @@ void prom_soc_init(struct ralink_soc_info *soc_info) cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; + + switch (dram_type) { + case SYSCFG0_DRAM_TYPE_SDRAM: + soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; + soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; + break; + + case SYSCFG0_DRAM_TYPE_DDR1: + soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; + soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; + break; + + case SYSCFG0_DRAM_TYPE_DDR2: + soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; + soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; + break; + default: + BUG(); + } + soc_info->mem_base = MT7620_DRAM_BASE; } -- cgit