From 7a6ee0bbab2551d7189ce0f5e625fef4d612ebea Mon Sep 17 00:00:00 2001 From: Arınç ÜNAL Date: Tue, 15 Mar 2022 19:01:50 +0300 Subject: mips: dts: ralink: add MT7621 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc dual-core CPU, a 5-port 10/100/1000 switch/PHY and one RGMII. Add the devicetrees for GB-PC1 and GB-PC2 devices which use MT7621 SoC. Acked-by: Sergio Paracuellos Acked-by: Thomas Bogendoerfer Signed-off-by: Arınç ÜNAL Link: https://lore.kernel.org/r/20220315160149.3617-1-arinc.unal@arinc9.com Signed-off-by: Greg Kroah-Hartman --- arch/mips/ralink/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/mips/ralink') diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 120adad51d6a..f9fe15630abb 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -54,10 +54,15 @@ choice select HAVE_PCI select PCI_DRIVERS_GENERIC select SOC_BUS + + help + The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc dual-core CPU, + a 5-port 10/100/1000 switch/PHY and one RGMII. endchoice choice prompt "Devicetree selection" + depends on !SOC_MT7621 default DTB_RT_NONE help Select the devicetree. -- cgit