From 0cc40dac8605b3b6b099b47cdde9500d592e6583 Mon Sep 17 00:00:00 2001 From: jerin jacob Date: Thu, 11 Oct 2012 22:18:51 +0530 Subject: MIPS: CMP: Fix physical core number calculation logic The CPUNum Field in EBase register is 10bit wide, so after 1 bit right shift, the mask value should be 0x1ff. Signed-off-by: jerin jacob Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4420/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp-cmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index afc379ca3753..06cd0c610f44 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -97,7 +97,7 @@ static void cmp_init_secondary(void) /* Enable per-cpu interrupts: platform specific */ - c->core = (read_c0_ebase() >> 1) & 0xff; + c->core = (read_c0_ebase() >> 1) & 0x1ff; #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE; #endif -- cgit