From 8bcd84a4a37c88d8304ca3a64f0461a51487e239 Mon Sep 17 00:00:00 2001 From: Douglas Leung Date: Mon, 13 Mar 2017 16:36:37 +0100 Subject: MIPS: math-emu: Fix BC1EQZ and BC1NEZ condition handling Correct the treatment of branching conditions for BC1EQZ and BC1NEZ instructions in function isBranchInstr(). Previously, corresponding conditions were swapped, which in turn meant that, for these two instructions, function isBranchInstr() returned wrong value in its output parameter contpc. This change is actually an extension of the fix done by the commit 93583e178ebf ("MIPS: math-emu: Fix BC1{EQ,NE}Z emulation"). That commit dealt with a similar problem in function cop1Emulate(), while this commit deals with condition handling in function isBranchInstr(). The code styles of changes in these two commits are kept as consistent as possible. Signed-off-by: Douglas Leung Signed-off-by: Miodrag Dinic Signed-off-by: Aleksandar Markovic Reviewed-by: Paul Burton Cc: james.hogan@imgtec.com Cc: leonid.yegoshin@imgtec.com Cc: petar.jovanovic@imgtec.com Cc: goran.ferenc@imgtec.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15489/ Signed-off-by: Ralf Baechle --- arch/mips/math-emu/cp1emu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index a298ac93edcc..f12fde10c8ad 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -439,6 +439,8 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, union mips_instruction insn = (union mips_instruction)dec_insn.insn; unsigned int fcr31; unsigned int bit = 0; + unsigned int bit0; + union fpureg *fpr; switch (insn.i_format.opcode) { case spec_op: @@ -706,14 +708,14 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, ((insn.i_format.rs == bc1eqz_op) || (insn.i_format.rs == bc1nez_op))) { bit = 0; + fpr = ¤t->thread.fpu.fpr[insn.i_format.rt]; + bit0 = get_fpr32(fpr, 0) & 0x1; switch (insn.i_format.rs) { case bc1eqz_op: - if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) - bit = 1; + bit = bit0 == 0; break; case bc1nez_op: - if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) - bit = 1; + bit = bit0 != 0; break; } if (bit) -- cgit