From d3a0b968186a7e197b7551e4d6080676372152ce Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Fri, 29 Sep 2017 16:26:31 +0100 Subject: MIPS: Use SLL by 0 for 32-bit truncation in `__read_64bit_c0_split' Optimize `__read_64bit_c0_split' and reduce the instruction count by 1, observing that a DSLL/DSRA pair by 32, is equivalent to SLL by 0, which architecturally truncates the value requested to 32 bits on 64-bit MIPS hardware regardless of whether the input operand is or is not a properly sign-extended 32-bit value. Signed-off-by: Maciej W. Rozycki Reviewed-by: James Hogan Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17399/ Signed-off-by: James Hogan --- arch/mips/include/asm/mipsregs.h | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index a6810923b3f0..6b1f1ad0542c 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1355,19 +1355,17 @@ do { \ if (sel == 0) \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsra\t%M0, %M0, 32\n\t" \ - "dsra\t%L0, %L0, 32\n\t" \ + "dmfc0\t%L0, " #source "\n\t" \ + "dsra\t%M0, %L0, 32\n\t" \ + "sll\t%L0, %L0, 0\n\t" \ ".set\tmips0" \ : "=r" (__val)); \ else \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsra\t%M0, %M0, 32\n\t" \ - "dsra\t%L0, %L0, 32\n\t" \ + "dmfc0\t%L0, " #source ", " #sel "\n\t" \ + "dsra\t%M0, %L0, 32\n\t" \ + "sll\t%L0, %L0, 0\n\t" \ ".set\tmips0" \ : "=r" (__val)); \ local_irq_restore(__flags); \ -- cgit