From 739d875dd6982618020d30f58f8acf10f6076e6d Mon Sep 17 00:00:00 2001 From: David Howells Date: Thu, 8 Mar 2018 09:48:46 +0000 Subject: mn10300: Remove the architecture Remove the MN10300 arch as the hardware is defunct. Suggested-by: Arnd Bergmann Signed-off-by: David Howells cc: Masahiro Yamada cc: linux-am33-list@redhat.com Signed-off-by: Arnd Bergmann --- arch/mn10300/proc-mn103e010/Makefile | 5 - arch/mn10300/proc-mn103e010/include/proc/cache.h | 43 -------- arch/mn10300/proc-mn103e010/include/proc/clock.h | 16 --- .../proc-mn103e010/include/proc/dmactl-regs.h | 102 ------------------ .../proc-mn103e010/include/proc/intctl-regs.h | 30 ------ arch/mn10300/proc-mn103e010/include/proc/irq.h | 34 ------ arch/mn10300/proc-mn103e010/include/proc/proc.h | 18 ---- arch/mn10300/proc-mn103e010/proc-init.c | 115 --------------------- 8 files changed, 363 deletions(-) delete mode 100644 arch/mn10300/proc-mn103e010/Makefile delete mode 100644 arch/mn10300/proc-mn103e010/include/proc/cache.h delete mode 100644 arch/mn10300/proc-mn103e010/include/proc/clock.h delete mode 100644 arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h delete mode 100644 arch/mn10300/proc-mn103e010/include/proc/intctl-regs.h delete mode 100644 arch/mn10300/proc-mn103e010/include/proc/irq.h delete mode 100644 arch/mn10300/proc-mn103e010/include/proc/proc.h delete mode 100644 arch/mn10300/proc-mn103e010/proc-init.c (limited to 'arch/mn10300/proc-mn103e010') diff --git a/arch/mn10300/proc-mn103e010/Makefile b/arch/mn10300/proc-mn103e010/Makefile deleted file mode 100644 index ac2c9784cd21..000000000000 --- a/arch/mn10300/proc-mn103e010/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the MN103E010 processor chip specific code -# -obj-y := proc-init.o - diff --git a/arch/mn10300/proc-mn103e010/include/proc/cache.h b/arch/mn10300/proc-mn103e010/include/proc/cache.h deleted file mode 100644 index 967d144f307e..000000000000 --- a/arch/mn10300/proc-mn103e010/include/proc/cache.h +++ /dev/null @@ -1,43 +0,0 @@ -/* MN103E010 Cache specification - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_PROC_CACHE_H -#define _ASM_PROC_CACHE_H - -/* L1 cache */ - -#define L1_CACHE_NWAYS 4 /* number of ways in caches */ -#define L1_CACHE_NENTRIES 256 /* number of entries in each way */ -#define L1_CACHE_BYTES 16 /* bytes per entry */ -#define L1_CACHE_SHIFT 4 /* shift for bytes per entry */ -#define L1_CACHE_WAYDISP 0x1000 /* displacement of one way from the next */ - -#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */ -#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */ -#define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */ -#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */ -#define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY) - -/* - * specification of the interval between interrupt checking intervals whilst - * managing the cache with the interrupts disabled - */ -#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4 - -/* - * The size of range at which it becomes more economical to just flush the - * whole cache rather than trying to flush the specified range. - */ -#define MN10300_DCACHE_FLUSH_BORDER \ - +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES) -#define MN10300_DCACHE_FLUSH_INV_BORDER \ - +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES) - -#endif /* _ASM_PROC_CACHE_H */ diff --git a/arch/mn10300/proc-mn103e010/include/proc/clock.h b/arch/mn10300/proc-mn103e010/include/proc/clock.h deleted file mode 100644 index 704a819f1f4b..000000000000 --- a/arch/mn10300/proc-mn103e010/include/proc/clock.h +++ /dev/null @@ -1,16 +0,0 @@ -/* MN103E010-specific clocks - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_PROC_CLOCK_H -#define _ASM_PROC_CLOCK_H - -#include - -#endif /* _ASM_PROC_CLOCK_H */ diff --git a/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h b/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h deleted file mode 100644 index d72d328d1f9c..000000000000 --- a/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h +++ /dev/null @@ -1,102 +0,0 @@ -/* MN103E010 on-board DMA controller registers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_PROC_DMACTL_REGS_H -#define _ASM_PROC_DMACTL_REGS_H - -#include - -#ifdef __KERNEL__ - -/* DMA registers */ -#define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */ -#define DMxCTR_BG 0x0000001f /* transfer request source */ -#define DMxCTR_BG_SOFT 0x00000000 /* - software source */ -#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */ -#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */ -#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */ -#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */ -#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */ -#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */ -#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */ -#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */ -#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */ -#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */ -#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */ -#define DMxCTR_BG_AFE 0x0000000d /* - analogue front-end interrupt source */ -#define DMxCTR_BG_ADC 0x0000000e /* - A/D conversion end interrupt source */ -#define DMxCTR_BG_IRDA 0x0000000f /* - IrDA interrupt source */ -#define DMxCTR_BG_RTC 0x00000010 /* - RTC interrupt source */ -#define DMxCTR_BG_XIRQ0 0x00000011 /* - XIRQ0 pin interrupt source */ -#define DMxCTR_BG_XIRQ1 0x00000012 /* - XIRQ1 pin interrupt source */ -#define DMxCTR_BG_XDMR0 0x00000013 /* - external request 0 source (XDMR0 pin) */ -#define DMxCTR_BG_XDMR1 0x00000014 /* - external request 1 source (XDMR1 pin) */ -#define DMxCTR_SAM 0x000000e0 /* DMA transfer src addr mode */ -#define DMxCTR_SAM_INCR 0x00000000 /* - increment */ -#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */ -#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */ -#define DMxCTR_DAM 0x00000000 /* DMA transfer dest addr mode */ -#define DMxCTR_DAM_INCR 0x00000000 /* - increment */ -#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */ -#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */ -#define DMxCTR_TM 0x00001800 /* DMA transfer mode */ -#define DMxCTR_TM_BATCH 0x00000000 /* - batch transfer */ -#define DMxCTR_TM_INTERM 0x00001000 /* - intermittent transfer */ -#define DMxCTR_UT 0x00006000 /* DMA transfer unit */ -#define DMxCTR_UT_1 0x00000000 /* - 1 byte */ -#define DMxCTR_UT_2 0x00002000 /* - 2 byte */ -#define DMxCTR_UT_4 0x00004000 /* - 4 byte */ -#define DMxCTR_UT_16 0x00006000 /* - 16 byte */ -#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */ -#define DMxCTR_RQM 0x00060000 /* external request input source mode */ -#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */ -#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */ -#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */ -#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */ -#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */ -#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */ - -#define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */ - -#define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */ - -#define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */ -#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */ - -#define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent - * size reg */ -#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */ - -#define DM0IRQ 16 /* DMA channel 0 complete IRQ */ -#define DM1IRQ 17 /* DMA channel 1 complete IRQ */ -#define DM2IRQ 18 /* DMA channel 2 complete IRQ */ -#define DM3IRQ 19 /* DMA channel 3 complete IRQ */ - -#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */ -#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */ -#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */ -#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */ - -#ifndef __ASSEMBLY__ - -struct mn10300_dmactl_regs { - u32 ctr; - const void *src; - void *dst; - u32 siz; - u32 cyc; -} __attribute__((aligned(0x100))); - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_PROC_DMACTL_REGS_H */ diff --git a/arch/mn10300/proc-mn103e010/include/proc/intctl-regs.h b/arch/mn10300/proc-mn103e010/include/proc/intctl-regs.h deleted file mode 100644 index 516afe824055..000000000000 --- a/arch/mn10300/proc-mn103e010/include/proc/intctl-regs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_PROC_INTCTL_REGS_H -#define _ASM_PROC_INTCTL_REGS_H - -#ifndef _ASM_INTCTL_REGS_H -# error "please don't include this file directly" -#endif - -/* intr acceptance group reg */ -#define IAGR __SYSREG(0xd4000100, u16) - -/* group number register */ -#define IAGR_GN 0x00fc - -#define __GET_XIRQ_TRIGGER(X, Z) (((Z) >> ((X) * 2)) & 3) - -#define __SET_XIRQ_TRIGGER(X, Y, Z) \ -({ \ - typeof(Z) x = (Z); \ - x &= ~(3 << ((X) * 2)); \ - x |= ((Y) & 3) << ((X) * 2); \ - (Z) = x; \ -}) - -/* external pin intr spec reg */ -#define EXTMD __SYSREG(0xd4000200, u16) -#define GET_XIRQ_TRIGGER(X) __GET_XIRQ_TRIGGER(X, EXTMD) -#define SET_XIRQ_TRIGGER(X, Y) __SET_XIRQ_TRIGGER(X, Y, EXTMD) - -#endif /* _ASM_PROC_INTCTL_REGS_H */ diff --git a/arch/mn10300/proc-mn103e010/include/proc/irq.h b/arch/mn10300/proc-mn103e010/include/proc/irq.h deleted file mode 100644 index aa6ee8f98b1b..000000000000 --- a/arch/mn10300/proc-mn103e010/include/proc/irq.h +++ /dev/null @@ -1,34 +0,0 @@ -/* MN103E010 On-board interrupt controller numbers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_PROC_IRQ_H -#define _ASM_PROC_IRQ_H - -#ifdef __KERNEL__ - -#define GxICR_NUM_IRQS 42 - -#define GxICR_NUM_XIRQS 8 - -#define XIRQ0 34 -#define XIRQ1 35 -#define XIRQ2 36 -#define XIRQ3 37 -#define XIRQ4 38 -#define XIRQ5 39 -#define XIRQ6 40 -#define XIRQ7 41 - -#define XIRQ2IRQ(num) (XIRQ0 + num) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_PROC_IRQ_H */ diff --git a/arch/mn10300/proc-mn103e010/include/proc/proc.h b/arch/mn10300/proc-mn103e010/include/proc/proc.h deleted file mode 100644 index 39c4f8e7d2d3..000000000000 --- a/arch/mn10300/proc-mn103e010/include/proc/proc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* MN103E010 Processor description - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_PROC_PROC_H -#define _ASM_PROC_PROC_H - -#define PROCESSOR_VENDOR_NAME "Panasonic" -#define PROCESSOR_MODEL_NAME "mn103e010" - -#endif /* _ASM_PROC_PROC_H */ diff --git a/arch/mn10300/proc-mn103e010/proc-init.c b/arch/mn10300/proc-mn103e010/proc-init.c deleted file mode 100644 index 102d86a6ae56..000000000000 --- a/arch/mn10300/proc-mn103e010/proc-init.c +++ /dev/null @@ -1,115 +0,0 @@ -/* MN103E010 Processor initialisation - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include - -/* - * initialise the on-silicon processor peripherals - */ -asmlinkage void __init processor_init(void) -{ - int loop; - - /* set up the exception table first */ - for (loop = 0x000; loop < 0x400; loop += 8) - __set_intr_stub(loop, __common_exception); - - __set_intr_stub(EXCEP_ITLBMISS, itlb_miss); - __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss); - __set_intr_stub(EXCEP_IAERROR, itlb_aerror); - __set_intr_stub(EXCEP_DAERROR, dtlb_aerror); - __set_intr_stub(EXCEP_BUSERROR, raw_bus_error); - __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault); - __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled); - __set_intr_stub(EXCEP_SYSCALL0, system_call); - - __set_intr_stub(EXCEP_NMI, nmi_handler); - __set_intr_stub(EXCEP_WDT, nmi_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler); - - IVAR0 = EXCEP_IRQ_LEVEL0; - IVAR1 = EXCEP_IRQ_LEVEL1; - IVAR2 = EXCEP_IRQ_LEVEL2; - IVAR3 = EXCEP_IRQ_LEVEL3; - IVAR4 = EXCEP_IRQ_LEVEL4; - IVAR5 = EXCEP_IRQ_LEVEL5; - IVAR6 = EXCEP_IRQ_LEVEL6; - - mn10300_dcache_flush_inv(); - mn10300_icache_inv(); - - /* disable all interrupts and set to priority 6 (lowest) */ - for (loop = 0; loop < NR_IRQS; loop++) - GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; - - /* clear the timers */ - TM0MD = 0; - TM1MD = 0; - TM2MD = 0; - TM3MD = 0; - TM4MD = 0; - TM5MD = 0; - TM6MD = 0; - TM6MDA = 0; - TM6MDB = 0; - TM7MD = 0; - TM8MD = 0; - TM9MD = 0; - TM10MD = 0; - TM11MD = 0; - - calibrate_clock(); -} - -/* - * determine the memory size and base from the memory controller regs - */ -void __init get_mem_info(unsigned long *mem_base, unsigned long *mem_size) -{ - unsigned long base, size; - - *mem_base = 0; - *mem_size = 0; - - base = SDBASE(0); - if (base & SDBASE_CE) { - size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT; - size = ~size + 1; - base &= SDBASE_CBA; - - printk(KERN_INFO "SDRAM[0]: %luMb @%08lx\n", size >> 20, base); - *mem_size += size; - *mem_base = base; - } - - base = SDBASE(1); - if (base & SDBASE_CE) { - size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT; - size = ~size + 1; - base &= SDBASE_CBA; - - printk(KERN_INFO "SDRAM[1]: %luMb @%08lx\n", size >> 20, base); - *mem_size += size; - if (*mem_base == 0) - *mem_base = base; - } -} -- cgit