From 8e6d08e0a15e7d4d4b608b56597350d4cdd77710 Mon Sep 17 00:00:00 2001 From: Stefan Kristiansson Date: Sun, 11 May 2014 21:49:34 +0300 Subject: openrisc: initial SMP support This patch introduces the SMP support for the OpenRISC architecture. The SMP architecture requires cores which have multi-core features which have been introduced a few years back including: - New SPRS SPR_COREID SPR_NUMCORES - Shadow SPRs - Atomic Instructions - Cache Coherency - A wired in IPI controller This patch adds all of the SMP specific changes to core infrastructure, it looks big but it needs to go all together as its hard to split this one up. Boot loader spinning of second cpu is not supported yet, it's assumed that Linux is booted straight after cpu reset. The bulk of these changes are trivial changes to refactor to use per cpu data structures throughout. The addition of the smp.c and changes in time.c are the changes. Some specific notes: MM changes ---------- The reason why this is created as an array, and not with DEFINE_PER_CPU is that doing it this way, we'll save a load in the tlb-miss handler (the load from __per_cpu_offset). TLB Flush --------- The SMP implementation of flush_tlb_* works by sending out a function-call IPI to all the non-local cpus by using the generic on_each_cpu() function. Currently, all flush_tlb_* functions will result in a flush_tlb_all(), which has always been the behaviour in the UP case. CPU INFO -------- This creates a per cpu cpuinfo struct and fills it out accordingly for each activated cpu. show_cpuinfo is also updated to reflect new version information in later versions of the spec. SMP API ------- This imitates the arm64 implementation by having a smp_cross_call callback that can be set by set_smp_cross_call to initiate an IPI and a handle_IPI function that is expected to be called from an IPI irqchip driver. Signed-off-by: Stefan Kristiansson [shorne@gmail.com: added cpu stop, checkpatch fixes, wrote commit message] Signed-off-by: Stafford Horne --- arch/openrisc/kernel/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/openrisc/kernel/Makefile') diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile index ec6d9d37cefd..7d94643c878d 100644 --- a/arch/openrisc/kernel/Makefile +++ b/arch/openrisc/kernel/Makefile @@ -8,6 +8,7 @@ obj-y := setup.o or32_ksyms.o process.o dma.o \ traps.o time.o irq.o entry.o ptrace.o signal.o \ sys_call_table.o +obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_OF) += prom.o -- cgit From eecac38b0423a69715073ecbde581dafd1abb28b Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Mon, 24 Jul 2017 21:44:35 +0900 Subject: openrisc: support framepointers and STACKTRACE_SUPPORT For lockdep support a reliable stack trace mechanism is needed. This patch adds support in OpenRISC for the stacktrace framework, implemented by a simple unwinder api. The unwinder api supports both framepointer and basic stack tracing. The unwinder is now used to replace the stack_dump() implementation as well. The new traces are inline with other architectures trace format: Call trace: [] show_stack+0x3c/0x58 [] dump_stack+0xa8/0xe4 [] __cpu_up+0x64/0x130 [] bringup_cpu+0x3c/0x178 [] cpuhp_invoke_callback+0xa8/0x1fc [] cpuhp_up_callbacks+0x44/0x14c [] cpu_up+0x14c/0x1bc [] smp_init+0x104/0x15c [] ? kernel_init+0x0/0x140 [] kernel_init_freeable+0xbc/0x25c [] ? kernel_init+0x0/0x140 [] kernel_init+0x1c/0x140 [] ? schedule_tail+0x18/0xa0 [] ret_from_fork+0x1c/0x9c Signed-off-by: Stafford Horne --- arch/openrisc/kernel/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/openrisc/kernel/Makefile') diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile index 7d94643c878d..b4b51a07016a 100644 --- a/arch/openrisc/kernel/Makefile +++ b/arch/openrisc/kernel/Makefile @@ -6,9 +6,10 @@ extra-y := head.o vmlinux.lds obj-y := setup.o or32_ksyms.o process.o dma.o \ traps.o time.o irq.o entry.o ptrace.o signal.o \ - sys_call_table.o + sys_call_table.o unwinder.o obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_OF) += prom.o -- cgit From 4553474d977d1ee8a81067cfbc588f1df84ce3e9 Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Fri, 7 Jul 2017 06:06:30 +0900 Subject: openrisc: add tick timer multi-core sync logic In case timers are not in sync when cpus start (i.e. hot plug / offset resets) we need to synchronize the secondary cpus internal timer with the main cpu. This is needed as in OpenRISC SMP there is only one clocksource registered which reads from the same ttcr register on each cpu. This synchronization routine heavily borrows from mips implementation that does something similar. Signed-off-by: Stafford Horne --- arch/openrisc/kernel/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/openrisc/kernel/Makefile') diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile index b4b51a07016a..9028e5a1fdd7 100644 --- a/arch/openrisc/kernel/Makefile +++ b/arch/openrisc/kernel/Makefile @@ -8,7 +8,7 @@ obj-y := setup.o or32_ksyms.o process.o dma.o \ traps.o time.o irq.o entry.o ptrace.o signal.o \ sys_call_table.o unwinder.o -obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SMP) += smp.o sync-timer.o obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_OF) += prom.o -- cgit