From 1fc7db2401d62df5a0b19250ddf3bb89d430dd86 Mon Sep 17 00:00:00 2001 From: John David Anglin Date: Wed, 30 Mar 2022 14:42:30 +0000 Subject: parisc: Don't enforce DMA completion order in cache flushes The only place we need to ensure all outstanding cache coherence operations are complete is in invalidate_kernel_vmap_range. All parisc drivers synchronize DMA operations internally and do not call invalidate_kernel_vmap_range. We only need this for non-coherent I/O operations. Signed-off-by: John David Anglin Signed-off-by: Helge Deller --- arch/parisc/include/asm/cache.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/parisc/include/asm/cache.h') diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h index 5032e758594e..e23d06b51a20 100644 --- a/arch/parisc/include/asm/cache.h +++ b/arch/parisc/include/asm/cache.h @@ -54,6 +54,7 @@ void parisc_setup_cache_timing(void); #define asm_io_sync() asm volatile("sync" \ ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \ ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory") +#define asm_syncdma() asm volatile("syncdma" :::"memory") #endif /* ! __ASSEMBLY__ */ -- cgit