From 62f64b49d04dc70687cd713c804fecd80216b2d6 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Tue, 17 May 2016 09:02:56 +0200 Subject: powerpc/8xx: add CONFIG_PIN_TLB_IMMR CONFIG_PIN_TLB maps IMMR area and the first 24 Mbytes of memory. In some circunstances it might be more interesting to not map IMMR but map 32 Mbytes of memory instead. Therefore we add config option CONFIG_PIN_TLB_IMMR to select if IMMR shall be pinned or not, hence whether we pin 24 or 32 Mbytes of RAM Signed-off-by: Christophe Leroy Signed-off-by: Scott Wood --- arch/powerpc/kernel/head_8xx.S | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/powerpc/kernel/head_8xx.S') diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 00cc9df7d322..43ddaae42baf 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -414,11 +414,11 @@ DataStoreTLBMiss: */ mfspr r11, SPRN_MD_EPN rlwinm r11, r11, 16, 0xfff8 -#ifndef CONFIG_PIN_TLB +#ifndef CONFIG_PIN_TLB_IMMR cmpli cr0, r11, VIRT_IMMR_BASE@h #endif cmpli cr7, r11, PAGE_OFFSET@h -#ifndef CONFIG_PIN_TLB +#ifndef CONFIG_PIN_TLB_IMMR _ENTRY(DTLBMiss_jmp) beq- DTLBMissIMMR #endif @@ -819,7 +819,6 @@ initial_mmu: #ifdef CONFIG_PIN_TLB oris r10, r10, MD_RSV4I@h - ori r10, r10, 0x1c00 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ #endif @@ -843,7 +842,10 @@ initial_mmu: /* Map a 512k page for the IMMR to get the processor * internal registers (among other things). */ -#ifdef CONFIG_PIN_TLB +#ifdef CONFIG_PIN_TLB_IMMR + ori r10, r10, 0x1c00 + mtspr SPRN_MD_CTR, r10 + mfspr r9, 638 /* Get current IMMR */ andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */ -- cgit