From 5b28df37d311ef95e6349af97e423842817bf06a Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Mon, 14 Feb 2022 13:58:39 +0000 Subject: riscv: dts: microchip: update peripherals in icicle kit device tree Assorted minor changes to the MPFS/Icicle kit device tree: - enable mmuart4 instead of mmuart0 - remove sifive pdma - split memory node to match updated fpga design - move stdout path to serial1 to avoid collision with bootloader running on the e51 Signed-off-by: Conor Dooley Acked-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- .../dts/microchip/microchip-mpfs-icicle-kit.dts | 23 +++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts') diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index c51bd7cf500f..dc5f351b10c4 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -18,20 +18,29 @@ serial1 = &mmuart1; serial2 = &mmuart2; serial3 = &mmuart3; + serial4 = &mmuart4; }; chosen { - stdout-path = "serial0:115200n8"; + stdout-path = "serial1:115200n8"; }; cpus { timebase-frequency = ; }; - memory@80000000 { + ddrc_cache_lo: memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; + reg = <0x0 0x80000000 0x0 0x2e000000>; clocks = <&clkcfg CLK_DDRC>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x0 0x0 0x40000000>; + clocks = <&clkcfg CLK_DDRC>; + status = "okay"; }; }; @@ -39,10 +48,6 @@ clock-frequency = <600000000>; }; -&mmuart0 { - status = "okay"; -}; - &mmuart1 { status = "okay"; }; @@ -55,6 +60,10 @@ status = "okay"; }; +&mmuart4 { + status = "okay"; +}; + &mmc { status = "okay"; -- cgit