From 8263a67e169fdf0d06d172acbf6c03ae172a69d4 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 17 Mar 2009 17:49:49 +0900 Subject: sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores. This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt --- arch/sh/Kconfig.cpu | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/sh/Kconfig.cpu') diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu index 0e27fe3b182b..c7d704381a6d 100644 --- a/arch/sh/Kconfig.cpu +++ b/arch/sh/Kconfig.cpu @@ -104,6 +104,9 @@ config CPU_HAS_SR_RB config CPU_HAS_PTEA bool +config CPU_HAS_PTEAEX + bool + config CPU_HAS_DSP bool -- cgit