From f29cf77609cc401d28e2e7ec5c57d9d178ef347d Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Tue, 13 Jun 2023 16:51:18 -0700 Subject: xtensa: add load/store exception handler Memory attached to instruction bus of the xtensa CPU is only accessible for a limited subset of opcodes. Other opcodes generate an exception with the load/store error cause code. This property complicates use of such systems. Provide a handler that recognizes and transparently fixes such exceptions. The following opcodes are recognized when used outside of FLIX bundles: l32i, l32i.n, l16ui, l16si, l8ui. Signed-off-by: Max Filippov --- arch/xtensa/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/xtensa/Kconfig') diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 45f72c8fa911..c1bcfc2a8581 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -203,6 +203,18 @@ config XTENSA_UNALIGNED_USER Say Y here to enable unaligned memory access in user space. +config XTENSA_LOAD_STORE + bool "Load/store exception handler for memory only readable with l32" + help + The Xtensa architecture only allows reading memory attached to its + instruction bus with l32r and l32i instructions, all other + instructions raise an exception with the LoadStoreErrorCause code. + This makes it hard to use some configurations, e.g. store string + literals in FLASH memory attached to the instruction bus. + + Say Y here to enable exception handler that allows transparent + byte and 2-byte access to memory attached to instruction bus. + config HAVE_SMP bool "System Supports SMP (MX)" depends on XTENSA_VARIANT_CUSTOM -- cgit