From 89b184f980f012421fb22c939b50b3dfd7fe16b3 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Tue, 28 Dec 2021 01:28:53 -0800 Subject: xtensa: make secondary reset vector support conditional Whether xtensa cores start from primary or secondary reset vector is configurable and may be chosen by board designer or controlled at runtime. When secondary reset vector is unused its location in memory may not be writable. Make secondary reset vector support conditional and don't build and load secondary reset vector code when it is disabled. Signed-off-by: Max Filippov --- arch/xtensa/kernel/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/xtensa/kernel/Makefile') diff --git a/arch/xtensa/kernel/Makefile b/arch/xtensa/kernel/Makefile index d4082c6a121b..5fd6cd15e0fb 100644 --- a/arch/xtensa/kernel/Makefile +++ b/arch/xtensa/kernel/Makefile @@ -13,7 +13,8 @@ obj-$(CONFIG_MMU) += pci-dma.o obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_MODULES) += xtensa_ksyms.o module.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o -obj-$(CONFIG_SMP) += smp.o mxhead.o +obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SECONDARY_RESET_VECTOR) += mxhead.o obj-$(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) += perf_event.o obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o obj-$(CONFIG_S32C1I_SELFTEST) += s32c1i_selftest.o -- cgit