From 640356a48750ff9ef3303d85158ef9c42c3a18b6 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 17 May 2016 15:31:04 +0100 Subject: MIPS: Clear Status IPL field when using EIC When using an external interrupt controller (EIC) the interrupt mask bits in the cop0 Status register are reused for the Interrupt Priority Level, and any interrupts with a priority lower than the field will be ignored. Clear the field to 0 by default such that all interrupts are serviced. Without doing so we default to arbitrarily ignoring all or some subset of interrupts. Signed-off-by: Paul Burton Reviewed-by: Matt Redfearn Tested-by: Matt Redfearn Cc: Guenter Roeck Cc: Sergei Shtylyov Cc: Joe Perches Cc: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13272/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/irq.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 8eb5af805964..f25f7eab7307 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -54,6 +54,9 @@ void __init init_IRQ(void) for (i = 0; i < NR_IRQS; i++) irq_set_noprobe(i); + if (cpu_has_veic) + clear_c0_status(ST0_IM); + arch_init_irq(); } -- cgit