From f8ce138029058fb7b144b866ae5cdb98db58f4fb Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Mon, 8 Jan 2018 07:30:55 -0500 Subject: ARM: dts: r7s72100: add USB device to device tree Add USB device support. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index ab9645a42eca..bd6366d1800b 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -667,4 +667,24 @@ power-domains = <&cpg_clocks>; status = "disabled"; }; + + usbhs0: usb@e8010000 { + compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; + reg = <0xe8010000 0x1a0>; + interrupts = ; + clocks = <&mstp7_clks R7S72100_CLK_USB0>; + renesas,buswait = <4>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + usbhs1: usb@e8207000 { + compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; + reg = <0xe8207000 0x1a0>; + interrupts = ; + clocks = <&mstp7_clks R7S72100_CLK_USB1>; + renesas,buswait = <4>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; }; -- cgit From b1548238b2252199b7ea217abbc3d96b742c7e63 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 12 Feb 2018 15:39:27 +0100 Subject: ARM: dts: r7s72100: add soc node Add soc node to represent the bus and move all nodes with a base address into this node. This is consistent with handling of R-Car Gen3 and Gen2 SoCs in mainline. It is intended to migrate other Renesas ARM-based SoCs to this scheme. The ordering is derived from simply moving each node with an address up to before any nodes without a base address that occur before the soc node. To improve maintainability follow-up patches will sort subnodes of both the new soc node and the root node. This patch should not introduce any functional change. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r7s72100.dtsi | 910 ++++++++++++++++++++-------------------- 1 file changed, 459 insertions(+), 451 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index bd6366d1800b..0aa74355e24f 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -15,7 +15,6 @@ / { compatible = "renesas,r7s72100"; - interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; @@ -87,6 +86,29 @@ clock-mult = <1>; clock-div = <12>; }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <400000000>; + clocks = <&cpg_clocks R7S72100_CLK_I>; + next-level-cache = <&L2>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; /* Special CPG clocks */ cpg_clocks: cpg_clocks@fcfe0000 { @@ -192,499 +214,485 @@ >; clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <400000000>; - clocks = <&cpg_clocks R7S72100_CLK_I>; - next-level-cache = <&L2>; + pinctrl: pin-controller@fcfe3000 { + compatible = "renesas,r7s72100-ports"; + + reg = <0xfcfe3000 0x4230>; + + port0: gpio-0 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 6>; + }; + + port1: gpio-1 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + port2: gpio-2 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + port3: gpio-3 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + port4: gpio-4 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + port5: gpio-5 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 80 11>; + }; + + port6: gpio-6 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + port7: gpio-7 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + port8: gpio-8 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + port9: gpio-9 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 144 8>; + }; + + port10: gpio-10 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 160 16>; + }; + + port11: gpio-11 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 176 16>; + }; }; - }; - pinctrl: pin-controller@fcfe3000 { - compatible = "renesas,r7s72100-ports"; - - reg = <0xfcfe3000 0x4230>; - - port0: gpio-0 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 6>; + scif0: serial@e8007000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8007000 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; }; - port1: gpio-1 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 16 16>; + scif1: serial@e8007800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8007800 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; }; - port2: gpio-2 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 32 16>; + scif2: serial@e8008000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8008000 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; }; - port3: gpio-3 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 48 16>; + scif3: serial@e8008800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8008800 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; }; - port4: gpio-4 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 64 16>; + scif4: serial@e8009000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8009000 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; }; - port5: gpio-5 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 80 11>; + scif5: serial@e8009800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8009800 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; }; - port6: gpio-6 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 96 16>; + scif6: serial@e800a000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe800a000 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; }; - port7: gpio-7 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 112 16>; + scif7: serial@e800a800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe800a800 64>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; }; - port8: gpio-8 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 128 16>; + spi0: spi@e800c800 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800c800 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI0>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; - port9: gpio-9 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 144 8>; + spi1: spi@e800d000 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800d000 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI1>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; - port10: gpio-10 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 160 16>; + spi2: spi@e800d800 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800d800 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI2>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; - port11: gpio-11 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 176 16>; + spi3: spi@e800e000 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800e000 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI3>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; - }; - - scif0: serial@e8007000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8007000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif1: serial@e8007800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8007800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif2: serial@e8008000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8008000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif3: serial@e8008800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8008800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif4: serial@e8009000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8009000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif5: serial@e8009800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8009800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif6: serial@e800a000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe800a000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif7: serial@e800a800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe800a800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - spi0: spi@e800c800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800c800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI0>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@e800d000 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800d000 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI1>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@e800d800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800d800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI2>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - spi3: spi@e800e000 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800e000 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI3>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@e800e800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800e800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI4>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + spi4: spi@e800e800 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800e800 0x24>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI4>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - gic: interrupt-controller@e8201000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0xe8201000 0x1000>, - <0xe8202000 0x1000>; - }; + gic: interrupt-controller@e8201000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe8201000 0x1000>, + <0xe8202000 0x1000>; + }; - L2: cache-controller@3ffff000 { - compatible = "arm,pl310-cache"; - reg = <0x3ffff000 0x1000>; - interrupts = ; - arm,early-bresp-disable; - arm,full-line-zero-disable; - cache-unified; - cache-level = <2>; - }; + L2: cache-controller@3ffff000 { + compatible = "arm,pl310-cache"; + reg = <0x3ffff000 0x1000>; + interrupts = ; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; + }; - wdt: watchdog@fcfe0000 { - compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; - reg = <0xfcfe0000 0x6>; - interrupts = ; - clocks = <&p0_clk>; - }; + wdt: watchdog@fcfe0000 { + compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; + reg = <0xfcfe0000 0x6>; + interrupts = ; + clocks = <&p0_clk>; + }; - i2c0: i2c@fcfee000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee000 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp9_clks R7S72100_CLK_I2C0>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; + i2c0: i2c@fcfee000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee000 0x44>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp9_clks R7S72100_CLK_I2C0>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; - i2c1: i2c@fcfee400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee400 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp9_clks R7S72100_CLK_I2C1>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; + i2c1: i2c@fcfee400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee400 0x44>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp9_clks R7S72100_CLK_I2C1>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; - i2c2: i2c@fcfee800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee800 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp9_clks R7S72100_CLK_I2C2>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; + i2c2: i2c@fcfee800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee800 0x44>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp9_clks R7S72100_CLK_I2C2>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; - i2c3: i2c@fcfeec00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfeec00 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp9_clks R7S72100_CLK_I2C3>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; + i2c3: i2c@fcfeec00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfeec00 0x44>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp9_clks R7S72100_CLK_I2C3>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; - mtu2: timer@fcff0000 { - compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; - reg = <0xfcff0000 0x400>; - interrupts = ; - interrupt-names = "tgi0a"; - clocks = <&mstp3_clks R7S72100_CLK_MTU2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; + mtu2: timer@fcff0000 { + compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; + reg = <0xfcff0000 0x400>; + interrupts = ; + interrupt-names = "tgi0a"; + clocks = <&mstp3_clks R7S72100_CLK_MTU2>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; - ether: ethernet@e8203000 { - compatible = "renesas,ether-r7s72100"; - reg = <0xe8203000 0x800>, - <0xe8204800 0x200>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_ETHER>; - power-domains = <&cpg_clocks>; - phy-mode = "mii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + ether: ethernet@e8203000 { + compatible = "renesas,ether-r7s72100"; + reg = <0xe8203000 0x800>, + <0xe8204800 0x200>; + interrupts = ; + clocks = <&mstp7_clks R7S72100_CLK_ETHER>; + power-domains = <&cpg_clocks>; + phy-mode = "mii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - mmcif: mmc@e804c800 { - compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; - reg = <0xe804c800 0x80>; - interrupts = ; - clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; - power-domains = <&cpg_clocks>; - reg-io-width = <4>; - bus-width = <8>; - status = "disabled"; - }; + mmcif: mmc@e804c800 { + compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; + reg = <0xe804c800 0x80>; + interrupts = ; + clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; + power-domains = <&cpg_clocks>; + reg-io-width = <4>; + bus-width = <8>; + status = "disabled"; + }; - sdhi0: sd@e804e000 { - compatible = "renesas,sdhi-r7s72100"; - reg = <0xe804e000 0x100>; - interrupts = ; - - clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, - <&mstp12_clks R7S72100_CLK_SDHI01>; - clock-names = "core", "cd"; - power-domains = <&cpg_clocks>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; + sdhi0: sd@e804e000 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e000 0x100>; + interrupts = ; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, + <&mstp12_clks R7S72100_CLK_SDHI01>; + clock-names = "core", "cd"; + power-domains = <&cpg_clocks>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; - sdhi1: sd@e804e800 { - compatible = "renesas,sdhi-r7s72100"; - reg = <0xe804e800 0x100>; - interrupts = ; - - clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, - <&mstp12_clks R7S72100_CLK_SDHI11>; - clock-names = "core", "cd"; - power-domains = <&cpg_clocks>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; + sdhi1: sd@e804e800 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e800 0x100>; + interrupts = ; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, + <&mstp12_clks R7S72100_CLK_SDHI11>; + clock-names = "core", "cd"; + power-domains = <&cpg_clocks>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; - ostm0: timer@fcfec000 { - compatible = "renesas,r7s72100-ostm", "renesas,ostm"; - reg = <0xfcfec000 0x30>; - interrupts = ; - clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; + ostm0: timer@fcfec000 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec000 0x30>; + interrupts = ; + clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; - ostm1: timer@fcfec400 { - compatible = "renesas,r7s72100-ostm", "renesas,ostm"; - reg = <0xfcfec400 0x30>; - interrupts = ; - clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; + ostm1: timer@fcfec400 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec400 0x30>; + interrupts = ; + clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; - rtc: rtc@fcff1000 { - compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; - reg = <0xfcff1000 0x2e>; - interrupts = ; - interrupt-names = "alarm", "period", "carry"; - clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, - <&rtc_x3_clk>, <&extal_clk>; - clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; + rtc: rtc@fcff1000 { + compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; + reg = <0xfcff1000 0x2e>; + interrupts = ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, + <&rtc_x3_clk>, <&extal_clk>; + clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; - usbhs0: usb@e8010000 { - compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; - reg = <0xe8010000 0x1a0>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_USB0>; - renesas,buswait = <4>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; + usbhs0: usb@e8010000 { + compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; + reg = <0xe8010000 0x1a0>; + interrupts = ; + clocks = <&mstp7_clks R7S72100_CLK_USB0>; + renesas,buswait = <4>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; - usbhs1: usb@e8207000 { - compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; - reg = <0xe8207000 0x1a0>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_USB1>; - renesas,buswait = <4>; - power-domains = <&cpg_clocks>; - status = "disabled"; + usbhs1: usb@e8207000 { + compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; + reg = <0xe8207000 0x1a0>; + interrupts = ; + clocks = <&mstp7_clks R7S72100_CLK_USB1>; + renesas,buswait = <4>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; }; }; -- cgit From f7255d1fa215fd68be876b0de5e2bf68eadfe9cf Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 12 Feb 2018 15:39:28 +0100 Subject: ARM: dts: r7s72100: sort subnodes of soc node Sort the subnodes of the soc node to improve maintainability. The sort key is the address on the bus with instances of the same IP block grouped together and sorted alphabetically. This patch should not introduce any functional change. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r7s72100.dtsi | 570 ++++++++++++++++++++-------------------- 1 file changed, 285 insertions(+), 285 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 0aa74355e24f..0d63dbe11e0d 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -110,187 +110,14 @@ #size-cells = <1>; ranges; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@fcfe0000 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-cpg-clocks", - "renesas,rz-cpg-clocks"; - reg = <0xfcfe0000 0x18>; - clocks = <&extal_clk>, <&usb_x1_clk>; - clock-output-names = "pll", "i", "g"; - #power-domain-cells = <0>; - }; - - /* MSTP clocks */ - mstp3_clks: mstp3_clks@fcfe0420 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0420 4>; - clocks = <&p0_clk>; - clock-indices = ; - clock-output-names = "mtu2"; - }; - - mstp4_clks: mstp4_clks@fcfe0424 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0424 4>; - clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, - <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; - clock-indices = < - R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 - R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 - >; - clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; - }; - - mstp5_clks: mstp5_clks@fcfe0428 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0428 4>; - clocks = <&p0_clk>, <&p0_clk>; - clock-indices = ; - clock-output-names = "ostm0", "ostm1"; - }; - - mstp6_clks: mstp6_clks@fcfe042c { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe042c 4>; - clocks = <&p0_clk>; - clock-indices = ; - clock-output-names = "rtc"; - }; - - mstp7_clks: mstp7_clks@fcfe0430 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0430 4>; - clocks = <&b_clk>, <&p1_clk>, <&p1_clk>; - clock-indices = ; - clock-output-names = "ether", "usb0", "usb1"; - }; - - mstp8_clks: mstp8_clks@fcfe0434 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0434 4>; - clocks = <&p1_clk>; - clock-indices = ; - clock-output-names = "mmcif"; - }; - - mstp9_clks: mstp9_clks@fcfe0438 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0438 4>; - clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>; - clock-indices = < - R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 - >; - clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3"; - }; - - mstp10_clks: mstp10_clks@fcfe043c { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe043c 4>; - clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, - <&p1_clk>; - clock-indices = < - R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 - R7S72100_CLK_SPI4 - >; - clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; - }; - mstp12_clks: mstp12_clks@fcfe0444 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0444 4>; - clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; - clock-indices = < - R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 - R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 - >; - clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; - }; - - pinctrl: pin-controller@fcfe3000 { - compatible = "renesas,r7s72100-ports"; - - reg = <0xfcfe3000 0x4230>; - - port0: gpio-0 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 6>; - }; - - port1: gpio-1 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - port2: gpio-2 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - port3: gpio-3 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - port4: gpio-4 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - port5: gpio-5 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 80 11>; - }; - - port6: gpio-6 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - port7: gpio-7 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 112 16>; - }; - - port8: gpio-8 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 128 16>; - }; - - port9: gpio-9 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 144 8>; - }; - - port10: gpio-10 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 160 16>; - }; - - port11: gpio-11 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 176 16>; - }; + L2: cache-controller@3ffff000 { + compatible = "arm,pl310-cache"; + reg = <0x3ffff000 0x1000>; + interrupts = ; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; }; scif0: serial@e8007000 { @@ -472,6 +299,71 @@ status = "disabled"; }; + usbhs0: usb@e8010000 { + compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; + reg = <0xe8010000 0x1a0>; + interrupts = ; + clocks = <&mstp7_clks R7S72100_CLK_USB0>; + renesas,buswait = <4>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + usbhs1: usb@e8207000 { + compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; + reg = <0xe8207000 0x1a0>; + interrupts = ; + clocks = <&mstp7_clks R7S72100_CLK_USB1>; + renesas,buswait = <4>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + mmcif: mmc@e804c800 { + compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; + reg = <0xe804c800 0x80>; + interrupts = ; + clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; + power-domains = <&cpg_clocks>; + reg-io-width = <4>; + bus-width = <8>; + status = "disabled"; + }; + + sdhi0: sd@e804e000 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e000 0x100>; + interrupts = ; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, + <&mstp12_clks R7S72100_CLK_SDHI01>; + clock-names = "core", "cd"; + power-domains = <&cpg_clocks>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: sd@e804e800 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e800 0x100>; + interrupts = ; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, + <&mstp12_clks R7S72100_CLK_SDHI11>; + clock-names = "core", "cd"; + power-domains = <&cpg_clocks>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + gic: interrupt-controller@e8201000 { compatible = "arm,pl390"; #interrupt-cells = <3>; @@ -481,14 +373,17 @@ <0xe8202000 0x1000>; }; - L2: cache-controller@3ffff000 { - compatible = "arm,pl310-cache"; - reg = <0x3ffff000 0x1000>; - interrupts = ; - arm,early-bresp-disable; - arm,full-line-zero-disable; - cache-unified; - cache-level = <2>; + ether: ethernet@e8203000 { + compatible = "renesas,ether-r7s72100"; + reg = <0xe8203000 0x800>, + <0xe8204800 0x200>; + interrupts = ; + clocks = <&mstp7_clks R7S72100_CLK_ETHER>; + power-domains = <&cpg_clocks>; + phy-mode = "mii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; wdt: watchdog@fcfe0000 { @@ -498,6 +393,207 @@ clocks = <&p0_clk>; }; + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@fcfe0000 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-cpg-clocks", + "renesas,rz-cpg-clocks"; + reg = <0xfcfe0000 0x18>; + clocks = <&extal_clk>, <&usb_x1_clk>; + clock-output-names = "pll", "i", "g"; + #power-domain-cells = <0>; + }; + + /* MSTP clocks */ + mstp3_clks: mstp3_clks@fcfe0420 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0420 4>; + clocks = <&p0_clk>; + clock-indices = ; + clock-output-names = "mtu2"; + }; + + mstp4_clks: mstp4_clks@fcfe0424 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0424 4>; + clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, + <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; + clock-indices = < + R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 + R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 + >; + clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; + }; + + mstp5_clks: mstp5_clks@fcfe0428 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0428 4>; + clocks = <&p0_clk>, <&p0_clk>; + clock-indices = ; + clock-output-names = "ostm0", "ostm1"; + }; + + mstp6_clks: mstp6_clks@fcfe042c { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe042c 4>; + clocks = <&p0_clk>; + clock-indices = ; + clock-output-names = "rtc"; + }; + + mstp7_clks: mstp7_clks@fcfe0430 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0430 4>; + clocks = <&b_clk>, <&p1_clk>, <&p1_clk>; + clock-indices = ; + clock-output-names = "ether", "usb0", "usb1"; + }; + + mstp8_clks: mstp8_clks@fcfe0434 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0434 4>; + clocks = <&p1_clk>; + clock-indices = ; + clock-output-names = "mmcif"; + }; + + mstp9_clks: mstp9_clks@fcfe0438 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0438 4>; + clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>; + clock-indices = < + R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 + >; + clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3"; + }; + + mstp10_clks: mstp10_clks@fcfe043c { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe043c 4>; + clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, + <&p1_clk>; + clock-indices = < + R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 + R7S72100_CLK_SPI4 + >; + clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; + }; + mstp12_clks: mstp12_clks@fcfe0444 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0444 4>; + clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; + clock-indices = < + R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 + R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 + >; + clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; + }; + + pinctrl: pin-controller@fcfe3000 { + compatible = "renesas,r7s72100-ports"; + + reg = <0xfcfe3000 0x4230>; + + port0: gpio-0 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 6>; + }; + + port1: gpio-1 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + port2: gpio-2 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + port3: gpio-3 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + port4: gpio-4 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + port5: gpio-5 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 80 11>; + }; + + port6: gpio-6 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + port7: gpio-7 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + port8: gpio-8 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + port9: gpio-9 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 144 8>; + }; + + port10: gpio-10 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 160 16>; + }; + + port11: gpio-11 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 176 16>; + }; + }; + + ostm0: timer@fcfec000 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec000 0x30>; + interrupts = ; + clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + ostm1: timer@fcfec400 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec400 0x30>; + interrupts = ; + clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + i2c0: i2c@fcfee000 { #address-cells = <1>; #size-cells = <0>; @@ -585,82 +681,6 @@ status = "disabled"; }; - ether: ethernet@e8203000 { - compatible = "renesas,ether-r7s72100"; - reg = <0xe8203000 0x800>, - <0xe8204800 0x200>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_ETHER>; - power-domains = <&cpg_clocks>; - phy-mode = "mii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmcif: mmc@e804c800 { - compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; - reg = <0xe804c800 0x80>; - interrupts = ; - clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; - power-domains = <&cpg_clocks>; - reg-io-width = <4>; - bus-width = <8>; - status = "disabled"; - }; - - sdhi0: sd@e804e000 { - compatible = "renesas,sdhi-r7s72100"; - reg = <0xe804e000 0x100>; - interrupts = ; - - clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, - <&mstp12_clks R7S72100_CLK_SDHI01>; - clock-names = "core", "cd"; - power-domains = <&cpg_clocks>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sdhi1: sd@e804e800 { - compatible = "renesas,sdhi-r7s72100"; - reg = <0xe804e800 0x100>; - interrupts = ; - - clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, - <&mstp12_clks R7S72100_CLK_SDHI11>; - clock-names = "core", "cd"; - power-domains = <&cpg_clocks>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - ostm0: timer@fcfec000 { - compatible = "renesas,r7s72100-ostm", "renesas,ostm"; - reg = <0xfcfec000 0x30>; - interrupts = ; - clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - ostm1: timer@fcfec400 { - compatible = "renesas,r7s72100-ostm", "renesas,ostm"; - reg = <0xfcfec400 0x30>; - interrupts = ; - clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - rtc: rtc@fcff1000 { compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; reg = <0xfcff1000 0x2e>; @@ -674,25 +694,5 @@ power-domains = <&cpg_clocks>; status = "disabled"; }; - - usbhs0: usb@e8010000 { - compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; - reg = <0xe8010000 0x1a0>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_USB0>; - renesas,buswait = <4>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - usbhs1: usb@e8207000 { - compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; - reg = <0xe8207000 0x1a0>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_USB1>; - renesas,buswait = <4>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; }; }; -- cgit From 6f9fe6a6521c84f267a08ee74090fc45d3ee199b Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 12 Feb 2018 15:39:29 +0100 Subject: ARM: dts: r7s72100: stop grouping clocks under a "clocks" subnode The current practice is to not group clocks under a "clocks" subnode, but just put them together with the other on-SoC devices. As per updates for R-Car Gen2 SoCs by Geert Uytterhoeven. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r7s72100.dtsi | 104 +++++++++++++++++++--------------------- 1 file changed, 49 insertions(+), 55 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 0d63dbe11e0d..d69d4810e597 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -30,62 +30,56 @@ spi4 = &spi4; }; - clocks { - ranges; - #address-cells = <1>; - #size-cells = <1>; + /* External clocks */ + extal_clk: extal { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board */ + clock-frequency = <0>; + }; - /* External clocks */ - extal_clk: extal { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board */ - clock-frequency = <0>; - }; - - usb_x1_clk: usb_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board */ - clock-frequency = <0>; - }; - - rtc_x1_clk: rtc_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board to 32678 */ - clock-frequency = <0>; - }; - - rtc_x3_clk: rtc_x3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board to 4000000 */ - clock-frequency = <0>; - }; - - /* Fixed factor clocks */ - b_clk: b { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <3>; - }; - p1_clk: p1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <6>; - }; - p0_clk: p0 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <12>; - }; + usb_x1_clk: usb_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board */ + clock-frequency = <0>; + }; + + rtc_x1_clk: rtc_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board to 32678 */ + clock-frequency = <0>; + }; + + rtc_x3_clk: rtc_x3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board to 4000000 */ + clock-frequency = <0>; + }; + + /* Fixed factor clocks */ + b_clk: b { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <3>; + }; + p1_clk: p1 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <6>; + }; + p0_clk: p0 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <12>; }; cpus { -- cgit From 5db40d7b26d30ac8b7c21313afe03d678cfffaa9 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 12 Feb 2018 15:39:30 +0100 Subject: ARM: dts: r7s72100: sort subnodes of root node Sort the subnodes of the soc node to improve maintainability. The sort has been done alphabetically with the node name as the key. This patch should not introduce any functional change. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r7s72100.dtsi | 78 +++++++++++++++++++++-------------------- 1 file changed, 40 insertions(+), 38 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index d69d4810e597..ecf9516bcda8 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -30,43 +30,45 @@ spi4 = &spi4; }; - /* External clocks */ - extal_clk: extal { + /* Fixed factor clocks */ + b_clk: b { #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board */ - clock-frequency = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <3>; }; - usb_x1_clk: usb_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board */ - clock-frequency = <0>; - }; + cpus { + #address-cells = <1>; + #size-cells = <0>; - rtc_x1_clk: rtc_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board to 32678 */ - clock-frequency = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <400000000>; + clocks = <&cpg_clocks R7S72100_CLK_I>; + next-level-cache = <&L2>; + }; }; - rtc_x3_clk: rtc_x3 { + /* External clocks */ + extal_clk: extal { #clock-cells = <0>; compatible = "fixed-clock"; - /* If clk present, value must be set by board to 4000000 */ + /* If clk present, value must be set by board */ clock-frequency = <0>; }; - /* Fixed factor clocks */ - b_clk: b { + p0_clk: p0 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R7S72100_CLK_PLL>; clock-mult = <1>; - clock-div = <3>; + clock-div = <12>; }; + p1_clk: p1 { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -74,26 +76,19 @@ clock-mult = <1>; clock-div = <6>; }; - p0_clk: p0 { + + rtc_x1_clk: rtc_x1 { #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <12>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board to 32678 */ + clock-frequency = <0>; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <400000000>; - clocks = <&cpg_clocks R7S72100_CLK_I>; - next-level-cache = <&L2>; - }; + rtc_x3_clk: rtc_x3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board to 4000000 */ + clock-frequency = <0>; }; soc { @@ -689,4 +684,11 @@ status = "disabled"; }; }; + + usb_x1_clk: usb_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board */ + clock-frequency = <0>; + }; }; -- cgit From 6929dfc5918049272e07653b1760b0b305f098e6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 3 Apr 2018 12:19:38 +0100 Subject: ARM: dts: r8a77470: Initial SoC device tree The initial R8A77470 SoC device tree including CPU0, GIC, timer, SYSC, RST, CPG, and the required clock descriptions. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 154 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 arch/arm/boot/dts/r8a77470.dtsi (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi new file mode 100644 index 000000000000..45785828771b --- /dev/null +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a77470 SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include +#include +#include +/ { + compatible = "renesas,r8a77470"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE 0>; + power-domains = <&sysc 5>; + next-level-cache = <&L2_CA7>; + }; + + + L2_CA7: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + power-domains = <&sysc 21>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77470-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77470-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77470-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x20000>; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE 6>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 720>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; -- cgit From f922fb5af1584c35bcd8bf661738b16dd4f65441 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 3 Apr 2018 12:19:39 +0100 Subject: ARM: dts: iwg23s-sbc: Add support for iWave G23S-SBC based on RZ/G1C Add support for iWave iW-RainboW-G23S single board computer based on RZ/G1C. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 35 +++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7e2424957809..17e781285a88 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -795,6 +795,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a7745-iwg22d-sodimm.dtb \ r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ r8a7745-sk-rzg1e.dtb \ + r8a77470-iwg23s-sbc.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \ diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts new file mode 100644 index 000000000000..d21baad9f0ad --- /dev/null +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1C single board computer + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a77470.dtsi" +/ { + model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C"; + compatible = "iwave,g23s", "renesas,r8a77470"; + + aliases { + serial1 = &scif1; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial1:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x20000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif1 { + status = "okay"; +}; -- cgit From b5857630a829a8d567627e5925a5710e5a80491a Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 19 Mar 2018 21:28:21 +0900 Subject: arm64: dts: renesas: r8a77965: add usb2_phy nodes This patch add usb2_phy nodes for r8a77965. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index f0871fcdd984..d498274fa0f3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -650,13 +650,26 @@ }; usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77965", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee080200 0 0x700>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; }; usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a77965", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0a0200 0 0x700>; - /* placeholder */ + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; }; ohci1: usb@ee0a0000 { -- cgit From 7a4a541eed654d62f82146f71b8aed869254e9ad Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 19 Mar 2018 21:28:22 +0900 Subject: arm64: dts: renesas: r8a77965: add usb3_phy node This patch adds usb3_phy node for r8a77965. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index d498274fa0f3..abb4d4dcc0ed 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -868,9 +868,16 @@ }; usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a77965-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc 32>; + resets = <&cpg 328>; #phy-cells = <0>; - /* placeholder */ + status = "disabled"; }; usb3_peri0: usb@ee020000 { -- cgit From 1dfa66cd906a06fe05703b32d3fe818710414aaf Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 19 Mar 2018 21:28:23 +0900 Subject: arm64: dts: renesas: r8a77965: add USB 2.0 host nodes This patch adds USB 2.0 host (EHCI/OHCI) nodes for r8a77965. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 38 +++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index abb4d4dcc0ed..ecc34ced3be2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -640,13 +640,28 @@ }; ohci0: usb@ee080000 { + compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + status = "disabled"; }; ehci0: usb@ee080100 { + compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + status = "disabled"; }; usb2_phy0: usb-phy@ee080200 { @@ -673,13 +688,28 @@ }; ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; reg = <0 0xee0a0000 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc 32>; + resets = <&cpg 702>; + status = "disabled"; }; ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; reg = <0 0xee0a0100 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc 32>; + resets = <&cpg 702>; + status = "disabled"; }; i2c0: i2c@e6500000 { -- cgit From dc68285152674f0178aff7004613a29efae23531 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 19 Mar 2018 21:28:24 +0900 Subject: arm64: dts: renesas: r8a77965: add usb_dmac nodes This patch adds USB-DMAC nodes for r8a77965. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index ecc34ced3be2..e5a5dd9d43da 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -832,6 +832,34 @@ }; }; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a77965-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc 32>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a77965-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc 32>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + hsusb: usb@e6590000 { reg = <0 0xe6590000 0 0x100>; /* placeholder */ -- cgit From a06e8af801760a98fd1d1355cafa92f89c78c771 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 19 Mar 2018 21:28:25 +0900 Subject: arm64: dts: renesas: r8a77965: add HS-USB node This patch adds HS-USB node for r8a77965. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index e5a5dd9d43da..ac74413d006f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -861,8 +861,20 @@ }; hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7796", + "renesas,rcar-gen3-usbhs"; reg = <0 0xe6590000 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc 32>; + resets = <&cpg 704>; + status = "disabled"; }; pciec0: pcie@fe000000 { -- cgit From e3cee8902e79705526c75efd5187081347c76ecf Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 19 Mar 2018 21:28:26 +0900 Subject: arm64: dts: renesas: r8a77965: add USB 3.0 host node This patch adds USB 3.0 host node for r8a77965. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index ac74413d006f..a34b80a0f304 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -956,8 +956,14 @@ }; xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a77965", + "renesas,rcar-gen3-xhci"; reg = <0 0xee000000 0 0xc00>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc 32>; + resets = <&cpg 328>; + status = "disabled"; }; wdt0: watchdog@e6020000 { -- cgit From 3a7dc06d833bd88f26c66fb16f56d93771cd4c2f Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 19 Mar 2018 21:28:27 +0900 Subject: arm64: dts: renesas: r8a77965: add USB 3.0 peripheral node This patch adds USB 3.0 peripheral node for r8a77965. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index a34b80a0f304..6f748e94a901 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -951,8 +951,14 @@ }; usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a77965-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; reg = <0 0xee020000 0 0x400>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc 32>; + resets = <&cpg 328>; + status = "disabled"; }; xhci0: usb@ee000000 { -- cgit From d2b860cb303fdeffa886c20bfbdbfd88cc52c85f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 20 Mar 2018 16:51:07 +0900 Subject: arm64: dts: renesas: r8a77970: Update IPMMU DS1 bit number Judging by "R-Car-Gen3-rev0.80" IPMMU IMSSTR register documentation for [R-Car V3M] the DS1 bit field should be bit 0. Update the ipmmu-main property to make it match the data sheet. Fixes: ce3b52a1595b ("arm64: dts: renesas: r8a77970: Add IPMMU device nodes") Signed-off-by: Magnus Damm Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index c6db8ea43906..e8358d9bfd66 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -160,7 +160,7 @@ ipmmu_ds1: mmu@e7740000 { compatible = "renesas,ipmmu-r8a77970"; reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; + renesas,ipmmu-main = <&ipmmu_mm 0>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; #iommu-cells = <1>; }; -- cgit From 6ef5e21294dfd2edcc3e1bb547aef3333d42e86d Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 23 Mar 2018 11:04:07 +0100 Subject: arm64: dts: renesas: r8a7796: sort subnodes of the root node Sort subnodes of the root node alphanumerically. This is part of an ongoing effort to provide consistent node order in the DT of Renesas SoCs to improve maintainability. This should not have any run-time effect. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 162 +++++++++++++++---------------- 1 file changed, 81 insertions(+), 81 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 556eb8e45499..78fbb4fd34bf 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -60,6 +60,72 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -161,72 +227,6 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - /* External PCIe clock - can be overridden by the board */ pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; @@ -234,13 +234,6 @@ clock-frequency = <0>; }; - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, @@ -250,6 +243,13 @@ interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; }; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, <&a57_1>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -2063,14 +2063,6 @@ }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - }; - thermal-zones { sensor_thermal1: sensor-thermal1 { polling-delay-passive = <250>; @@ -2151,6 +2143,14 @@ }; }; + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + }; + /* External USB clocks - can be overridden by the board */ usb3s0_clk: usb3s0 { compatible = "fixed-clock"; -- cgit From 3684a030bd0fded121bbce9af0d2126fe894d700 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 23 Mar 2018 11:04:08 +0100 Subject: arm64: dts: renesas: r8a7796: sort subnodes of the soc node Sort subnodes of the soc node. - The primary key is the bus address. - The secondary key is the IP block. - The tertiary key is the node name. This is part of an ongoing effort to provide consistent node order in the DT of Renesas SoCs to improve maintainability. This should not have any run-time effect. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 1824 +++++++++++++++--------------- 1 file changed, 912 insertions(+), 912 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 78fbb4fd34bf..55a64169d3d4 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -269,23 +269,6 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - wdt0: watchdog@e6020000 { compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; @@ -421,100 +404,6 @@ reg = <0 0xe6060000 0 0x50c>; }; - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7796_PD_A3VC>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: mmu@fd950000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A7796_PD_A3IR>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - cpg: clock-controller@e6150000 { compatible = "renesas,r8a7796-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -530,17 +419,27 @@ reg = <0 0xe6160000 0 0x0200>; }; - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a7796-sysc"; reg = <0 0xe6180000 0 0x0400>; #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a7796-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a7796", "renesas,irqc"; #interrupt-cells = <2>; @@ -557,92 +456,6 @@ resets = <&cpg 407>; }; - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7796", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; @@ -758,226 +571,19 @@ status = "disabled"; }; - can0: can@e6c30000 { - compatible = "renesas,can-r8a7796", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7796", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a7796", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a7796-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - drif00: rif@e6f40000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; - status = "disabled"; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; - status = "disabled"; - }; - - drif10: rif@e6f60000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; - status = "disabled"; - }; - - drif11: rif@e6f70000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; - status = "disabled"; - }; - - drif20: rif@e6f80000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac1 0x28>, <&dmac2 0x28>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; - status = "disabled"; - }; - - drif21: rif@e6f90000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; - status = "disabled"; - }; - - drif30: rif@e6fa0000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; - status = "disabled"; - }; - - drif31: rif@e6fb0000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; - status = "disabled"; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7796", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1069,162 +675,61 @@ status = "disabled"; }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7796", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 207>; + resets = <&cpg 704>; status = "disabled"; }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7796-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; }; - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7796-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; }; - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a7796-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; + resets = <&cpg 328>; + #phy-cells = <0>; status = "disabled"; }; @@ -1354,304 +859,550 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; + #iommu-cells = <1>; }; - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, - <&ipmmu_mp 18>, <&ipmmu_mp 19>, - <&ipmmu_mp 20>, <&ipmmu_mp 21>, - <&ipmmu_mp 22>, <&ipmmu_mp 23>, - <&ipmmu_mp 24>, <&ipmmu_mp 25>, - <&ipmmu_mp 26>, <&ipmmu_mp 27>, - <&ipmmu_mp 28>, <&ipmmu_mp 29>, - <&ipmmu_mp 30>, <&ipmmu_mp 31>; + #iommu-cells = <1>; }; - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7796-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; + #iommu-cells = <1>; + status = "disabled"; }; - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7796-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A7796_PD_A3IR>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; + #iommu-cells = <1>; }; - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7796", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0>; - phy-names = "usb"; + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 5>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv1: mmu@fd950000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfd950000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 8>; + power-domains = <&sysc R8A7796_PD_A3VC>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7796", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a7796", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a7796", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a7796-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 704>; + resets = <&cpg 204>; status = "disabled"; }; - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a7796-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; + resets = <&cpg 203>; status = "disabled"; }; - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a7796", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; + resets = <&cpg 202>; status = "disabled"; }; - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a7796-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; - companion= <&ohci0>; + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7796", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>; - #phy-cells = <0>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; + drif00: rif@e6f40000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f40000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>; + clock-names = "fck"; + dmas = <&dmac1 0x20>, <&dmac2 0x20>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; + resets = <&cpg 515>; + renesas,bonding = <&drif01>; status = "disabled"; }; - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; - companion= <&ohci1>; + drif01: rif@e6f50000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f50000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>; + clock-names = "fck"; + dmas = <&dmac1 0x22>, <&dmac2 0x22>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; + resets = <&cpg 514>; + renesas,bonding = <&drif00>; status = "disabled"; }; - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7796", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; + drif10: rif@e6f60000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f60000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 513>; + clock-names = "fck"; + dmas = <&dmac1 0x24>, <&dmac2 0x24>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <0>; + resets = <&cpg 513>; + renesas,bonding = <&drif11>; status = "disabled"; }; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; + drif11: rif@e6f70000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f70000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 512>; + clock-names = "fck"; + dmas = <&dmac1 0x26>, <&dmac2 0x26>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 314>; + resets = <&cpg 512>; + renesas,bonding = <&drif10>; status = "disabled"; }; - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; + drif20: rif@e6f80000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f80000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 511>; + clock-names = "fck"; + dmas = <&dmac1 0x28>, <&dmac2 0x28>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 313>; + resets = <&cpg 511>; + renesas,bonding = <&drif21>; status = "disabled"; }; - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; + drif21: rif@e6f90000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f90000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 510>; + clock-names = "fck"; + dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 312>; + resets = <&cpg 510>; + renesas,bonding = <&drif20>; status = "disabled"; }; - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; + drif30: rif@e6fa0000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fa0000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 509>; + clock-names = "fck"; + dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 311>; + resets = <&cpg 509>; + renesas,bonding = <&drif31>; status = "disabled"; }; - tsc: thermal@e6198000 { - compatible = "renesas,r8a7796-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; + drif31: rif@e6fb0000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fb0000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 508>; + clock-names = "fck"; + dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - status = "okay"; + resets = <&cpg 508>; + renesas,bonding = <&drif30>; + status = "disabled"; }; rcar_sound: sound@ec500000 { @@ -1796,58 +1547,302 @@ }; }; - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, + <&ipmmu_mp 2>, <&ipmmu_mp 3>, + <&ipmmu_mp 4>, <&ipmmu_mp 5>, + <&ipmmu_mp 6>, <&ipmmu_mp 7>, + <&ipmmu_mp 8>, <&ipmmu_mp 9>, + <&ipmmu_mp 10>, <&ipmmu_mp 11>, + <&ipmmu_mp 12>, <&ipmmu_mp 13>, + <&ipmmu_mp 14>, <&ipmmu_mp 15>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, + <&ipmmu_mp 18>, <&ipmmu_mp 19>, + <&ipmmu_mp 20>, <&ipmmu_mp 21>, + <&ipmmu_mp 22>, <&ipmmu_mp 23>, + <&ipmmu_mp 24>, <&ipmmu_mp 25>, + <&ipmmu_mp 26>, <&ipmmu_mp 27>, + <&ipmmu_mp 28>, <&ipmmu_mp 29>, + <&ipmmu_mp 30>, <&ipmmu_mp 31>; + }; + + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a7796", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a7796-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion= <&ohci0>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + companion= <&ohci1>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a7796", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a7796", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <0>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; pciec0: pcie@fe000000 { @@ -1860,6 +1855,26 @@ /* placeholder */ }; + imr-lx4@fe860000 { + compatible = "renesas,r8a7796-imr-lx4", + "renesas,imr-lx4"; + reg = <0 0xfe860000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 823>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 823>; + }; + + imr-lx4@fe870000 { + compatible = "renesas,r8a7796-imr-lx4", + "renesas,imr-lx4"; + reg = <0 0xfe870000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 822>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 822>; + }; + fdp1@fe940000 { compatible = "renesas,fdp1"; reg = <0 0xfe940000 0 0x2400>; @@ -1878,17 +1893,6 @@ resets = <&cpg 615>; }; - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - fcpvb0: fcp@fe96f000 { compatible = "renesas,fcpv"; reg = <0 0xfe96f000 0 0x200>; @@ -1897,17 +1901,6 @@ resets = <&cpg 607>; }; - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - fcpvi0: fcp@fe9af000 { compatible = "renesas,fcpv"; reg = <0 0xfe9af000 0 0x200>; @@ -1917,6 +1910,44 @@ iommus = <&ipmmu_vc0 19>; }; + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 601>; + iommus = <&ipmmu_vi0 10>; + }; + + vspb: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x8000>; @@ -1928,15 +1959,6 @@ renesas,fcp = <&fcpvd0>; }; - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; reg = <0 0xfea28000 0 0x8000>; @@ -1948,15 +1970,6 @@ renesas,fcp = <&fcpvd1>; }; - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; reg = <0 0xfea30000 0 0x8000>; @@ -1968,13 +1981,15 @@ renesas,fcp = <&fcpvd2>; }; - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi0 10>; + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; }; hdmi0: hdmi@fead0000 { @@ -2042,24 +2057,9 @@ }; }; - imr-lx4@fe860000 { - compatible = "renesas,r8a7796-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe860000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 823>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 823>; - }; - - imr-lx4@fe870000 { - compatible = "renesas,r8a7796-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe870000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 822>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 822>; + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; }; }; -- cgit From 82cf1d158ed6a0bd53b10e0eac4d8fd1b8f9c9e7 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 23 Mar 2018 11:04:05 +0100 Subject: arm64: dts: renesas: r8a7795: sort subnodes of the root node Sort subnodes of the root node alphanumerically. This is part of an ongoing effort to provide consistent node order in the DT of Renesas SoCs to improve maintainability. Also remove excessive line-wrapping of interrupts-extended property of timer node. This should not have any run-time effect. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 218 +++++++++++++++---------------- 1 file changed, 105 insertions(+), 113 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 1d5e3ac0231c..bb96c7e23370 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -30,6 +30,91 @@ i2c7 = &i2c_dvfs; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -155,91 +240,6 @@ clock-frequency = <0>; }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - }; - /* External PCIe clock - can be overridden by the board */ pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; @@ -247,18 +247,6 @@ clock-frequency = <0>; }; - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>, - <&a57_2>, - <&a57_3>; - }; - pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, @@ -271,6 +259,18 @@ <&a53_3>; }; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, + <&a57_1>, + <&a57_2>, + <&a57_3>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -2428,22 +2428,6 @@ }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(8) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(8) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(8) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(8) | - IRQ_TYPE_LEVEL_LOW)>; - }; - thermal-zones { sensor_thermal1: sensor-thermal1 { polling-delay-passive = <250>; @@ -2524,6 +2508,14 @@ }; }; + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + /* External USB clocks - can be overridden by the board */ usb3s0_clk: usb3s0 { compatible = "fixed-clock"; -- cgit From e0f0bda79337701a08141a6ec5417be96b12a265 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 23 Mar 2018 11:04:06 +0100 Subject: arm64: dts: renesas: r8a7795: sort subnodes of the soc node Sort subnodes of the soc node. - The primary key is the bus address. - The secondary key is the IP block. - The tertiary key is the node name. This is part of an ongoing effort to provide consistent node order in the DT of Renesas SoCs to improve maintainability. This should not have any run-time effect. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 1858 +++++++++++++++--------------- 1 file changed, 929 insertions(+), 929 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index bb96c7e23370..0e958ecd2a41 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -291,23 +291,6 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - wdt0: watchdog@e6020000 { compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; @@ -437,6 +420,11 @@ resets = <&cpg 905>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7795"; + reg = <0 0xe6060000 0 0x50c>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7795-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -452,20 +440,25 @@ reg = <0 0xe6160000 0 0x0200>; }; - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a7795-sysc"; reg = <0 0xe6180000 0 0x0400>; #power-domain-cells = <1>; }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7795"; - reg = <0 0xe6060000 0 0x50c>; + tsc: thermal@e6198000 { + compatible = "renesas,r8a7795-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; }; intc_ex: interrupt-controller@e61c0000 { @@ -484,153 +477,326 @@ resets = <&cpg 407>; }; - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; }; - ipmmu_vi1: mmu@febe0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfebe0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 15>; + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - ipmmu_vp0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A7795_PD_A3VP>; - #iommu-cells = <1>; + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - ipmmu_vp1: mmu@fe980000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe980000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 17>; - power-domains = <&sysc R8A7795_PD_A3VP>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A7795_PD_A3VC>; - #iommu-cells = <1>; + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; - ipmmu_vc1: mmu@fe6f0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe6f0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 13>; - power-domains = <&sysc R8A7795_PD_A3VC>; - #iommu-cells = <1>; + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; - ipmmu_pv1: mmu@fd950000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - ipmmu_pv2: mmu@fd960000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd960000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7795", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; status = "disabled"; }; - ipmmu_pv3: mmu@fd970000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd970000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 520>; status = "disabled"; }; - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A7795_PD_A3IR>; - #iommu-cells = <1>; + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 519>; status = "disabled"; }; - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 518>; status = "disabled"; }; - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 517>; status = "disabled"; }; - ipmmu_mp0: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 516>; status = "disabled"; }; - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7795", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 704>; + status = "disabled"; }; - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; + hsusb3: usb@e659c000 { + compatible = "renesas,usbhs-r8a7795", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe659c000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 705>; + dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, + <&usb_dmac3 0>, <&usb_dmac3 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy3>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 705>; + status = "disabled"; }; - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac2: dma-controller@e6460000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe6460000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 326>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 326>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac3: dma-controller@e6470000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe6470000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 329>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 329>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a7795-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 328>; + #phy-cells = <0>; + status = "disabled"; }; dmac0: dma-controller@e6700000 { @@ -759,460 +925,325 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, - <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, - <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, - <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, - <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, - <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, - <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, - <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; + #iommu-cells = <1>; }; - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, - <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, - <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, - <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, - <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, - <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, - <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, - <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; + #iommu-cells = <1>; }; - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7795", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; + #iommu-cells = <1>; status = "disabled"; }; - can0: can@e6c30000 { - compatible = "renesas,can-r8a7795", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 916>; + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A7795_PD_A3IR>; + #iommu-cells = <1>; status = "disabled"; }; - can1: can@e6c38000 { - compatible = "renesas,can-r8a7795", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; + #iommu-cells = <1>; }; - canfd: can@e66c0000 { - compatible = "renesas,r8a7795-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; + ipmmu_mp0: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 914>; + #iommu-cells = <1>; status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; }; - drif00: rif@e6f40000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; + #iommu-cells = <1>; status = "disabled"; }; - drif01: rif@e6f50000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; + ipmmu_pv1: mmu@fd950000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd950000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; + #iommu-cells = <1>; status = "disabled"; }; - drif10: rif@e6f60000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; + ipmmu_pv2: mmu@fd960000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd960000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 8>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; + #iommu-cells = <1>; status = "disabled"; }; - drif11: rif@e6f70000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; + ipmmu_pv3: mmu@fd970000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd970000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; + #iommu-cells = <1>; status = "disabled"; }; - drif20: rif@e6f80000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac1 0x28>, <&dmac2 0x28>; - dma-names = "rx", "rx"; + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; + #iommu-cells = <1>; status = "disabled"; }; - drif21: rif@e6f90000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; - dma-names = "rx", "rx"; + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A7795_PD_A3VC>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_vc1: mmu@fe6f0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe6f0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 13>; + power-domains = <&sysc R8A7795_PD_A3VC>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; + #iommu-cells = <1>; + }; + + ipmmu_vi1: mmu@febe0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfebe0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 15>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; status = "disabled"; }; - drif30: rif@e6fa0000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; - dma-names = "rx", "rx"; + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A7795_PD_A3VP>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_vp1: mmu@fe980000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe980000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 17>; + power-domains = <&sysc R8A7795_PD_A3VP>; + #iommu-cells = <1>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7795", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - drif31: rif@e6fb0000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; - dma-names = "rx", "rx"; + can0: can@e6c30000 { + compatible = "renesas,can-r8a7795", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; + resets = <&cpg 916>; status = "disabled"; }; - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; + can1: can@e6c38000 { + compatible = "renesas,can-r8a7795", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 520>; + resets = <&cpg 915>; status = "disabled"; }; - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; + canfd: can@e66c0000 { + compatible = "renesas,r8a7795-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 519>; + resets = <&cpg 914>; status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; }; - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 518>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 517>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 516>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; @@ -1316,204 +1347,185 @@ status = "disabled"; }; - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7795", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a7795", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { + resets = <&cpg 211>; #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a7795", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - i2c4: i2c@e66d8000 { + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a7795", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 209>; #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; - i2c5: i2c@e66e0000 { + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a7795", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; + drif00: rif@e6f40000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f40000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>; + clock-names = "fck"; + dmas = <&dmac1 0x20>, <&dmac2 0x20>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 515>; + renesas,bonding = <&drif01>; status = "disabled"; }; - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif01: rif@e6f50000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f50000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>; + clock-names = "fck"; + dmas = <&dmac1 0x22>, <&dmac2 0x22>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 514>; + renesas,bonding = <&drif00>; status = "disabled"; }; - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif10: rif@e6f60000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f60000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 513>; + clock-names = "fck"; + dmas = <&dmac1 0x24>, <&dmac2 0x24>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 513>; + renesas,bonding = <&drif11>; status = "disabled"; }; - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif11: rif@e6f70000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f70000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 512>; + clock-names = "fck"; + dmas = <&dmac1 0x26>, <&dmac2 0x26>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 512>; + renesas,bonding = <&drif10>; status = "disabled"; }; - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif20: rif@e6f80000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f80000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 511>; + clock-names = "fck"; + dmas = <&dmac1 0x28>, <&dmac2 0x28>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 511>; + renesas,bonding = <&drif21>; status = "disabled"; }; - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif21: rif@e6f90000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f90000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 510>; + clock-names = "fck"; + dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 510>; + renesas,bonding = <&drif20>; status = "disabled"; }; - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif30: rif@e6fa0000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fa0000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 509>; + clock-names = "fck"; + dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 509>; + renesas,bonding = <&drif31>; status = "disabled"; }; - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif31: rif@e6fb0000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fb0000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 508>; + clock-names = "fck"; + dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 508>; + renesas,bonding = <&drif30>; status = "disabled"; }; @@ -1713,29 +1725,88 @@ }; }; - sata: sata@ee300000 { - compatible = "renesas,sata-r8a7795", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - iommus = <&ipmmu_hc 2>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, + <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, + <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, + <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, + <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, + <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, + <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, + <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; }; - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a7795-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, + <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, + <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, + <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, + <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, + <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, + <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, + <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; }; xhci0: usb@ee000000 { @@ -1759,153 +1830,51 @@ status = "disabled"; }; - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac2: dma-controller@e6460000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe6460000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 326>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 326>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac3: dma-controller@e6470000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe6470000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 329>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 329>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 703>; - #phy-cells = <0>; status = "disabled"; }; - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = ; clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 702>; - #phy-cells = <0>; status = "disabled"; }; - usb2_phy2: usb-phy@ee0c0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0c0200 0 0x700>; + ohci2: usb@ee0c0000 { + compatible = "generic-ohci"; + reg = <0 0xee0c0000 0 0x100>; + interrupts = ; clocks = <&cpg CPG_MOD 701>; + phys = <&usb2_phy2>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 701>; - #phy-cells = <0>; status = "disabled"; }; - usb2_phy3: usb-phy@ee0e0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0e0200 0 0x700>; + ohci3: usb@ee0e0000 { + compatible = "generic-ohci"; + reg = <0 0xee0e0000 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 700>; + phys = <&usb2_phy3>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 700>; - #phy-cells = <0>; status = "disabled"; }; @@ -1961,86 +1930,127 @@ status = "disabled"; }; - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; interrupts = ; clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 703>; + #phy-cells = <0>; status = "disabled"; }; - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 702>; + #phy-cells = <0>; status = "disabled"; }; - ohci2: usb@ee0c0000 { - compatible = "generic-ohci"; - reg = <0 0xee0c0000 0 0x100>; - interrupts = ; + usb2_phy2: usb-phy@ee0c0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0c0200 0 0x700>; clocks = <&cpg CPG_MOD 701>; - phys = <&usb2_phy2>; - phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 701>; + resets = <&cpg 701>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2_phy3: usb-phy@ee0e0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0e0200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 700>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 700>; + #phy-cells = <0>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; - ohci3: usb@ee0e0000 { - compatible = "generic-ohci"; - reg = <0 0xee0e0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 700>; - phys = <&usb2_phy3>; - phy-names = "usb"; + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 700>; + resets = <&cpg 311>; status = "disabled"; }; - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7795", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0>; - phy-names = "usb"; + sata: sata@ee300000 { + compatible = "renesas,sata-r8a7795", + "renesas,rcar-gen3-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = ; + clocks = <&cpg CPG_MOD 815>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 704>; + resets = <&cpg 815>; status = "disabled"; + iommus = <&ipmmu_hc 2>; }; - hsusb3: usb@e659c000 { - compatible = "renesas,usbhs-r8a7795", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe659c000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>; - dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, - <&usb_dmac3 0>, <&usb_dmac3 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy3>; - phy-names = "usb"; + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 705>; - status = "disabled"; + resets = <&cpg 408>; }; pciec0: pcie@fe000000 { @@ -2137,24 +2147,24 @@ resets = <&cpg 820>; }; - vspbc: vsp@fe920000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 624>; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 624>; - - renesas,fcp = <&fcpvb1>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; }; - fcpvb1: fcp@fe92f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe92f000 0 0x200>; - clocks = <&cpg CPG_MOD 606>; + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 606>; - iommus = <&ipmmu_vp1 7>; + resets = <&cpg 118>; + renesas,fcp = <&fcpf1>; }; fcpf0: fcp@fe950000 { @@ -2175,17 +2185,6 @@ iommus = <&ipmmu_vp1 1>; }; - vspbd: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - fcpvb0: fcp@fe96f000 { compatible = "renesas,fcpv"; reg = <0 0xfe96f000 0 0x200>; @@ -2195,15 +2194,13 @@ iommus = <&ipmmu_vp0 5>; }; - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; + fcpvb1: fcp@fe92f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe92f000 0 0x200>; + clocks = <&cpg CPG_MOD 606>; power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; + resets = <&cpg 606>; + iommus = <&ipmmu_vp1 7>; }; fcpvi0: fcp@fe9af000 { @@ -2215,17 +2212,6 @@ iommus = <&ipmmu_vp0 8>; }; - vspi1: vsp@fe9b0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9b0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 630>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 630>; - - renesas,fcp = <&fcpvi1>; - }; - fcpvi1: fcp@fe9bf000 { compatible = "renesas,fcpv"; reg = <0 0xfe9bf000 0 0x200>; @@ -2235,6 +2221,55 @@ iommus = <&ipmmu_vp1 9>; }; + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 601>; + iommus = <&ipmmu_vi1 10>; + }; + + vspbd: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + vspbc: vsp@fe920000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 624>; + + renesas,fcp = <&fcpvb1>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x8000>; @@ -2246,15 +2281,6 @@ renesas,fcp = <&fcpvd0>; }; - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; reg = <0 0xfea28000 0 0x8000>; @@ -2266,15 +2292,6 @@ renesas,fcp = <&fcpvd1>; }; - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; reg = <0 0xfea30000 0 0x8000>; @@ -2286,33 +2303,26 @@ renesas,fcp = <&fcpvd2>; }; - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi1 10>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 631>; power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; }; - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; + vspi1: vsp@fe9b0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9b0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 630>; power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 118>; - renesas,fcp = <&fcpf1>; + resets = <&cpg 630>; + + renesas,fcp = <&fcpvi1>; }; hdmi0: hdmi@fead0000 { @@ -2412,19 +2422,9 @@ }; }; - tsc: thermal@e6198000 { - compatible = "renesas,r8a7795-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - status = "okay"; + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; }; }; -- cgit From 93b0e5643a684ff0843b9d0222eae168838b2ffa Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Fri, 23 Mar 2018 10:19:09 +0100 Subject: arm64: dts: renesas: r8a77965: Add all MSIOF device nodes Add the device nodes for all MSIOF SPI controllers. Based on several similar patches of the R8A7796 device tree by Geert Uytterhoeven and Simon Horman . Signed-off-by: Takeshi Kihara [geert: Use numerical power domain indices for initial r8a77965.dtsi] Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 62 +++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 6f748e94a901..4371be3e869a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -805,6 +805,68 @@ /* placeholder */ }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + du: display@feb00000 { reg = <0 0xfeb00000 0 0x80000>, <0 0xfeb90000 0 0x14>; -- cgit From e3ddf00f87d998e81ac1e5c925145c24bb10411d Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 23 Mar 2018 20:32:51 +0900 Subject: arm64: dts: renesas: r8a77965: Add PWM device nodes This patch adds PWM device nodes for r8a77965. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 48 ++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 4371be3e869a..a41f91653d93 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -770,39 +770,73 @@ }; pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 8>; - /* placeholder */ + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; }; pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e31000 0 8>; #pwm-cells = <2>; - /* placeholder */ + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; }; pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e32000 0 8>; - /* placeholder */ + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; }; pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e33000 0 8>; - /* placeholder */ + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; }; pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e34000 0 8>; - /* placeholder */ + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; }; pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e35000 0 8>; - /* placeholder */ + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; }; pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e36000 0 8>; - /* placeholder */ + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; }; msiof0: spi@e6e90000 { -- cgit From 1d26a5217187189fdbee15bc03d3713d8e8ae7e9 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Thu, 22 Mar 2018 21:30:40 +0000 Subject: ARM: dts: wheat: Fix ADV7513 address usage The r8a7792 Wheat board has two ADV7513 devices sharing a single I2C bus, however in low power mode the ADV7513 will reset it's slave maps to use the hardware defined default addresses. The ADV7511 driver was adapted to allow the two devices to be registered correctly - but it did not take into account the fault whereby the devices reset the addresses. This results in an address conflict between the device using the default addresses, and the other device if it is in low-power-mode. Repair this issue by moving both devices away from the default address definitions. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Fixes: f6eea82a87db ("ARM: dts: wheat: add DU support") Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-wheat.dts | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index b9471b67b728..95aab56a56ab 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -240,9 +240,15 @@ status = "okay"; clock-frequency = <400000>; + /* + * The adv75xx resets its addresses to defaults during low power mode. + * Because we have two ADV7513 devices on the same bus, we must change + * both of them away from the defaults so that they do not conflict. + */ hdmi@3d { compatible = "adi,adv7513"; - reg = <0x3d>; + reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>; + reg-names = "main", "cec", "edid", "packet"; adi,input-depth = <8>; adi,input-colorspace = "rgb"; @@ -272,7 +278,8 @@ hdmi@39 { compatible = "adi,adv7513"; - reg = <0x39>; + reg = <0x39>, <0x29>, <0x49>, <0x59>; + reg-names = "main", "cec", "edid", "packet"; adi,input-depth = <8>; adi,input-colorspace = "rgb"; -- cgit From faa5c3176a67ed53a5bfefdf8b5e91dab9785d0d Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 6 Apr 2018 15:08:06 +0200 Subject: arm64: dts: renesas: r8a77970: add FCPVD support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe FCPVD0 in the R8A77970 device tree; it will be used by VSPD0 in the next patch... Based on the original (and large) patch by Daisuke Matsushita . Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Niklas Söderlund Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index e8358d9bfd66..71f466daa036 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -617,6 +617,14 @@ #address-cells = <1>; #size-cells = <0>; }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; }; timer { -- cgit From 9eb663e838aba244b97fed0000cb3917f6013e96 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 17 Apr 2018 00:02:32 +0900 Subject: ARM: dts: renesas: replace toshiba, mmc-wrprotect-disable with disable-wp Follow up commit 788778b0d21a ("mmc: tmio: deprecate "toshiba, mmc-wrprotect-disable" DT property"). Signed-off-by: Masahiro Yamada Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4-ape6evm.dts | 4 ++-- arch/arm/boot/dts/sh73a0.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index ec7c86e06538..125c39c0222f 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -234,7 +234,7 @@ &sdhi0 { vmmc-supply = <&vcc_sdhi0>; bus-width = <4>; - toshiba,mmc-wrprotect-disable; + disable-wp; pinctrl-names = "default"; pinctrl-0 = <&sdhi0_pins>; status = "okay"; @@ -244,7 +244,7 @@ vmmc-supply = <&ape6evm_fixed_3v3>; bus-width = <4>; broken-cd; - toshiba,mmc-wrprotect-disable; + disable-wp; pinctrl-names = "default"; pinctrl-0 = <&sdhi1_pins>; status = "okay"; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 914a7c2a584f..39cc58672bf4 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -336,7 +336,7 @@ GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; power-domains = <&pd_a3sp>; - toshiba,mmc-wrprotect-disable; + disable-wp; cap-sd-highspeed; status = "disabled"; }; @@ -348,7 +348,7 @@ GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; power-domains = <&pd_a3sp>; - toshiba,mmc-wrprotect-disable; + disable-wp; cap-sd-highspeed; status = "disabled"; }; -- cgit From e7f36fb8ffafbda9c168e1aafab5b5ebe54ebaa8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 22 Apr 2018 13:35:26 +0300 Subject: ARM: dts: renesas: r8a7791: Add FDP1 instances The r8a7791 has two FDP1 instances. Signed-off-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index f11dab71b03a..55b5a56da35e 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1621,6 +1621,24 @@ resets = <&cpg 127>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 118>; + }; + jpu: jpeg-codec@fe980000 { compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu"; -- cgit From d7ce14dfbaff685a65b56bdb6622b430ae9ad57a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 22 Apr 2018 13:35:27 +0300 Subject: ARM: dts: renesas: r8a7793: Add FDP1 instances The r8a7793 has two FDP1 instances. Signed-off-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index f9c5a557107d..61c58029e03e 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -1290,6 +1290,24 @@ resets = <&cpg 408>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 118>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7793"; reg = <0 0xfeb00000 0 0x40000>, -- cgit From 898cf5a67c169a8efb41cc6483935f1bc61e8157 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 22 Apr 2018 13:35:28 +0300 Subject: ARM: dts: renesas: r8a7794: Add FDP1 instances The r8a7794 has one FDP1 instance. Signed-off-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index d588efa6aeaa..56f5fa6a2c0f 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1323,6 +1323,15 @@ resets = <&cpg 128>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7794"; reg = <0 0xfeb00000 0 0x40000>; -- cgit From 2e5775e3fd0667f7140a00748465af1c3d0aa5bb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 20 Apr 2018 16:27:06 +0100 Subject: ARM: dts: r8a77470: Add SYS-DMAC support Describe SYS-DMAC0/1 in the R8A77470 device tree. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 66 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 45785828771b..c39acebc6a72 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -104,6 +104,72 @@ reg = <0 0xe6300000 0 0x20000>; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a77470", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a77470", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + scif1: serial@e6e68000 { compatible = "renesas,scif-r8a77470", "renesas,rcar-gen2-scif", "renesas,scif"; -- cgit From 141fb10294e3ba5ee2d34d464ddc8a9952bd3372 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 20 Apr 2018 16:27:07 +0100 Subject: ARM: dts: r8a77470: Add IRQC support Describe the IRQC interrupt controller in the R8A77470 device tree. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index c39acebc6a72..2f89f33f5b88 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -81,6 +81,26 @@ #power-domain-cells = <1>; }; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a77470", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc 32>; + resets = <&cpg 407>; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; -- cgit From f558d42a9d1c4724a8b3880fe230a66fa16e21c8 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 22 Feb 2018 11:37:20 +0100 Subject: ARM: dts: r7s72100: Add Capture Engine Unit (CEU) Add Capture Engine Unit (CEU) node to device tree. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Acked-by: Hans Verkuil [simon: rebased] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index ecf9516bcda8..4a1aade0e751 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -375,6 +375,15 @@ status = "disabled"; }; + ceu: camera@e8210000 { + reg = <0xe8210000 0x3000>; + compatible = "renesas,r7s72100-ceu"; + interrupts = ; + clocks = <&mstp6_clks R7S72100_CLK_CEU>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + wdt: watchdog@fcfe0000 { compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; reg = <0xfcfe0000 0x6>; @@ -429,9 +438,9 @@ #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0xfcfe042c 4>; - clocks = <&p0_clk>; - clock-indices = ; - clock-output-names = "rtc"; + clocks = <&b_clk>, <&p0_clk>; + clock-indices = ; + clock-output-names = "ceu", "rtc"; }; mstp7_clks: mstp7_clks@fcfe0430 { -- cgit From 0b7d5ccacac9cd54785a2cf1695a0601907f3e78 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:11 +0000 Subject: ARM: dts: r8a7743: Adjust SMP routine size This patch adjusts the definition of the SMP routine size according to the latest changes made by commit: "ARM: shmobile: Add watchdog support" Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 1d9073ba0ce0..0381b86b7591 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -407,7 +407,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; -- cgit From 7270dedc8438c7247474a33a8334f3920816e2c2 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:12 +0000 Subject: ARM: dts: r8a7745: Adjust SMP routine size This patch adjusts the definition of the SMP routine size according to the latest changes made by commit: "ARM: shmobile: Add watchdog support" Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index dd49a8b48f3e..0c3f4c5b345b 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -360,7 +360,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; -- cgit From 5c6c17a51f809bf831086d014f8655fa5a9f421b Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:13 +0000 Subject: ARM: dts: r8a7790: Adjust SMP routine size This patch adjusts the definition of the SMP routine size according to the latest changes made by commit: "ARM: shmobile: Add watchdog support" Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index e4367cecad18..317325e271c9 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -443,7 +443,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; -- cgit From a332210049e3d0e502253afdc52640bc2a87ac91 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:14 +0000 Subject: ARM: dts: r8a7791: Adjust SMP routine size This patch adjusts the definition of the SMP routine size according to the latest changes made by commit: "ARM: shmobile: Add watchdog support" Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 55b5a56da35e..8b05f59738c3 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -407,7 +407,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; -- cgit From 75f666509fe6545754755a166cc00f84e8018866 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:15 +0000 Subject: ARM: dts: r8a7792: Adjust SMP routine size This patch adjusts the definition of the SMP routine size according to the latest changes made by commit: "ARM: shmobile: Add watchdog support" Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 268987ff0201..bea0f12f03d3 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -341,7 +341,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; -- cgit From f515e5996a85fd4e042f3eec38d82a4250ac1a6c Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:16 +0000 Subject: ARM: dts: r8a7793: Adjust SMP routine size This patch adjusts the definition of the SMP routine size according to the latest changes made by commit: "ARM: shmobile: Add watchdog support" Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 61c58029e03e..72d9b0004928 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -392,7 +392,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; -- cgit From 8bcbcfd9e3ea981c188cb21cac5add7784580ee4 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:17 +0000 Subject: ARM: dts: r8a7794: Adjust SMP routine size This patch adjusts the definition of the SMP routine size according to the latest changes made by commit: "ARM: shmobile: Add watchdog support" Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 56f5fa6a2c0f..34c111907eb7 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -348,7 +348,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; -- cgit From b5beb5d4c81c358f50a8310108e7d8614eec8bfd Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:29 +0000 Subject: ARM: dts: r8a7743: Add watchdog support to SoC dtsi This patch adds watchdog support to the r8a7743 SoC dtsi. Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 0381b86b7591..69d8f7e0f053 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -297,6 +297,16 @@ reg = <0 0xe6160000 0 0x100>; }; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7743-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7743-sysc"; reg = <0 0xe6180000 0 0x200>; -- cgit From 5f39290ff3e5f56c78adf16a8c7a0a2938c733f5 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:30 +0000 Subject: ARM: dts: r8a7745: Add watchdog support to SoC dtsi This patch adds watchdog support to the r8a7745 SoC dtsi. Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 0c3f4c5b345b..3de69cb66c44 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -262,6 +262,16 @@ reg = <0 0xe6160000 0 0x100>; }; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7745-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7745-sysc"; reg = <0 0xe6180000 0 0x200>; -- cgit From c69f844380966ccd305ede64e568d81f0e0cfa85 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:31 +0000 Subject: ARM: dts: r8a7790: Add watchdog support to SoC dtsi This commit adds watchdog support to the r8a7790 dtsi. Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 317325e271c9..7ba62b7aa0ba 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -218,6 +218,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7790-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; -- cgit From 6912394d66471296d4cd16e41e70f4758827a3e6 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:32 +0000 Subject: ARM: dts: r8a7791: Add watchdog support to SoC dtsi This commit adds watchdog support to the r8a7791 dtsi. Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 8b05f59738c3..570ca12422c5 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -142,6 +142,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7791-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; -- cgit From aaef9f5051935c3b174df3fd7e73171b84c81485 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:33 +0000 Subject: ARM: dts: r8a7794: Add watchdog support to SoC dtsi This commit adds watchdog support to the r8a7794 dtsi. Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 34c111907eb7..76aadcdf9d37 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -119,6 +119,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7794-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; -- cgit From fc9d3be893f8f175879657f844040d0722eb17fe Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:34 +0000 Subject: ARM: dts: iwg20m: Add watchdog support to SoM dtsi This patch enables the watchdog from within the iwg20m SoM dtsi. Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi index 1d3e9503c5bd..d364685d9184 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi @@ -91,6 +91,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-names = "default"; -- cgit From a8e2c377fe2483f7fcd5746ab4e0c43c3262c1de Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 12 Feb 2018 17:44:35 +0000 Subject: ARM: dts: iwg22m: Add watchdog support to SoM dtsi This patch enables the watchdog from within the iwg20m SoM dtsi. Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram Reviewed-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi index 8d0a392b6811..29b6e10fdf96 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi @@ -91,6 +91,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-names = "default"; -- cgit From 49dba98c1981da471739e44a74244f658777c6fd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 8 Feb 2018 11:34:08 +0100 Subject: ARM: dts: r8a7792: Add RWDT node Add a device node for the Watchdog Timer (WDT) controller on the Renesas R-Car V2H (r8a7792) SoC. Signed-off-by: Geert Uytterhoeven Acked-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index bea0f12f03d3..d2cf8dd2d9b0 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -101,6 +101,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7792-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7792", "renesas,rcar-gen2-gpio"; -- cgit From 5ba173e677100a79bc6bcfb063c3ea736f7319a1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 8 Feb 2018 11:34:09 +0100 Subject: ARM: dts: r8a7793: Add RWDT node Add a device node for the Watchdog Timer (WDT) controller on the Renesas R-Car M2-N (r8a7793) SoC. Signed-off-by: Geert Uytterhoeven Acked-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 72d9b0004928..6975b0efc46c 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -126,6 +126,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7793-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; -- cgit From 53e480fcb1cb00a74d6af2070bfcd1e995b19d47 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 8 Feb 2018 11:34:10 +0100 Subject: ARM: dts: lager: Enable watchdog support Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by: Geert Uytterhoeven Acked-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 063fdb65dc60..3c66366f7c55 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -917,6 +917,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &ssi1 { shared-pin; }; -- cgit From 9245dccc4a198997d2b0d2b51eef14763ccf2b30 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 8 Feb 2018 11:34:11 +0100 Subject: ARM: dts: koelsch: Enable watchdog support Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by: Geert Uytterhoeven Acked-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index f40321a1c917..fcdd0164142b 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -637,6 +637,11 @@ status = "okay"; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &sata0 { status = "okay"; }; -- cgit From 389f6f8b3eb00972f05f0ca03295c2d00ddef53d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 8 Feb 2018 11:34:12 +0100 Subject: ARM: dts: porter: Enable watchdog support Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by: Geert Uytterhoeven Acked-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-porter.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index c14e6fe9e4f6..4dd5a5db2de8 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -471,6 +471,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &ssi1 { shared-pin; }; -- cgit From b27f039979a057c66e67c9310a625152b473cbe8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 8 Feb 2018 11:34:13 +0100 Subject: ARM: dts: blanche: Enable watchdog support Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by: Geert Uytterhoeven Acked-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index 9b67dca6c9ef..04fb70931b3b 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -239,6 +239,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; -- cgit From 9a3b0adee13a9a65bee0c305286793ebb96a1cd8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 8 Feb 2018 11:34:14 +0100 Subject: ARM: dts: wheat: Enable watchdog support Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by: Geert Uytterhoeven Acked-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-wheat.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index 95aab56a56ab..db01de7a3811 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -168,6 +168,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; -- cgit From 80aed52aff94875c600d976d6d94126f31c7c052 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 8 Feb 2018 11:34:15 +0100 Subject: ARM: dts: gose: Enable watchdog support Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by: Geert Uytterhoeven Acked-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793-gose.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 9ed6961f2d9a..7a66d885e657 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -595,6 +595,11 @@ status = "okay"; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; -- cgit From 2d8cc50d9633fd4145272e10080ed6ac086129d4 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 8 Feb 2018 11:34:16 +0100 Subject: ARM: dts: alt: Enable watchdog support Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by: Geert Uytterhoeven Acked-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-alt.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 26a883484ea8..1ecc5b9135f3 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -330,6 +330,11 @@ status = "okay"; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-1 = <&sdhi0_pins_uhs>; -- cgit From c9603026f9dd47f5f4b079a3ca587e135ccd4e72 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 8 Feb 2018 11:34:17 +0100 Subject: ARM: dts: silk: Enable watchdog support Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by: Geert Uytterhoeven Acked-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-silk.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 351cb3b3d966..e2642d2c2eed 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -540,6 +540,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &ssi1 { shared-pin; }; -- cgit From 8cdb8f1ab7efbd88868d3067ec1f211ff289bc01 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 24 Apr 2018 09:56:03 +0100 Subject: ARM: dts: r8a77470: Add SCIF support Describe SCIF ports in the R8A77470 device tree. Also it fixes the CPG clock index ZS from 6 to 5. Fixes: 6929dfc5918049 ("ARM: dts: r8a77470: Initial SoC device tree") Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 69 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 67 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 2f89f33f5b88..39549f28be85 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -190,19 +190,84 @@ dma-channels = <15>; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE 5>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 721>; + status = "disabled"; + }; + scif1: serial@e6e68000 { compatible = "renesas,scif-r8a77470", "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e68000 0 0x40>; interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE 6>, <&scif_clk>; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE 5>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc 32>; resets = <&cpg 720>; status = "disabled"; }; + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE 5>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 719>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE 5>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 718>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE 5>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 715>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE 5>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 714>; + status = "disabled"; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit From e4696122205634f40e26f9c33359a71823d1e68c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 24 Apr 2018 09:56:04 +0100 Subject: ARM: dts: r8a77470: Add SCIF DMA support Add SCIF DMA support for R8A77470 SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 39549f28be85..baec3cae49d5 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -198,6 +198,9 @@ clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE 5>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 721>; status = "disabled"; @@ -211,6 +214,9 @@ clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE 5>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 720>; status = "disabled"; @@ -224,6 +230,9 @@ clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE 5>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 719>; status = "disabled"; @@ -237,6 +246,9 @@ clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE 5>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 718>; status = "disabled"; @@ -250,6 +262,9 @@ clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE 5>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 715>; status = "disabled"; @@ -263,6 +278,9 @@ clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE 5>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 714>; status = "disabled"; -- cgit From 5d3b50d3c04dc277258dfca02afdddd8e69ecd29 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 22 Apr 2018 13:35:25 +0300 Subject: ARM: dts: renesas: r8a7790: Add FDP1 instances The r8a7790 has three FDP1 instances. Signed-off-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 7ba62b7aa0ba..0f1948d560d7 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1616,6 +1616,33 @@ resets = <&cpg 128>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 118>; + }; + + fdp1@fe948000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe948000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 117>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 117>; + }; + vsp@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; -- cgit From f70b0958c044a73188056a231d40a8af55c04dd2 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 24 Apr 2018 16:37:32 +0100 Subject: ARM: dts: r8a77470: Add EtherAVB support Define the generic R8A77470 part of the EtherAVB device node. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index baec3cae49d5..c85032f9605b 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -190,6 +190,19 @@ dma-channels = <15>; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77470", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc 32>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77470", "renesas,rcar-gen2-scif", "renesas,scif"; -- cgit From b6ef074bcadf9f89295bc7ee19424714b6ffc4c8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 24 Apr 2018 16:37:33 +0100 Subject: ARM: dts: iwg23s-sbc: Add EtherAVB support Define the iW-RainboW-G23S board dependent part of the EtherAVB device node. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index d21baad9f0ad..e3585daafdd6 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -12,11 +12,12 @@ compatible = "iwave,g23s", "renesas,r8a77470"; aliases { + ethernet0 = &avb; serial1 = &scif1; }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial1:115200n8"; }; @@ -26,6 +27,18 @@ }; }; +&avb { + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + reg = <3>; + micrel,led-mode = <1>; + }; +}; + &extal_clk { clock-frequency = <20000000>; }; -- cgit From b9ac80c815eabb81b66dc2dad2bb1a376915aeca Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Mon, 30 Apr 2018 11:53:25 +0100 Subject: ARM: dts: r8a7790: Fix sort order of VSP1/FDP1 nodes Commit 5d3b50d3c04d ("ARM: dts: renesas: r8a7790: Add FDP1 instances") introduced the FDP1 for the r8a7790, but broke the sort ordering of the device tree nodes. Move the last VSP up to it's peers to correct the ordering. Signed-off-by: Kieran Bingham Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 0f1948d560d7..b64d99e3ad9d 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1616,6 +1616,15 @@ resets = <&cpg 128>; }; + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + fdp1@fe940000 { compatible = "renesas,fdp1"; reg = <0 0xfe940000 0 0x2400>; @@ -1643,15 +1652,6 @@ resets = <&cpg 117>; }; - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - jpu: jpeg-codec@fe980000 { compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu"; -- cgit From bedbe61959a803b54350df93a517d98329ec160e Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 26 Apr 2018 11:42:43 +0200 Subject: ARM: dts: lager: Drop unnecessary address properties from port node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The vin port node does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/r8a7790-lager.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef1000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Simon Horman Reviewed-by: Niklas Söderlund --- arch/arm/boot/dts/r8a7790-lager.dts | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 3c66366f7c55..d1e582b0ab66 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -890,9 +890,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - vin1ep0: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; -- cgit From 99a755f586ac113cfd2c4355f7a794b3b2361229 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 26 Apr 2018 11:42:43 +0200 Subject: ARM: dts: porter: Drop unnecessary address properties from vin port node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The vin port node does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/r8a7791-porter.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without Signed-off-by: Simon Horman Reviewed-by: Niklas Söderlund --- arch/arm/boot/dts/r8a7791-porter.dts | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index 4dd5a5db2de8..876d38f46367 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -386,9 +386,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; -- cgit From c1eb7457ad6e9f3e2937f39ebfefb82cd729d625 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 26 Apr 2018 11:42:43 +0200 Subject: ARM: dts: gose: Drop unnecessary address properties from port nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The vin port nodes does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/r8a7793-gose.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/boot/dts/r8a7793-gose.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef1000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Simon Horman Reviewed-by: Niklas Söderlund --- arch/arm/boot/dts/r8a7793-gose.dts | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 7a66d885e657..ec94e2402bdf 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -759,9 +759,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep2: endpoint { remote-endpoint = <&adv7612_out>; bus-width = <24>; @@ -781,9 +778,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - vin1ep: endpoint { remote-endpoint = <&adv7180_out>; bus-width = <8>; -- cgit From 778dff91e83da64c55dd7cbe3489793797a9775e Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 26 Apr 2018 11:42:43 +0200 Subject: ARM: dts: koelsch: Drop unnecessary address properties from port nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The vin port nodes does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/r8a7791-koelsch.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/boot/dts/r8a7791-koelsch.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef1000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Simon Horman Reviewed-by: Niklas Söderlund --- arch/arm/boot/dts/r8a7791-koelsch.dts | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index fcdd0164142b..68e8272cb90e 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -849,9 +849,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep2: endpoint { remote-endpoint = <&adv7612_out>; bus-width = <24>; @@ -870,9 +867,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin1ep: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; -- cgit From 03c3a66b4d72aa1ad9bf7a943270f1794c443e50 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 26 Apr 2018 11:42:43 +0200 Subject: ARM: dts: alt: Drop unnecessary address properties from vin port node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The vin port node does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/r8a7794-alt.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Simon Horman Reviewed-by: Niklas Söderlund --- arch/arm/boot/dts/r8a7794-alt.dts | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 1ecc5b9135f3..c210412f80ec 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -380,9 +380,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; -- cgit From d6e801d102b6d970a2d0b328b8bf589eee977e3e Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 26 Apr 2018 11:42:43 +0200 Subject: ARM: dts: silk: Drop unnecessary address properties from vin port node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The vin port node does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/r8a7794-silk.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Simon Horman Reviewed-by: Niklas Söderlund --- arch/arm/boot/dts/r8a7794-silk.dts | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index e2642d2c2eed..7808aaee6644 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -475,9 +475,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; -- cgit From 715d571162e0956a332ef52c5ba465f4f7089746 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 26 Apr 2018 11:42:43 +0200 Subject: ARM: dts: kzm9d: Drop unnecessary address properties from gpio_keys node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The gpio_keys node does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/emev2-kzm9d.dtb: Warning (avoid_unnecessary_addr_size): /gpio_keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Simon Horman Reviewed-by: Niklas Söderlund --- arch/arm/boot/dts/emev2-kzm9d.dts | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index c238407133bf..0af44b7eadb9 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -34,9 +34,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - one { debounce-interval = <50>; wakeup-source; -- cgit From 0b3d8740a835b7e5476be617b77f1c494236c306 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 7 May 2018 14:40:02 +0200 Subject: ARM: shmobile: r8a7794: alt: add EEPROM to DTS Same EEPROM as on Koelsch, et al. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-alt.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index c210412f80ec..e17027532941 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -181,6 +181,12 @@ }; }; }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; }; /* -- cgit From 2acb79e15119512da9b6a49906840e7678cfb618 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:19:52 +0200 Subject: ARM: dts: r8a7790: Correct mask for GIC PPI interrupts R-Car H2 (r8a7790) contains four Cortex-A15 and four Cortex-A7 cores, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts can be delivered to all 8 processor cores. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index b64d99e3ad9d..0a426548a212 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1554,7 +1554,7 @@ interrupt-controller; reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; @@ -1761,10 +1761,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clock - can be overridden by the board */ -- cgit From 45e75c425bdd1dd75d93eeaaef4c81d1563f2efa Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:19:53 +0200 Subject: ARM: dts: r8a73a4: Correct mask for GIC PPI interrupts R-Mobile APE6 (r8a73a4) contains four Cortex-A15 and four Cortex-A7 cores, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", so GIC interrupts are delivered to all 8 processor cores. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 8e48090e4fdc..080d037f5733 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -57,10 +57,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; dbsc1: memory-controller@e6790000 { @@ -464,7 +464,7 @@ <0 0xf1002000 0 0x2000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; + interrupts = ; clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; clock-names = "clk"; power-domains = <&pd_c4>; -- cgit From 57a66497e1b7486609250a482f05935eae5035e9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:40:04 +0200 Subject: ARM: dts: sh73a0: Add missing interrupt-affinity to PMU node The PMU node references two interrupts, but lacks the interrupt-affinity property, which is required in that case: hw perfevents: no interrupt-affinity property for /pmu, guessing. Add the missing property to fix this. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 39cc58672bf4..c953648a5f41 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -22,7 +22,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; @@ -31,7 +31,7 @@ power-domains = <&pd_a2sl>; next-level-cache = <&L2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; @@ -91,6 +91,7 @@ compatible = "arm,cortex-a9-pmu"; interrupts = , ; + interrupt-affinity = <&cpu0>, <&cpu1>; }; cmt1: timer@e6138000 { -- cgit From 7207b94754b6f503b278b5b200faaf662ffa1da8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:40:05 +0200 Subject: ARM: dts: emev2: Add missing interrupt-affinity to PMU node The PMU node references two interrupts, but lacks the interrupt-affinity property, which is required in that case: hw perfevents: no interrupt-affinity property for /pmu, guessing. Add the missing property to fix this. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/emev2.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 42ea246e71cb..fec1241b858f 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -31,13 +31,13 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <533000000>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; @@ -57,6 +57,7 @@ compatible = "arm,cortex-a9-pmu"; interrupts = , ; + interrupt-affinity = <&cpu0>, <&cpu1>; }; clocks@e0110000 { -- cgit From c02cc235a215e9c518f98da25753b9e02bb7144f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:24:48 +0200 Subject: ARM: dts: r7s72100: Correct watchdog timer interrupt type According to table 7.3 ("List of Interrupt IDs") in the RZ/A1H Hardware User's Manual rev. 3.00, the watchdog timer interrupt is a level interrupt. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 4a1aade0e751..c7b3dca6d81c 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -387,7 +387,7 @@ wdt: watchdog@fcfe0000 { compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; reg = <0xfcfe0000 0x6>; - interrupts = ; + interrupts = ; clocks = <&p0_clk>; }; -- cgit From cad8e5a7a1e27e9efe4e706ace75e0826a79707f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:24:49 +0200 Subject: ARM: dts: r7s72100: Correct RTC interrupt types According to table 7.3 ("List of Interrupt IDs") in the RZ/A1H Hardware User's Manual rev. 3.00, the realtime clock interrupts are level not edge interrupts. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index c7b3dca6d81c..eb2e6f95a2e8 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -682,9 +682,9 @@ rtc: rtc@fcff1000 { compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; reg = <0xfcff1000 0x2e>; - interrupts = ; + interrupts = , + , + ; interrupt-names = "alarm", "period", "carry"; clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, <&rtc_x3_clk>, <&extal_clk>; -- cgit From 74a0e50d70aa8f7baeaad7a5c5f7d6bdaf92ff1a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:57:00 +0200 Subject: ARM: dts: r7s72100: Add PMU device node Enable support for the ARM Performance Monitor Units in the Cortex-A9 CPU core on RZ/A1H by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index eb2e6f95a2e8..a54822e97bac 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -77,6 +77,11 @@ clock-div = <6>; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + rtc_x1_clk: rtc_x1 { #clock-cells = <0>; compatible = "fixed-clock"; -- cgit From 5b68384469af764caa2c02f2c651409c6930c767 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:57:01 +0200 Subject: ARM: dts: r8a7790: Add PMU device nodes Enable support for the ARM Performance Monitor Units in the Cortex-A15 and Cortex-A7 CPU cores on R-Car H2 by adding device nodes for the two PMUs. New Linux output: hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available hw perfevents: /pmu-1: failed to probe PMU! hw perfevents: /pmu-1: failed to register PMU devices! The last two lines are due to the Cortex-A7 CPU cores being described in DT, but not enabled by the firmware. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 0a426548a212..ae97ec146260 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -202,6 +202,24 @@ clock-frequency = <0>; }; + pmu-0 { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + pmu-1 { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; -- cgit From 8607428c96b94e9f53f46b6e5aa3b9dbd604ad07 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:57:02 +0200 Subject: ARM: dts: r8a7791: Add PMU device node Enable support for the ARM Performance Monitor Units in the Cortex-A15 CPU cores on R-Car M2-W by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 570ca12422c5..828ad78c3337 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -126,6 +126,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; -- cgit From 0f2bcba999463fcc2ad2d6ae0c91b62649d45190 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:57:03 +0200 Subject: ARM: dts: r8a7792: Add PMU device node Enable support for the ARM Performance Monitor Units in the Cortex-A15 CPU cores on R-Car V2H by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index d2cf8dd2d9b0..f44257dd86f6 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -85,6 +85,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; -- cgit From cd1ce84a08e69450ee196edcb7686c78ff5b57c5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:57:04 +0200 Subject: ARM: dts: r8a7793: Add PMU device node Enable support for the ARM Performance Monitor Units in the Cortex-A15 CPU cores on R-Car M2-N by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 6975b0efc46c..4c29de510481 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -110,6 +110,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; -- cgit From 123703f0beebcd432ea204e9ac83150b23646088 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:57:05 +0200 Subject: ARM: dts: r8a7794: Add PMU device node Enable support for the ARM Performance Monitor Units in the Cortex-A7 CPU cores on R-Car E2 by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 76aadcdf9d37..736196903d22 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -103,6 +103,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; -- cgit From fe60e933b053f00e53cd01fe323f25ebe8fecd52 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:57:06 +0200 Subject: ARM: dts: r8a7743: Add PMU device node Enable support for the ARM Performance Monitor Units in the Cortex-A15 CPU cores on RZ/G1M by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 69d8f7e0f053..142949d7066f 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -125,6 +125,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; -- cgit From 9562a6b1d0f6a287f5dda16a4538526c59408927 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 15:57:07 +0200 Subject: ARM: dts: r8a7745: Add PMU device node Enable support for the ARM Performance Monitor Units in the Cortex-A7 CPU cores on RZ/G1E by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 3de69cb66c44..1cb7a7ab0418 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -105,6 +105,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; -- cgit From c4e96f74ad46d1139e1f31ec925c5bb21aa9830e Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 11 Apr 2018 18:35:53 +0900 Subject: arm64: dts: renesas: Add Renesas R8A77990 Kconfig support Add configuration option for the R-Car E3 (R8A77990) SoC. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/Kconfig.platforms | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 2b1535cdeb7c..d5aeac351fc3 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -208,6 +208,12 @@ config ARCH_R8A77980 help This enables support for the Renesas R-Car V3H SoC. +config ARCH_R8A77990 + bool "Renesas R-Car E3 SoC Platform" + depends on ARCH_RENESAS + help + This enables support for the Renesas R-Car E3 SoC. + config ARCH_R8A77995 bool "Renesas R-Car D3 SoC Platform" depends on ARCH_RENESAS -- cgit From 02f15e4be78610fbde26aa182ff147f2cc8d2e77 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Tue, 17 Apr 2018 22:54:27 +0200 Subject: arm64: dts: renesas: r8a7795: decrease temperature hysteresis MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To incorporate more tests by the hardware team decrease the hysteresis value to 1C. Signed-off-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 0e958ecd2a41..acf0c6f72a4d 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -2437,12 +2437,12 @@ trips { sensor1_passive: sensor1-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor1_crit: sensor1-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2463,12 +2463,12 @@ trips { sensor2_passive: sensor2-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor2_crit: sensor2-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2489,12 +2489,12 @@ trips { sensor3_passive: sensor3-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor3_crit: sensor3-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; -- cgit From 1f153093b0bb6a9b46cb410ee3535d990348a2b3 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Tue, 17 Apr 2018 22:54:28 +0200 Subject: arm64: dts: renesas: r8a7796: decrease temperature hysteresis MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To incorporate more tests by the hardware team decrease the hysteresis value to 1C. Signed-off-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 55a64169d3d4..e6254711556c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -2072,12 +2072,12 @@ trips { sensor1_passive: sensor1-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor1_crit: sensor1-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2098,12 +2098,12 @@ trips { sensor2_passive: sensor2-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor2_crit: sensor2-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2124,12 +2124,12 @@ trips { sensor3_passive: sensor3-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor3_crit: sensor3-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; -- cgit From b4f92030d5d39df427e72ace7f7db04dc8b35ddb Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 12 Apr 2018 10:13:58 +0200 Subject: arm64: dts: renesas: r8a77970: add VSPD support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe VSPD0 in the R8A77970 device tree; it will be used by DU in the next patch... Based on the original (and large) patch by Daisuke Matsushita . Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Niklas Söderlund Signed-off-by: Jacopo Mondi Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 71f466daa036..9a7cf2ab099e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -625,6 +625,16 @@ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 603>; }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 623>; + renesas,fcp = <&fcpvd0>; + }; }; timer { -- cgit From f66598b95dbac72365f5b81ffa61ca6357af6b22 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 12 Apr 2018 10:13:59 +0200 Subject: arm64: dts: renesas: r8a77970: add DU support Define the generic R8A77970 part of the DU device node. Based on the original (and large) patch by Daisuke Matsushita . Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 9a7cf2ab099e..8efb5c3a5da1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -635,6 +635,35 @@ resets = <&cpg 623>; renesas,fcp = <&fcpvd0>; }; + + du: display@feb00000 { + compatible = "renesas,du-r8a77970"; + reg = <0 0xfeb00000 0 0x80000>; + interrupts = ; + clocks = <&cpg CPG_MOD 724>; + clock-names = "du.0"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 724>; + vsps = <&vspd0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + }; + }; }; timer { -- cgit From 3cd0bd7d92bb54dc224e23dcb2cc319ff83b7b73 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 12 Apr 2018 10:14:00 +0200 Subject: arm64: dts: renesas: r8a77970: add LVDS support Define the generic R8A77970 part of the LVDS device node. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 8efb5c3a5da1..a194cb8d7d62 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -660,6 +660,34 @@ port@1 { reg = <1>; du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds-encoder@feb90000 { + compatible = "renesas,r8a77970-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = + <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { }; }; }; -- cgit From 3c3d1672664aff2f7f938d2d206e47cecdf6b4ef Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 12 Apr 2018 10:14:01 +0200 Subject: arm64: dts: renesas: eagle: Enable HDMI output MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable HDMI output on Renesas R-Car V3M Eagle board. The HDMI output is enabled connecting the DU LVDS output to the transparent LVDS converter THC63LVD1024, and successively routing its RGB output to the ADV7511W HDMI encoder. Signed-off-by: Niklas Söderlund Signed-off-by: Jacopo Mondi Reviewed-by: Laurent Pinchart [for THC63LVD1024: ] Reviewed-by: Andrzej Hajda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 93 ++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 3c5f598c9766..ebfbb51ab168 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -31,6 +31,51 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + d3p3: regulator-fixed { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + lvds-decoder { + compatible = "thine,thc63lvd1024"; + + vcc-supply = <&d3p3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + thc63lvd1024_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@2 { + reg = <2>; + thc63lvd1024_out: endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; + }; }; &avb { @@ -68,6 +113,38 @@ gpio-controller; #gpio-cells = <2>; }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&thc63lvd1024_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; }; &pfc { @@ -93,3 +170,19 @@ status = "okay"; }; + +&du { + status = "okay"; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&thc63lvd1024_in>; + }; + }; + }; +}; -- cgit From 21559e2b0448cb43e880d46b1381008dc5e9707d Mon Sep 17 00:00:00 2001 From: Yoshihiro Kaneko Date: Thu, 19 Apr 2018 05:14:36 +0900 Subject: arm64: dts: renesas: r8a77995: sort subnodes of the root node Sort subnodes of the root node alphanumerically. This is part of an ongoing effort to provide consistent node order in the DT of Renesas SoCs to improve maintainability. This should not have any run-time effect. Signed-off-by: Yoshihiro Kaneko Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 82aed7ee984c..cf476556504a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -18,9 +18,11 @@ #address-cells = <2>; #size-cells = <2>; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; cpus { @@ -51,18 +53,16 @@ clock-frequency = <0>; }; - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; -- cgit From 7c55747fbe82237b4e22eaae3673e7d166c175d6 Mon Sep 17 00:00:00 2001 From: Yoshihiro Kaneko Date: Thu, 19 Apr 2018 05:14:37 +0900 Subject: arm64: dts: renesas: r8a77995: sort subnodes of the soc node Sort subnodes of the soc node. - The primary key is the bus address. - The secondary key is the IP block. - The tertiary key is the node name. This is part of an ongoing effort to provide consistent node order in the DT of Renesas SoCs to improve maintainability. This should not have any run-time effect. Signed-off-by: Yoshihiro Kaneko Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 697 +++++++++++++++--------------- 1 file changed, 348 insertions(+), 349 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index cf476556504a..a97830589b0d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -76,23 +76,6 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - rwdt: watchdog@e6020000 { compatible = "renesas,r8a77995-wdt", "renesas,rcar-gen3-wdt"; @@ -103,88 +86,123 @@ status = "disabled"; }; - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_vp0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - #iommu-cells = <1>; - status = "disabled"; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 9>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - #iommu-cells = <1>; - status = "disabled"; + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - #iommu-cells = <1>; - status = "disabled"; + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - #iommu-cells = <1>; - status = "disabled"; + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 10>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - #iommu-cells = <1>; - status = "disabled"; + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - #iommu-cells = <1>; - status = "disabled"; + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 21>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - #iommu-cells = <1>; - status = "disabled"; + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 14>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 906>; }; - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77995"; + reg = <0 0xe6060000 0 0x508>; }; - cpg: clock-controller@e6150000 { compatible = "renesas,r8a77995-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -200,16 +218,6 @@ reg = <0 0xe6160000 0 0x0200>; }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77995"; - reg = <0 0xe6060000 0 0x508>; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a77995-sysc"; reg = <0 0xe6180000 0 0x0400>; @@ -232,6 +240,98 @@ resets = <&cpg 407>; }; + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a77995-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77995_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a77995", "renesas,rcar-dmac"; @@ -304,173 +404,85 @@ dma-channels = <8>; }; - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 9>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 911>; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + #iommu-cells = <1>; + status = "disabled"; }; - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 910>; + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + #iommu-cells = <1>; + status = "disabled"; }; - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 10>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 909>; + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + #iommu-cells = <1>; + status = "disabled"; }; - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 908>; + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; }; - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 21>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 907>; + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + #iommu-cells = <1>; + status = "disabled"; }; - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 14>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 906>; + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + #iommu-cells = <1>; + status = "disabled"; }; - can0: can@e6c30000 { - compatible = "renesas,can-r8a77995", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 916>; + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + #iommu-cells = <1>; status = "disabled"; }; - can1: can@e6c38000 { - compatible = "renesas,can-r8a77995", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 915>; + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + #iommu-cells = <1>; status = "disabled"; }; - canfd: can@e66c0000 { - compatible = "renesas,r8a77995-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 914>; + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + #iommu-cells = <1>; status = "disabled"; + }; - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + #iommu-cells = <1>; + status = "disabled"; }; avb: ethernet@e6800000 { @@ -519,87 +531,35 @@ status = "disabled"; }; - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; + can0: can@e6c30000 { + compatible = "renesas,can-r8a77995", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A77995_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; + assigned-clock-rates = <40000000>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 916>; status = "disabled"; }; - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; + can1: can@e6c38000 { + compatible = "renesas,can-r8a77995", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A77995_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; + assigned-clock-rates = <40000000>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 915>; status = "disabled"; }; @@ -643,38 +603,43 @@ status = "disabled"; }; - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a77995", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 312>; + resets = <&cpg 310>; status = "disabled"; }; - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 703>; phys = <&usb2_phy0>; phy-names = "usb"; - companion = <&ohci0>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 703>; status = "disabled"; }; - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 703>; phys = <&usb2_phy0>; phy-names = "usb"; + companion = <&ohci0>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 703>; status = "disabled"; @@ -692,6 +657,35 @@ status = "disabled"; }; + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a77995", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + vspbs: vsp@fe960000 { compatible = "renesas,vsp2"; reg = <0 0xfe960000 0 0x8000>; @@ -702,15 +696,6 @@ renesas,fcp = <&fcpvb0>; }; - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x8000>; @@ -721,15 +706,6 @@ renesas,fcp = <&fcpvd0>; }; - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; reg = <0 0xfea28000 0 0x8000>; @@ -740,6 +716,24 @@ renesas,fcp = <&fcpvd1>; }; + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 607>; + iommus = <&ipmmu_vp0 5>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + fcpvd1: fcp@fea2f000 { compatible = "renesas,fcpv"; reg = <0 0xfea2f000 0 0x200>; @@ -783,6 +777,11 @@ }; }; }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; }; timer { -- cgit From 001f3b032fa12069244d17a15ecd06cbf3040880 Mon Sep 17 00:00:00 2001 From: Yoshihiro Kaneko Date: Thu, 19 Apr 2018 05:14:38 +0900 Subject: arm64: dts: renesas: r8a77965: sort subnodes of the root node Sort subnodes of the root node alphanumerically. This is part of an ongoing effort to provide consistent node order in the DT of Renesas SoCs to improve maintainability. This should not have any run-time effect. Signed-off-by: Yoshihiro Kaneko Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 120 +++++++++++++++--------------- 1 file changed, 60 insertions(+), 60 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index a41f91653d93..d110382276b7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -22,9 +22,34 @@ i2c7 = &i2c_dvfs; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; cpus { @@ -71,34 +96,24 @@ clock-frequency = <0>; }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, + <&a57_1>; }; - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; }; /* External SCIF clock - to be overridden by boards that provide it */ @@ -108,42 +123,6 @@ clock-frequency = <0>; }; - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>; - }; - soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -1073,4 +1052,25 @@ /* placeholder */ }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; }; -- cgit From 2af6f5a3fd585427fcab5848e87223a486e74c37 Mon Sep 17 00:00:00 2001 From: Yoshihiro Kaneko Date: Thu, 19 Apr 2018 05:14:39 +0900 Subject: arm64: dts: renesas: r8a77965: sort subnodes of the soc node Sort subnodes of the soc node. - The primary key is the bus address. - The secondary key is the IP block. - The tertiary key is the node name. This is part of an ongoing effort to provide consistent node order in the DT of Renesas SoCs to improve maintainability. This should not have any run-time effect. Signed-off-by: Yoshihiro Kaneko Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 912 +++++++++++++++--------------- 1 file changed, 456 insertions(+), 456 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index d110382276b7..b12f41755aea 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -130,52 +130,9 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc 32>; - resets = <&cpg 408>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77965"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77965-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77965-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77965-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; + wdt0: watchdog@e6020000 { + reg = <0 0xe6020000 0 0x0c>; + /* placeholder */ }; gpio0: gpio@e6050000 { @@ -298,6 +255,32 @@ resets = <&cpg 905>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77965"; + reg = <0 0xe6060000 0 0x50c>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77965-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77965-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77965-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; #interrupt-cells = <2>; @@ -314,6 +297,121 @@ resets = <&cpg 407>; }; + i2c0: i2c@e6500000 { + reg = <0 0xe6500000 0 0x40>; + /* placeholder */ + }; + + i2c1: i2c@e6508000 { + reg = <0 0xe6508000 0 0x40>; + /* placeholder */ + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0xe6510000 0 0x40>; + /* placeholder */ + }; + + i2c3: i2c@e66d0000 { + reg = <0 0xe66d0000 0 0x40>; + /* placeholder */ + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0xe66d8000 0 0x40>; + /* placeholder */ + }; + + i2c5: i2c@e66e0000 { + reg = <0 0xe66e0000 0 0x40>; + /* placeholder */ + }; + + i2c6: i2c@e66e8000 { + reg = <0 0xe66e8000 0 0x40>; + /* placeholder */ + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a77965", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc 32>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7796", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc 32>; + resets = <&cpg 704>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a77965-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc 32>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a77965-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc 32>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a77965-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc 32>; + resets = <&cpg 328>; + #phy-cells = <0>; + status = "disabled"; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a77965", "renesas,rcar-dmac"; @@ -416,35 +514,150 @@ dma-channels = <16>; }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77965", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc 32>; - resets = <&cpg 207>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc 32>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE 20>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE 20>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 206>; status = "disabled"; @@ -513,69 +726,66 @@ status = "disabled"; }; - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77965", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; - resets = <&cpg 812>; - phy-mode = "rgmii"; + resets = <&cpg 211>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; - csi20: csi2@fea80000 { - reg = <0 0xfea80000 0 0x10000>; - /* placeholder */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - }; + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; - csi40: csi2@feaa0000 { - reg = <0 0xfeaa0000 0 0x10000>; - /* placeholder */ + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; vin0: video@e6ef0000 { @@ -618,6 +828,58 @@ /* placeholder */ }; + rcar_sound: sound@ec500000 { + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + /* placeholder */ + + rcar_sound,dvc { + dvc0: dvc-0 { + }; + dvc1: dvc-1 { + }; + }; + + rcar_sound,src { + src0: src-0 { + }; + src1: src-1 { + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + }; + ssi1: ssi-1 { + }; + }; + }; + + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a77965", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc 32>; + resets = <&cpg 328>; + status = "disabled"; + }; + + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a77965-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc 32>; + resets = <&cpg 328>; + status = "disabled"; + }; + ohci0: usb@ee080000 { compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; @@ -630,6 +892,18 @@ status = "disabled"; }; + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc 32>; + resets = <&cpg 702>; + status = "disabled"; + }; + ehci0: usb@ee080100 { compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; @@ -643,6 +917,19 @@ status = "disabled"; }; + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc 32>; + resets = <&cpg 702>; + status = "disabled"; + }; + usb2_phy0: usb-phy@ee080200 { compatible = "renesas,usb2-phy-r8a77965", "renesas,rcar-gen3-usb2-phy"; @@ -666,218 +953,71 @@ status = "disabled"; }; - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; - power-domains = <&sysc 32>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc 32>; - resets = <&cpg 702>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - reg = <0 0xe6500000 0 0x40>; + sdhi0: sd@ee100000 { + reg = <0 0xee100000 0 0x2000>; /* placeholder */ }; - i2c1: i2c@e6508000 { - reg = <0 0xe6508000 0 0x40>; + sdhi1: sd@ee120000 { + reg = <0 0xee120000 0 0x2000>; /* placeholder */ }; - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0 0xe6510000 0 0x40>; + sdhi2: sd@ee140000 { + reg = <0 0xee140000 0 0x2000>; /* placeholder */ }; - i2c3: i2c@e66d0000 { - reg = <0 0xe66d0000 0 0x40>; + sdhi3: sd@ee160000 { + reg = <0 0xee160000 0 0x2000>; /* placeholder */ }; - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0 0xe66d8000 0 0x40>; - /* placeholder */ + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; }; - i2c5: i2c@e66e0000 { - reg = <0 0xe66e0000 0 0x40>; + pciec0: pcie@fe000000 { + reg = <0 0xfe000000 0 0x80000>; /* placeholder */ }; - i2c6: i2c@e66e8000 { - reg = <0 0xe66e8000 0 0x40>; + pciec1: pcie@ee800000 { + reg = <0 0xee800000 0 0x80000>; /* placeholder */ }; - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a77965", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc 32>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc 32>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc 32>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc 32>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc 32>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc 32>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc 32>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc 32>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + csi20: csi2@fea80000 { + reg = <0 0xfea80000 0 0x10000>; + /* placeholder */ - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + csi40: csi2@feaa0000 { + reg = <0 0xfeaa0000 0 0x10000>; + /* placeholder */ - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; du: display@feb00000 { @@ -907,149 +1047,9 @@ }; }; - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a77965-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc 32>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a77965-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc 32>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7796", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&sysc 32>; - resets = <&cpg 704>; - status = "disabled"; - }; - - pciec0: pcie@fe000000 { - reg = <0 0xfe000000 0 0x80000>; - /* placeholder */ - }; - - pciec1: pcie@ee800000 { - reg = <0 0xee800000 0 0x80000>; - /* placeholder */ - }; - - rcar_sound: sound@ec500000 { - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - /* placeholder */ - - rcar_sound,dvc { - dvc0: dvc-0 { - }; - dvc1: dvc-1 { - }; - }; - - rcar_sound,src { - src0: src-0 { - }; - src1: src-1 { - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - }; - ssi1: ssi-1 { - }; - }; - }; - - sdhi0: sd@ee100000 { - reg = <0 0xee100000 0 0x2000>; - /* placeholder */ - }; - - sdhi1: sd@ee120000 { - reg = <0 0xee120000 0 0x2000>; - /* placeholder */ - }; - - sdhi2: sd@ee140000 { - reg = <0 0xee140000 0 0x2000>; - /* placeholder */ - }; - - sdhi3: sd@ee160000 { - reg = <0 0xee160000 0 0x2000>; - /* placeholder */ - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a77965-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc 32>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a77965-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc 32>; - resets = <&cpg 328>; - status = "disabled"; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a77965", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc 32>; - resets = <&cpg 328>; - status = "disabled"; - }; - - wdt0: watchdog@e6020000 { - reg = <0 0xe6020000 0 0x0c>; - /* placeholder */ + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; }; }; -- cgit From 2964d7546f71c793581382a518b3f2da7a2ad5b6 Mon Sep 17 00:00:00 2001 From: Yoshihiro Kaneko Date: Thu, 19 Apr 2018 05:14:40 +0900 Subject: arm64: dts: renesas: r8a77970: sort subnodes of the soc node Sort subnodes of the soc node. - The primary key is the bus address. - The secondary key is the IP block. - The tertiary key is the node name. This is part of an ongoing effort to provide consistent node order in the DT of Renesas SoCs to improve maintainability. This should not have any run-time effect. Signed-off-by: Yoshihiro Kaneko [simon: rebased; move fcpvd0 to after vspd0] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 388 +++++++++++++++--------------- 1 file changed, 194 insertions(+), 194 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index a194cb8d7d62..c06d7fbfb7be 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -83,23 +83,6 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1010000 0 0x1000>, - <0 0xf1020000 0 0x20000>, - <0 0xf1040000 0 0x20000>, - <0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - rwdt: watchdog@e6020000 { compatible = "renesas,r8a77970-wdt", "renesas,rcar-gen3-wdt"; @@ -110,75 +93,6 @@ status = "disabled"; }; - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77970-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77970-rst"; - reg = <0 0xe6160000 0 0x200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77970-sysc"; - reg = <0 0xe6180000 0 0x440>; - #power-domain-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A77970_PD_A3IR>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77970"; - reg = <0 0xe6060000 0 0x504>; - }; - gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77970", "renesas,rcar-gen3-gpio"; @@ -269,6 +183,32 @@ resets = <&cpg 907>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77970"; + reg = <0 0xe6060000 0 0x504>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77970-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77970-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77970-sysc"; + reg = <0 0xe6180000 0 0x440>; + #power-domain-cells = <1>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; #interrupt-cells = <2>; @@ -285,67 +225,6 @@ resets = <&cpg 407>; }; - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77970", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77970", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; - }; - i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a77970", "renesas,rcar-gen3-i2c"; @@ -502,6 +381,51 @@ status = "disabled"; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77970", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_rt 3>; + #address-cells = <1>; + #size-cells = <0>; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77970", "renesas,rcar-gen3-scif", @@ -573,57 +497,120 @@ status = "disabled"; }; - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77970", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a77970", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_rt 3>; - #address-cells = <1>; - #size-cells = <0>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <8>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; }; - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a77970", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 603>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <8>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A77970_PD_A3IR>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1010000 0 0x1000>, + <0 0xf1020000 0 0x20000>, + <0 0xf1040000 0 0x20000>, + <0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; vspd0: vsp@fea20000 { @@ -636,6 +623,14 @@ renesas,fcp = <&fcpvd0>; }; + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a77970"; reg = <0 0xfeb00000 0 0x80000>; @@ -692,6 +687,11 @@ }; }; }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; }; timer { -- cgit From f37a7767f6c4ec66c3df227ad4028e5390322202 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 20 Apr 2018 21:28:16 +0900 Subject: arm64: dts: renesas: Add Renesas R8A77990 SoC support This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC: - PSCI - CPU (single) - Cache controller - Main clocks and controller - Interrupt controller - Timer - PMU - Reset controller - Product register - System controller - UART for console Inspried by a patch by Takeshi Kihara in the BSP. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 127 ++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77990.dtsi (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi new file mode 100644 index 000000000000..3a19b9ebdd6e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree Source for the r8a77990 SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r8a77990"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* 1 core only at this point */ + a53_0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc 5>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA53: cache-controller@0 { + compatible = "cache"; + reg = <0>; + power-domains = <&sysc 21>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77990-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77990-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77990-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a77990", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 310>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- cgit From 77049191b24b45868f68b34f43d6eb072b26c847 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Fri, 20 Apr 2018 21:28:17 +0900 Subject: arm64: dts: renesas: Add Renesas Ebisu board support Basic support for the Renesas Ebisu board based on R-Car E3: - Memory, - Main crystal, - Serial console, Signed-off-by: Takeshi Kihara [shimoda: rebase and add SPDX-License-Identifier] Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/Makefile | 1 + arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 37 ++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 5ede06000ea4..a235961c6532 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -10,4 +10,5 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb +dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts new file mode 100644 index 000000000000..63ee1347bb19 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree Source for the ebisu board + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a77990.dtsi" + +/ { + model = "Renesas Ebisu board based on r8a77990"; + compatible = "renesas,ebisu", "renesas,r8a77990"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <48000000>; +}; + +&scif2 { + status = "okay"; +}; -- cgit From d2ed9ffcab09f251aae6ac1d5da8a6ae62501150 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Sun, 22 Apr 2018 19:08:15 +0900 Subject: arm64: dts: renesas: r8a7795: Enable IPMMU devices Remove 'status = "disabled"' to make sure all IPMMU devices are enabled in DT on the r8a7795 SoC. Signed-off-by: Magnus Damm Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index acf0c6f72a4d..32870cbaf94d 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -947,7 +947,6 @@ renesas,ipmmu-main = <&ipmmu_mm 2>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_ir: mmu@ff8b0000 { @@ -956,7 +955,6 @@ renesas,ipmmu-main = <&ipmmu_mm 3>; power-domains = <&sysc R8A7795_PD_A3IR>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_mm: mmu@e67b0000 { @@ -974,7 +972,6 @@ renesas,ipmmu-main = <&ipmmu_mm 4>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_pv0: mmu@fd800000 { @@ -983,7 +980,6 @@ renesas,ipmmu-main = <&ipmmu_mm 6>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_pv1: mmu@fd950000 { @@ -992,7 +988,6 @@ renesas,ipmmu-main = <&ipmmu_mm 7>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_pv2: mmu@fd960000 { @@ -1001,7 +996,6 @@ renesas,ipmmu-main = <&ipmmu_mm 8>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_pv3: mmu@fd970000 { @@ -1010,7 +1004,6 @@ renesas,ipmmu-main = <&ipmmu_mm 9>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_rt: mmu@ffc80000 { @@ -1019,7 +1012,6 @@ renesas,ipmmu-main = <&ipmmu_mm 10>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_vc0: mmu@fe6b0000 { @@ -1028,7 +1020,6 @@ renesas,ipmmu-main = <&ipmmu_mm 12>; power-domains = <&sysc R8A7795_PD_A3VC>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_vc1: mmu@fe6f0000 { @@ -1037,7 +1028,6 @@ renesas,ipmmu-main = <&ipmmu_mm 13>; power-domains = <&sysc R8A7795_PD_A3VC>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_vi0: mmu@febd0000 { @@ -1054,7 +1044,6 @@ renesas,ipmmu-main = <&ipmmu_mm 15>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_vp0: mmu@fe990000 { @@ -1063,7 +1052,6 @@ renesas,ipmmu-main = <&ipmmu_mm 16>; power-domains = <&sysc R8A7795_PD_A3VP>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_vp1: mmu@fe980000 { -- cgit From 330f2dc009e937efe6618096718f12a4a5a847f8 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Sun, 22 Apr 2018 19:08:24 +0900 Subject: arm64: dts: renesas: r8a7796: Enable IPMMU devices Remove 'status = "disabled"' to make sure all IPMMU devices are enabled in DT on the r8a7796 SoC. Signed-off-by: Magnus Damm Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index e6254711556c..f33063dd7cd7 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -881,7 +881,6 @@ renesas,ipmmu-main = <&ipmmu_mm 2>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_ir: mmu@ff8b0000 { @@ -890,7 +889,6 @@ renesas,ipmmu-main = <&ipmmu_mm 3>; power-domains = <&sysc R8A7796_PD_A3IR>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_mm: mmu@e67b0000 { @@ -924,7 +922,6 @@ renesas,ipmmu-main = <&ipmmu_mm 6>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_rt: mmu@ffc80000 { @@ -933,7 +930,6 @@ renesas,ipmmu-main = <&ipmmu_mm 7>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_vc0: mmu@fe6b0000 { @@ -942,7 +938,6 @@ renesas,ipmmu-main = <&ipmmu_mm 8>; power-domains = <&sysc R8A7796_PD_A3VC>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_vi0: mmu@febd0000 { -- cgit From 344aa8f37ebf2a028fb5a1d7fac68b9b1817a2c3 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Sun, 22 Apr 2018 19:08:32 +0900 Subject: arm64: dts: renesas: r8a77970: Enable IPMMU devices Remove 'status = "disabled"' to make sure all IPMMU devices are enabled in DT on the r8a77970 SoC. Signed-off-by: Magnus Damm Reviewed-by: Geert Uytterhoeven [simon: rebased] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index c06d7fbfb7be..6ed2e95eb53d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -567,7 +567,6 @@ renesas,ipmmu-main = <&ipmmu_mm 3>; power-domains = <&sysc R8A77970_PD_A3IR>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_mm: mmu@e67b0000 { @@ -593,7 +592,6 @@ renesas,ipmmu-main = <&ipmmu_mm 9>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; #iommu-cells = <1>; - status = "disabled"; }; gic: interrupt-controller@f1010000 { -- cgit From 1c2a0de390c8c4c27c2c1dbacbecf85fcbbf9f76 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Sun, 22 Apr 2018 19:08:41 +0900 Subject: arm64: dts: renesas: r8a77995: Enable IPMMU devices Remove 'status = "disabled"' to make sure all IPMMU devices are enabled in DT on the r8a77995 SoC. Signed-off-by: Magnus Damm Reviewed-by: Geert Uytterhoeven [simon: rebased] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index a97830589b0d..ba98865b0c9b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -409,7 +409,6 @@ reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_ds1: mmu@e7740000 { @@ -417,7 +416,6 @@ reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_hc: mmu@e6570000 { @@ -425,7 +423,6 @@ reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_mm: mmu@e67b0000 { @@ -434,7 +431,6 @@ interrupts = , ; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_mp: mmu@ec670000 { @@ -442,7 +438,6 @@ reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_pv0: mmu@fd800000 { @@ -450,7 +445,6 @@ reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_rt: mmu@ffc80000 { @@ -458,7 +452,6 @@ reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 10>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_vc0: mmu@fe6b0000 { @@ -466,7 +459,6 @@ reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_vi0: mmu@febd0000 { @@ -474,7 +466,6 @@ reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; #iommu-cells = <1>; - status = "disabled"; }; ipmmu_vp0: mmu@fe990000 { @@ -482,7 +473,6 @@ reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; #iommu-cells = <1>; - status = "disabled"; }; avb: ethernet@e6800000 { -- cgit From 5f7d7808ae1162d55b835cb2faf31db19b69fdf2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 12 Mar 2018 16:12:00 +0100 Subject: arm64: dts: renesas: draak: Rename EtherAVB "mdc" pin group to "mdio" On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, now the pinctrl drivers for R-Car H3, M3-W, and M3-N have gained support for the traditional pin group name. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index d03f19414028..9d73de8bc94d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -91,7 +91,7 @@ &pfc { avb0_pins: avb { mux { - groups = "avb0_link", "avb0_mdc", "avb0_mii"; + groups = "avb0_link", "avb0_mdio", "avb0_mii"; function = "avb0"; }; }; -- cgit From 77bf06adb128ef0b47b9c49b1ae8f3313c684a70 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 12 Mar 2018 16:11:58 +0100 Subject: arm64: dts: renesas: salvator-common: Rename EtherAVB "mdc" pin group to "mdio" On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, now the pinctrl drivers for R-Car H3, M3-W, and M3-N have gained support for the traditional pin group name. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 2a7f36abd2dd..1642bc9c8906 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -416,12 +416,12 @@ avb_pins: avb { mux { - groups = "avb_link", "avb_mdc", "avb_mii"; + groups = "avb_link", "avb_mdio", "avb_mii"; function = "avb"; }; - pins_mdc { - groups = "avb_mdc"; + pins_mdio { + groups = "avb_mdio"; drive-strength = <24>; }; -- cgit From 1518ad140b9ea73cee8bc89e39f8962fbd2bb7bb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 12 Mar 2018 16:11:59 +0100 Subject: arm64: dts: renesas: ulcb: Rename EtherAVB "mdc" pin group to "mdio" On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, now the pinctrl drivers for R-Car H3, M3-W, and M3-N have gained support for the traditional pin group name. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 6f814845f8b6..93402783d52f 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -255,12 +255,12 @@ avb_pins: avb { mux { - groups = "avb_link", "avb_mdc", "avb_mii"; + groups = "avb_link", "avb_mdio", "avb_mii"; function = "avb"; }; - pins_mdc { - groups = "avb_mdc"; + pins_mdio { + groups = "avb_mdio"; drive-strength = <24>; }; -- cgit From 1119cffef3bf69e4904f5ea690dcbf70e3372d58 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 14 Mar 2018 22:58:33 +0300 Subject: arm64: dts: renesas: eagle: add EtherAVB pins Add the (previously omitted) EtherAVB pin data to the Eagle board's device tree. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index ebfbb51ab168..b800a119753b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -79,6 +79,9 @@ }; &avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; phy-handle = <&phy0>; phy-mode = "rgmii-id"; @@ -148,6 +151,11 @@ }; &pfc { + avb_pins: avb0 { + groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + i2c0_pins: i2c0 { groups = "i2c0"; function = "i2c0"; -- cgit From 68d3b03fcb5a2e7c71b1e72c6d856e6030c4f2fd Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 14 Mar 2018 23:30:34 +0300 Subject: arm64: dts: renesas: v3msk: add EtherAVB pins Add the (previously omitted) EtherAVB pin data to the V3M Starter Kit board's device tree. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index a8ceeac77992..55aa01b663e5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -32,6 +32,9 @@ }; &avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; phy-handle = <&phy0>; phy-mode = "rgmii-id"; @@ -52,6 +55,11 @@ }; &pfc { + avb_pins: avb0 { + groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + scif0_pins: scif0 { groups = "scif0_data"; function = "scif0"; -- cgit From cef26946f247c75a3b1c7919ea801d2ea8511f00 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 9 Mar 2018 15:06:32 +0300 Subject: arm64: dts: renesas: r8a77980: add PFC support Define the generic R8A77980 part of the PFC device node. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 03845fd74996..08c6708eb9dd 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -71,6 +71,11 @@ #size-cells = <2>; ranges; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77980"; + reg = <0 0xe6060000 0 0x50c>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a77980-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- cgit From a824e63cfcfd60289023d990fe01839ec0db5950 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 9 Mar 2018 15:07:51 +0300 Subject: arm64: dts: renesas: condor: add SCIF0 pins Add the (previously omitted) SCIF0 pin data to the Condor board's device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 06cf6845765a..38f11cee42dc 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -49,7 +49,22 @@ clock-frequency = <32768>; }; +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_b"; + function = "scif_clk"; + }; +}; + &scif0 { + pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; + pinctrl-names = "default"; + status = "okay"; }; -- cgit From 55cda28160e1ea852955ee17464d0dccfa67fa72 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 9 Mar 2018 15:09:38 +0300 Subject: arm64: dts: renesas: condor: add EtherAVB pins Add the (previously omitted) EtherAVB pin data to the Condor board's device tree. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 38f11cee42dc..7af5afa41795 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -30,6 +30,9 @@ }; &avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; renesas,no-ether-link; @@ -50,6 +53,11 @@ }; &pfc { + avb_pins: avb { + groups = "avb_mdio", "avb_rgmii"; + function = "avb"; + }; + scif0_pins: scif0 { groups = "scif0_data"; function = "scif0"; -- cgit From 63eb8ee5333657677789ba3454dd5b86fc53311b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 14 Apr 2018 22:27:04 +0300 Subject: arm64: dts: renesas: r8a77980: add MMC support Define the generic R8A77980 part of the MMC0 (SDHI2) device node. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 08c6708eb9dd..d27b80bcdbb4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -353,6 +353,18 @@ dma-channels = <16>; }; + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a77980", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + power-domains = <&sysc 32>; + resets = <&cpg 314>; + max-frequency = <200000000>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit From 5a0d8a6f504b04b26ae52449941c45263dd3a478 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 23 Apr 2018 01:39:39 +0000 Subject: arm64: dts: renesas: r8a7795: add HDMI sound support Signed-off-by: Kuninori Morimoto Tested-by: Nguyen Viet Dung Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 32870cbaf94d..b1c52dae4d49 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -2335,6 +2335,10 @@ port@1 { reg = <1>; }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; }; }; @@ -2360,6 +2364,10 @@ port@1 { reg = <1>; }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; }; }; -- cgit From c39f09876275022cd3e0095b9ed0a2875a065a3e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 23 Apr 2018 01:39:56 +0000 Subject: arm64: dts: renesas: r8a7796: add HDMI sound support Signed-off-by: Kuninori Morimoto Tested-by: Nguyen Viet Dung Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index f33063dd7cd7..f41bc25b3933 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -2009,6 +2009,10 @@ port@1 { reg = <1>; }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; }; }; -- cgit From 06a574c7ef69bd0bd26ed08e35967acb76622ab3 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 23 Apr 2018 01:40:16 +0000 Subject: arm64: dts: renesas: salvator-common: use audio-graph-card for Sound Current Sound is using simple-audio-card which can't support HDMI. To use HDMI sound, we need to use audio-graph-card. But, one note is that r8a7795 has 2 HDMI ports, but r8a7796 has 1. Because of this mismatch, supporting HDMI on salvator-common is impossible. Thus, this patch exchange sound card to audio-graph-card and keep supporting ak4613 as 1st sound node. r8a7795/r8a7796 salvator-x{s} need to add HDMI sound individually. Signed-off-by: Kuninori Morimoto Tested-by: Nguyen Viet Dung Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 38 ++++++++++++++---------- 1 file changed, 22 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 1642bc9c8906..9116f4caa3c6 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -93,20 +93,12 @@ regulator-always-on; }; - rsnd_ak4613: sound { - compatible = "simple-audio-card"; + sound_card: sound { + compatible = "audio-graph-card"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcpu>; - simple-audio-card,frame-master = <&sndcpu>; + label = "rcar-sound"; - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4613>; - }; + dais = <&rsnd_port0>; }; vbus0_usb2: regulator-vbus0-usb2 { @@ -322,6 +314,12 @@ asahi-kasei,out4-single-end; asahi-kasei,out5-single-end; asahi-kasei,out6-single-end; + + port { + ak4613_endpoint: endpoint { + remote-endpoint = <&rsnd_endpoint0>; + }; + }; }; cs2000: clk_multiplier@4f { @@ -581,10 +579,18 @@ <&audio_clk_c>, <&cpg CPG_CORE CPG_AUDIO_CLK_I>; - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src0 &dvc0>; - capture = <&ssi1 &src1 &dvc1>; + ports { + rsnd_port0: port@0 { + rsnd_endpoint0: endpoint { + remote-endpoint = <&ak4613_endpoint>; + + dai-format = "left_j"; + bitclock-master = <&rsnd_endpoint0>; + frame-master = <&rsnd_endpoint0>; + + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; }; }; }; -- cgit From 6b39e3b68babb7a85b1c4070229c001ca19a6a80 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 23 Apr 2018 01:40:34 +0000 Subject: arm64: dts: renesas: r8a7795-es1-salvator-x: enable HDMI sound Signed-off-by: Kuninori Morimoto Tested-by: Nguyen Viet Dung Signed-off-by: Simon Horman --- .../boot/dts/renesas/r8a7795-es1-salvator-x.dts | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts index 7f2a3d923f21..3f46345a4644 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts @@ -56,6 +56,12 @@ status = "okay"; }; +&sound_card { + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ + &rsnd_port2>; /* HDMI1 */ +}; + &hdmi0 { status = "okay"; @@ -66,6 +72,12 @@ remote-endpoint = <&hdmi0_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint1>; + }; + }; }; }; @@ -83,6 +95,12 @@ remote-endpoint = <&hdmi1_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi1_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint2>; + }; + }; }; }; @@ -94,6 +112,34 @@ status = "okay"; }; +&rcar_sound { + ports { + /* rsnd_port0 is on salvator-common */ + rsnd_port1: port@1 { + rsnd_endpoint1: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint1>; + frame-master = <&rsnd_endpoint1>; + + playback = <&ssi2>; + }; + }; + rsnd_port2: port@2 { + rsnd_endpoint2: endpoint { + remote-endpoint = <&dw_hdmi1_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint2>; + frame-master = <&rsnd_endpoint2>; + + playback = <&ssi3>; + }; + }; + }; +}; + &pfc { usb2_pins: usb2 { groups = "usb2"; -- cgit From b27ebfa73de08c55414514f632758402529226b4 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 23 Apr 2018 01:40:52 +0000 Subject: arm64: dts: renesas: r8a7795-salvator-xs: enable HDMI sound Signed-off-by: Kuninori Morimoto Tested-by: Nguyen Viet Dung Signed-off-by: Simon Horman --- .../arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts index 8b50ceb746e8..83676684c6b4 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts @@ -56,6 +56,12 @@ status = "okay"; }; +&sound_card { + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ + &rsnd_port2>; /* HDMI1 */ +}; + &hdmi0 { status = "okay"; @@ -66,6 +72,12 @@ remote-endpoint = <&hdmi0_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint1>; + }; + }; }; }; @@ -83,6 +95,12 @@ remote-endpoint = <&hdmi1_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi1_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint2>; + }; + }; }; }; @@ -94,6 +112,34 @@ status = "okay"; }; +&rcar_sound { + ports { + /* rsnd_port0 is on salvator-common */ + rsnd_port1: port@1 { + rsnd_endpoint1: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint1>; + frame-master = <&rsnd_endpoint1>; + + playback = <&ssi2>; + }; + }; + rsnd_port2: port@2 { + rsnd_endpoint2: endpoint { + remote-endpoint = <&dw_hdmi1_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint2>; + frame-master = <&rsnd_endpoint2>; + + playback = <&ssi3>; + }; + }; + }; +}; + &pfc { usb2_pins: usb2 { groups = "usb2"; -- cgit From d134635f1cd2ba47edbb4c120769f22406373384 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 23 Apr 2018 01:41:07 +0000 Subject: arm64: dts: renesas: r8a7796-salvator-xs: enable HDMI sound Signed-off-by: Kuninori Morimoto Tested-by: Nguyen Viet Dung Signed-off-by: Simon Horman --- .../arm64/boot/dts/renesas/r8a7796-salvator-xs.dts | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts index 2c37055efa94..ddf35d4cd5e5 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts @@ -40,6 +40,11 @@ "dclkin.0", "dclkin.1", "dclkin.2"; }; +&sound_card { + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1>; /* HDMI0 */ +}; + &hdmi0 { status = "okay"; @@ -50,9 +55,32 @@ remote-endpoint = <&hdmi0_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint1>; + }; + }; }; }; &hdmi0_con { remote-endpoint = <&rcar_dw_hdmi0_out>; }; + +&rcar_sound { + ports { + /* rsnd_port0 is on salvator-common */ + rsnd_port1: port@1 { + rsnd_endpoint1: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint1>; + frame-master = <&rsnd_endpoint1>; + + playback = <&ssi2>; + }; + }; + }; +}; -- cgit From a4ff9aed55eb0172291005f0b1a0174be257b892 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 23 Apr 2018 01:41:23 +0000 Subject: arm64: dts: renesas: r8a7795-salvator-x: enable HDMI sound Signed-off-by: Kuninori Morimoto Tested-by: Nguyen Viet Dung Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index af467419266a..0efbef5ea9b7 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -56,6 +56,12 @@ status = "okay"; }; +&sound_card { + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ + &rsnd_port2>; /* HDMI1 */ +}; + &hdmi0 { status = "okay"; @@ -66,6 +72,12 @@ remote-endpoint = <&hdmi0_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint1>; + }; + }; }; }; @@ -83,6 +95,12 @@ remote-endpoint = <&hdmi1_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi1_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint2>; + }; + }; }; }; @@ -94,6 +112,34 @@ status = "okay"; }; +&rcar_sound { + ports { + /* rsnd_port0 is on salvator-common */ + rsnd_port1: port@1 { + rsnd_endpoint1: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint1>; + frame-master = <&rsnd_endpoint1>; + + playback = <&ssi2>; + }; + }; + rsnd_port2: port@2 { + rsnd_endpoint2: endpoint { + remote-endpoint = <&dw_hdmi1_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint2>; + frame-master = <&rsnd_endpoint2>; + + playback = <&ssi3>; + }; + }; + }; +}; + &pfc { usb2_pins: usb2 { groups = "usb2"; -- cgit From 5c29ba526ca8f4e34a3f2935651f1ab4592c03a3 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 23 Apr 2018 01:41:39 +0000 Subject: arm64: dts: renesas: r8a7796-salvator-x: enable HDMI sound Signed-off-by: Kuninori Morimoto Tested-by: Nguyen Viet Dung Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index 498c9e807dc4..90cca09b9a5e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -40,6 +40,11 @@ "dclkin.0", "dclkin.1", "dclkin.2"; }; +&sound_card { + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1>; /* HDMI0 */ +}; + &hdmi0 { status = "okay"; @@ -50,9 +55,32 @@ remote-endpoint = <&hdmi0_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint1>; + }; + }; }; }; &hdmi0_con { remote-endpoint = <&rcar_dw_hdmi0_out>; }; + +&rcar_sound { + ports { + /* rsnd_port0 is on salvator-common */ + rsnd_port1: port@1 { + rsnd_endpoint1: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint1>; + frame-master = <&rsnd_endpoint1>; + + playback = <&ssi2>; + }; + }; + }; +}; -- cgit From 2246f002595aa942b906fc631b7a5e830aa74a39 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 24 Apr 2018 11:26:59 +0200 Subject: arm64: dts: renesas: r8a7795-es1: Enable IPMMU devices Remove 'status = "disabled"' to make sure all IPMMU devices are enabled in DT on the r8a7795 ES1.0 Soc. This is a follow up for a patch by Magnus Damm for the the r8a7795 ES2.0 and other R-Car Gen 3 SoCs. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index f9acd125d687..0177f5e60e5a 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -39,7 +39,6 @@ reg = <0 0xe7730000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; #iommu-cells = <1>; - status = "disabled"; }; /delete-node/ usb-phy@ee0e0200; -- cgit From bc26b8f4e43acc4d2e3ae0bbf8f20515b4de5c5b Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 25 Apr 2018 17:20:10 +0900 Subject: arm64: dts: renesas: r8a77990: Revise the psci node The basic support patch 9491a8b17530 ("arm64: dts: renesas: Add Renesas R8A77990 SoC support") lacks the compatible "arm,psci-1.0" in the psci node. So, this patch revises it. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 3a19b9ebdd6e..19c1f7cea913 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -50,7 +50,7 @@ }; psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; -- cgit From de1eb23c6d0f08f6a2eff99afe29b08f023e392d Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 25 Apr 2018 17:20:09 +0900 Subject: arm64: dts: renesas: r8a77990: Revise the cache controller node The cache controller node should not have unit-addresses and reg properties. So, this patch removes them. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 19c1f7cea913..46580290b7fb 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -27,9 +27,8 @@ enable-method = "psci"; }; - L2_CA53: cache-controller@0 { + L2_CA53: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc 21>; cache-unified; cache-level = <2>; -- cgit From 104243b2e831fd0a5cf86429b9bcea271f7a3d4d Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Fri, 27 Apr 2018 23:02:15 +0100 Subject: arm64: dts: renesas: r8a77965: Add FCPF and FCPV instances The FCPs handle the interface between various IP cores and memory. Add the instances related to the FDPs and VSP2s. Based on a similar patch of the R8A7796 device tree by Laurent Pinchart . Signed-off-by: Takeshi Kihara [Kieran: Rebase to top of tree] Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 41 +++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index b12f41755aea..74a7ae4ebccc 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -10,6 +10,7 @@ #include #include +#include #define CPG_AUDIO_CLK_I 10 @@ -1000,6 +1001,46 @@ /* placeholder */ }; + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 615>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 607>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 611>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 602>; + }; + csi20: csi2@fea80000 { reg = <0 0xfea80000 0 0x10000>; /* placeholder */ -- cgit From 85cb3229218a99bc0084d58a438d00b36713fd1b Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Fri, 27 Apr 2018 23:02:16 +0100 Subject: arm64: dts: renesas: r8a77965: Add VSP instances The r8a77965 has 4 VSP instances. Based on a similar patch of the R8A7796 device tree by Laurent Pinchart . Signed-off-by: Takeshi Kihara [Kieran: Rebased to top of tree, fixed sort orders] Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 44 +++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 74a7ae4ebccc..362eddc6b3d1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1009,6 +1009,17 @@ resets = <&cpg 615>; }; + vspb: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + fcpvb0: fcp@fe96f000 { compatible = "renesas,fcpv"; reg = <0 0xfe96f000 0 0x200>; @@ -1017,6 +1028,17 @@ resets = <&cpg 607>; }; + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + fcpvi0: fcp@fe9af000 { compatible = "renesas,fcpv"; reg = <0 0xfe9af000 0 0x200>; @@ -1025,6 +1047,17 @@ resets = <&cpg 611>; }; + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + fcpvd0: fcp@fea27000 { compatible = "renesas,fcpv"; reg = <0 0xfea27000 0 0x200>; @@ -1033,6 +1066,17 @@ resets = <&cpg 603>; }; + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + fcpvd1: fcp@fea2f000 { compatible = "renesas,fcpv"; reg = <0 0xfea2f000 0 0x200>; -- cgit From 2f2c71bfc8c5ee3d17304a61c69a4b8ea200b9f9 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Fri, 27 Apr 2018 23:02:17 +0100 Subject: arm64: dts: renesas: r8a77965: Populate the DU instance placeholder The DU entity node has been previously added but only as a placeholder. Populate the node with the properties to use the device. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 362eddc6b3d1..a35ea2f32da2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1106,9 +1106,19 @@ }; du: display@feb00000 { - reg = <0 0xfeb00000 0 0x80000>, - <0 0xfeb90000 0 0x14>; - /* placeholder */ + compatible = "renesas,du-r8a77965"; + reg = <0 0xfeb00000 0 0x80000>; + reg-names = "du"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>; + clock-names = "du.0", "du.1", "du.3"; + status = "disabled"; + + vsps = <&vspd0 0 &vspd1 0 &vspd0 1>; ports { #address-cells = <1>; -- cgit From 5daa6f9f160bcc63664aeb6fd597a9e712bcd4d0 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Fri, 27 Apr 2018 23:02:18 +0100 Subject: arm64: dts: renesas: r8a77965: Add HDMI encoder instance Add the HDMI encoder to the R8A77965 DT in disabled state. Based on a similar patch of the R8A7796 device tree by Laurent Pinchart . Signed-off-by: Takeshi Kihara [Kieran: Rebase to top of tree] Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index a35ea2f32da2..b46af2744135 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -8,7 +8,7 @@ * Copyright (C) 2016 Renesas Electronics Corp. */ -#include +#include #include #include @@ -1105,6 +1105,33 @@ }; }; + hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a77965-hdmi", + "renesas,rcar-gen3-hdmi"; + reg = <0 0xfead0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 729>, + <&cpg CPG_CORE R8A77965_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 729>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; + }; + port@1 { + reg = <1>; + }; + }; + }; + du: display@feb00000 { compatible = "renesas,du-r8a77965"; reg = <0 0xfeb00000 0 0x80000>; @@ -1132,6 +1159,7 @@ port@1 { reg = <1>; du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; }; }; port@2 { -- cgit From a0b0be30a096a18f050bc53eed6c9b814d84cfac Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Fri, 27 Apr 2018 23:02:19 +0100 Subject: arm64: dts: renesas: r8a77965-salvator-x: Enable DU external clocks and HDMI The DU1 external dot clock is provided by the fixed frequency clock generator X21, while the DU0 and DU3 clocks are provided by the programmable Versaclock5 clock generator. Enable the clocks, and the HDMI encoder for the M3-N Salvator-X board and hook it up to the HDMI connector. Based on patches from Takeshi Kihara Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- .../arm64/boot/dts/renesas/r8a77965-salvator-x.dts | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts index 75d890d91df9..340a3c72b65a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts @@ -19,3 +19,31 @@ reg = <0x0 0x48000000 0x0 0x78000000>; }; }; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&x21_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; + +&hdmi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + }; +}; + +&hdmi0_con { + remote-endpoint = <&rcar_dw_hdmi0_out>; +}; -- cgit From a1f23ed4539ef113397afa69bd227d8a561fb9ee Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Fri, 27 Apr 2018 23:02:20 +0100 Subject: arm64: dts: renesas: r8a77965-salvator-xs: Enable DU external clocks and HDMI The DU1 external dot clock is provided by the fixed frequency clock generator X21, while the DU0 and DU3 clocks are provided by the programmable Versaclock6 clock generator. Enable the clocks, and the HDMI encoder for the M3-N Salvator-XS, and hook it up to the HDMI connector Based on patches from Takeshi Kihara Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- .../boot/dts/renesas/r8a77965-salvator-xs.dts | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts index a83a00deed9e..9de4e3db1621 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts @@ -19,3 +19,31 @@ reg = <0x0 0x48000000 0x0 0x78000000>; }; }; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock6 1>, + <&x21_clk>, + <&versaclock6 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; + +&hdmi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + }; +}; + +&hdmi0_con { + remote-endpoint = <&rcar_dw_hdmi0_out>; +}; -- cgit From cc9222448a339b62a05bb7cc6f3a091718ff182e Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 24 Apr 2018 22:25:24 +0300 Subject: arm64: dts: renesas: condor: add eMMC support Define the Condor board dependent part of the MMC0 (connected to eMMC chip) device node along with the necessary voltage regulators... Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 43 +++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 7af5afa41795..b8df7604dece 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -27,6 +27,24 @@ /* first 128MB is reserved for secure area. */ reg = <0 0x48000000 0 0x78000000>; }; + + d3_3v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vddq_vin01: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VDDQ_VIN01"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; }; &avb { @@ -52,12 +70,37 @@ clock-frequency = <32768>; }; +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&d3_3v>; + vqmmc-supply = <&vddq_vin01>; + mmc-hs200-1_8v; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &pfc { avb_pins: avb { groups = "avb_mdio", "avb_rgmii"; function = "avb"; }; + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <3300>; + }; + + mmc_pins_uhs: mmc_uhs { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + scif0_pins: scif0 { groups = "scif0_data"; function = "scif0"; -- cgit From 0c1861fe0a39e1f4d5d2684f1aec5a60b30c7400 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 23 Apr 2018 23:45:49 +0300 Subject: arm64: dts: renesas: v3msk: add DU/LVDS/HDMI support Define the V3M Starter Kit board dependent part of the DU and LVDS device nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and Analog Devices ADV7511W HDMI transmitter... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 129 +++++++++++++++++++++++++ 1 file changed, 129 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 55aa01b663e5..9fce031a596f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -29,6 +29,65 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + osc5_clk: osc5-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + vcc_d1_8v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VCC_D1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_d3_3v: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + lvds-decoder { + compatible = "thine,thc63lvd1024"; + vcc-supply = <&vcc_d3_3v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + thc63lvd1024_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@2 { + reg = <2>; + thc63lvd1024_out: endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; }; &avb { @@ -46,6 +105,13 @@ }; }; +&du { + clocks = <&cpg CPG_MOD 724>, + <&osc5_clk>; + clock-names = "du.0", "dclkin.0"; + status = "okay"; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -60,12 +126,75 @@ function = "avb0"; }; + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + scif0_pins: scif0 { groups = "scif0_data"; function = "scif0"; }; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + hdmi@39{ + compatible = "adi,adv7511w"; + #sound-dai-cells = <0>; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + avdd-supply = <&vcc_d1_8v>; + dvdd-supply = <&vcc_d1_8v>; + pvdd-supply = <&vcc_d1_8v>; + bgvdd-supply = <&vcc_d1_8v>; + dvdd-3v-supply = <&vcc_d3_3v>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&thc63lvd1024_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&thc63lvd1024_in>; + }; + }; + }; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; -- cgit From 2d87dc0e5be26fd45d7e5d0a8e59aad6c74d54c1 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 26 Apr 2018 11:42:43 +0200 Subject: arm64: dts: renesas: r8a7795: Add address properties to rcar_sound port nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rcar_sound port nodes have unit names and thus should have register properties. This is flagged by dtc as follows: # make dtbs W=1 ... DTC arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@1: node has a unit name, but no reg property arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@2: node has a unit name, but no reg property ... DTC arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@1: node has a unit name, but no reg property arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@2: node has a unit name, but no reg property DTC arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@1: node has a unit name, but no reg property arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@2: node has a unit name, but no reg property Prior to this patch the port nodes only defined in board DTS files. As the register properties are common this patch defines the port nodes and provides register properties in the SoC DTS file. Signed-off-by: Simon Horman Reviewed-by: Niklas Söderlund --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index b1c52dae4d49..9b080a864ea1 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1711,6 +1711,20 @@ dma-names = "rx", "tx", "rxu", "txu"; }; }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + }; }; audma0: dma-controller@ec700000 { -- cgit From 78bc93b3ffb2cd71341a3373fd14b62847091b7e Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 26 Apr 2018 11:42:43 +0200 Subject: arm64: dts: renesas: r8a7796: Add address properties to rcar_sound port nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rcar_sound port nodes have unit names and thus should have register properties. This is flagged by dtc as follows: # make dtbs W=1 ... DTC arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@1: node has a unit name, but no reg property ... DTC arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@1: node has a unit name, but no reg property Prior to this patch the port nodes only defined in board DTS files. As the register properties are common this patch defines the port nodes and provides register properties in the SoC DTS file. Signed-off-by: Simon Horman Reviewed-by: Niklas Söderlund --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index f41bc25b3933..3fbd86590fb0 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -1594,6 +1594,17 @@ dma-names = "rx", "tx", "rxu", "txu"; }; }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + }; }; audma0: dma-controller@ec700000 { -- cgit From e94ac4c7f4f0b9b2c28cfba3b7c6ba089092a22d Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 26 Apr 2018 11:42:43 +0200 Subject: arm64: dts: renesas: r8a77965: Add address properties to rcar_sound port nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rcar_sound port nodes have unit names and thus should have register properties. This is flagged by dtc as follows: # make dtbs W=1 ... DTC arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dtb arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property DTC arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dtb arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property Prior to this patch the port nodes only defined in board DTS files. As the register properties are common this patch defines the port nodes and provides register properties in the SoC DTS file. Signed-off-by: Simon Horman Reviewed-by: Niklas Söderlund --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index b46af2744135..7c9555309c0a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -857,6 +857,14 @@ ssi1: ssi-1 { }; }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + }; }; xhci0: usb@ee000000 { -- cgit From c64cc3683ff2622fe3528af93a5df01a6584e871 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 26 Apr 2018 13:43:56 +0300 Subject: arm64: dts: renesas: r8a77980: use CPG core clock macros Now that the commit 35b3c462dae1 ("dt-bindings: clock: add R8A77980 CPG core clock definitions") has hit Linus' tree, we can replace the bare numbers (we had to use to avoid a cross tree dependency) with these macro definitions... Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index d27b80bcdbb4..fddbaf250087 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -6,9 +6,9 @@ * Copyright (C) 2018 Cogent Embedded, Inc. */ +#include #include #include -#include / { compatible = "renesas,r8a77980"; @@ -23,7 +23,7 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0>; - clocks = <&cpg CPG_CORE 0>; + clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; power-domains = <&sysc 5>; next-level-cache = <&L2_CA53>; enable-method = "psci"; @@ -104,7 +104,7 @@ reg = <0 0xe6540000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x31>, <&dmac1 0x30>, @@ -122,7 +122,7 @@ reg = <0 0xe6550000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x33>, <&dmac1 0x32>, @@ -140,7 +140,7 @@ reg = <0 0xe6560000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x35>, <&dmac1 0x34>, @@ -158,7 +158,7 @@ reg = <0 0xe66a0000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x37>, <&dmac1 0x36>, @@ -220,7 +220,7 @@ reg = <0 0xe6e60000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x51>, <&dmac1 0x50>, @@ -238,7 +238,7 @@ reg = <0 0xe6e68000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x53>, <&dmac1 0x52>, @@ -256,7 +256,7 @@ reg = <0 0xe6c50000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x57>, <&dmac1 0x56>, @@ -274,7 +274,7 @@ reg = <0 0xe6c40000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x59>, <&dmac1 0x58>, -- cgit From 1184ea3fd4c83a7bf6a8f51fcf73d620706557ce Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 26 Apr 2018 13:45:21 +0300 Subject: arm64: dts: renesas: r8a77980: use SYSC power domain macros Now that the commit 7755b40d07a8 ("dt-bindings: power: add R8A77980 SYSC power domain definitions") has hit Linus' tree, we can replace the bare numbers (we had to use to avoid a cross tree dependency) with these macro definitions... Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index fddbaf250087..5c865fcd3986 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "renesas,r8a77980"; @@ -24,14 +25,14 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0>; clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc 5>; + power-domains = <&sysc R8A77980_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; }; L2_CA53: cache-controller { compatible = "cache"; - power-domains = <&sysc 21>; + power-domains = <&sysc R8A77980_PD_CA53_SCU>; cache-unified; cache-level = <2>; }; @@ -110,7 +111,7 @@ dmas = <&dmac1 0x31>, <&dmac1 0x30>, <&dmac2 0x31>, <&dmac2 0x30>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 520>; status = "disabled"; }; @@ -128,7 +129,7 @@ dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 519>; status = "disabled"; }; @@ -146,7 +147,7 @@ dmas = <&dmac1 0x35>, <&dmac1 0x34>, <&dmac2 0x35>, <&dmac2 0x34>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 518>; status = "disabled"; }; @@ -164,7 +165,7 @@ dmas = <&dmac1 0x37>, <&dmac1 0x36>, <&dmac2 0x37>, <&dmac2 0x36>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 517>; status = "disabled"; }; @@ -206,7 +207,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; #address-cells = <1>; @@ -226,7 +227,7 @@ dmas = <&dmac1 0x51>, <&dmac1 0x50>, <&dmac2 0x51>, <&dmac2 0x50>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 207>; status = "disabled"; }; @@ -244,7 +245,7 @@ dmas = <&dmac1 0x53>, <&dmac1 0x52>, <&dmac2 0x53>, <&dmac2 0x52>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 206>; status = "disabled"; }; @@ -262,7 +263,7 @@ dmas = <&dmac1 0x57>, <&dmac1 0x56>, <&dmac2 0x57>, <&dmac2 0x56>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 204>; status = "disabled"; }; @@ -280,7 +281,7 @@ dmas = <&dmac1 0x59>, <&dmac1 0x58>, <&dmac2 0x59>, <&dmac2 0x58>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 203>; status = "disabled"; }; @@ -313,7 +314,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <16>; @@ -347,7 +348,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 217>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <16>; @@ -359,7 +360,7 @@ reg = <0 0xee140000 0 0x2000>; interrupts = ; clocks = <&cpg CPG_MOD 314>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 314>; max-frequency = <200000000>; status = "disabled"; @@ -378,7 +379,7 @@ IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 408>; }; -- cgit From 7e26520fb466ddbecf7d0c1eea44126c1a353a19 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Thu, 26 Apr 2018 21:34:47 +0200 Subject: arm64: dts: renesas: r8a77965: use r8a77965-sysc binding definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the hardcoded power domain indices by R8A77965_PD_* symbols. Signed-off-by: Niklas Söderlund Reviewed-by: Jacopo Mondi [simon: dropped hunk to include r8a77965-sysc.h which is already present] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 94 +++++++++++++++---------------- 1 file changed, 47 insertions(+), 47 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 7c9555309c0a..536fed8eec6a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -61,7 +61,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; - power-domains = <&sysc 0>; + power-domains = <&sysc R8A77965_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; @@ -70,14 +70,14 @@ compatible = "arm,cortex-a57","arm,armv8"; reg = <0x1>; device_type = "cpu"; - power-domains = <&sysc 1>; + power-domains = <&sysc R8A77965_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; L2_CA57: cache-controller-0 { compatible = "cache"; - power-domains = <&sysc 12>; + power-domains = <&sysc R8A77965_PD_CA57_SCU>; cache-unified; cache-level = <2>; }; @@ -147,7 +147,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 912>; }; @@ -162,7 +162,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 911>; }; @@ -177,7 +177,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 910>; }; @@ -192,7 +192,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 909>; }; @@ -207,7 +207,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 908>; }; @@ -222,7 +222,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 907>; }; @@ -237,7 +237,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 906>; }; @@ -252,7 +252,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 905>; }; @@ -294,7 +294,7 @@ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 407>; }; @@ -348,7 +348,7 @@ reg = <0 0xe60b0000 0 0x425>; interrupts = ; clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 926>; dmas = <&dmac0 0x11>, <&dmac0 0x10>; dma-names = "tx", "rx"; @@ -367,7 +367,7 @@ renesas,buswait = <11>; phys = <&usb2_phy0>; phy-names = "usb"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 704>; status = "disabled"; }; @@ -380,7 +380,7 @@ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 330>; #dma-cells = <1>; dma-channels = <2>; @@ -394,7 +394,7 @@ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 331>; #dma-cells = <1>; dma-channels = <2>; @@ -407,7 +407,7 @@ clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, <&usb_extal_clk>; clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 328>; #phy-cells = <0>; status = "disabled"; @@ -441,7 +441,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <16>; @@ -475,7 +475,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <16>; @@ -509,7 +509,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 217>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <16>; @@ -552,7 +552,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; #address-cells = <1>; @@ -566,7 +566,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; status = "disabled"; }; @@ -576,7 +576,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; status = "disabled"; }; @@ -586,7 +586,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; status = "disabled"; }; @@ -596,7 +596,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; status = "disabled"; }; @@ -606,7 +606,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; status = "disabled"; }; @@ -616,7 +616,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; status = "disabled"; }; @@ -626,7 +626,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; status = "disabled"; }; @@ -642,7 +642,7 @@ dmas = <&dmac1 0x51>, <&dmac1 0x50>, <&dmac2 0x51>, <&dmac2 0x50>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 207>; status = "disabled"; }; @@ -659,7 +659,7 @@ dmas = <&dmac1 0x53>, <&dmac1 0x52>, <&dmac2 0x53>, <&dmac2 0x52>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 206>; status = "disabled"; }; @@ -673,7 +673,7 @@ <&cpg CPG_CORE 20>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 310>; status = "disabled"; }; @@ -689,7 +689,7 @@ clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x57>, <&dmac0 0x56>; dma-names = "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 204>; status = "disabled"; }; @@ -705,7 +705,7 @@ clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x59>, <&dmac0 0x58>; dma-names = "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 203>; status = "disabled"; }; @@ -722,7 +722,7 @@ dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, <&dmac2 0x5b>, <&dmac2 0x5a>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 202>; status = "disabled"; }; @@ -736,7 +736,7 @@ dmas = <&dmac1 0x41>, <&dmac1 0x40>, <&dmac2 0x41>, <&dmac2 0x40>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 211>; #address-cells = <1>; #size-cells = <0>; @@ -752,7 +752,7 @@ dmas = <&dmac1 0x43>, <&dmac1 0x42>, <&dmac2 0x43>, <&dmac2 0x42>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 210>; #address-cells = <1>; #size-cells = <0>; @@ -767,7 +767,7 @@ clocks = <&cpg CPG_MOD 209>; dmas = <&dmac0 0x45>, <&dmac0 0x44>; dma-names = "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 209>; #address-cells = <1>; #size-cells = <0>; @@ -782,7 +782,7 @@ clocks = <&cpg CPG_MOD 208>; dmas = <&dmac0 0x47>, <&dmac0 0x46>; dma-names = "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; @@ -873,7 +873,7 @@ reg = <0 0xee000000 0 0xc00>; interrupts = ; clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 328>; status = "disabled"; }; @@ -884,7 +884,7 @@ reg = <0 0xee020000 0 0x400>; interrupts = ; clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 328>; status = "disabled"; }; @@ -896,7 +896,7 @@ clocks = <&cpg CPG_MOD 703>; phys = <&usb2_phy0>; phy-names = "usb"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 703>; status = "disabled"; }; @@ -908,7 +908,7 @@ clocks = <&cpg CPG_MOD 702>; phys = <&usb2_phy1>; phy-names = "usb"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 702>; status = "disabled"; }; @@ -921,7 +921,7 @@ phys = <&usb2_phy0>; phy-names = "usb"; companion = <&ohci0>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 703>; status = "disabled"; }; @@ -934,7 +934,7 @@ phys = <&usb2_phy1>; phy-names = "usb"; companion = <&ohci1>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 702>; status = "disabled"; }; @@ -945,7 +945,7 @@ reg = <0 0xee080200 0 0x700>; interrupts = ; clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 703>; #phy-cells = <0>; status = "disabled"; @@ -956,7 +956,7 @@ "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0a0200 0 0x700>; clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 703>; #phy-cells = <0>; status = "disabled"; @@ -995,7 +995,7 @@ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 408>; }; -- cgit From 4c529600eef0a6b77e9fd27d89fbe0d2f030ede4 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Thu, 26 Apr 2018 21:49:06 +0200 Subject: arm64: dts: renesas: r8a77965: Add R-Car Gen3 thermal support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on previous work by Ryo Kataoka . Signed-off-by: Niklas Söderlund [simon: moved thermal node to preseve ordering of nodes by bus address] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 59 +++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 536fed8eec6a..b93281affd63 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -282,6 +282,21 @@ #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a77965-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; #interrupt-cells = <2>; @@ -1192,6 +1207,50 @@ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + /* External USB clocks - can be overridden by the board */ usb3s0_clk: usb3s0 { compatible = "fixed-clock"; -- cgit From 81a579d53a89dbf8380cefff37794c0321cfbed5 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 26 Apr 2018 23:33:14 +0300 Subject: arm64: dts: renesas: r8a77970: add CAN-FD support Define the generic R8A77970 part of the CAN-FD device node. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Acked-by: Ramesh Shanmugasundaram Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 6ed2e95eb53d..37b843c0677a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -68,6 +68,13 @@ method = "smc"; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; @@ -381,6 +388,31 @@ status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a77970-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77970_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77970", "renesas,etheravb-rcar-gen3"; -- cgit From bb8d20331f051a920df21aaf263a189e2ede20e6 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 26 Apr 2018 23:34:35 +0300 Subject: arm64: dts: renesas: eagle: add CAN-FD support Define the Eagle board dependent part of the CAN-FD device node. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Acked-by: Ramesh Shanmugasundaram Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index b800a119753b..21f9cf5c6e84 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -95,6 +95,16 @@ }; }; +&canfd { + pinctrl-0 = <&canfd0_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -156,6 +166,11 @@ function = "avb0"; }; + canfd0_pins: canfd0 { + groups = "canfd0_data_a"; + function = "canfd0"; + }; + i2c0_pins: i2c0 { groups = "i2c0"; function = "i2c0"; -- cgit From f38c41727211f2cdd9bb6f2999d46daafeacc5aa Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 27 Apr 2018 22:12:51 +0300 Subject: arm64: dts: renesas: r8a77980: add CAN-FD support Define the generic R8A77980 part of the CAN-FD device node. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov [simon: consistently use tabs for indentation] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 5c865fcd3986..3a127643d1dc 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -38,6 +38,13 @@ }; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; @@ -170,6 +177,30 @@ status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a77980-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77980_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77980", "renesas,etheravb-rcar-gen3"; -- cgit From 7a9706d25fe4707ee35be543f3e7ae01183ae86d Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 27 Apr 2018 22:14:26 +0300 Subject: arm64: dts: renesas: condor: add CAN-FD support Define the Condor board dependent part of the CAN-FD device node. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index b8df7604dece..0b93a7d76585 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -62,6 +62,16 @@ }; }; +&canfd { + pinctrl-0 = <&canfd0_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -89,6 +99,11 @@ function = "avb"; }; + canfd0_pins: canfd0 { + groups = "canfd0_data_a"; + function = "canfd0"; + }; + mmc_pins: mmc { groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; function = "mmc"; -- cgit From 99b1eb0f62f90159da2c0ff7791f4db9f9c66f64 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sun, 29 Apr 2018 20:26:39 +0200 Subject: arm64: dts: renesas: salvator-common: add eeprom Add the EEPROM found on Salvator-X and -XS boards for H3, M3-W, and M3-N on the IIC_DVFS bus. Signed-off-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 9116f4caa3c6..803220a02f50 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -385,6 +385,12 @@ }; }; }; + + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; }; &ohci0 { -- cgit From cd49f631dd7dc2dcd08a22c0f78197aa7970fe5d Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 27 Apr 2018 15:34:30 +0900 Subject: arm64: dts: renesas: r8a7795: salvator-xs: enable usb2_phy3 node This patch enables usb2_phy3 node for r8a7795 with Salvator-XS. You must change the SW31 to OFF-OFF-ON-ON-ON-ON on the board. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- .../arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts index 83676684c6b4..622b2a22ab0f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts @@ -145,6 +145,23 @@ groups = "usb2"; function = "usb2"; }; + + /* + * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins + * (when SW31 is the default setting on Salvator-XS). + * - If SW31 is the default setting, you cannot use USB2.0 ch3 on + * r8a7795 with Salvator-XS. + * Hence the SW31 setting must be changed like 2) below. + * 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF: + * - Connect GP6_3[01] to ADV7842. + * 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON: + * - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power). + * - Connect GP6_{04,21} to ADV7842. + */ + usb2_ch3_pins: usb2_ch3 { + groups = "usb2_ch3"; + function = "usb2_ch3"; + }; }; &usb2_phy2 { @@ -153,3 +170,10 @@ status = "okay"; }; + +&usb2_phy3 { + pinctrl-0 = <&usb2_ch3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit From 5650011a0607930b1691108ad66034aef1a75fa0 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 27 Apr 2018 15:34:31 +0900 Subject: arm64: dts: renesas: r8a7795: salvator-xs: enable hsusb channel 3 node This patch enables HS-USB channel3 node for r8a7795 with Salvator-XS. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts index 622b2a22ab0f..bbf5a8812b70 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts @@ -56,6 +56,11 @@ status = "okay"; }; +&hsusb3 { + dr_mode = "otg"; + status = "okay"; +}; + &sound_card { dais = <&rsnd_port0 /* ak4613 */ &rsnd_port1 /* HDMI0 */ -- cgit From 610fd5deb11ab0ec0af318e0912da8b1dcb5637d Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 27 Apr 2018 15:34:32 +0900 Subject: arm64: dts: renesas: r8a7795: salvator-xs: enable USB2.0 host channel 3 This patch enables USB2.0 host channel 3 for r8a7795 with Salvator-XS. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts index bbf5a8812b70..e231b5a7cbab 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts @@ -56,6 +56,11 @@ status = "okay"; }; +&ehci3 { + dr_mode = "otg"; + status = "okay"; +}; + &hsusb3 { dr_mode = "otg"; status = "okay"; @@ -117,6 +122,11 @@ status = "okay"; }; +&ohci3 { + dr_mode = "otg"; + status = "okay"; +}; + &rcar_sound { ports { /* rsnd_port0 is on salvator-common */ -- cgit From 399ec3ffb161ccfa0a6aba4e3162a1c5ec90af71 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 May 2018 14:38:28 +0200 Subject: arm64: dts: renesas: r8a7795: Correct whitespace Add missing spaces after commas. Replace 8 consecutive spaces by a TAB. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 9b080a864ea1..91486b4910ce 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -132,7 +132,7 @@ }; a57_1: cpu@1 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x1>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA57_CPU1>; @@ -144,7 +144,7 @@ }; a57_2: cpu@2 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x2>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA57_CPU2>; @@ -156,7 +156,7 @@ }; a57_3: cpu@3 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x3>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA57_CPU3>; @@ -179,7 +179,7 @@ }; a53_1: cpu@101 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x101>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA53_CPU1>; @@ -190,7 +190,7 @@ }; a53_2: cpu@102 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x102>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA53_CPU2>; @@ -201,7 +201,7 @@ }; a53_3: cpu@103 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x103>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA53_CPU3>; @@ -262,7 +262,7 @@ pmu_a57 { compatible = "arm,cortex-a57-pmu"; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&a57_0>, -- cgit From e4d9242a30dce2ec01e8a321237c4b8d08c12c7b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 May 2018 14:38:29 +0200 Subject: arm64: dts: renesas: r8a7796: Correct whitespace Add missing spaces after commas. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 3fbd86590fb0..6ffab2da07cb 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -143,7 +143,7 @@ }; a57_1: cpu@1 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x1>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA57_CPU1>; @@ -166,7 +166,7 @@ }; a53_1: cpu@101 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x101>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA53_CPU1>; @@ -177,7 +177,7 @@ }; a53_2: cpu@102 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x102>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA53_CPU2>; @@ -188,7 +188,7 @@ }; a53_3: cpu@103 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x103>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA53_CPU3>; -- cgit From 80f7297c08079055d9c651f5827e26aa73bd1403 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 May 2018 14:38:30 +0200 Subject: arm64: dts: renesas: r8a77965: Correct whitespace Add missing space after comma. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index b93281affd63..ba0edda431a5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -67,7 +67,7 @@ }; a57_1: cpu@1 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x1>; device_type = "cpu"; power-domains = <&sysc R8A77965_PD_CA57_CPU1>; -- cgit From 786f3cc022f73973eda247a0f80f73971ebda764 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 May 2018 14:30:49 +0200 Subject: arm64: dts: renesas: ulcb: Add BD9571 PMIC Add a device node for the ROHM BD9571MWV PMIC. This was based on the example in the DT binding documentation, but using IRQ0 instead of a GPIO interrupt, as that matches the schematics, and because INTC-EX is a simpler block. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 93402783d52f..ee4249287fbd 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -243,6 +243,30 @@ &i2c_dvfs { status = "okay"; + + pmic: pmic@30 { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + + compatible = "rohm,bd9571mwv"; + reg = <0x30>; + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + regulators { + dvfs: dvfs { + regulator-name = "dvfs"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1030000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &ohci1 { @@ -276,6 +300,11 @@ function = "i2c2"; }; + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; -- cgit From d666493fd6da3b13b9a0d4957ee1d0e52ece0e13 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 May 2018 14:30:50 +0200 Subject: arm64: dts: renesas: salvator-common: Add PMIC DDR Backup Power config On Salvator-X(S), all of the DDR0, DDR1, DDR0C, and DDR1C power rails need to be kept powered when backup mode is enabled. Reflect this in the "rohm,ddr-backup-power" property for the BD9571MWV PMIC node. The accessory power switch (SW23) is a toggle switch, hence specify "rohm,rstbmode-level". Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 803220a02f50..96b51e572666 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -374,6 +374,8 @@ #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + rohm,ddr-backup-power = <0xf>; + rohm,rstbmode-level; regulators { dvfs: dvfs { -- cgit From 1c81a633de0e271d1f6f75f7f3e8a515d4a3085e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 May 2018 14:30:51 +0200 Subject: arm64: dts: renesas: ulcb: Add PMIC DDR Backup Power config On the R-Car Starter Kit Premier/Pro, all of the DDR0, DDR1, DDR0C, and DDR1C power rails need to be kept powered when backup mode is enabled. Reflect this in the "rohm,ddr-backup-power" property for the BD9571MWV PMIC node. The accessory power switch (SW8) is a momentary switch, hense specify "rohm,rstbmode-pulse". Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index ee4249287fbd..0edb16e6b372 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -256,6 +256,8 @@ #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + rohm,ddr-backup-power = <0xf>; + rohm,rstbmode-pulse; regulators { dvfs: dvfs { -- cgit From aa7a6365d03aacd4714ae62630f0262cac82a478 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Wed, 9 May 2018 21:38:24 +0900 Subject: arm64: dts: renesas: r8a77965: Add SDHI device nodes Add SDHI nodes to the DT of the r8a77965 SoC. Based on several similar patches of the R8A7796 device tree by Simon Horman . Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 36 +++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index ba0edda431a5..f51c1b2cbae4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -978,23 +978,51 @@ }; sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a77965", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; }; sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a77965", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; }; sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a77965", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; }; sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a77965", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; }; gic: interrupt-controller@f1010000 { -- cgit From 77899dd2c094fc99413e18264384cc428c23cd23 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 9 May 2018 17:23:22 +0200 Subject: arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core Add a device node for the second Cortex-A53 CPU core on the Renesas R-Car V3M (r8a77970) SoC, and adjust the interrupt delivery masks for ARM Generic Interrupt Controller and Architectured Timer. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 37b843c0677a..1efaad71804d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -41,6 +41,16 @@ enable-method = "psci"; }; + a53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <1>; + clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; + power-domains = <&sysc R8A77970_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA53: cache-controller { compatible = "cache"; power-domains = <&sysc R8A77970_PD_CA53_SCU>; @@ -635,7 +645,7 @@ <0 0xf1020000 0 0x20000>, <0 0xf1040000 0 0x20000>, <0 0xf1060000 0 0x20000>; - interrupts = ; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; @@ -726,9 +736,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; }; -- cgit From d005b562be9c3379151f40b70a774ba61ed8bb0e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 9 May 2018 17:23:23 +0200 Subject: arm64: dts: renesas: r8a77970: Add Cortex-A53 PMU node Enable the performance monitor unit for the Cortex-A53 cores on the R-Car V3M (r8a77970) SoC. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 1efaad71804d..50046405d348 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -73,6 +73,13 @@ clock-frequency = <0>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; -- cgit From 22fb06cd54f92132bf7a8b7740abc7db79a5130b Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 9 May 2018 19:54:09 +0200 Subject: arm64: dts: renesas: r8a77980: add resets property to CAN-FD node Add resets property to CAN-FD node to describe it in the reset topology of on-SoC devices. This allows to reset the CAN-FD device using the Reset Controller API. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 3a127643d1dc..32db26f2c8b5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -190,6 +190,7 @@ assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; assigned-clock-rates = <40000000>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 914>; status = "disabled"; channel0 { -- cgit From d86bd47fefbb6e4db53d733fe95bc13bc9ddedb1 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Fri, 11 May 2018 12:00:01 +0200 Subject: arm64: dts: renesas: r8a77995: Add VIN4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe VIN4 interface for R-Car D3 R8A77995 SoC. Signed-off-by: Jacopo Mondi Acked-by: Niklas Söderlund [simon: sorted node by bus address] Signed-off-by: Simon Horman Reviewed-by: Laurent Pinchart --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index ba98865b0c9b..2506f46293e8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -610,6 +610,17 @@ status = "disabled"; }; + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a77995"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + }; + ohci0: usb@ee080000 { compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; -- cgit From 9223eef03f2659bd9650c2bc4364b1748e62eade Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 11 May 2018 23:21:57 +0300 Subject: arm64: dts: renesas: r8a77970: disable EtherAVB When adding the R8A77970 EtherAVB device I failed to notice that it does not have the usual "status" property disabling the described devices in anticipation that the board device trees enable the devices according to their needs. This causes the EtherAVB driver to successfully probe despite e.g. the needed pins not having been configured -- luckily, "eth" device can't be opened anyway... Fixes: bea2ab136eaa ("arm64: dts: renesas: r8a77970: add EtherAVB support") Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 50046405d348..c8464d1ef1b2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -473,6 +473,7 @@ iommus = <&ipmmu_rt 3>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; scif0: serial@e6e60000 { -- cgit From 52d2e0cec73e61123860230d6d034cd07775dd78 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 11 May 2018 23:23:26 +0300 Subject: arm64: dts: renesas: r8a77980: disable EtherAVB When adding the R8A77980 EtherAVB device I failed to notice that it does not have the usual "status" property disabling the described devices in anticipation that the board device trees enable the devices according to their needs. This causes the EtherAVB driver to successfully probe despite e.g. the needed pins not having been configured -- luckily, "eth" device can't be opened anyway... Fixes: bf6f90832f81 ("arm64: dts: renesas: r8a77980: add EtherAVB support") Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 32db26f2c8b5..4c40f9f0ebc9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -244,6 +244,7 @@ phy-mode = "rgmii"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; scif0: serial@e6e60000 { -- cgit From 116a12f7d6c00e1e477aaec9e486cd510fa1895c Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 10 May 2018 21:12:30 +0300 Subject: arm64: dts: renesas: initial V3HSK board device tree Add the initial device tree for the V3H Starter Kit board. The board has 1 debug serial port (SCIF0); include support for it, so that the serial console can work. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/Makefile | 2 +- arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 60 ++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index a235961c6532..9e2394bc3c62 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -9,6 +9,6 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb -dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb +dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts new file mode 100644 index 000000000000..c9680994555d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the V3H Starter Kit board + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a77980.dtsi" + +/ { + model = "Renesas V3H Starter Kit board"; + compatible = "renesas,v3hsk", "renesas,r8a77980"; + + aliases { + serial0 = &scif0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0 0x48000000 0 0x78000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_b"; + function = "scif_clk"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; -- cgit From 4ab0df3399699c3d440940863234d318fa649b72 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 11 May 2018 13:31:18 +0900 Subject: arm64: dts: renesas: r8a77990: Add PFC device node This patch adds PFC device node for r8a77990 (R-Car E3). Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 46580290b7fb..efc3c0ba36c2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -60,6 +60,11 @@ #size-cells = <2>; ranges; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77990"; + reg = <0 0xe6060000 0 0x508>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a77990-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- cgit From 0d292de1ebe0cfc599d7eeccdff4aa0d77a03f55 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 11 May 2018 13:31:19 +0900 Subject: arm64: dts: renesas: r8a77990: Add GPIO device nodes This patch adds GPIO nodes for r8a77990 (R-Car E3). Based on a patch from Takeshi Kihara Signed-off-by: Yoshihiro Shimoda [simon: dropped use of deprecated "renesas,gpio-rcar"] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 105 ++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index efc3c0ba36c2..bbc3db50bc01 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -60,6 +60,111 @@ #size-cells = <2>; ranges; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc 32>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc 32>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc 32>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc 32>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 11>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc 32>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 20>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc 32>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc 32>; + resets = <&cpg 906>; + }; + pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a77990"; reg = <0 0xe6060000 0 0x508>; -- cgit From 913a78b575c313b8bee8384a542e637049232e40 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 11 May 2018 13:31:20 +0900 Subject: arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes This patch adds EthernetAVB node for r8a77990 (R-Car E3). Based on a patch from Takeshi Kihara Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 45 +++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index bbc3db50bc01..be4f519711a1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -191,6 +191,51 @@ #power-domain-cells = <1>; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77990", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc 32>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a77990", "renesas,rcar-gen3-scif", "renesas,scif"; -- cgit From 8441ef643d7dc8b4df85cbd7d8b99efc08ec00f3 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 11 May 2018 13:31:21 +0900 Subject: arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB This patch enables EthernetAVB for r8a77990 Ebisu board. Based on a patch from Takeshi Kihara Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 28 ++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 63ee1347bb19..7a09d0524f9b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "r8a77990.dtsi" +#include / { model = "Renesas Ebisu board based on r8a77990"; @@ -14,6 +15,7 @@ aliases { serial0 = &scif2; + ethernet0 = &avb; }; chosen { @@ -28,10 +30,36 @@ }; }; +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy-mode = "rgmii-txid"; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + }; +}; + &extal_clk { clock-frequency = <48000000>; }; +&pfc { + avb_pins: avb { + mux { + groups = "avb_link", "avb_mii"; + function = "avb"; + }; + }; +}; + &scif2 { status = "okay"; }; -- cgit From 111d3ffe1692af078609516b407e494ac985684b Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Fri, 11 May 2018 16:00:29 +0200 Subject: arm64: dts: renesas: r8a77965: add I2C support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 99 ++++++++++++++++++++++++++++--- 1 file changed, 90 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index f51c1b2cbae4..1f67aea49305 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -20,6 +20,13 @@ #size-cells = <2>; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; i2c7 = &i2c_dvfs; }; @@ -314,44 +321,118 @@ }; i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; reg = <0 0xe6500000 0 0x40>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; }; i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; reg = <0 0xe6508000 0 0x40>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; }; i2c2: i2c@e6510000 { #address-cells = <1>; #size-cells = <0>; - + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; reg = <0 0xe6510000 0 0x40>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; }; i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; reg = <0 0xe66d0000 0 0x40>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; }; i2c4: i2c@e66d8000 { #address-cells = <1>; #size-cells = <0>; - + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; reg = <0 0xe66d8000 0 0x40>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; }; i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; reg = <0 0xe66e0000 0 0x40>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; }; i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; reg = <0 0xe66e8000 0 0x40>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; }; i2c_dvfs: i2c@e60b0000 { -- cgit From 15da7132f1da1c0c42c175a0b938af1e0615de90 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Wed, 16 May 2018 03:58:48 +0200 Subject: arm64: dts: renesas: r8a7795: add VIN and CSI-2 nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 389 +++++++++++++++++++++++++++++++ 1 file changed, 389 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 91486b4910ce..d842940b2f43 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1397,6 +1397,262 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin4>; + }; + vin4csi41: endpoint@3 { + reg = <3>; + remote-endpoint= <&csi41vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin5>; + }; + vin5csi41: endpoint@3 { + reg = <3>; + remote-endpoint= <&csi41vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin6>; + }; + vin6csi41: endpoint@3 { + reg = <3>; + remote-endpoint= <&csi41vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin7>; + }; + vin7csi41: endpoint@3 { + reg = <3>; + remote-endpoint= <&csi41vin7>; + }; + }; + }; + }; + drif00: rif@e6f40000 { compatible = "renesas,r8a7795-drif", "renesas,rcar-gen3-drif"; @@ -2327,6 +2583,139 @@ renesas,fcp = <&fcpvi1>; }; + csi20: csi2@fea80000 { + compatible = "renesas,r8a7795-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a7795-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + }; + }; + }; + + csi41: csi2@feab0000 { + compatible = "renesas,r8a7795-csi2"; + reg = <0 0xfeab0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi41vin4: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin4csi41>; + }; + csi41vin5: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin5csi41>; + }; + csi41vin6: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin6csi41>; + }; + csi41vin7: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin7csi41>; + }; + }; + }; + }; + hdmi0: hdmi@fead0000 { compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; reg = <0 0xfead0000 0 0x10000>; -- cgit From e51c09d53719c0d348f07af7deb14463ec1aeec7 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Wed, 16 May 2018 03:58:49 +0200 Subject: arm64: dts: renesas: r8a7795-es1: add CSI-2 node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Renesas H3 ES1.0 have one extra CSI-2 node, CSI21 which is not present for later ES versions of H3. Signed-off-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 143 +++++++++++++++++++++++++++ 1 file changed, 143 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index 0177f5e60e5a..e19dcd6cb767 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -107,6 +107,61 @@ resets = <&cpg 117>; renesas,fcp = <&fcpf2>; }; + + csi21: csi2@fea90000 { + compatible = "renesas,r8a7795-csi2"; + reg = <0 0xfea90000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi21vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi21>; + }; + csi21vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi21>; + }; + csi21vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi21>; + }; + csi21vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi21>; + }; + csi21vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi21>; + }; + csi21vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi21>; + }; + csi21vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi21>; + }; + csi21vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi21>; + }; + }; + }; + }; }; &gpio1 { @@ -174,3 +229,91 @@ &du { vsps = <&vspd0 &vspd1 &vspd2 &vspd3>; }; + +&vin0 { + ports { + port@1 { + vin0csi21: endpoint@1 { + reg = <1>; + remote-endpoint= <&csi21vin0>; + }; + }; + }; +}; + +&vin1 { + ports { + port@1 { + vin1csi21: endpoint@1 { + reg = <1>; + remote-endpoint= <&csi21vin1>; + }; + }; + }; +}; + +&vin2 { + ports { + port@1 { + vin2csi21: endpoint@1 { + reg = <1>; + remote-endpoint= <&csi21vin2>; + }; + }; + }; +}; + +&vin3 { + ports { + port@1 { + vin3csi21: endpoint@1 { + reg = <1>; + remote-endpoint= <&csi21vin3>; + }; + }; + }; +}; + +&vin4 { + ports { + port@1 { + vin4csi21: endpoint@1 { + reg = <1>; + remote-endpoint= <&csi21vin4>; + }; + }; + }; +}; + +&vin5 { + ports { + port@1 { + vin5csi21: endpoint@1 { + reg = <1>; + remote-endpoint= <&csi21vin5>; + }; + }; + }; +}; + +&vin6 { + ports { + port@1 { + vin6csi21: endpoint@1 { + reg = <1>; + remote-endpoint= <&csi21vin6>; + }; + }; + }; +}; + +&vin7 { + ports { + port@1 { + vin7csi21: endpoint@1 { + reg = <1>; + remote-endpoint= <&csi21vin7>; + }; + }; + }; +}; -- cgit From 0e5819f10bb1230088c9893aaad7e6884611b061 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Wed, 16 May 2018 03:58:50 +0200 Subject: arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 367 +++++++++++++++++++++++++++++++ 1 file changed, 367 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 6ffab2da07cb..7c25be6b5af3 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -1280,6 +1280,262 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin4>; + }; + vin4csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin5>; + }; + vin5csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin6>; + }; + vin6csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin7>; + }; + vin7csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin7>; + }; + }; + }; + }; + drif00: rif@e6f40000 { compatible = "renesas,r8a7796-drif", "renesas,rcar-gen3-drif"; @@ -1998,6 +2254,117 @@ renesas,fcp = <&fcpvi0>; }; + csi20: csi2@fea80000 { + compatible = "renesas,r8a7796-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a7796-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + csi40vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi40>; + }; + csi40vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi40>; + }; + csi40vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi40>; + }; + csi40vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi40>; + }; + }; + + }; + }; + hdmi0: hdmi@fead0000 { compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi"; reg = <0 0xfead0000 0 0x10000>; -- cgit From 98b6badf77d5a877c918ae12b070caae8f1df968 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Wed, 16 May 2018 03:58:51 +0200 Subject: arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 326 +++++++++++++++++++++++++++++- 1 file changed, 316 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 1f67aea49305..486aecacb22a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -886,43 +886,259 @@ }; vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a77965"; reg = <0 0xe6ef0000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; + }; + }; + }; }; vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a77965"; reg = <0 0xe6ef1000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin1>; + }; + }; + }; }; vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a77965"; reg = <0 0xe6ef2000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin2>; + }; + }; + }; }; vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a77965"; reg = <0 0xe6ef3000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin3>; + }; + }; + }; }; vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a77965"; reg = <0 0xe6ef4000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin4>; + }; + vin4csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin4>; + }; + }; + }; }; vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a77965"; reg = <0 0xe6ef5000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin5>; + }; + vin5csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin5>; + }; + }; + }; }; vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a77965"; reg = <0 0xe6ef6000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin6>; + }; + vin6csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin6>; + }; + }; + }; }; vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a77965"; reg = <0 0xe6ef7000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin7>; + }; + vin7csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin7>; + }; + }; + }; }; rcar_sound: sound@ec500000 { @@ -1218,22 +1434,112 @@ }; csi20: csi2@fea80000 { + compatible = "renesas,r8a77965-csi2"; reg = <0 0xfea80000 0 0x10000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; }; }; csi40: csi2@feaa0000 { + compatible = "renesas,r8a77965-csi2"; reg = <0 0xfeaa0000 0 0x10000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + csi40vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi40>; + }; + csi40vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi40>; + }; + csi40vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi40>; + }; + csi40vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi40>; + }; + }; }; }; -- cgit From 51b09327863d7a97e5e284262daf44c9aa60827e Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Wed, 16 May 2018 03:58:52 +0200 Subject: arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 152 ++++++++++++++++++++++++++++++ 1 file changed, 152 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index c8464d1ef1b2..98a2317a16c4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -547,6 +547,119 @@ status = "disabled"; }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin3>; + }; + }; + }; + }; + dmac1: dma-controller@e7300000 { compatible = "renesas,dmac-r8a77970", "renesas,rcar-dmac"; @@ -679,6 +792,45 @@ resets = <&cpg 603>; }; + csi40: csi2@feaa0000 { + compatible = "renesas,r8a77970-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + }; + }; + }; + du: display@feb00000 { compatible = "renesas,du-r8a77970"; reg = <0 0xfeb00000 0 0x80000>; -- cgit From afa6dceca1fb55d6124825fb0f6c3d611b991aa3 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Wed, 16 May 2018 03:58:54 +0200 Subject: arm64: dts: renesas: salvator-common: enable VIN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 96b51e572666..263e5787270e 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -703,6 +703,38 @@ clock-frequency = <100000000>; }; +&vin0 { + status = "okay"; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; + +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&vin6 { + status = "okay"; +}; + +&vin7 { + status = "okay"; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; -- cgit From 6ff6991bb4adc74cc248f2aaea2e5560671b34c2 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 26 Apr 2018 20:24:43 +0200 Subject: ARM: dts: r8a7740: Add CEU0 Describe CEU0 peripheral for Renesas R-Mobile A1 R8A7740 Soc. Reported-by: Geert Uytterhoeven Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven [simon: dropped clock-names property] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index afd3bc5e6cf2..180eb9d2a390 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -67,6 +67,15 @@ power-domains = <&pd_d4>; }; + ceu0: ceu@fe910000 { + reg = <0xfe910000 0x3000>; + compatible = "renesas,r8a7740-ceu"; + interrupts = ; + clocks = <&mstp1_clks R8A7740_CLK_CEU20>; + power-domains = <&pd_a4r>; + status = "disabled"; + }; + cmt1: timer@e6138000 { compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; reg = <0xe6138000 0x170>; -- cgit From 7fad92d05887319998b8d2bb40082b8b224d5ef5 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 15 May 2018 10:00:38 +0200 Subject: ARM: dts: r8a7740: Add CEU1 Describe CEU1 peripheral for Renesas R-Mobile A1 R8A7740 Soc. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven Reviewed-by: Jacopo Mondi --- arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 180eb9d2a390..eb9a911deefb 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -76,6 +76,15 @@ status = "disabled"; }; + ceu1: ceu@fe914000 { + reg = <0xfe914000 0x3000>; + compatible = "renesas,r8a7740-ceu"; + interrupts = ; + clocks = <&mstp1_clks R8A7740_CLK_CEU21>; + power-domains = <&pd_a4r>; + status = "disabled"; + }; + cmt1: timer@e6138000 { compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; reg = <0xe6138000 0x170>; -- cgit From 908001d778eba06ee1d832863d4e9a1e2cfd4746 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 16 May 2018 03:58:53 +0200 Subject: arm64: dts: renesas: salvator-common: Add ADV7482 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Salvator boards use an ADV7482 receiver for HDMI and CVBS inputs. Provide ADV7482 node on the i2c4 bus, along with connectors for the hdmi and cvbs inputs, and link to the csi20 and csi40 nodes as outputs. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 103 +++++++++++++++++++++++ 1 file changed, 103 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 263e5787270e..9256fbaaab7f 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -66,6 +66,29 @@ enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; }; + cvbs-in { + compatible = "composite-video-connector"; + label = "CVBS IN"; + + port { + cvbs_con: endpoint { + remote-endpoint = <&adv7482_ain7>; + }; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + label = "HDMI IN"; + type = "a"; + + port { + hdmi_in_con: endpoint { + remote-endpoint = <&adv7482_hdmi>; + }; + }; + }; + reg_1p8v: regulator0 { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -260,6 +283,37 @@ }; }; +&csi20 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + csi20_in: endpoint { + clock-lanes = <0>; + data-lanes = <1>; + remote-endpoint = <&adv7482_txb>; + }; + }; + }; +}; + +&csi40 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7482_txa>; + }; + }; + }; +}; + &du { pinctrl-0 = <&du_pins>; pinctrl-names = "default"; @@ -357,6 +411,55 @@ shunt-resistor-micro-ohms = <5000>; }; + + video-receiver@70 { + compatible = "adi,adv7482"; + reg = <0x70>; + + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gpio6>; + interrupt-names = "intrq1", "intrq2"; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>, + <31 IRQ_TYPE_LEVEL_LOW>; + + port@7 { + reg = <7>; + + adv7482_ain7: endpoint { + remote-endpoint = <&cvbs_con>; + }; + }; + + port@8 { + reg = <8>; + + adv7482_hdmi: endpoint { + remote-endpoint = <&hdmi_in_con>; + }; + }; + + port@10 { + reg = <10>; + + adv7482_txa: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + + port@11 { + reg = <11>; + + adv7482_txb: endpoint { + clock-lanes = <0>; + data-lanes = <1>; + remote-endpoint = <&csi20_in>; + }; + }; + }; }; &i2c_dvfs { -- cgit