From 0e2b75af658b5dccce27e8ec265e96b84fdf7036 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 1 Sep 2019 21:32:39 +0200 Subject: ARM: pxa: split mach/generic.h Only one declaration from this header is actually used in drivers, so move that one into the global location and leave everything else private. Acked-by: Robert Jarzmik Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/generic.h | 6 +----- arch/arm/mach-pxa/include/mach/generic.h | 6 +++++- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 3b7873f8e1f8..67925d3ea026 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -7,6 +7,7 @@ */ #include +#include struct irq_data; @@ -71,8 +72,3 @@ extern unsigned pxa25x_get_clk_frequency_khz(int); #define pxa27x_get_clk_frequency_khz(x) (0) #endif -#ifdef CONFIG_PXA3xx -extern unsigned pxa3xx_get_clk_frequency_khz(int); -#else -#define pxa3xx_get_clk_frequency_khz(x) (0) -#endif diff --git a/arch/arm/mach-pxa/include/mach/generic.h b/arch/arm/mach-pxa/include/mach/generic.h index 665542e0c9e2..613f6a299d0d 100644 --- a/arch/arm/mach-pxa/include/mach/generic.h +++ b/arch/arm/mach-pxa/include/mach/generic.h @@ -1 +1,5 @@ -#include "../../generic.h" +#ifdef CONFIG_PXA3xx +extern unsigned pxa3xx_get_clk_frequency_khz(int); +#else +#define pxa3xx_get_clk_frequency_khz(x) (0) +#endif -- cgit From d23dc21c99b2f22c737cb50e4d04aea6e059138f Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 1 Sep 2019 21:33:34 +0200 Subject: ARM: pxa: make mainstone.h private No driver includes this any more, so don't expose it globally. Acked-by: Robert Jarzmik Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/include/mach/mainstone.h | 142 ----------------------------- arch/arm/mach-pxa/mainstone.c | 2 +- arch/arm/mach-pxa/mainstone.h | 140 ++++++++++++++++++++++++++++ 3 files changed, 141 insertions(+), 143 deletions(-) delete mode 100644 arch/arm/mach-pxa/include/mach/mainstone.h create mode 100644 arch/arm/mach-pxa/mainstone.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h deleted file mode 100644 index 1698f2ffd7c7..000000000000 --- a/arch/arm/mach-pxa/include/mach/mainstone.h +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-pxa/include/mach/mainstone.h - * - * Author: Nicolas Pitre - * Created: Nov 14, 2002 - * Copyright: MontaVista Software Inc. - */ - -#ifndef ASM_ARCH_MAINSTONE_H -#define ASM_ARCH_MAINSTONE_H - -#include - -#define MST_ETH_PHYS PXA_CS4_PHYS - -#define MST_FPGA_PHYS PXA_CS2_PHYS -#define MST_FPGA_VIRT (0xf0000000) -#define MST_P2V(x) ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT) -#define MST_V2P(x) ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS) - -#ifndef __ASSEMBLY__ -# define __MST_REG(x) (*((volatile unsigned long *)MST_P2V(x))) -#else -# define __MST_REG(x) MST_P2V(x) -#endif - -/* board level registers in the FPGA */ - -#define MST_LEDDAT1 __MST_REG(0x08000010) -#define MST_LEDDAT2 __MST_REG(0x08000014) -#define MST_LEDCTRL __MST_REG(0x08000040) -#define MST_GPSWR __MST_REG(0x08000060) -#define MST_MSCWR1 __MST_REG(0x08000080) -#define MST_MSCWR2 __MST_REG(0x08000084) -#define MST_MSCWR3 __MST_REG(0x08000088) -#define MST_MSCRD __MST_REG(0x08000090) -#define MST_INTMSKENA __MST_REG(0x080000c0) -#define MST_INTSETCLR __MST_REG(0x080000d0) -#define MST_PCMCIA0 __MST_REG(0x080000e0) -#define MST_PCMCIA1 __MST_REG(0x080000e4) - -#define MST_MSCWR1_CAMERA_ON (1 << 15) /* Camera interface power control */ -#define MST_MSCWR1_CAMERA_SEL (1 << 14) /* Camera interface mux control */ -#define MST_MSCWR1_LCD_CTL (1 << 13) /* General-purpose LCD control */ -#define MST_MSCWR1_MS_ON (1 << 12) /* Memory Stick power control */ -#define MST_MSCWR1_MMC_ON (1 << 11) /* MultiMediaCard* power control */ -#define MST_MSCWR1_MS_SEL (1 << 10) /* SD/MS multiplexer control */ -#define MST_MSCWR1_BB_SEL (1 << 9) /* PCMCIA/Baseband multiplexer */ -#define MST_MSCWR1_BT_ON (1 << 8) /* Bluetooth UART transceiver */ -#define MST_MSCWR1_BTDTR (1 << 7) /* Bluetooth UART DTR */ - -#define MST_MSCWR1_IRDA_MASK (3 << 5) /* IrDA transceiver mode */ -#define MST_MSCWR1_IRDA_FULL (0 << 5) /* full distance power */ -#define MST_MSCWR1_IRDA_OFF (1 << 5) /* shutdown */ -#define MST_MSCWR1_IRDA_MED (2 << 5) /* 2/3 distance power */ -#define MST_MSCWR1_IRDA_LOW (3 << 5) /* 1/3 distance power */ - -#define MST_MSCWR1_IRDA_FIR (1 << 4) /* IrDA transceiver SIR/FIR */ -#define MST_MSCWR1_GREENLED (1 << 3) /* LED D1 control */ -#define MST_MSCWR1_PDC_CTL (1 << 2) /* reserved */ -#define MST_MSCWR1_MTR_ON (1 << 1) /* Silent alert motor */ -#define MST_MSCWR1_SYSRESET (1 << 0) /* System reset */ - -#define MST_MSCWR2_USB_OTG_RST (1 << 6) /* USB On The Go reset */ -#define MST_MSCWR2_USB_OTG_SEL (1 << 5) /* USB On The Go control */ -#define MST_MSCWR2_nUSBC_SC (1 << 4) /* USB client soft connect control */ -#define MST_MSCWR2_I2S_SPKROFF (1 << 3) /* I2S CODEC amplifier control */ -#define MST_MSCWR2_AC97_SPKROFF (1 << 2) /* AC97 CODEC amplifier control */ -#define MST_MSCWR2_RADIO_PWR (1 << 1) /* Radio module power control */ -#define MST_MSCWR2_RADIO_WAKE (1 << 0) /* Radio module wake-up signal */ - -#define MST_MSCWR3_GPIO_RESET_EN (1 << 2) /* Enable GPIO Reset */ -#define MST_MSCWR3_GPIO_RESET (1 << 1) /* Initiate a GPIO Reset */ -#define MST_MSCWR3_COMMS_SW_RESET (1 << 0) /* Communications Processor Reset Control */ - -#define MST_MSCRD_nPENIRQ (1 << 9) /* ADI7873* nPENIRQ signal */ -#define MST_MSCRD_nMEMSTK_CD (1 << 8) /* Memory Stick detection signal */ -#define MST_MSCRD_nMMC_CD (1 << 7) /* SD/MMC card detection signal */ -#define MST_MSCRD_nUSIM_CD (1 << 6) /* USIM card detection signal */ -#define MST_MSCRD_USB_CBL (1 << 5) /* USB client cable status */ -#define MST_MSCRD_TS_BUSY (1 << 4) /* ADI7873 busy */ -#define MST_MSCRD_BTDSR (1 << 3) /* Bluetooth UART DSR */ -#define MST_MSCRD_BTRI (1 << 2) /* Bluetooth UART Ring Indicator */ -#define MST_MSCRD_BTDCD (1 << 1) /* Bluetooth UART DCD */ -#define MST_MSCRD_nMMC_WP (1 << 0) /* SD/MMC write-protect status */ - -#define MST_INT_S1_IRQ (1 << 15) /* PCMCIA socket 1 IRQ */ -#define MST_INT_S1_STSCHG (1 << 14) /* PCMCIA socket 1 status changed */ -#define MST_INT_S1_CD (1 << 13) /* PCMCIA socket 1 card detection */ -#define MST_INT_S0_IRQ (1 << 11) /* PCMCIA socket 0 IRQ */ -#define MST_INT_S0_STSCHG (1 << 10) /* PCMCIA socket 0 status changed */ -#define MST_INT_S0_CD (1 << 9) /* PCMCIA socket 0 card detection */ -#define MST_INT_nEXBRD_INT (1 << 7) /* Expansion board IRQ */ -#define MST_INT_MSINS (1 << 6) /* Memory Stick* detection */ -#define MST_INT_PENIRQ (1 << 5) /* ADI7873* touch-screen IRQ */ -#define MST_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ -#define MST_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ -#define MST_INT_USBC (1 << 2) /* USB client cable detection IRQ */ -#define MST_INT_USIM (1 << 1) /* USIM card detection IRQ */ -#define MST_INT_MMC (1 << 0) /* MMC/SD card detection IRQ */ - -#define MST_PCMCIA_nIRQ (1 << 10) /* IRQ / ready signal */ -#define MST_PCMCIA_nSPKR_BVD2 (1 << 9) /* VDD sense / digital speaker */ -#define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8) /* VDD sense / card status changed */ -#define MST_PCMCIA_nVS2 (1 << 7) /* VSS voltage sense */ -#define MST_PCMCIA_nVS1 (1 << 6) /* VSS voltage sense */ -#define MST_PCMCIA_nCD (1 << 5) /* Card detection signal */ -#define MST_PCMCIA_RESET (1 << 4) /* Card reset signal */ -#define MST_PCMCIA_PWR_MASK (0x000f) /* MAX1602 power-supply controls */ - -#define MST_PCMCIA_PWR_VPP_0 0x0 /* voltage VPP = 0V */ -#define MST_PCMCIA_PWR_VPP_120 0x2 /* voltage VPP = 12V*/ -#define MST_PCMCIA_PWR_VPP_VCC 0x1 /* voltage VPP = VCC */ -#define MST_PCMCIA_PWR_VCC_0 0x0 /* voltage VCC = 0V */ -#define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */ -#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ - -#define MST_PCMCIA_INPUTS \ - (MST_PCMCIA_nIRQ | MST_PCMCIA_nSPKR_BVD2 | MST_PCMCIA_nSTSCHG_BVD1 | \ - MST_PCMCIA_nVS2 | MST_PCMCIA_nVS1 | MST_PCMCIA_nCD) - -/* board specific IRQs */ -#define MAINSTONE_NR_IRQS IRQ_BOARD_START - -#define MAINSTONE_IRQ(x) (MAINSTONE_NR_IRQS + (x)) -#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) -#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) -#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) -#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) -#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) -#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) -#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) -#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) -#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) -#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) -#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) -#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) -#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) -#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) - -#endif diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index d237bd030238..997f6e502201 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -45,7 +45,7 @@ #include #include "pxa27x.h" -#include +#include "mainstone.h" #include #include #include diff --git a/arch/arm/mach-pxa/mainstone.h b/arch/arm/mach-pxa/mainstone.h new file mode 100644 index 000000000000..ba003742e003 --- /dev/null +++ b/arch/arm/mach-pxa/mainstone.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Author: Nicolas Pitre + * Created: Nov 14, 2002 + * Copyright: MontaVista Software Inc. + */ + +#ifndef ASM_ARCH_MAINSTONE_H +#define ASM_ARCH_MAINSTONE_H + +#include + +#define MST_ETH_PHYS PXA_CS4_PHYS + +#define MST_FPGA_PHYS PXA_CS2_PHYS +#define MST_FPGA_VIRT (0xf0000000) +#define MST_P2V(x) ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT) +#define MST_V2P(x) ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS) + +#ifndef __ASSEMBLY__ +# define __MST_REG(x) (*((volatile unsigned long *)MST_P2V(x))) +#else +# define __MST_REG(x) MST_P2V(x) +#endif + +/* board level registers in the FPGA */ + +#define MST_LEDDAT1 __MST_REG(0x08000010) +#define MST_LEDDAT2 __MST_REG(0x08000014) +#define MST_LEDCTRL __MST_REG(0x08000040) +#define MST_GPSWR __MST_REG(0x08000060) +#define MST_MSCWR1 __MST_REG(0x08000080) +#define MST_MSCWR2 __MST_REG(0x08000084) +#define MST_MSCWR3 __MST_REG(0x08000088) +#define MST_MSCRD __MST_REG(0x08000090) +#define MST_INTMSKENA __MST_REG(0x080000c0) +#define MST_INTSETCLR __MST_REG(0x080000d0) +#define MST_PCMCIA0 __MST_REG(0x080000e0) +#define MST_PCMCIA1 __MST_REG(0x080000e4) + +#define MST_MSCWR1_CAMERA_ON (1 << 15) /* Camera interface power control */ +#define MST_MSCWR1_CAMERA_SEL (1 << 14) /* Camera interface mux control */ +#define MST_MSCWR1_LCD_CTL (1 << 13) /* General-purpose LCD control */ +#define MST_MSCWR1_MS_ON (1 << 12) /* Memory Stick power control */ +#define MST_MSCWR1_MMC_ON (1 << 11) /* MultiMediaCard* power control */ +#define MST_MSCWR1_MS_SEL (1 << 10) /* SD/MS multiplexer control */ +#define MST_MSCWR1_BB_SEL (1 << 9) /* PCMCIA/Baseband multiplexer */ +#define MST_MSCWR1_BT_ON (1 << 8) /* Bluetooth UART transceiver */ +#define MST_MSCWR1_BTDTR (1 << 7) /* Bluetooth UART DTR */ + +#define MST_MSCWR1_IRDA_MASK (3 << 5) /* IrDA transceiver mode */ +#define MST_MSCWR1_IRDA_FULL (0 << 5) /* full distance power */ +#define MST_MSCWR1_IRDA_OFF (1 << 5) /* shutdown */ +#define MST_MSCWR1_IRDA_MED (2 << 5) /* 2/3 distance power */ +#define MST_MSCWR1_IRDA_LOW (3 << 5) /* 1/3 distance power */ + +#define MST_MSCWR1_IRDA_FIR (1 << 4) /* IrDA transceiver SIR/FIR */ +#define MST_MSCWR1_GREENLED (1 << 3) /* LED D1 control */ +#define MST_MSCWR1_PDC_CTL (1 << 2) /* reserved */ +#define MST_MSCWR1_MTR_ON (1 << 1) /* Silent alert motor */ +#define MST_MSCWR1_SYSRESET (1 << 0) /* System reset */ + +#define MST_MSCWR2_USB_OTG_RST (1 << 6) /* USB On The Go reset */ +#define MST_MSCWR2_USB_OTG_SEL (1 << 5) /* USB On The Go control */ +#define MST_MSCWR2_nUSBC_SC (1 << 4) /* USB client soft connect control */ +#define MST_MSCWR2_I2S_SPKROFF (1 << 3) /* I2S CODEC amplifier control */ +#define MST_MSCWR2_AC97_SPKROFF (1 << 2) /* AC97 CODEC amplifier control */ +#define MST_MSCWR2_RADIO_PWR (1 << 1) /* Radio module power control */ +#define MST_MSCWR2_RADIO_WAKE (1 << 0) /* Radio module wake-up signal */ + +#define MST_MSCWR3_GPIO_RESET_EN (1 << 2) /* Enable GPIO Reset */ +#define MST_MSCWR3_GPIO_RESET (1 << 1) /* Initiate a GPIO Reset */ +#define MST_MSCWR3_COMMS_SW_RESET (1 << 0) /* Communications Processor Reset Control */ + +#define MST_MSCRD_nPENIRQ (1 << 9) /* ADI7873* nPENIRQ signal */ +#define MST_MSCRD_nMEMSTK_CD (1 << 8) /* Memory Stick detection signal */ +#define MST_MSCRD_nMMC_CD (1 << 7) /* SD/MMC card detection signal */ +#define MST_MSCRD_nUSIM_CD (1 << 6) /* USIM card detection signal */ +#define MST_MSCRD_USB_CBL (1 << 5) /* USB client cable status */ +#define MST_MSCRD_TS_BUSY (1 << 4) /* ADI7873 busy */ +#define MST_MSCRD_BTDSR (1 << 3) /* Bluetooth UART DSR */ +#define MST_MSCRD_BTRI (1 << 2) /* Bluetooth UART Ring Indicator */ +#define MST_MSCRD_BTDCD (1 << 1) /* Bluetooth UART DCD */ +#define MST_MSCRD_nMMC_WP (1 << 0) /* SD/MMC write-protect status */ + +#define MST_INT_S1_IRQ (1 << 15) /* PCMCIA socket 1 IRQ */ +#define MST_INT_S1_STSCHG (1 << 14) /* PCMCIA socket 1 status changed */ +#define MST_INT_S1_CD (1 << 13) /* PCMCIA socket 1 card detection */ +#define MST_INT_S0_IRQ (1 << 11) /* PCMCIA socket 0 IRQ */ +#define MST_INT_S0_STSCHG (1 << 10) /* PCMCIA socket 0 status changed */ +#define MST_INT_S0_CD (1 << 9) /* PCMCIA socket 0 card detection */ +#define MST_INT_nEXBRD_INT (1 << 7) /* Expansion board IRQ */ +#define MST_INT_MSINS (1 << 6) /* Memory Stick* detection */ +#define MST_INT_PENIRQ (1 << 5) /* ADI7873* touch-screen IRQ */ +#define MST_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ +#define MST_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ +#define MST_INT_USBC (1 << 2) /* USB client cable detection IRQ */ +#define MST_INT_USIM (1 << 1) /* USIM card detection IRQ */ +#define MST_INT_MMC (1 << 0) /* MMC/SD card detection IRQ */ + +#define MST_PCMCIA_nIRQ (1 << 10) /* IRQ / ready signal */ +#define MST_PCMCIA_nSPKR_BVD2 (1 << 9) /* VDD sense / digital speaker */ +#define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8) /* VDD sense / card status changed */ +#define MST_PCMCIA_nVS2 (1 << 7) /* VSS voltage sense */ +#define MST_PCMCIA_nVS1 (1 << 6) /* VSS voltage sense */ +#define MST_PCMCIA_nCD (1 << 5) /* Card detection signal */ +#define MST_PCMCIA_RESET (1 << 4) /* Card reset signal */ +#define MST_PCMCIA_PWR_MASK (0x000f) /* MAX1602 power-supply controls */ + +#define MST_PCMCIA_PWR_VPP_0 0x0 /* voltage VPP = 0V */ +#define MST_PCMCIA_PWR_VPP_120 0x2 /* voltage VPP = 12V*/ +#define MST_PCMCIA_PWR_VPP_VCC 0x1 /* voltage VPP = VCC */ +#define MST_PCMCIA_PWR_VCC_0 0x0 /* voltage VCC = 0V */ +#define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */ +#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ + +#define MST_PCMCIA_INPUTS \ + (MST_PCMCIA_nIRQ | MST_PCMCIA_nSPKR_BVD2 | MST_PCMCIA_nSTSCHG_BVD1 | \ + MST_PCMCIA_nVS2 | MST_PCMCIA_nVS1 | MST_PCMCIA_nCD) + +/* board specific IRQs */ +#define MAINSTONE_NR_IRQS IRQ_BOARD_START + +#define MAINSTONE_IRQ(x) (MAINSTONE_NR_IRQS + (x)) +#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) +#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) +#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) +#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) +#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) +#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) +#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) +#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) +#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) +#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) +#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) +#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) +#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) +#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) + +#endif -- cgit From ff62bdb25e952a1c7c431e041b7b5b77dbcb944c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 1 Sep 2019 21:34:47 +0200 Subject: ARM: pxa: make mach/regs-uart.h private This is not used by any drivers, so make it private to the platform. Acked-by: Robert Jarzmik Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/include/mach/regs-uart.h | 144 ----------------------------- arch/arm/mach-pxa/regs-uart.h | 144 +++++++++++++++++++++++++++++ arch/arm/mach-pxa/viper.c | 2 +- arch/arm/mach-pxa/zeus.c | 2 +- 4 files changed, 146 insertions(+), 146 deletions(-) delete mode 100644 arch/arm/mach-pxa/include/mach/regs-uart.h create mode 100644 arch/arm/mach-pxa/regs-uart.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/regs-uart.h b/arch/arm/mach-pxa/include/mach/regs-uart.h deleted file mode 100644 index 9a168f83afeb..000000000000 --- a/arch/arm/mach-pxa/include/mach/regs-uart.h +++ /dev/null @@ -1,144 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARCH_REGS_UART_H -#define __ASM_ARCH_REGS_UART_H - -/* - * UARTs - */ - -/* Full Function UART (FFUART) */ -#define FFUART FFRBR -#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ -#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ -#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ -#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ -#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ -#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ -#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ -#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ -#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ -#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ -#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ -#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Bluetooth UART (BTUART) */ -#define BTUART BTRBR -#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ -#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ -#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ -#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ -#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ -#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ -#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ -#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ -#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ -#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ -#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ -#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Standard UART (STUART) */ -#define STUART STRBR -#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ -#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ -#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ -#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ -#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ -#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ -#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ -#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ -#define STMSR __REG(0x40700018) /* Reserved */ -#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ -#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ -#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Hardware UART (HWUART) */ -#define HWUART HWRBR -#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ -#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ -#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ -#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ -#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ -#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ -#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ -#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ -#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ -#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ -#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ -#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ -#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ -#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ -#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -#define IER_DMAE (1 << 7) /* DMA Requests Enable */ -#define IER_UUE (1 << 6) /* UART Unit Enable */ -#define IER_NRZE (1 << 5) /* NRZ coding Enable */ -#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ -#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ -#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ -#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ -#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ - -#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ -#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ -#define IIR_TOD (1 << 3) /* Time Out Detected */ -#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ -#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ -#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ - -#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ -#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ -#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ -#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ -#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ -#define FCR_ITL_1 (0) -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ -#define LCR_SB (1 << 6) /* Set Break */ -#define LCR_STKYP (1 << 5) /* Sticky Parity */ -#define LCR_EPS (1 << 4) /* Even Parity Select */ -#define LCR_PEN (1 << 3) /* Parity Enable */ -#define LCR_STB (1 << 2) /* Stop Bit */ -#define LCR_WLS1 (1 << 1) /* Word Length Select */ -#define LCR_WLS0 (1 << 0) /* Word Length Select */ - -#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ -#define LSR_TEMT (1 << 6) /* Transmitter Empty */ -#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ -#define LSR_BI (1 << 4) /* Break Interrupt */ -#define LSR_FE (1 << 3) /* Framing Error */ -#define LSR_PE (1 << 2) /* Parity Error */ -#define LSR_OE (1 << 1) /* Overrun Error */ -#define LSR_DR (1 << 0) /* Data Ready */ - -#define MCR_LOOP (1 << 4) -#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ -#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ -#define MCR_RTS (1 << 1) /* Request to Send */ -#define MCR_DTR (1 << 0) /* Data Terminal Ready */ - -#define MSR_DCD (1 << 7) /* Data Carrier Detect */ -#define MSR_RI (1 << 6) /* Ring Indicator */ -#define MSR_DSR (1 << 5) /* Data Set Ready */ -#define MSR_CTS (1 << 4) /* Clear To Send */ -#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ -#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ -#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ -#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ - -/* - * IrSR (Infrared Selection Register) - */ -#define STISR_RXPL (1 << 4) /* Receive Data Polarity */ -#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ -#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ -#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ -#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ - -#endif /* __ASM_ARCH_REGS_UART_H */ diff --git a/arch/arm/mach-pxa/regs-uart.h b/arch/arm/mach-pxa/regs-uart.h new file mode 100644 index 000000000000..9a168f83afeb --- /dev/null +++ b/arch/arm/mach-pxa/regs-uart.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_ARCH_REGS_UART_H +#define __ASM_ARCH_REGS_UART_H + +/* + * UARTs + */ + +/* Full Function UART (FFUART) */ +#define FFUART FFRBR +#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ +#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ +#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ +#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ +#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ +#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ +#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ +#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ +#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ +#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ +#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ +#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Bluetooth UART (BTUART) */ +#define BTUART BTRBR +#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ +#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ +#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ +#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ +#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ +#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ +#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ +#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ +#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ +#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ +#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ +#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Standard UART (STUART) */ +#define STUART STRBR +#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ +#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ +#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ +#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ +#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ +#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ +#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ +#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ +#define STMSR __REG(0x40700018) /* Reserved */ +#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ +#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ +#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Hardware UART (HWUART) */ +#define HWUART HWRBR +#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ +#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ +#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ +#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ +#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ +#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ +#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ +#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ +#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ +#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ +#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ +#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ +#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ +#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ +#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +#define IER_DMAE (1 << 7) /* DMA Requests Enable */ +#define IER_UUE (1 << 6) /* UART Unit Enable */ +#define IER_NRZE (1 << 5) /* NRZ coding Enable */ +#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ +#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ +#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ +#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ +#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ + +#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ +#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ +#define IIR_TOD (1 << 3) /* Time Out Detected */ +#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ +#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ +#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ + +#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ +#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ +#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ +#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ +#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ +#define FCR_ITL_1 (0) +#define FCR_ITL_8 (FCR_ITL1) +#define FCR_ITL_16 (FCR_ITL2) +#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) + +#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ +#define LCR_SB (1 << 6) /* Set Break */ +#define LCR_STKYP (1 << 5) /* Sticky Parity */ +#define LCR_EPS (1 << 4) /* Even Parity Select */ +#define LCR_PEN (1 << 3) /* Parity Enable */ +#define LCR_STB (1 << 2) /* Stop Bit */ +#define LCR_WLS1 (1 << 1) /* Word Length Select */ +#define LCR_WLS0 (1 << 0) /* Word Length Select */ + +#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ +#define LSR_TEMT (1 << 6) /* Transmitter Empty */ +#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ +#define LSR_BI (1 << 4) /* Break Interrupt */ +#define LSR_FE (1 << 3) /* Framing Error */ +#define LSR_PE (1 << 2) /* Parity Error */ +#define LSR_OE (1 << 1) /* Overrun Error */ +#define LSR_DR (1 << 0) /* Data Ready */ + +#define MCR_LOOP (1 << 4) +#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ +#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ +#define MCR_RTS (1 << 1) /* Request to Send */ +#define MCR_DTR (1 << 0) /* Data Terminal Ready */ + +#define MSR_DCD (1 << 7) /* Data Carrier Detect */ +#define MSR_RI (1 << 6) /* Ring Indicator */ +#define MSR_DSR (1 << 5) /* Data Set Ready */ +#define MSR_CTS (1 << 4) /* Clear To Send */ +#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ +#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ +#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ +#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ + +/* + * IrSR (Infrared Selection Register) + */ +#define STISR_RXPL (1 << 4) /* Receive Data Polarity */ +#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ +#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ +#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ +#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ + +#endif /* __ASM_ARCH_REGS_UART_H */ diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 3aa34e9a15d3..4b81c0117971 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -48,7 +48,7 @@ #include "pxa25x.h" #include #include -#include +#include "regs-uart.h" #include #include "viper.h" diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 97700429633e..5d02f10b5b5a 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -39,7 +39,7 @@ #include "pxa27x.h" #include "devices.h" -#include +#include "regs-uart.h" #include #include #include "pxa27x-udc.h" -- cgit From eec05d26ea5e20dec50fdcddcaa6e0787f394691 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 1 Sep 2019 23:06:17 +0200 Subject: ARM: pxa: remove mach/dma.h The file no longer contains anything useful, so remove it. Acked-by: Robert Jarzmik Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/include/mach/dma.h | 17 ----------------- arch/arm/mach-pxa/pxa25x.c | 1 - arch/arm/mach-pxa/pxa27x.c | 1 - arch/arm/mach-pxa/pxa3xx.c | 1 - 4 files changed, 20 deletions(-) delete mode 100644 arch/arm/mach-pxa/include/mach/dma.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h deleted file mode 100644 index 79f9842a7e1c..000000000000 --- a/arch/arm/mach-pxa/include/mach/dma.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-pxa/include/mach/dma.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software, Inc. - */ -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -#include - -/* DMA Controller Registers Definitions */ -#define DMAC_REGS_VIRT io_p2v(0x40000000) - -#endif /* _ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 678641ab46e5..0d25cc45f825 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -34,7 +34,6 @@ #include "pxa25x.h" #include #include "pm.h" -#include #include #include "generic.h" diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index f0ba7ed24cb6..f7e89831e85b 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -33,7 +33,6 @@ #include #include #include "pm.h" -#include #include #include "generic.h" diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 560160682df6..6eb1c24d7395 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -32,7 +32,6 @@ #include #include #include "pm.h" -#include #include #include -- cgit From 08d3df8c81537089fc8f21006b56f2f6fb23c6f8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 1 Sep 2019 22:26:10 +0200 Subject: ARM: pxa: split up mach/hardware.h The mach/hardware.h is included in lots of places, and it provides three different things on pxa: - the cpu_is_pxa* macros - an indirect inclusion of mach/addr-map.h - the __REG() and io_pv2() helper macros Split it up into separate and mach/pxa-regs.h headers, then change all the files that use mach/hardware.h to include the exact set of those three headers that they actually need, allowing for further more targeted cleanup. linux/soc/pxa/cpu.h can remain permanently exported and is now in a global location along with similar headers. pxa-regs.h and addr-map.h are only used in a very small number of drivers now and can be moved to arch/arm/mach-pxa/ directly when those drivers are to pass the necessary data as resources. Cc: Michael Turquette Cc: Stephen Boyd Acked-by: Viresh Kumar Acked-by: Dmitry Torokhov Cc: Jacek Anaszewski Cc: Pavel Machek Acked-by: Ulf Hansson Cc: Dominik Brodowski Acked-by: Alexandre Belloni Cc: Greg Kroah-Hartman Cc: Guenter Roeck Acked-by: Mark Brown Cc: linux-clk@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-input@vger.kernel.org Cc: linux-leds@vger.kernel.org Cc: linux-mmc@vger.kernel.org Cc: linux-mtd@lists.infradead.org Cc: linux-rtc@vger.kernel.org Cc: linux-usb@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: linux-fbdev@vger.kernel.org Cc: linux-watchdog@vger.kernel.org Cc: alsa-devel@alsa-project.org Signed-off-by: Arnd Bergmann --- arch/arm/common/locomo.c | 1 - arch/arm/common/sa1111.c | 5 +- arch/arm/mach-pxa/cm-x300.c | 2 + arch/arm/mach-pxa/colibri-evalboard.c | 1 - arch/arm/mach-pxa/colibri-pxa270-income.c | 1 - arch/arm/mach-pxa/colibri-pxa300.c | 1 + arch/arm/mach-pxa/colibri-pxa3xx.c | 1 - arch/arm/mach-pxa/corgi.c | 1 - arch/arm/mach-pxa/corgi_pm.c | 1 - arch/arm/mach-pxa/csb726.c | 1 + arch/arm/mach-pxa/devices.c | 2 +- arch/arm/mach-pxa/ezx.c | 1 - arch/arm/mach-pxa/generic.c | 3 +- arch/arm/mach-pxa/gumstix.c | 1 - arch/arm/mach-pxa/hx4700.c | 2 +- arch/arm/mach-pxa/idp.c | 1 - arch/arm/mach-pxa/include/mach/hardware.h | 305 --------------------------- arch/arm/mach-pxa/include/mach/pxa-regs.h | 52 +++++ arch/arm/mach-pxa/include/mach/pxa2xx-regs.h | 2 +- arch/arm/mach-pxa/include/mach/pxa3xx-regs.h | 2 +- arch/arm/mach-pxa/include/mach/regs-ac97.h | 2 +- arch/arm/mach-pxa/include/mach/regs-ost.h | 2 +- arch/arm/mach-pxa/include/mach/trizeps4.h | 1 + arch/arm/mach-pxa/irq.c | 3 +- arch/arm/mach-pxa/littleton.c | 1 - arch/arm/mach-pxa/lpd270.c | 2 +- arch/arm/mach-pxa/lubbock.c | 1 - arch/arm/mach-pxa/magician.c | 2 +- arch/arm/mach-pxa/mainstone.c | 2 +- arch/arm/mach-pxa/mfp-pxa2xx.c | 1 + arch/arm/mach-pxa/mfp-pxa3xx.c | 1 - arch/arm/mach-pxa/poodle.c | 1 - arch/arm/mach-pxa/pxa-regs.h | 1 + arch/arm/mach-pxa/pxa25x.c | 3 +- arch/arm/mach-pxa/pxa25x.h | 2 +- arch/arm/mach-pxa/pxa27x-udc.h | 2 + arch/arm/mach-pxa/pxa27x.c | 3 +- arch/arm/mach-pxa/pxa27x.h | 2 +- arch/arm/mach-pxa/pxa2xx.c | 1 - arch/arm/mach-pxa/pxa300.c | 1 + arch/arm/mach-pxa/pxa320.c | 1 + arch/arm/mach-pxa/pxa3xx-ulpi.c | 2 +- arch/arm/mach-pxa/pxa3xx.c | 3 +- arch/arm/mach-pxa/pxa3xx.h | 2 +- arch/arm/mach-pxa/pxa930.c | 1 + arch/arm/mach-pxa/regs-rtc.h | 2 +- arch/arm/mach-pxa/regs-uart.h | 2 + arch/arm/mach-pxa/sleep.S | 1 - arch/arm/mach-pxa/smemc.c | 2 +- arch/arm/mach-pxa/spitz_pm.c | 1 - arch/arm/mach-pxa/standby.S | 1 - arch/arm/mach-pxa/xcep.c | 2 +- arch/arm/mach-pxa/zylonite.c | 1 + arch/arm/mach-pxa/zylonite.h | 2 + arch/arm/mach-pxa/zylonite_pxa300.c | 1 + arch/arm/mach-pxa/zylonite_pxa320.c | 1 + 56 files changed, 101 insertions(+), 344 deletions(-) delete mode 100644 arch/arm/mach-pxa/include/mach/hardware.h create mode 100644 arch/arm/mach-pxa/include/mach/pxa-regs.h create mode 100644 arch/arm/mach-pxa/pxa-regs.h (limited to 'arch') diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index 24d21ba63030..da30a4d4f35c 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -23,7 +23,6 @@ #include #include -#include #include #include diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 5367f03beb46..2343e2b6214d 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -26,13 +26,16 @@ #include #include -#include #include #include #include #include +#ifdef CONFIG_ARCH_SA1100 +#include +#endif + /* SA1111 IRQs */ #define IRQ_GPAIN0 (0) #define IRQ_GPAIN1 (1) diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 2e35354b61f5..85e2537fdc15 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -40,6 +40,8 @@ #include #include +#include + #include #include #include diff --git a/arch/arm/mach-pxa/colibri-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c index b9c173ede891..b62af07b8f96 100644 --- a/arch/arm/mach-pxa/colibri-evalboard.c +++ b/arch/arm/mach-pxa/colibri-evalboard.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c index e5879e8b0682..f6eaf464ca83 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-income.c +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c @@ -25,7 +25,6 @@ #include #include -#include #include #include #include "pxa27x.h" diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c index 82052dfd96b6..4ceeea142bfd 100644 --- a/arch/arm/mach-pxa/colibri-pxa300.c +++ b/arch/arm/mach-pxa/colibri-pxa300.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index 3cead80a2b37..701dfef930eb 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 44659fbc37ba..f897762c8b58 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -39,7 +39,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index 092dcb9fced5..ff1ac9bf37cb 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c @@ -19,7 +19,6 @@ #include #include -#include #include #include diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index 98fcdc6e2944..d48493445ae5 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c @@ -17,6 +17,7 @@ #include #include + #include "csb726.h" #include "pxa27x.h" #include diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 09b8495f3fd9..7ca97ddef6fe 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "udc.h" #include @@ -20,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index eb85950e7c0e..69c2ec02a16c 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -29,7 +29,6 @@ #include "pxa27x.h" #include #include -#include #include #include diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index ab7cdffd7ea8..3c3cd90bb9b4 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -17,11 +17,12 @@ #include #include #include +#include -#include #include #include +#include #include #include #include diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index 49dd618b10f7..72b08a9bf0fd 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index e1870fbb19e7..191a6c24fe19 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -36,11 +36,11 @@ #include #include -#include #include #include #include "pxa27x.h" +#include #include #include diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index fb0850af8496..57c0511472bc 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h deleted file mode 100644 index ee7eab16135f..000000000000 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ /dev/null @@ -1,305 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-pxa/include/mach/hardware.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include - -/* - * Workarounds for at least 2 errata so far require this. - * The mapping is set in mach-pxa/generic.c. - */ -#define UNCACHED_PHYS_0 0xfe000000 -#define UNCACHED_PHYS_0_SIZE 0x00100000 - -/* - * Intel PXA2xx internal register mapping: - * - * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff - * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff - * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff - * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff - * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff - * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff - * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff - * - * Note that not all PXA2xx chips implement all those addresses, and the - * kernel only maps the minimum needed range of this mapping. - */ -#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) -#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) - -#ifndef __ASSEMBLY__ -# define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) - -/* With indexed regs we don't want to feed the index through io_p2v() - especially if it is a variable, otherwise horrible code will result. */ -# define __REG2(x,y) \ - (*(volatile u32 __iomem*)((u32)&__REG(x) + (y))) - -# define __PREG(x) (io_v2p((u32)&(x))) - -#else - -# define __REG(x) io_p2v(x) -# define __PREG(x) io_v2p(x) - -#endif - -#ifndef __ASSEMBLY__ - -#include - -/* - * CPU Stepping CPU_ID JTAG_ID - * - * PXA210 B0 0x69052922 0x2926C013 - * PXA210 B1 0x69052923 0x3926C013 - * PXA210 B2 0x69052924 0x4926C013 - * PXA210 C0 0x69052D25 0x5926C013 - * - * PXA250 A0 0x69052100 0x09264013 - * PXA250 A1 0x69052101 0x19264013 - * PXA250 B0 0x69052902 0x29264013 - * PXA250 B1 0x69052903 0x39264013 - * PXA250 B2 0x69052904 0x49264013 - * PXA250 C0 0x69052D05 0x59264013 - * - * PXA255 A0 0x69052D06 0x69264013 - * - * PXA26x A0 0x69052903 0x39264013 - * PXA26x B0 0x69052D05 0x59264013 - * - * PXA27x A0 0x69054110 0x09265013 - * PXA27x A1 0x69054111 0x19265013 - * PXA27x B0 0x69054112 0x29265013 - * PXA27x B1 0x69054113 0x39265013 - * PXA27x C0 0x69054114 0x49265013 - * PXA27x C5 0x69054117 0x79265013 - * - * PXA30x A0 0x69056880 0x0E648013 - * PXA30x A1 0x69056881 0x1E648013 - * PXA31x A0 0x69056890 0x0E649013 - * PXA31x A1 0x69056891 0x1E649013 - * PXA31x A2 0x69056892 0x2E649013 - * PXA32x B1 0x69056825 0x5E642013 - * PXA32x B2 0x69056826 0x6E642013 - * - * PXA930 B0 0x69056835 0x5E643013 - * PXA930 B1 0x69056837 0x7E643013 - * PXA930 B2 0x69056838 0x8E643013 - * - * PXA935 A0 0x56056931 0x1E653013 - * PXA935 B0 0x56056936 0x6E653013 - * PXA935 B1 0x56056938 0x8E653013 - */ -#ifdef CONFIG_PXA25x -#define __cpu_is_pxa210(id) \ - ({ \ - unsigned int _id = (id) & 0xf3f0; \ - _id == 0x2120; \ - }) - -#define __cpu_is_pxa250(id) \ - ({ \ - unsigned int _id = (id) & 0xf3ff; \ - _id <= 0x2105; \ - }) - -#define __cpu_is_pxa255(id) \ - ({ \ - unsigned int _id = (id) & 0xffff; \ - _id == 0x2d06; \ - }) - -#define __cpu_is_pxa25x(id) \ - ({ \ - unsigned int _id = (id) & 0xf300; \ - _id == 0x2100; \ - }) -#else -#define __cpu_is_pxa210(id) (0) -#define __cpu_is_pxa250(id) (0) -#define __cpu_is_pxa255(id) (0) -#define __cpu_is_pxa25x(id) (0) -#endif - -#ifdef CONFIG_PXA27x -#define __cpu_is_pxa27x(id) \ - ({ \ - unsigned int _id = (id) >> 4 & 0xfff; \ - _id == 0x411; \ - }) -#else -#define __cpu_is_pxa27x(id) (0) -#endif - -#ifdef CONFIG_CPU_PXA300 -#define __cpu_is_pxa300(id) \ - ({ \ - unsigned int _id = (id) >> 4 & 0xfff; \ - _id == 0x688; \ - }) -#else -#define __cpu_is_pxa300(id) (0) -#endif - -#ifdef CONFIG_CPU_PXA310 -#define __cpu_is_pxa310(id) \ - ({ \ - unsigned int _id = (id) >> 4 & 0xfff; \ - _id == 0x689; \ - }) -#else -#define __cpu_is_pxa310(id) (0) -#endif - -#ifdef CONFIG_CPU_PXA320 -#define __cpu_is_pxa320(id) \ - ({ \ - unsigned int _id = (id) >> 4 & 0xfff; \ - _id == 0x603 || _id == 0x682; \ - }) -#else -#define __cpu_is_pxa320(id) (0) -#endif - -#ifdef CONFIG_CPU_PXA930 -#define __cpu_is_pxa930(id) \ - ({ \ - unsigned int _id = (id) >> 4 & 0xfff; \ - _id == 0x683; \ - }) -#else -#define __cpu_is_pxa930(id) (0) -#endif - -#ifdef CONFIG_CPU_PXA935 -#define __cpu_is_pxa935(id) \ - ({ \ - unsigned int _id = (id) >> 4 & 0xfff; \ - _id == 0x693; \ - }) -#else -#define __cpu_is_pxa935(id) (0) -#endif - -#define cpu_is_pxa210() \ - ({ \ - __cpu_is_pxa210(read_cpuid_id()); \ - }) - -#define cpu_is_pxa250() \ - ({ \ - __cpu_is_pxa250(read_cpuid_id()); \ - }) - -#define cpu_is_pxa255() \ - ({ \ - __cpu_is_pxa255(read_cpuid_id()); \ - }) - -#define cpu_is_pxa25x() \ - ({ \ - __cpu_is_pxa25x(read_cpuid_id()); \ - }) - -#define cpu_is_pxa27x() \ - ({ \ - __cpu_is_pxa27x(read_cpuid_id()); \ - }) - -#define cpu_is_pxa300() \ - ({ \ - __cpu_is_pxa300(read_cpuid_id()); \ - }) - -#define cpu_is_pxa310() \ - ({ \ - __cpu_is_pxa310(read_cpuid_id()); \ - }) - -#define cpu_is_pxa320() \ - ({ \ - __cpu_is_pxa320(read_cpuid_id()); \ - }) - -#define cpu_is_pxa930() \ - ({ \ - __cpu_is_pxa930(read_cpuid_id()); \ - }) - -#define cpu_is_pxa935() \ - ({ \ - __cpu_is_pxa935(read_cpuid_id()); \ - }) - - - -/* - * CPUID Core Generation Bit - * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x - */ -#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) -#define __cpu_is_pxa2xx(id) \ - ({ \ - unsigned int _id = (id) >> 13 & 0x7; \ - _id <= 0x2; \ - }) -#else -#define __cpu_is_pxa2xx(id) (0) -#endif - -#ifdef CONFIG_PXA3xx -#define __cpu_is_pxa3xx(id) \ - ({ \ - __cpu_is_pxa300(id) \ - || __cpu_is_pxa310(id) \ - || __cpu_is_pxa320(id) \ - || __cpu_is_pxa93x(id); \ - }) -#else -#define __cpu_is_pxa3xx(id) (0) -#endif - -#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935) -#define __cpu_is_pxa93x(id) \ - ({ \ - __cpu_is_pxa930(id) \ - || __cpu_is_pxa935(id); \ - }) -#else -#define __cpu_is_pxa93x(id) (0) -#endif - -#define cpu_is_pxa2xx() \ - ({ \ - __cpu_is_pxa2xx(read_cpuid_id()); \ - }) - -#define cpu_is_pxa3xx() \ - ({ \ - __cpu_is_pxa3xx(read_cpuid_id()); \ - }) - -#define cpu_is_pxa93x() \ - ({ \ - __cpu_is_pxa93x(read_cpuid_id()); \ - }) - - -/* - * return current memory and LCD clock frequency in units of 10kHz - */ -extern unsigned int get_memclk_frequency_10khz(void); - -#endif - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h new file mode 100644 index 000000000000..ba5120c06b8a --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + */ +#ifndef __ASM_MACH_PXA_REGS_H +#define __ASM_MACH_PXA_REGS_H + +/* + * Workarounds for at least 2 errata so far require this. + * The mapping is set in mach-pxa/generic.c. + */ +#define UNCACHED_PHYS_0 0xfe000000 +#define UNCACHED_PHYS_0_SIZE 0x00100000 + +/* + * Intel PXA2xx internal register mapping: + * + * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff + * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff + * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff + * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff + * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff + * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff + * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff + * + * Note that not all PXA2xx chips implement all those addresses, and the + * kernel only maps the minimum needed range of this mapping. + */ +#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) +#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) + +#ifndef __ASSEMBLY__ +# define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) + +/* With indexed regs we don't want to feed the index through io_p2v() + especially if it is a variable, otherwise horrible code will result. */ +# define __REG2(x,y) \ + (*(volatile u32 __iomem*)((u32)&__REG(x) + (y))) + +# define __PREG(x) (io_v2p((u32)&(x))) + +#else + +# define __REG(x) io_p2v(x) +# define __PREG(x) io_v2p(x) + +#endif + + +#endif diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index fa121e135915..f68b573ab4a0 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -11,7 +11,7 @@ #ifndef __PXA2XX_REGS_H #define __PXA2XX_REGS_H -#include +#include "pxa-regs.h" /* * Power Manager diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index 070f6c74196e..8eb1ba533e1c 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -10,7 +10,7 @@ #ifndef __ASM_ARCH_PXA3XX_REGS_H #define __ASM_ARCH_PXA3XX_REGS_H -#include +#include "pxa-regs.h" /* * Oscillator Configuration Register (OSCC) diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h index 1db96fd4df32..ec09b9635e25 100644 --- a/arch/arm/mach-pxa/include/mach/regs-ac97.h +++ b/arch/arm/mach-pxa/include/mach/regs-ac97.h @@ -2,7 +2,7 @@ #ifndef __ASM_ARCH_REGS_AC97_H #define __ASM_ARCH_REGS_AC97_H -#include +#include "pxa-regs.h" /* * AC97 Controller registers diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h index deb564ed8ee7..109d0ed264df 100644 --- a/arch/arm/mach-pxa/include/mach/regs-ost.h +++ b/arch/arm/mach-pxa/include/mach/regs-ost.h @@ -2,7 +2,7 @@ #ifndef __ASM_MACH_REGS_OST_H #define __ASM_MACH_REGS_OST_H -#include +#include "pxa-regs.h" /* * OS Timer & Match Registers diff --git a/arch/arm/mach-pxa/include/mach/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h index 3cddb1428c5e..27926629f9c6 100644 --- a/arch/arm/mach-pxa/include/mach/trizeps4.h +++ b/arch/arm/mach-pxa/include/mach/trizeps4.h @@ -11,6 +11,7 @@ #ifndef _TRIPEPS4_H_ #define _TRIPEPS4_H_ +#include #include "irqs.h" /* PXA_GPIO_TO_IRQ */ /* physical memory regions */ diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 74efc3ab595f..f25c30e8a834 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -17,13 +17,14 @@ #include #include #include +#include #include -#include #include #include "generic.h" +#include "pxa-regs.h" #define ICIP (0x000) #define ICMR (0x004) diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 73f5953b3bb6..f98dc61e87af 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 6fc40bc06910..eac32bd9e385 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include @@ -39,6 +38,7 @@ #include "pxa27x.h" #include "lpd270.h" +#include #include #include #include diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index e2411971422d..72816e7c206f 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 200fd35168e0..345a44d15a2c 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -29,12 +29,12 @@ #include #include -#include #include #include #include #include "pxa27x.h" +#include #include #include #include diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 997f6e502201..cf74adfe65df 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include @@ -52,6 +51,7 @@ #include #include #include +#include #include #include "generic.h" diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 6a5451b186c2..6bc7206fd2ac 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "mfp-pxa2xx.h" diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c index 56114df9700d..f26b5e5412cf 100644 --- a/arch/arm/mach-pxa/mfp-pxa3xx.c +++ b/arch/arm/mach-pxa/mfp-pxa3xx.c @@ -16,7 +16,6 @@ #include #include -#include #include "mfp-pxa3xx.h" #include diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 58cfa434afde..ca52882433d4 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -30,7 +30,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/mach-pxa/pxa-regs.h b/arch/arm/mach-pxa/pxa-regs.h new file mode 100644 index 000000000000..584d2ac592cc --- /dev/null +++ b/arch/arm/mach-pxa/pxa-regs.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 0d25cc45f825..305047ebd2f1 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -26,14 +26,15 @@ #include #include #include +#include #include #include -#include #include #include "pxa25x.h" #include #include "pm.h" +#include #include #include "generic.h" diff --git a/arch/arm/mach-pxa/pxa25x.h b/arch/arm/mach-pxa/pxa25x.h index b58d0fbdb4db..403bc16c2ed2 100644 --- a/arch/arm/mach-pxa/pxa25x.h +++ b/arch/arm/mach-pxa/pxa25x.h @@ -2,7 +2,7 @@ #ifndef __MACH_PXA25x_H #define __MACH_PXA25x_H -#include +#include #include #include "mfp-pxa25x.h" #include diff --git a/arch/arm/mach-pxa/pxa27x-udc.h b/arch/arm/mach-pxa/pxa27x-udc.h index faf73804697f..2d3df3b1cb68 100644 --- a/arch/arm/mach-pxa/pxa27x-udc.h +++ b/arch/arm/mach-pxa/pxa27x-udc.h @@ -2,6 +2,8 @@ #ifndef _ASM_ARCH_PXA27X_UDC_H #define _ASM_ARCH_PXA27X_UDC_H +#include "pxa-regs.h" + #ifdef _ASM_ARCH_PXA25X_UDC_H #error You cannot include both PXA25x and PXA27x UDC support #endif diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index f7e89831e85b..a81ac88ecbfd 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -23,9 +23,9 @@ #include #include #include +#include #include -#include #include #include #include @@ -33,6 +33,7 @@ #include #include #include "pm.h" +#include #include #include "generic.h" diff --git a/arch/arm/mach-pxa/pxa27x.h b/arch/arm/mach-pxa/pxa27x.h index abdc02fb4f03..6c99090647d2 100644 --- a/arch/arm/mach-pxa/pxa27x.h +++ b/arch/arm/mach-pxa/pxa27x.h @@ -3,7 +3,7 @@ #define __MACH_PXA27x_H #include -#include +#include #include #include "mfp-pxa27x.h" #include diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c index 2d26cd2afbf3..ac72acb43e26 100644 --- a/arch/arm/mach-pxa/pxa2xx.c +++ b/arch/arm/mach-pxa/pxa2xx.c @@ -12,7 +12,6 @@ #include #include -#include #include #include "mfp-pxa25x.h" #include diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c index 7f2f5a6a2263..f77ec118d5b9 100644 --- a/arch/arm/mach-pxa/pxa300.c +++ b/arch/arm/mach-pxa/pxa300.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "pxa300.h" diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c index 78abcc741df7..e372e6c118de 100644 --- a/arch/arm/mach-pxa/pxa320.c +++ b/arch/arm/mach-pxa/pxa320.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "pxa320.h" diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c index 4bd7da1f8657..c29a7f0fa1b0 100644 --- a/arch/arm/mach-pxa/pxa3xx-ulpi.c +++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c @@ -21,8 +21,8 @@ #include #include #include +#include -#include #include "regs-u2d.h" #include diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 6eb1c24d7395..fc84aed99481 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -24,14 +24,15 @@ #include #include #include +#include #include #include -#include #include #include #include #include "pm.h" +#include #include #include diff --git a/arch/arm/mach-pxa/pxa3xx.h b/arch/arm/mach-pxa/pxa3xx.h index 6d4502aa9d06..22ace053ea25 100644 --- a/arch/arm/mach-pxa/pxa3xx.h +++ b/arch/arm/mach-pxa/pxa3xx.h @@ -2,7 +2,7 @@ #ifndef __MACH_PXA3XX_H #define __MACH_PXA3XX_H -#include +#include #include #include diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c index bf91de4267e5..b9021a40cbd1 100644 --- a/arch/arm/mach-pxa/pxa930.c +++ b/arch/arm/mach-pxa/pxa930.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "pxa930.h" diff --git a/arch/arm/mach-pxa/regs-rtc.h b/arch/arm/mach-pxa/regs-rtc.h index b1f9ff14e335..96255a0f595e 100644 --- a/arch/arm/mach-pxa/regs-rtc.h +++ b/arch/arm/mach-pxa/regs-rtc.h @@ -2,7 +2,7 @@ #ifndef __ASM_MACH_REGS_RTC_H #define __ASM_MACH_REGS_RTC_H -#include +#include "pxa-regs.h" /* * Real Time Clock diff --git a/arch/arm/mach-pxa/regs-uart.h b/arch/arm/mach-pxa/regs-uart.h index 9a168f83afeb..490e9ca16297 100644 --- a/arch/arm/mach-pxa/regs-uart.h +++ b/arch/arm/mach-pxa/regs-uart.h @@ -2,6 +2,8 @@ #ifndef __ASM_ARCH_REGS_UART_H #define __ASM_ARCH_REGS_UART_H +#include "pxa-regs.h" + /* * UARTs */ diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index 6c5b3ffd2cd3..272efeb954f4 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -13,7 +13,6 @@ #include #include -#include #include #include diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c index 32e82cc92ea5..47b99549d616 100644 --- a/arch/arm/mach-pxa/smemc.c +++ b/arch/arm/mach-pxa/smemc.c @@ -8,8 +8,8 @@ #include #include #include +#include -#include #include #ifdef CONFIG_PM diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 25a1f8c5a738..201dabe883b6 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c @@ -18,7 +18,6 @@ #include #include -#include #include #include "pxa27x.h" diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S index eab1645bb4ad..626fecdefb1c 100644 --- a/arch/arm/mach-pxa/standby.S +++ b/arch/arm/mach-pxa/standby.S @@ -11,7 +11,6 @@ #include #include -#include #include diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c index f485146b899f..e6ab428287ae 100644 --- a/arch/arm/mach-pxa/xcep.c +++ b/arch/arm/mach-pxa/xcep.c @@ -24,8 +24,8 @@ #include #include -#include #include "pxa25x.h" +#include #include #include "generic.h" diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 79f0025fa17a..9bcb81688201 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-pxa/zylonite.h b/arch/arm/mach-pxa/zylonite.h index 7300ec2aac0d..afe3efcb8e04 100644 --- a/arch/arm/mach-pxa/zylonite.h +++ b/arch/arm/mach-pxa/zylonite.h @@ -2,6 +2,8 @@ #ifndef __ASM_ARCH_ZYLONITE_H #define __ASM_ARCH_ZYLONITE_H +#include + #define ZYLONITE_ETH_PHYS 0x14000000 #define EXT_GPIO(x) (128 + (x)) diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c index 956fec1c4940..50a8a3547dbc 100644 --- a/arch/arm/mach-pxa/zylonite_pxa300.c +++ b/arch/arm/mach-pxa/zylonite_pxa300.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "pxa300.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c index 94cb834f36cd..67cab4f1194b 100644 --- a/arch/arm/mach-pxa/zylonite_pxa320.c +++ b/arch/arm/mach-pxa/zylonite_pxa320.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "pxa320.h" #include "zylonite.h" -- cgit From 2a0fd0a95a1e63f18df189c178459c5965d4ce6c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 1 Sep 2019 23:25:15 +0200 Subject: ARM: pxa: stop using mach/bitfield.h There are two identical copies of mach/bitfield.h, one for mach-sa1100 and one for mach-pxa. The pxafb driver only makes use of two macros, which can be trivially open-coded in the header. Cc: dri-devel@lists.freedesktop.org Acked-by: Bartlomiej Zolnierkiewicz Acked-by: Robert Jarzmik Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/idp.c | 1 - arch/arm/mach-pxa/include/mach/regs-lcd.h | 5 +++-- arch/arm/mach-pxa/regs-u2d.h | 2 -- 3 files changed, 3 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index 57c0511472bc..525d01ddfbbb 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -30,7 +30,6 @@ #include "pxa25x.h" #include "idp.h" #include -#include #include #include diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h index e2b6e3d1f625..6a434675f84a 100644 --- a/arch/arm/mach-pxa/include/mach/regs-lcd.h +++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h @@ -2,8 +2,6 @@ #ifndef __ASM_ARCH_REGS_LCD_H #define __ASM_ARCH_REGS_LCD_H -#include - /* * LCD Controller Registers and Bits Definitions */ @@ -86,6 +84,9 @@ #define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */ #define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */ +#define Fld(Size, Shft) (((Size) << 16) + (Shft)) +#define FShft(Field) ((Field) & 0x0000FFFF) + #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) diff --git a/arch/arm/mach-pxa/regs-u2d.h b/arch/arm/mach-pxa/regs-u2d.h index fe4c80ad87ec..ab517ba62c9a 100644 --- a/arch/arm/mach-pxa/regs-u2d.h +++ b/arch/arm/mach-pxa/regs-u2d.h @@ -2,8 +2,6 @@ #ifndef __ASM_ARCH_PXA3xx_U2D_H #define __ASM_ARCH_PXA3xx_U2D_H -#include - /* * USB2 device controller registers and bits definitions */ -- cgit From 22f0866513c2e531ae65a9d5dfc82f24497ef3b3 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 2 Sep 2019 00:02:08 +0200 Subject: ARM: pxa: move mach/sound.h to linux/platform_data/ This is a basically a platform_data file, so move it out of the mach/* header directory. Cc: Marek Vasut Cc: Tomas Cech Cc: Sergey Lapin Acked-by: Mark Brown Acked-by: Robert Jarzmik Cc: alsa-devel@alsa-project.org Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/balloon3.c | 2 +- arch/arm/mach-pxa/cm-x300.c | 2 +- arch/arm/mach-pxa/colibri-pxa270.c | 2 +- arch/arm/mach-pxa/colibri-pxa300.c | 2 +- arch/arm/mach-pxa/colibri-pxa320.c | 2 +- arch/arm/mach-pxa/csb726.c | 2 +- arch/arm/mach-pxa/devices.c | 2 +- arch/arm/mach-pxa/eseries.c | 2 +- arch/arm/mach-pxa/include/mach/audio.h | 31 ------------------------------- arch/arm/mach-pxa/lpd270.c | 2 +- arch/arm/mach-pxa/lubbock.c | 2 +- arch/arm/mach-pxa/mainstone.c | 2 +- arch/arm/mach-pxa/mioa701.c | 2 +- arch/arm/mach-pxa/palm27x.c | 2 +- arch/arm/mach-pxa/palmld.c | 2 +- arch/arm/mach-pxa/palmt5.c | 2 +- arch/arm/mach-pxa/palmtc.c | 2 +- arch/arm/mach-pxa/palmte2.c | 2 +- arch/arm/mach-pxa/palmtreo.c | 2 +- arch/arm/mach-pxa/palmtx.c | 2 +- arch/arm/mach-pxa/palmz72.c | 2 +- arch/arm/mach-pxa/pcm990-baseboard.c | 2 +- arch/arm/mach-pxa/tosa.c | 2 +- arch/arm/mach-pxa/trizeps4.c | 2 +- arch/arm/mach-pxa/viper.c | 2 +- arch/arm/mach-pxa/vpac270.c | 2 +- arch/arm/mach-pxa/zeus.c | 2 +- arch/arm/mach-pxa/zylonite.c | 2 +- 28 files changed, 27 insertions(+), 58 deletions(-) delete mode 100644 arch/arm/mach-pxa/include/mach/audio.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index 26140249c784..82f9299f67d3 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -41,7 +41,7 @@ #include "pxa27x.h" #include -#include +#include #include #include #include "udc.h" diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 85e2537fdc15..09a5264a27c8 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -53,7 +53,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c index 2f2cd2ae4187..5dc669752836 100644 --- a/arch/arm/mach-pxa/colibri-pxa270.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c @@ -23,7 +23,7 @@ #include #include -#include +#include #include "colibri.h" #include "pxa27x.h" diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c index 4ceeea142bfd..11ca6c4795e7 100644 --- a/arch/arm/mach-pxa/colibri-pxa300.c +++ b/arch/arm/mach-pxa/colibri-pxa300.c @@ -24,7 +24,7 @@ #include "colibri.h" #include #include -#include +#include #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c index 35dd3adb7712..1a59056e181e 100644 --- a/arch/arm/mach-pxa/colibri-pxa320.c +++ b/arch/arm/mach-pxa/colibri-pxa320.c @@ -24,7 +24,7 @@ #include "colibri.h" #include #include -#include +#include #include "pxa27x-udc.h" #include "udc.h" diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index d48493445ae5..88f2f1d96c7b 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c @@ -22,7 +22,7 @@ #include "pxa27x.h" #include #include -#include +#include #include #include "generic.h" diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 7ca97ddef6fe..454523237c97 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index f37c44b6139d..a8b6483ff665 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -34,7 +34,7 @@ #include "pxa25x.h" #include #include "eseries-irq.h" -#include +#include #include #include "udc.h" #include diff --git a/arch/arm/mach-pxa/include/mach/audio.h b/arch/arm/mach-pxa/include/mach/audio.h deleted file mode 100644 index 7beebf7297b5..000000000000 --- a/arch/arm/mach-pxa/include/mach/audio.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARCH_AUDIO_H__ -#define __ASM_ARCH_AUDIO_H__ - -#include -#include -#include - -/* - * @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95) - * a -1 value means no gpio will be used for reset - * @codec_pdata: AC97 codec platform_data - - * reset_gpio should only be specified for pxa27x CPUs where a silicon - * bug prevents correct operation of the reset line. If not specified, - * the default behaviour on these CPUs is to consider gpio 113 as the - * AC97 reset line, which is the default on most boards. - */ -typedef struct { - int (*startup)(struct snd_pcm_substream *, void *); - void (*shutdown)(struct snd_pcm_substream *, void *); - void (*suspend)(void *); - void (*resume)(void *); - void *priv; - int reset_gpio; - void *codec_pdata[AC97_BUS_MAX_DEVICES]; -} pxa2xx_audio_ops_t; - -extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops); - -#endif diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index eac32bd9e385..7f10b86f85fd 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -39,7 +39,7 @@ #include "pxa27x.h" #include "lpd270.h" #include -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 72816e7c206f..46aef93c0615 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -45,7 +45,7 @@ #include #include "pxa25x.h" -#include +#include #include #include "udc.h" #include diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index cf74adfe65df..c8200fc2159d 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -45,7 +45,7 @@ #include "pxa27x.h" #include "mainstone.h" -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index a79f296e81e0..907cd7b5f58c 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -41,7 +41,7 @@ #include "udc.h" #include "pxa27x-udc.h" #include -#include +#include #include #include "mioa701.h" diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c index 6230381a7ca0..1a8d25eecac3 100644 --- a/arch/arm/mach-pxa/palm27x.c +++ b/arch/arm/mach-pxa/palm27x.c @@ -25,7 +25,7 @@ #include #include "pxa27x.h" -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index 5f73716a77f0..d85146957004 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -29,7 +29,7 @@ #include #include "pxa27x.h" -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 7c7cbb4e677e..460a8b1043a5 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c @@ -29,7 +29,7 @@ #include #include "pxa27x.h" -#include +#include #include "palmt5.h" #include #include diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index 455cb8ccaf26..c59fc76c0c3d 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -29,7 +29,7 @@ #include #include "pxa25x.h" -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index a2b10db4aacc..fedac670a8af 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -29,7 +29,7 @@ #include #include "pxa25x.h" -#include +#include #include "palmte2.h" #include #include diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index 2bf0f7f3ea24..d6d5b90d9578 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -29,7 +29,7 @@ #include "pxa27x.h" #include "pxa27x-udc.h" -#include +#include #include "palmtreo.h" #include #include diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index 07332c92c9f7..097b88638863 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -32,7 +32,7 @@ #include #include "pxa27x.h" -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index b4a5fe02a0af..66e8fe6f1661 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -34,7 +34,7 @@ #include #include "pxa27x.h" -#include +#include #include "palmz72.h" #include #include diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 8dfcc366d0fe..33a9d2eeca1c 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -26,7 +26,7 @@ #include #include "pxa27x.h" -#include +#include #include #include #include "pcm990_baseboard.h" diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 431709725d02..5af980d77d39 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -45,7 +45,7 @@ #include #include "udc.h" #include "tosa_bt.h" -#include +#include #include #include diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index f76f8be09554..1337008cc760 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -41,7 +41,7 @@ #include "pxa27x.h" #include -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 4b81c0117971..ac94b10bf8c1 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -46,7 +46,7 @@ #include #include "pxa25x.h" -#include +#include #include #include "regs-uart.h" #include diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index 14505e83479e..7067d1464689 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c @@ -29,7 +29,7 @@ #include #include "pxa27x.h" -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 5d02f10b5b5a..67396e85bb66 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -46,7 +46,7 @@ #include "udc.h" #include #include "pm.h" -#include +#include #include #include "zeus.h" #include diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 9bcb81688201..c48dd6d03df9 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -25,7 +25,7 @@ #include #include #include "pxa3xx.h" -#include +#include #include #include "zylonite.h" #include -- cgit From ee84cbd5df2beaf14e8af0955f1ab15ad3f81504 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 2 Sep 2019 00:15:44 +0200 Subject: ARM: pxa: move regs-lcd.h into driver Only the pxafb driver uses this header, so move it into the same directory. The SMART_* macros are required by some platform data definitions and can go into the linux/platform_data/video-pxafb.h header. Acked-by: Bartlomiej Zolnierkiewicz Acked-by: Robert Jarzmik Cc: dri-devel@lists.freedesktop.org Cc: linux-fbdev@vger.kernel.org Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/include/mach/regs-lcd.h | 199 ------------------------------ 1 file changed, 199 deletions(-) delete mode 100644 arch/arm/mach-pxa/include/mach/regs-lcd.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h deleted file mode 100644 index 6a434675f84a..000000000000 --- a/arch/arm/mach-pxa/include/mach/regs-lcd.h +++ /dev/null @@ -1,199 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARCH_REGS_LCD_H -#define __ASM_ARCH_REGS_LCD_H - -/* - * LCD Controller Registers and Bits Definitions - */ -#define LCCR0 (0x000) /* LCD Controller Control Register 0 */ -#define LCCR1 (0x004) /* LCD Controller Control Register 1 */ -#define LCCR2 (0x008) /* LCD Controller Control Register 2 */ -#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ -#define LCCR4 (0x010) /* LCD Controller Control Register 4 */ -#define LCCR5 (0x014) /* LCD Controller Control Register 5 */ -#define LCSR (0x038) /* LCD Controller Status Register 0 */ -#define LCSR1 (0x034) /* LCD Controller Status Register 1 */ -#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ -#define TMEDRGBR (0x040) /* TMED RGB Seed Register */ -#define TMEDCR (0x044) /* TMED Control Register */ - -#define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ -#define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ -#define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */ -#define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */ -#define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */ -#define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ -#define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ - -#define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */ -#define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */ -#define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */ -#define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */ - -#define CMDCR (0x100) /* Command Control Register */ -#define PRSR (0x104) /* Panel Read Status Register */ - -#define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0)) - -#define LCCR3_PDFOR_0 (0 << 30) -#define LCCR3_PDFOR_1 (1 << 30) -#define LCCR3_PDFOR_2 (2 << 30) -#define LCCR3_PDFOR_3 (3 << 30) - -#define LCCR4_PAL_FOR_0 (0 << 15) -#define LCCR4_PAL_FOR_1 (1 << 15) -#define LCCR4_PAL_FOR_2 (2 << 15) -#define LCCR4_PAL_FOR_3 (3 << 15) -#define LCCR4_PAL_FOR_MASK (3 << 15) - -#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ -#define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ -#define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */ -#define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */ -#define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */ -#define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */ -#define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ - -#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ -#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ -#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ -#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ -#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display Select */ -#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ -#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ - -#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ -#define LCCR0_SFM (1 << 4) /* Start of frame mask */ -#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ -#define LCCR0_EFM (1 << 6) /* End of Frame mask */ -#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */ -#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ -#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ -#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */ -#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */ -#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */ -#define LCCR0_DIS (1 << 10) /* LCD Disable */ -#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ -#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ -#define LCCR0_PDD_S 12 -#define LCCR0_BM (1 << 20) /* Branch mask */ -#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ -#define LCCR0_LCDT (1 << 22) /* LCD panel type */ -#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ -#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */ -#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */ -#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */ - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) -#define FShft(Field) ((Field) & 0x0000FFFF) - -#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ -#define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) - -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ -#define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW)) - -#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */ -#define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW)) - -#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ -#define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW)) - -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ -#define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP)) - -#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */ -#define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW)) - -#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ -#define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW)) - -#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ -#define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW)) - -#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ -#define LCCR3_API_S 16 -#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ -#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ -#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */ -#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ -#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ - -#define LCCR3_OEP (1 << 23) /* Output Enable Polarity */ -#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ -#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ - -#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ -#define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD))) - -#define LCCR3_ACB Fld (8, 8) /* AC Bias */ -#define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB))) - -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */ - -#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */ -#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */ - -#define LCCR5_IUM(x) (1 << ((x) + 23)) /* input underrun mask */ -#define LCCR5_BSM(x) (1 << ((x) + 15)) /* branch mask */ -#define LCCR5_EOFM(x) (1 << ((x) + 7)) /* end of frame mask */ -#define LCCR5_SOFM(x) (1 << ((x) + 0)) /* start of frame mask */ - -#define LCSR_LDD (1 << 0) /* LCD Disable Done */ -#define LCSR_SOF (1 << 1) /* Start of frame */ -#define LCSR_BER (1 << 2) /* Bus error */ -#define LCSR_ABC (1 << 3) /* AC Bias count */ -#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ -#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ -#define LCSR_OU (1 << 6) /* output FIFO underrun */ -#define LCSR_QD (1 << 7) /* quick disable */ -#define LCSR_EOF (1 << 8) /* end of frame */ -#define LCSR_BS (1 << 9) /* branch status */ -#define LCSR_SINT (1 << 10) /* subsequent interrupt */ -#define LCSR_RD_ST (1 << 11) /* read status */ -#define LCSR_CMD_INT (1 << 12) /* command interrupt */ - -#define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */ -#define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */ -#define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */ -#define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */ - -#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ - -/* overlay control registers */ -#define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */ -#define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */ -#define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */ -#define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */ -#define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */ -#define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */ -#define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */ - -/* smartpanel related */ -#define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ -#define PRSR_A0 (1 << 8) /* Read Data Source */ -#define PRSR_ST_OK (1 << 9) /* Status OK */ -#define PRSR_CON_NT (1 << 10) /* Continue to Next Command */ - -#define SMART_CMD_A0 (0x1 << 8) -#define SMART_CMD_READ_STATUS_REG (0x0 << 9) -#define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0) -#define SMART_CMD_WRITE_COMMAND (0x1 << 9) -#define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0) -#define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0) -#define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9) -#define SMART_CMD_NOOP (0x4 << 9) -#define SMART_CMD_INTERRUPT (0x5 << 9) - -#define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) -#define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) - -/* SMART_DELAY() is introduced for software controlled delay primitive which - * can be inserted between command sequences, unused command 0x6 is used here - * and delay ranges from 0ms ~ 255ms - */ -#define SMART_CMD_DELAY (0x6 << 9) -#define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff)) -#endif /* __ASM_ARCH_REGS_LCD_H */ -- cgit From e86bd43bcfc579cf8935c1913e92cb76b4ba81c2 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 8 Sep 2019 22:33:51 +0200 Subject: watchdog: sa1100: use platform device registration Rather than relying on machine specific headers to pass down the reboot status and the register locations, use resources and platform_data. Aside from this, keep the changes to a minimum. Cc: Wim Van Sebroeck Cc: linux-watchdog@vger.kernel.org Acked-by: Guenter Roeck Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/devices.c | 11 +++++++++++ arch/arm/mach-pxa/include/mach/regs-ost.h | 2 ++ arch/arm/mach-pxa/include/mach/reset.h | 2 +- arch/arm/mach-pxa/pxa25x.c | 2 +- arch/arm/mach-pxa/pxa27x.c | 2 +- arch/arm/mach-pxa/pxa3xx.c | 2 +- arch/arm/mach-pxa/reset.c | 3 --- arch/arm/mach-sa1100/generic.c | 6 +++--- arch/arm/mach-sa1100/include/mach/reset.h | 1 - 9 files changed, 20 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 454523237c97..12f78636045f 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -24,6 +24,8 @@ #include #include +#include +#include #include "devices.h" #include "generic.h" @@ -1118,3 +1120,12 @@ void __init pxa2xx_set_dmac_info(struct mmp_dma_platdata *dma_pdata) { pxa_register_device(&pxa2xx_pxa_dma, dma_pdata); } + +void __init pxa_register_wdt(unsigned int reset_status) +{ + struct resource res = DEFINE_RES_MEM(OST_PHYS, OST_LEN); + + reset_status &= RESET_STATUS_WATCHDOG; + platform_device_register_resndata(NULL, "sa1100_wdt", -1, &res, 1, + &reset_status, sizeof(reset_status)); +} diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h index 109d0ed264df..c8001cfc8d6b 100644 --- a/arch/arm/mach-pxa/include/mach/regs-ost.h +++ b/arch/arm/mach-pxa/include/mach/regs-ost.h @@ -7,6 +7,8 @@ /* * OS Timer & Match Registers */ +#define OST_PHYS 0x40A00000 +#define OST_LEN 0x00000020 #define OSMR0 io_p2v(0x40A00000) /* */ #define OSMR1 io_p2v(0x40A00004) /* */ diff --git a/arch/arm/mach-pxa/include/mach/reset.h b/arch/arm/mach-pxa/include/mach/reset.h index e1c4d100fd45..963dd190bc13 100644 --- a/arch/arm/mach-pxa/include/mach/reset.h +++ b/arch/arm/mach-pxa/include/mach/reset.h @@ -8,8 +8,8 @@ #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ #define RESET_STATUS_ALL (0xf) -extern unsigned int reset_status; extern void clear_reset_status(unsigned int mask); +extern void pxa_register_wdt(unsigned int reset_status); /** * init_gpio_reset() - register GPIO as reset generator diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 305047ebd2f1..dfc90b41fba3 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -240,7 +240,7 @@ static int __init pxa25x_init(void) if (cpu_is_pxa25x()) { - reset_status = RCSR; + pxa_register_wdt(RCSR); pxa25x_init_pm(); diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index a81ac88ecbfd..38fdd22c4dc5 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -337,7 +337,7 @@ static int __init pxa27x_init(void) if (cpu_is_pxa27x()) { - reset_status = RCSR; + pxa_register_wdt(RCSR); pxa27x_init_pm(); diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index fc84aed99481..7c569fa2a6da 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -463,7 +463,7 @@ static int __init pxa3xx_init(void) if (cpu_is_pxa3xx()) { - reset_status = ARSR; + pxa_register_wdt(ARSR); /* * clear RDH bit every time after reset diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c index af78405aa4e9..fcb791c5ae3e 100644 --- a/arch/arm/mach-pxa/reset.c +++ b/arch/arm/mach-pxa/reset.c @@ -11,9 +11,6 @@ #include #include -unsigned int reset_status; -EXPORT_SYMBOL(reset_status); - static void do_hw_reset(void); static int reset_gpio = -1; diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 4dfb7554649d..6c21f214cd60 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -39,9 +39,6 @@ #include "generic.h" #include -unsigned int reset_status; -EXPORT_SYMBOL(reset_status); - #define NR_FREQS 16 /* @@ -319,10 +316,13 @@ static struct platform_device *sa11x0_devices[] __initdata = { static int __init sa1100_init(void) { + struct resource wdt_res = DEFINE_RES_MEM(0x90000000, 0x20); pm_power_off = sa1100_power_off; regulator_has_full_constraints(); + platform_device_register_simple("sa1100_wdt", -1, &wdt_res, 1); + return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices)); } diff --git a/arch/arm/mach-sa1100/include/mach/reset.h b/arch/arm/mach-sa1100/include/mach/reset.h index 27695650a567..a6723d45ae2a 100644 --- a/arch/arm/mach-sa1100/include/mach/reset.h +++ b/arch/arm/mach-sa1100/include/mach/reset.h @@ -10,7 +10,6 @@ #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ #define RESET_STATUS_ALL (0xf) -extern unsigned int reset_status; static inline void clear_reset_status(unsigned int mask) { RCSR = mask; -- cgit From 2548e6c76ebfae09f25f941ae172535cc918c906 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 10 Sep 2019 15:23:52 +0200 Subject: ARM: pxa: pxa2xx-ac97-lib: use IRQ resource The pxa2xx-ac97-lib code is the last driver to use mach/irqs.h for PXA. Almost everything already passes the interrupt as a resource, so use it from there. The one exception is the mxm8x10 machine, which apparently has a resource-less device. Replacing it with the correct one enables the driver here as well. Cc: alsa-devel@alsa-project.org Acked-by: Robert Jarzmik Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/mxm8x10.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c index fde386f6cffe..35546b59c88e 100644 --- a/arch/arm/mach-pxa/mxm8x10.c +++ b/arch/arm/mach-pxa/mxm8x10.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "pxa320.h" #include "mxm8x10.h" @@ -356,14 +357,9 @@ void __init mxm_8x10_usb_host_init(void) pxa_set_ohci_info(&mxm_8x10_ohci_platform_data); } -/* AC97 Sound Support */ -static struct platform_device mxm_8x10_ac97_device = { - .name = "pxa2xx-ac97" -}; - void __init mxm_8x10_ac97_init(void) { - platform_device_register(&mxm_8x10_ac97_device); + pxa_set_ac97_info(NULL); } /* NAND flash Support */ -- cgit From b83deaa741558babf4b8d51d34f6637ccfff1b26 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 28 May 2020 22:57:40 +0200 Subject: ARM: pxa: move pcmcia board data into mach-pxa The drivers/pcmcia/pxa2xx_*.c are essentially part of the board files, but for historic reasons located in drivers/pcmcia. Move them into the same place as the actual board file to avoid lots of machine header inclusions. Cc: Marek Vasut Cc: Dominik Brodowski Cc: Jonathan Cameron Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/Makefile | 18 +-- arch/arm/mach-pxa/balloon3-pcmcia.c | 137 ++++++++++++++++++++ arch/arm/mach-pxa/balloon3.c | 2 +- arch/arm/mach-pxa/balloon3.h | 181 +++++++++++++++++++++++++++ arch/arm/mach-pxa/colibri-pcmcia.c | 165 ++++++++++++++++++++++++ arch/arm/mach-pxa/e740-pcmcia.c | 127 +++++++++++++++++++ arch/arm/mach-pxa/hx4700-pcmcia.c | 118 ++++++++++++++++++ arch/arm/mach-pxa/include/mach/balloon3.h | 181 --------------------------- arch/arm/mach-pxa/include/mach/palmtc.h | 84 ------------- arch/arm/mach-pxa/include/mach/palmtx.h | 110 ---------------- arch/arm/mach-pxa/include/mach/trizeps4.h | 166 ------------------------- arch/arm/mach-pxa/include/mach/vpac270.h | 38 ------ arch/arm/mach-pxa/palmld-pcmcia.c | 110 ++++++++++++++++ arch/arm/mach-pxa/palmtc-pcmcia.c | 162 ++++++++++++++++++++++++ arch/arm/mach-pxa/palmtc.c | 2 +- arch/arm/mach-pxa/palmtc.h | 84 +++++++++++++ arch/arm/mach-pxa/palmtx-pcmcia.c | 111 +++++++++++++++++ arch/arm/mach-pxa/palmtx.c | 2 +- arch/arm/mach-pxa/palmtx.h | 110 ++++++++++++++++ arch/arm/mach-pxa/trizeps4-pcmcia.c | 200 ++++++++++++++++++++++++++++++ arch/arm/mach-pxa/trizeps4.c | 2 +- arch/arm/mach-pxa/trizeps4.h | 166 +++++++++++++++++++++++++ arch/arm/mach-pxa/viper-pcmcia.c | 180 +++++++++++++++++++++++++++ arch/arm/mach-pxa/viper-pcmcia.h | 12 ++ arch/arm/mach-pxa/viper.c | 2 +- arch/arm/mach-pxa/vpac270-pcmcia.c | 137 ++++++++++++++++++++ arch/arm/mach-pxa/vpac270.c | 2 +- arch/arm/mach-pxa/vpac270.h | 38 ++++++ arch/arm/mach-pxa/zeus.c | 2 +- 29 files changed, 2056 insertions(+), 593 deletions(-) create mode 100644 arch/arm/mach-pxa/balloon3-pcmcia.c create mode 100644 arch/arm/mach-pxa/balloon3.h create mode 100644 arch/arm/mach-pxa/colibri-pcmcia.c create mode 100644 arch/arm/mach-pxa/e740-pcmcia.c create mode 100644 arch/arm/mach-pxa/hx4700-pcmcia.c delete mode 100644 arch/arm/mach-pxa/include/mach/balloon3.h delete mode 100644 arch/arm/mach-pxa/include/mach/palmtc.h delete mode 100644 arch/arm/mach-pxa/include/mach/palmtx.h delete mode 100644 arch/arm/mach-pxa/include/mach/trizeps4.h delete mode 100644 arch/arm/mach-pxa/include/mach/vpac270.h create mode 100644 arch/arm/mach-pxa/palmld-pcmcia.c create mode 100644 arch/arm/mach-pxa/palmtc-pcmcia.c create mode 100644 arch/arm/mach-pxa/palmtc.h create mode 100644 arch/arm/mach-pxa/palmtx-pcmcia.c create mode 100644 arch/arm/mach-pxa/palmtx.h create mode 100644 arch/arm/mach-pxa/trizeps4-pcmcia.c create mode 100644 arch/arm/mach-pxa/trizeps4.h create mode 100644 arch/arm/mach-pxa/viper-pcmcia.c create mode 100644 arch/arm/mach-pxa/viper-pcmcia.h create mode 100644 arch/arm/mach-pxa/vpac270-pcmcia.c create mode 100644 arch/arm/mach-pxa/vpac270.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 68730ceb8b7c..0aec36e67dc1 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -37,7 +37,8 @@ obj-$(CONFIG_MACH_SAAR) += saar.o obj-$(CONFIG_ARCH_PXA_IDP) += idp.o obj-$(CONFIG_ARCH_VIPER) += viper.o obj-$(CONFIG_MACH_ARCOM_ZEUS) += zeus.o -obj-$(CONFIG_MACH_BALLOON3) += balloon3.o +obj-$(CONFIG_ARCOM_PCMCIA) += viper-pcmcia.o +obj-$(CONFIG_MACH_BALLOON3) += balloon3.o balloon3-pcmcia.o obj-$(CONFIG_MACH_CSB726) += csb726.o obj-$(CONFIG_CSB726_CSB701) += csb701.o obj-$(CONFIG_MACH_CM_X300) += cm-x300.o @@ -47,18 +48,20 @@ obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o obj-$(CONFIG_MACH_XCEP) += xcep.o obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o +obj-$(CONFIG_TRIZEPS_PCMCIA) += trizeps4-pcmcia.o obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o obj-$(CONFIG_MACH_PCM027) += pcm027.o obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o -obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o +obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o colibri-pcmcia.o obj-$(CONFIG_MACH_COLIBRI_EVALBOARD) += colibri-evalboard.o obj-$(CONFIG_MACH_COLIBRI_PXA270_INCOME) += colibri-pxa270-income.o obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o -obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o -obj-$(CONFIG_MACH_VPAC270) += vpac270.o +obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o colibri-pcmcia.o +obj-$(CONFIG_MACH_VPAC270) += vpac270.o vpac270-pcmcia.o # End-user Products obj-$(CONFIG_MACH_H4700) += hx4700.o +obj-$(CONFIG_MACH_H4700) += hx4700-pcmcia.o obj-$(CONFIG_MACH_H5000) += h5000.o obj-$(CONFIG_MACH_HIMALAYA) += himalaya.o obj-$(CONFIG_MACH_MAGICIAN) += magician.o @@ -66,12 +69,12 @@ obj-$(CONFIG_MACH_MIOA701) += mioa701.o mioa701_bootresume.o obj-$(CONFIG_PXA_EZX) += ezx.o obj-$(CONFIG_MACH_MP900C) += mp900.o obj-$(CONFIG_MACH_PALMTE2) += palmte2.o -obj-$(CONFIG_MACH_PALMTC) += palmtc.o +obj-$(CONFIG_MACH_PALMTC) += palmtc.o palmtc-pcmcia.o obj-$(CONFIG_MACH_PALM27X) += palm27x.o obj-$(CONFIG_MACH_PALMT5) += palmt5.o -obj-$(CONFIG_MACH_PALMTX) += palmtx.o +obj-$(CONFIG_MACH_PALMTX) += palmtx.o palmtx-pcmcia.o obj-$(CONFIG_MACH_PALMZ72) += palmz72.o -obj-$(CONFIG_MACH_PALMLD) += palmld.o +obj-$(CONFIG_MACH_PALMLD) += palmld.o palmld-pcmcia.o obj-$(CONFIG_PALM_TREO) += palmtreo.o obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o @@ -79,6 +82,7 @@ obj-$(CONFIG_MACH_POODLE) += poodle.o obj-$(CONFIG_MACH_TOSA) += tosa.o obj-$(CONFIG_MACH_ICONTROL) += icontrol.o mxm8x10.o obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o +obj-$(CONFIG_MACH_E740) += e740-pcmcia.o obj-$(CONFIG_MACH_ZIPIT2) += z2.o obj-$(CONFIG_PXA_SYSTEMS_CPLDS) += pxa_cplds_irqs.o diff --git a/arch/arm/mach-pxa/balloon3-pcmcia.c b/arch/arm/mach-pxa/balloon3-pcmcia.c new file mode 100644 index 000000000000..6a27b76cc603 --- /dev/null +++ b/arch/arm/mach-pxa/balloon3-pcmcia.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/drivers/pcmcia/pxa2xx_balloon3.c + * + * Balloon3 PCMCIA specific routines. + * + * Author: Nick Bane + * Created: June, 2006 + * Copyright: Toby Churchill Ltd + * Derived from pxa2xx_mainstone.c, by Nico Pitre + * + * Various modification by Marek Vasut + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "balloon3.h" + +#include + +#include + +static int balloon3_pcmcia_hw_init(struct soc_pcmcia_socket *skt) +{ + uint16_t ver; + + ver = __raw_readw(BALLOON3_FPGA_VER); + if (ver < 0x4f08) + pr_warn("The FPGA code, version 0x%04x, is too old. " + "PCMCIA/CF support might be broken in this version!", + ver); + + skt->socket.pci_irq = BALLOON3_BP_CF_NRDY_IRQ; + skt->stat[SOC_STAT_CD].gpio = BALLOON3_GPIO_S0_CD; + skt->stat[SOC_STAT_CD].name = "PCMCIA0 CD"; + skt->stat[SOC_STAT_BVD1].irq = BALLOON3_BP_NSTSCHG_IRQ; + skt->stat[SOC_STAT_BVD1].name = "PCMCIA0 STSCHG"; + + return 0; +} + +static unsigned long balloon3_pcmcia_status[2] = { + BALLOON3_CF_nSTSCHG_BVD1, + BALLOON3_CF_nSTSCHG_BVD1 +}; + +static void balloon3_pcmcia_socket_state(struct soc_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + uint16_t status; + int flip; + + /* This actually reads the STATUS register */ + status = __raw_readw(BALLOON3_CF_STATUS_REG); + flip = (status ^ balloon3_pcmcia_status[skt->nr]) + & BALLOON3_CF_nSTSCHG_BVD1; + /* + * Workaround for STSCHG which can't be deasserted: + * We therefore disable/enable corresponding IRQs + * as needed to avoid IRQ locks. + */ + if (flip) { + balloon3_pcmcia_status[skt->nr] = status; + if (status & BALLOON3_CF_nSTSCHG_BVD1) + enable_irq(BALLOON3_BP_NSTSCHG_IRQ); + else + disable_irq(BALLOON3_BP_NSTSCHG_IRQ); + } + + state->ready = !!(status & BALLOON3_CF_nIRQ); + state->bvd1 = !!(status & BALLOON3_CF_nSTSCHG_BVD1); + state->bvd2 = 0; /* not available */ + state->vs_3v = 1; /* Always true its a CF card */ + state->vs_Xv = 0; /* not available */ +} + +static int balloon3_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, + const socket_state_t *state) +{ + __raw_writew(BALLOON3_CF_RESET, BALLOON3_CF_CONTROL_REG + + ((state->flags & SS_RESET) ? + BALLOON3_FPGA_SETnCLR : 0)); + return 0; +} + +static struct pcmcia_low_level balloon3_pcmcia_ops = { + .owner = THIS_MODULE, + .hw_init = balloon3_pcmcia_hw_init, + .socket_state = balloon3_pcmcia_socket_state, + .configure_socket = balloon3_pcmcia_configure_socket, + .first = 0, + .nr = 1, +}; + +static struct platform_device *balloon3_pcmcia_device; + +static int __init balloon3_pcmcia_init(void) +{ + int ret; + + if (!machine_is_balloon3()) + return -ENODEV; + + balloon3_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); + if (!balloon3_pcmcia_device) + return -ENOMEM; + + ret = platform_device_add_data(balloon3_pcmcia_device, + &balloon3_pcmcia_ops, sizeof(balloon3_pcmcia_ops)); + + if (!ret) + ret = platform_device_add(balloon3_pcmcia_device); + + if (ret) + platform_device_put(balloon3_pcmcia_device); + + return ret; +} + +static void __exit balloon3_pcmcia_exit(void) +{ + platform_device_unregister(balloon3_pcmcia_device); +} + +module_init(balloon3_pcmcia_init); +module_exit(balloon3_pcmcia_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nick Bane "); +MODULE_ALIAS("platform:pxa2xx-pcmcia"); +MODULE_DESCRIPTION("Balloon3 board CF/PCMCIA driver"); diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index 82f9299f67d3..896d47d9a8dc 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -40,7 +40,7 @@ #include #include "pxa27x.h" -#include +#include "balloon3.h" #include #include #include diff --git a/arch/arm/mach-pxa/balloon3.h b/arch/arm/mach-pxa/balloon3.h new file mode 100644 index 000000000000..f351358c0e5b --- /dev/null +++ b/arch/arm/mach-pxa/balloon3.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/include/asm-arm/arch-pxa/balloon3.h + * + * Authors: Nick Bane and Wookey + * Created: Oct, 2005 + * Copyright: Toby Churchill Ltd + * Cribbed from mainstone.c, by Nicholas Pitre + */ + +#ifndef ASM_ARCH_BALLOON3_H +#define ASM_ARCH_BALLOON3_H + +#include /* PXA_NR_BUILTIN_GPIO */ + +enum balloon3_features { + BALLOON3_FEATURE_OHCI, + BALLOON3_FEATURE_MMC, + BALLOON3_FEATURE_CF, + BALLOON3_FEATURE_AUDIO, + BALLOON3_FEATURE_TOPPOLY, +}; + +#define BALLOON3_FPGA_PHYS PXA_CS4_PHYS +#define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */ +#define BALLOON3_FPGA_LENGTH 0x01000000 + +#define BALLOON3_FPGA_SETnCLR (0x1000) + +/* FPGA / CPLD registers for CF socket */ +#define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008) +#define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008) +/* FPGA / CPLD version register */ +#define BALLOON3_FPGA_VER (BALLOON3_FPGA_VIRT + 0x00e0001c) +/* FPGA / CPLD registers for NAND flash */ +#define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000) +#define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000) +#define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010) +#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00014) +#define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014) + +/* fpga/cpld interrupt control register */ +#define BALLOON3_INT_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e0000C) +#define BALLOON3_VERSION_REG (BALLOON3_FPGA_VIRT + 0x00e0001c) + +#define BALLOON3_SAMOSA_ADDR_REG (BALLOON3_FPGA_VIRT + 0x00c00000) +#define BALLOON3_SAMOSA_DATA_REG (BALLOON3_FPGA_VIRT + 0x00c00004) +#define BALLOON3_SAMOSA_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00c0001c) + +/* CF Status Register bits (read-only) bits */ +#define BALLOON3_CF_nIRQ (1 << 0) +#define BALLOON3_CF_nSTSCHG_BVD1 (1 << 1) + +/* CF Control Set Register bits / CF Control Clear Register bits (write-only) */ +#define BALLOON3_CF_RESET (1 << 0) +#define BALLOON3_CF_ENABLE (1 << 1) +#define BALLOON3_CF_ADD_ENABLE (1 << 2) + +/* CF Interrupt sources */ +#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0) +#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1) + +/* NAND Control register */ +#define BALLOON3_NAND_CONTROL_FLWP (1 << 7) +#define BALLOON3_NAND_CONTROL_FLSE (1 << 6) +#define BALLOON3_NAND_CONTROL_FLCE3 (1 << 5) +#define BALLOON3_NAND_CONTROL_FLCE2 (1 << 4) +#define BALLOON3_NAND_CONTROL_FLCE1 (1 << 3) +#define BALLOON3_NAND_CONTROL_FLCE0 (1 << 2) +#define BALLOON3_NAND_CONTROL_FLALE (1 << 1) +#define BALLOON3_NAND_CONTROL_FLCLE (1 << 0) + +/* NAND Status register */ +#define BALLOON3_NAND_STAT_RNB (1 << 0) + +/* NAND Control2 register */ +#define BALLOON3_NAND_CONTROL2_16BIT (1 << 0) + +/* GPIOs for irqs */ +#define BALLOON3_GPIO_AUX_NIRQ (94) +#define BALLOON3_GPIO_CODEC_IRQ (95) + +/* Timer and Idle LED locations */ +#define BALLOON3_GPIO_LED_NAND (9) +#define BALLOON3_GPIO_LED_IDLE (10) + +/* backlight control */ +#define BALLOON3_GPIO_RUN_BACKLIGHT (99) + +#define BALLOON3_GPIO_S0_CD (105) + +/* NAND */ +#define BALLOON3_GPIO_RUN_NAND (102) + +/* PCF8574A Leds */ +#define BALLOON3_PCF_GPIO_BASE 160 +#define BALLOON3_PCF_GPIO_LED0 (BALLOON3_PCF_GPIO_BASE + 0) +#define BALLOON3_PCF_GPIO_LED1 (BALLOON3_PCF_GPIO_BASE + 1) +#define BALLOON3_PCF_GPIO_LED2 (BALLOON3_PCF_GPIO_BASE + 2) +#define BALLOON3_PCF_GPIO_LED3 (BALLOON3_PCF_GPIO_BASE + 3) +#define BALLOON3_PCF_GPIO_LED4 (BALLOON3_PCF_GPIO_BASE + 4) +#define BALLOON3_PCF_GPIO_LED5 (BALLOON3_PCF_GPIO_BASE + 5) +#define BALLOON3_PCF_GPIO_LED6 (BALLOON3_PCF_GPIO_BASE + 6) +#define BALLOON3_PCF_GPIO_LED7 (BALLOON3_PCF_GPIO_BASE + 7) + +/* FPGA Interrupt Mask/Acknowledge Register */ +#define BALLOON3_INT_S0_IRQ (1 << 0) /* PCMCIA 0 IRQ */ +#define BALLOON3_INT_S0_STSCHG (1 << 1) /* PCMCIA 0 status changed */ + +/* CPLD (and FPGA) interface definitions */ +#define CPLD_LCD0_DATA_SET 0x00 +#define CPLD_LCD0_DATA_CLR 0x10 +#define CPLD_LCD0_COMMAND_SET 0x01 +#define CPLD_LCD0_COMMAND_CLR 0x11 +#define CPLD_LCD1_DATA_SET 0x02 +#define CPLD_LCD1_DATA_CLR 0x12 +#define CPLD_LCD1_COMMAND_SET 0x03 +#define CPLD_LCD1_COMMAND_CLR 0x13 + +#define CPLD_MISC_SET 0x07 +#define CPLD_MISC_CLR 0x17 +#define CPLD_MISC_LOON_NRESET_BIT 0 +#define CPLD_MISC_LOON_UNSUSP_BIT 1 +#define CPLD_MISC_RUN_5V_BIT 2 +#define CPLD_MISC_CHG_D0_BIT 3 +#define CPLD_MISC_CHG_D1_BIT 4 +#define CPLD_MISC_DAC_NCS_BIT 5 + +#define CPLD_LCD_SET 0x08 +#define CPLD_LCD_CLR 0x18 +#define CPLD_LCD_BACKLIGHT_EN_0_BIT 0 +#define CPLD_LCD_BACKLIGHT_EN_1_BIT 1 +#define CPLD_LCD_LED_RED_BIT 4 +#define CPLD_LCD_LED_GREEN_BIT 5 +#define CPLD_LCD_NRESET_BIT 7 + +#define CPLD_LCD_RO_SET 0x09 +#define CPLD_LCD_RO_CLR 0x19 +#define CPLD_LCD_RO_LCD0_nWAIT_BIT 0 +#define CPLD_LCD_RO_LCD1_nWAIT_BIT 1 + +#define CPLD_SERIAL_SET 0x0a +#define CPLD_SERIAL_CLR 0x1a +#define CPLD_SERIAL_GSM_RI_BIT 0 +#define CPLD_SERIAL_GSM_CTS_BIT 1 +#define CPLD_SERIAL_GSM_DTR_BIT 2 +#define CPLD_SERIAL_LPR_CTS_BIT 3 +#define CPLD_SERIAL_TC232_CTS_BIT 4 +#define CPLD_SERIAL_TC232_DSR_BIT 5 + +#define CPLD_SROUTING_SET 0x0b +#define CPLD_SROUTING_CLR 0x1b +#define CPLD_SROUTING_MSP430_LPR 0 +#define CPLD_SROUTING_MSP430_TC232 1 +#define CPLD_SROUTING_MSP430_GSM 2 +#define CPLD_SROUTING_LOON_LPR (0 << 4) +#define CPLD_SROUTING_LOON_TC232 (1 << 4) +#define CPLD_SROUTING_LOON_GSM (2 << 4) + +#define CPLD_AROUTING_SET 0x0c +#define CPLD_AROUTING_CLR 0x1c +#define CPLD_AROUTING_MIC2PHONE_BIT 0 +#define CPLD_AROUTING_PHONE2INT_BIT 1 +#define CPLD_AROUTING_PHONE2EXT_BIT 2 +#define CPLD_AROUTING_LOONL2INT_BIT 3 +#define CPLD_AROUTING_LOONL2EXT_BIT 4 +#define CPLD_AROUTING_LOONR2PHONE_BIT 5 +#define CPLD_AROUTING_LOONR2INT_BIT 6 +#define CPLD_AROUTING_LOONR2EXT_BIT 7 + +/* Balloon3 Interrupts */ +#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x)) + +#define BALLOON3_AUX_NIRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ) +#define BALLOON3_CODEC_IRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ) + +#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16) + +extern int balloon3_has(enum balloon3_features feature); + +#endif diff --git a/arch/arm/mach-pxa/colibri-pcmcia.c b/arch/arm/mach-pxa/colibri-pcmcia.c new file mode 100644 index 000000000000..9da7b478e5eb --- /dev/null +++ b/arch/arm/mach-pxa/colibri-pcmcia.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/drivers/pcmcia/pxa2xx_colibri.c + * + * Driver for Toradex Colibri PXA270 CF socket + * + * Copyright (C) 2010 Marek Vasut + */ + +#include +#include +#include +#include + +#include + +#include + +#define COLIBRI270_RESET_GPIO 53 +#define COLIBRI270_PPEN_GPIO 107 +#define COLIBRI270_BVD1_GPIO 83 +#define COLIBRI270_BVD2_GPIO 82 +#define COLIBRI270_DETECT_GPIO 84 +#define COLIBRI270_READY_GPIO 1 + +#define COLIBRI320_RESET_GPIO 77 +#define COLIBRI320_PPEN_GPIO 57 +#define COLIBRI320_BVD1_GPIO 53 +#define COLIBRI320_BVD2_GPIO 79 +#define COLIBRI320_DETECT_GPIO 81 +#define COLIBRI320_READY_GPIO 29 + +enum { + DETECT = 0, + READY = 1, + BVD1 = 2, + BVD2 = 3, + PPEN = 4, + RESET = 5, +}; + +/* Contents of this array are configured on-the-fly in init function */ +static struct gpio colibri_pcmcia_gpios[] = { + { 0, GPIOF_IN, "PCMCIA Detect" }, + { 0, GPIOF_IN, "PCMCIA Ready" }, + { 0, GPIOF_IN, "PCMCIA BVD1" }, + { 0, GPIOF_IN, "PCMCIA BVD2" }, + { 0, GPIOF_INIT_LOW, "PCMCIA PPEN" }, + { 0, GPIOF_INIT_HIGH,"PCMCIA Reset" }, +}; + +static int colibri_pcmcia_hw_init(struct soc_pcmcia_socket *skt) +{ + int ret; + + ret = gpio_request_array(colibri_pcmcia_gpios, + ARRAY_SIZE(colibri_pcmcia_gpios)); + if (ret) + goto err1; + + skt->socket.pci_irq = gpio_to_irq(colibri_pcmcia_gpios[READY].gpio); + skt->stat[SOC_STAT_CD].irq = gpio_to_irq(colibri_pcmcia_gpios[DETECT].gpio); + skt->stat[SOC_STAT_CD].name = "PCMCIA CD"; + +err1: + return ret; +} + +static void colibri_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) +{ + gpio_free_array(colibri_pcmcia_gpios, + ARRAY_SIZE(colibri_pcmcia_gpios)); +} + +static void colibri_pcmcia_socket_state(struct soc_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + + state->detect = !!gpio_get_value(colibri_pcmcia_gpios[DETECT].gpio); + state->ready = !!gpio_get_value(colibri_pcmcia_gpios[READY].gpio); + state->bvd1 = !!gpio_get_value(colibri_pcmcia_gpios[BVD1].gpio); + state->bvd2 = !!gpio_get_value(colibri_pcmcia_gpios[BVD2].gpio); + state->vs_3v = 1; + state->vs_Xv = 0; +} + +static int +colibri_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, + const socket_state_t *state) +{ + gpio_set_value(colibri_pcmcia_gpios[PPEN].gpio, + !(state->Vcc == 33 && state->Vpp < 50)); + gpio_set_value(colibri_pcmcia_gpios[RESET].gpio, + state->flags & SS_RESET); + return 0; +} + +static struct pcmcia_low_level colibri_pcmcia_ops = { + .owner = THIS_MODULE, + + .first = 0, + .nr = 1, + + .hw_init = colibri_pcmcia_hw_init, + .hw_shutdown = colibri_pcmcia_hw_shutdown, + + .socket_state = colibri_pcmcia_socket_state, + .configure_socket = colibri_pcmcia_configure_socket, +}; + +static struct platform_device *colibri_pcmcia_device; + +static int __init colibri_pcmcia_init(void) +{ + int ret; + + if (!machine_is_colibri() && !machine_is_colibri320()) + return -ENODEV; + + colibri_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); + if (!colibri_pcmcia_device) + return -ENOMEM; + + /* Colibri PXA270 */ + if (machine_is_colibri()) { + colibri_pcmcia_gpios[RESET].gpio = COLIBRI270_RESET_GPIO; + colibri_pcmcia_gpios[PPEN].gpio = COLIBRI270_PPEN_GPIO; + colibri_pcmcia_gpios[BVD1].gpio = COLIBRI270_BVD1_GPIO; + colibri_pcmcia_gpios[BVD2].gpio = COLIBRI270_BVD2_GPIO; + colibri_pcmcia_gpios[DETECT].gpio = COLIBRI270_DETECT_GPIO; + colibri_pcmcia_gpios[READY].gpio = COLIBRI270_READY_GPIO; + /* Colibri PXA320 */ + } else if (machine_is_colibri320()) { + colibri_pcmcia_gpios[RESET].gpio = COLIBRI320_RESET_GPIO; + colibri_pcmcia_gpios[PPEN].gpio = COLIBRI320_PPEN_GPIO; + colibri_pcmcia_gpios[BVD1].gpio = COLIBRI320_BVD1_GPIO; + colibri_pcmcia_gpios[BVD2].gpio = COLIBRI320_BVD2_GPIO; + colibri_pcmcia_gpios[DETECT].gpio = COLIBRI320_DETECT_GPIO; + colibri_pcmcia_gpios[READY].gpio = COLIBRI320_READY_GPIO; + } + + ret = platform_device_add_data(colibri_pcmcia_device, + &colibri_pcmcia_ops, sizeof(colibri_pcmcia_ops)); + + if (!ret) + ret = platform_device_add(colibri_pcmcia_device); + + if (ret) + platform_device_put(colibri_pcmcia_device); + + return ret; +} + +static void __exit colibri_pcmcia_exit(void) +{ + platform_device_unregister(colibri_pcmcia_device); +} + +module_init(colibri_pcmcia_init); +module_exit(colibri_pcmcia_exit); + +MODULE_AUTHOR("Marek Vasut "); +MODULE_DESCRIPTION("PCMCIA support for Toradex Colibri PXA270/PXA320"); +MODULE_ALIAS("platform:pxa2xx-pcmcia"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-pxa/e740-pcmcia.c b/arch/arm/mach-pxa/e740-pcmcia.c new file mode 100644 index 000000000000..133535d7ac05 --- /dev/null +++ b/arch/arm/mach-pxa/e740-pcmcia.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Toshiba e740 PCMCIA specific routines. + * + * (c) 2004 Ian Molton + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include + +static int e740_pcmcia_hw_init(struct soc_pcmcia_socket *skt) +{ + if (skt->nr == 0) { + skt->stat[SOC_STAT_CD].gpio = GPIO_E740_PCMCIA_CD0; + skt->stat[SOC_STAT_CD].name = "CF card detect"; + skt->stat[SOC_STAT_RDY].gpio = GPIO_E740_PCMCIA_RDY0; + skt->stat[SOC_STAT_RDY].name = "CF ready"; + } else { + skt->stat[SOC_STAT_CD].gpio = GPIO_E740_PCMCIA_CD1; + skt->stat[SOC_STAT_CD].name = "Wifi switch"; + skt->stat[SOC_STAT_RDY].gpio = GPIO_E740_PCMCIA_RDY1; + skt->stat[SOC_STAT_RDY].name = "Wifi ready"; + } + + return 0; +} + +static void e740_pcmcia_socket_state(struct soc_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + state->vs_3v = 1; + state->vs_Xv = 0; +} + +static int e740_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, + const socket_state_t *state) +{ + if (state->flags & SS_RESET) { + if (skt->nr == 0) + gpio_set_value(GPIO_E740_PCMCIA_RST0, 1); + else + gpio_set_value(GPIO_E740_PCMCIA_RST1, 1); + } else { + if (skt->nr == 0) + gpio_set_value(GPIO_E740_PCMCIA_RST0, 0); + else + gpio_set_value(GPIO_E740_PCMCIA_RST1, 0); + } + + switch (state->Vcc) { + case 0: /* Socket off */ + if (skt->nr == 0) + gpio_set_value(GPIO_E740_PCMCIA_PWR0, 0); + else + gpio_set_value(GPIO_E740_PCMCIA_PWR1, 1); + break; + case 50: + case 33: /* socket on */ + if (skt->nr == 0) + gpio_set_value(GPIO_E740_PCMCIA_PWR0, 1); + else + gpio_set_value(GPIO_E740_PCMCIA_PWR1, 0); + break; + default: + printk(KERN_ERR "e740_cs: Unsupported Vcc: %d\n", state->Vcc); + } + + return 0; +} + +static struct pcmcia_low_level e740_pcmcia_ops = { + .owner = THIS_MODULE, + .hw_init = e740_pcmcia_hw_init, + .socket_state = e740_pcmcia_socket_state, + .configure_socket = e740_pcmcia_configure_socket, + .nr = 2, +}; + +static struct platform_device *e740_pcmcia_device; + +static int __init e740_pcmcia_init(void) +{ + int ret; + + if (!machine_is_e740()) + return -ENODEV; + + e740_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); + if (!e740_pcmcia_device) + return -ENOMEM; + + ret = platform_device_add_data(e740_pcmcia_device, &e740_pcmcia_ops, + sizeof(e740_pcmcia_ops)); + + if (!ret) + ret = platform_device_add(e740_pcmcia_device); + + if (ret) + platform_device_put(e740_pcmcia_device); + + return ret; +} + +static void __exit e740_pcmcia_exit(void) +{ + platform_device_unregister(e740_pcmcia_device); +} + +module_init(e740_pcmcia_init); +module_exit(e740_pcmcia_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Ian Molton "); +MODULE_ALIAS("platform:pxa2xx-pcmcia"); +MODULE_DESCRIPTION("e740 PCMCIA platform support"); diff --git a/arch/arm/mach-pxa/hx4700-pcmcia.c b/arch/arm/mach-pxa/hx4700-pcmcia.c new file mode 100644 index 000000000000..e8acbfc9ef6c --- /dev/null +++ b/arch/arm/mach-pxa/hx4700-pcmcia.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Paul Parsons + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include + +static struct gpio gpios[] = { + { GPIO114_HX4700_CF_RESET, GPIOF_OUT_INIT_LOW, "CF reset" }, + { EGPIO4_CF_3V3_ON, GPIOF_OUT_INIT_LOW, "CF 3.3V enable" }, +}; + +static int hx4700_pcmcia_hw_init(struct soc_pcmcia_socket *skt) +{ + int ret; + + ret = gpio_request_array(gpios, ARRAY_SIZE(gpios)); + if (ret) + goto out; + + /* + * IRQ type must be set before soc_pcmcia_hw_init() calls request_irq(). + * The asic3 default IRQ type is level trigger low level detect, exactly + * the the signal present on GPIOD4_CF_nCD when a CF card is inserted. + * If the IRQ type is not changed, the asic3 interrupt handler will loop + * repeatedly because it is unable to clear the level trigger interrupt. + */ + irq_set_irq_type(gpio_to_irq(GPIOD4_CF_nCD), IRQ_TYPE_EDGE_BOTH); + + skt->stat[SOC_STAT_CD].gpio = GPIOD4_CF_nCD; + skt->stat[SOC_STAT_CD].name = "PCMCIA CD"; + skt->stat[SOC_STAT_RDY].gpio = GPIO60_HX4700_CF_RNB; + skt->stat[SOC_STAT_RDY].name = "PCMCIA Ready"; + +out: + return ret; +} + +static void hx4700_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) +{ + gpio_free_array(gpios, ARRAY_SIZE(gpios)); +} + +static void hx4700_pcmcia_socket_state(struct soc_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + state->vs_3v = 1; + state->vs_Xv = 0; +} + +static int hx4700_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, + const socket_state_t *state) +{ + switch (state->Vcc) { + case 0: + gpio_set_value(EGPIO4_CF_3V3_ON, 0); + break; + case 33: + gpio_set_value(EGPIO4_CF_3V3_ON, 1); + break; + default: + printk(KERN_ERR "pcmcia: Unsupported Vcc: %d\n", state->Vcc); + return -EINVAL; + } + + gpio_set_value(GPIO114_HX4700_CF_RESET, (state->flags & SS_RESET) != 0); + + return 0; +} + +static struct pcmcia_low_level hx4700_pcmcia_ops = { + .owner = THIS_MODULE, + .nr = 1, + .hw_init = hx4700_pcmcia_hw_init, + .hw_shutdown = hx4700_pcmcia_hw_shutdown, + .socket_state = hx4700_pcmcia_socket_state, + .configure_socket = hx4700_pcmcia_configure_socket, +}; + +static struct platform_device *hx4700_pcmcia_device; + +static int __init hx4700_pcmcia_init(void) +{ + struct platform_device *pdev; + + if (!machine_is_h4700()) + return -ENODEV; + + pdev = platform_device_register_data(NULL, "pxa2xx-pcmcia", -1, + &hx4700_pcmcia_ops, sizeof(hx4700_pcmcia_ops)); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + hx4700_pcmcia_device = pdev; + + return 0; +} + +static void __exit hx4700_pcmcia_exit(void) +{ + platform_device_unregister(hx4700_pcmcia_device); +} + +module_init(hx4700_pcmcia_init); +module_exit(hx4700_pcmcia_exit); + +MODULE_AUTHOR("Paul Parsons "); +MODULE_DESCRIPTION("HP iPAQ hx4700 PCMCIA driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h deleted file mode 100644 index 04f3639c4082..000000000000 --- a/arch/arm/mach-pxa/include/mach/balloon3.h +++ /dev/null @@ -1,181 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * linux/include/asm-arm/arch-pxa/balloon3.h - * - * Authors: Nick Bane and Wookey - * Created: Oct, 2005 - * Copyright: Toby Churchill Ltd - * Cribbed from mainstone.c, by Nicholas Pitre - */ - -#ifndef ASM_ARCH_BALLOON3_H -#define ASM_ARCH_BALLOON3_H - -#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ - -enum balloon3_features { - BALLOON3_FEATURE_OHCI, - BALLOON3_FEATURE_MMC, - BALLOON3_FEATURE_CF, - BALLOON3_FEATURE_AUDIO, - BALLOON3_FEATURE_TOPPOLY, -}; - -#define BALLOON3_FPGA_PHYS PXA_CS4_PHYS -#define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */ -#define BALLOON3_FPGA_LENGTH 0x01000000 - -#define BALLOON3_FPGA_SETnCLR (0x1000) - -/* FPGA / CPLD registers for CF socket */ -#define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008) -#define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008) -/* FPGA / CPLD version register */ -#define BALLOON3_FPGA_VER (BALLOON3_FPGA_VIRT + 0x00e0001c) -/* FPGA / CPLD registers for NAND flash */ -#define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000) -#define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000) -#define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010) -#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00014) -#define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014) - -/* fpga/cpld interrupt control register */ -#define BALLOON3_INT_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e0000C) -#define BALLOON3_VERSION_REG (BALLOON3_FPGA_VIRT + 0x00e0001c) - -#define BALLOON3_SAMOSA_ADDR_REG (BALLOON3_FPGA_VIRT + 0x00c00000) -#define BALLOON3_SAMOSA_DATA_REG (BALLOON3_FPGA_VIRT + 0x00c00004) -#define BALLOON3_SAMOSA_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00c0001c) - -/* CF Status Register bits (read-only) bits */ -#define BALLOON3_CF_nIRQ (1 << 0) -#define BALLOON3_CF_nSTSCHG_BVD1 (1 << 1) - -/* CF Control Set Register bits / CF Control Clear Register bits (write-only) */ -#define BALLOON3_CF_RESET (1 << 0) -#define BALLOON3_CF_ENABLE (1 << 1) -#define BALLOON3_CF_ADD_ENABLE (1 << 2) - -/* CF Interrupt sources */ -#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0) -#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1) - -/* NAND Control register */ -#define BALLOON3_NAND_CONTROL_FLWP (1 << 7) -#define BALLOON3_NAND_CONTROL_FLSE (1 << 6) -#define BALLOON3_NAND_CONTROL_FLCE3 (1 << 5) -#define BALLOON3_NAND_CONTROL_FLCE2 (1 << 4) -#define BALLOON3_NAND_CONTROL_FLCE1 (1 << 3) -#define BALLOON3_NAND_CONTROL_FLCE0 (1 << 2) -#define BALLOON3_NAND_CONTROL_FLALE (1 << 1) -#define BALLOON3_NAND_CONTROL_FLCLE (1 << 0) - -/* NAND Status register */ -#define BALLOON3_NAND_STAT_RNB (1 << 0) - -/* NAND Control2 register */ -#define BALLOON3_NAND_CONTROL2_16BIT (1 << 0) - -/* GPIOs for irqs */ -#define BALLOON3_GPIO_AUX_NIRQ (94) -#define BALLOON3_GPIO_CODEC_IRQ (95) - -/* Timer and Idle LED locations */ -#define BALLOON3_GPIO_LED_NAND (9) -#define BALLOON3_GPIO_LED_IDLE (10) - -/* backlight control */ -#define BALLOON3_GPIO_RUN_BACKLIGHT (99) - -#define BALLOON3_GPIO_S0_CD (105) - -/* NAND */ -#define BALLOON3_GPIO_RUN_NAND (102) - -/* PCF8574A Leds */ -#define BALLOON3_PCF_GPIO_BASE 160 -#define BALLOON3_PCF_GPIO_LED0 (BALLOON3_PCF_GPIO_BASE + 0) -#define BALLOON3_PCF_GPIO_LED1 (BALLOON3_PCF_GPIO_BASE + 1) -#define BALLOON3_PCF_GPIO_LED2 (BALLOON3_PCF_GPIO_BASE + 2) -#define BALLOON3_PCF_GPIO_LED3 (BALLOON3_PCF_GPIO_BASE + 3) -#define BALLOON3_PCF_GPIO_LED4 (BALLOON3_PCF_GPIO_BASE + 4) -#define BALLOON3_PCF_GPIO_LED5 (BALLOON3_PCF_GPIO_BASE + 5) -#define BALLOON3_PCF_GPIO_LED6 (BALLOON3_PCF_GPIO_BASE + 6) -#define BALLOON3_PCF_GPIO_LED7 (BALLOON3_PCF_GPIO_BASE + 7) - -/* FPGA Interrupt Mask/Acknowledge Register */ -#define BALLOON3_INT_S0_IRQ (1 << 0) /* PCMCIA 0 IRQ */ -#define BALLOON3_INT_S0_STSCHG (1 << 1) /* PCMCIA 0 status changed */ - -/* CPLD (and FPGA) interface definitions */ -#define CPLD_LCD0_DATA_SET 0x00 -#define CPLD_LCD0_DATA_CLR 0x10 -#define CPLD_LCD0_COMMAND_SET 0x01 -#define CPLD_LCD0_COMMAND_CLR 0x11 -#define CPLD_LCD1_DATA_SET 0x02 -#define CPLD_LCD1_DATA_CLR 0x12 -#define CPLD_LCD1_COMMAND_SET 0x03 -#define CPLD_LCD1_COMMAND_CLR 0x13 - -#define CPLD_MISC_SET 0x07 -#define CPLD_MISC_CLR 0x17 -#define CPLD_MISC_LOON_NRESET_BIT 0 -#define CPLD_MISC_LOON_UNSUSP_BIT 1 -#define CPLD_MISC_RUN_5V_BIT 2 -#define CPLD_MISC_CHG_D0_BIT 3 -#define CPLD_MISC_CHG_D1_BIT 4 -#define CPLD_MISC_DAC_NCS_BIT 5 - -#define CPLD_LCD_SET 0x08 -#define CPLD_LCD_CLR 0x18 -#define CPLD_LCD_BACKLIGHT_EN_0_BIT 0 -#define CPLD_LCD_BACKLIGHT_EN_1_BIT 1 -#define CPLD_LCD_LED_RED_BIT 4 -#define CPLD_LCD_LED_GREEN_BIT 5 -#define CPLD_LCD_NRESET_BIT 7 - -#define CPLD_LCD_RO_SET 0x09 -#define CPLD_LCD_RO_CLR 0x19 -#define CPLD_LCD_RO_LCD0_nWAIT_BIT 0 -#define CPLD_LCD_RO_LCD1_nWAIT_BIT 1 - -#define CPLD_SERIAL_SET 0x0a -#define CPLD_SERIAL_CLR 0x1a -#define CPLD_SERIAL_GSM_RI_BIT 0 -#define CPLD_SERIAL_GSM_CTS_BIT 1 -#define CPLD_SERIAL_GSM_DTR_BIT 2 -#define CPLD_SERIAL_LPR_CTS_BIT 3 -#define CPLD_SERIAL_TC232_CTS_BIT 4 -#define CPLD_SERIAL_TC232_DSR_BIT 5 - -#define CPLD_SROUTING_SET 0x0b -#define CPLD_SROUTING_CLR 0x1b -#define CPLD_SROUTING_MSP430_LPR 0 -#define CPLD_SROUTING_MSP430_TC232 1 -#define CPLD_SROUTING_MSP430_GSM 2 -#define CPLD_SROUTING_LOON_LPR (0 << 4) -#define CPLD_SROUTING_LOON_TC232 (1 << 4) -#define CPLD_SROUTING_LOON_GSM (2 << 4) - -#define CPLD_AROUTING_SET 0x0c -#define CPLD_AROUTING_CLR 0x1c -#define CPLD_AROUTING_MIC2PHONE_BIT 0 -#define CPLD_AROUTING_PHONE2INT_BIT 1 -#define CPLD_AROUTING_PHONE2EXT_BIT 2 -#define CPLD_AROUTING_LOONL2INT_BIT 3 -#define CPLD_AROUTING_LOONL2EXT_BIT 4 -#define CPLD_AROUTING_LOONR2PHONE_BIT 5 -#define CPLD_AROUTING_LOONR2INT_BIT 6 -#define CPLD_AROUTING_LOONR2EXT_BIT 7 - -/* Balloon3 Interrupts */ -#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x)) - -#define BALLOON3_AUX_NIRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ) -#define BALLOON3_CODEC_IRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ) - -#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16) - -extern int balloon3_has(enum balloon3_features feature); - -#endif diff --git a/arch/arm/mach-pxa/include/mach/palmtc.h b/arch/arm/mach-pxa/include/mach/palmtc.h deleted file mode 100644 index 9257a02c46e5..000000000000 --- a/arch/arm/mach-pxa/include/mach/palmtc.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * linux/include/asm-arm/arch-pxa/palmtc-gpio.h - * - * GPIOs and interrupts for Palm Tungsten|C Handheld Computer - * - * Authors: Alex Osborne - * Marek Vasut - * Holger Bocklet - */ - -#ifndef _INCLUDE_PALMTC_H_ -#define _INCLUDE_PALMTC_H_ - -#include "irqs.h" /* PXA_GPIO_TO_IRQ */ - -/** HERE ARE GPIOs **/ - -/* GPIOs */ -#define GPIO_NR_PALMTC_EARPHONE_DETECT 2 -#define GPIO_NR_PALMTC_CRADLE_DETECT 5 -#define GPIO_NR_PALMTC_HOTSYNC_BUTTON 7 - -/* SD/MMC */ -#define GPIO_NR_PALMTC_SD_DETECT_N 12 -#define GPIO_NR_PALMTC_SD_POWER 32 -#define GPIO_NR_PALMTC_SD_READONLY 54 - -/* WLAN */ -#define GPIO_NR_PALMTC_PCMCIA_READY 13 -#define GPIO_NR_PALMTC_PCMCIA_PWRREADY 14 -#define GPIO_NR_PALMTC_PCMCIA_POWER1 15 -#define GPIO_NR_PALMTC_PCMCIA_POWER2 33 -#define GPIO_NR_PALMTC_PCMCIA_POWER3 55 -#define GPIO_NR_PALMTC_PCMCIA_RESET 78 - -/* UDC */ -#define GPIO_NR_PALMTC_USB_DETECT_N 4 -#define GPIO_NR_PALMTC_USB_POWER 36 - -/* LCD/BACKLIGHT */ -#define GPIO_NR_PALMTC_BL_POWER 16 -#define GPIO_NR_PALMTC_LCD_POWER 44 -#define GPIO_NR_PALMTC_LCD_BLANK 38 - -/* UART */ -#define GPIO_NR_PALMTC_RS232_POWER 37 - -/* IRDA */ -#define GPIO_NR_PALMTC_IR_DISABLE 45 - -/* IRQs */ -#define IRQ_GPIO_PALMTC_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_SD_DETECT_N) -#define IRQ_GPIO_PALMTC_WLAN_READY PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_WLAN_READY) - -/* UCB1400 GPIOs */ -#define GPIO_NR_PALMTC_POWER_DETECT (0x80 | 0x00) -#define GPIO_NR_PALMTC_HEADPHONE_DETECT (0x80 | 0x01) -#define GPIO_NR_PALMTC_SPEAKER_ENABLE (0x80 | 0x03) -#define GPIO_NR_PALMTC_VIBRA_POWER (0x80 | 0x05) -#define GPIO_NR_PALMTC_LED_POWER (0x80 | 0x07) - -/** HERE ARE INIT VALUES **/ -#define PALMTC_UCB1400_GPIO_OFFSET 0x80 - -/* BATTERY */ -#define PALMTC_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */ -#define PALMTC_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */ -#define PALMTC_BAT_MAX_CURRENT 0 /* unknown */ -#define PALMTC_BAT_MIN_CURRENT 0 /* unknown */ -#define PALMTC_BAT_MAX_CHARGE 1 /* unknown */ -#define PALMTC_BAT_MIN_CHARGE 1 /* unknown */ -#define PALMTC_MAX_LIFE_MINS 240 /* on-life in minutes */ - -#define PALMTC_BAT_MEASURE_DELAY (HZ * 1) - -/* BACKLIGHT */ -#define PALMTC_MAX_INTENSITY 0xFE -#define PALMTC_DEFAULT_INTENSITY 0x7E -#define PALMTC_LIMIT_MASK 0x7F -#define PALMTC_PRESCALER 0x3F -#define PALMTC_PERIOD_NS 3500 - -#endif diff --git a/arch/arm/mach-pxa/include/mach/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h deleted file mode 100644 index ec88abf0fc6c..000000000000 --- a/arch/arm/mach-pxa/include/mach/palmtx.h +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIOs and interrupts for Palm T|X Handheld Computer - * - * Based on palmld-gpio.h by Alex Osborne - * - * Authors: Marek Vasut - * Cristiano P. - * Jan Herman <2hp@seznam.cz> - */ - -#ifndef _INCLUDE_PALMTX_H_ -#define _INCLUDE_PALMTX_H_ - -#include "irqs.h" /* PXA_GPIO_TO_IRQ */ - -/** HERE ARE GPIOs **/ - -/* GPIOs */ -#define GPIO_NR_PALMTX_GPIO_RESET 1 - -#define GPIO_NR_PALMTX_POWER_DETECT 12 /* 90 */ -#define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N 10 -#define GPIO_NR_PALMTX_EARPHONE_DETECT 107 - -/* SD/MMC */ -#define GPIO_NR_PALMTX_SD_DETECT_N 14 -#define GPIO_NR_PALMTX_SD_POWER 114 /* probably */ -#define GPIO_NR_PALMTX_SD_READONLY 115 /* probably */ - -/* TOUCHSCREEN */ -#define GPIO_NR_PALMTX_WM9712_IRQ 27 - -/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ -#define GPIO_NR_PALMTX_IR_DISABLE 40 - -/* USB */ -#define GPIO_NR_PALMTX_USB_DETECT_N 13 -#define GPIO_NR_PALMTX_USB_PULLUP 93 - -/* LCD/BACKLIGHT */ -#define GPIO_NR_PALMTX_BL_POWER 84 -#define GPIO_NR_PALMTX_LCD_POWER 96 - -/* LCD BORDER */ -#define GPIO_NR_PALMTX_BORDER_SWITCH 98 -#define GPIO_NR_PALMTX_BORDER_SELECT 22 - -/* BLUETOOTH */ -#define GPIO_NR_PALMTX_BT_POWER 17 -#define GPIO_NR_PALMTX_BT_RESET 83 - -/* PCMCIA (WiFi) */ -#define GPIO_NR_PALMTX_PCMCIA_POWER1 94 -#define GPIO_NR_PALMTX_PCMCIA_POWER2 108 -#define GPIO_NR_PALMTX_PCMCIA_RESET 79 -#define GPIO_NR_PALMTX_PCMCIA_READY 116 - -/* NAND Flash ... this GPIO may be incorrect! */ -#define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79 - -/* INTERRUPTS */ -#define IRQ_GPIO_PALMTX_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_SD_DETECT_N) -#define IRQ_GPIO_PALMTX_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_WM9712_IRQ) -#define IRQ_GPIO_PALMTX_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_USB_DETECT) -#define IRQ_GPIO_PALMTX_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_GPIO_RESET) - -/** HERE ARE INIT VALUES **/ - -/* Various addresses */ -#define PALMTX_PCMCIA_PHYS 0x28000000 -#define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000) -#define PALMTX_PCMCIA_SIZE 0x100000 - -#define PALMTX_PHYS_RAM_START 0xa0000000 -#define PALMTX_PHYS_IO_START 0x40000000 - -#define PALMTX_STR_BASE 0xa0200000 - -#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */ -#define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */ - -#define PALMTX_NAND_ALE_PHYS (PALMTX_PHYS_NAND_START | (1 << 24)) -#define PALMTX_NAND_CLE_PHYS (PALMTX_PHYS_NAND_START | (1 << 25)) -#define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000) -#define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000) - -/* TOUCHSCREEN */ -#define AC97_LINK_FRAME 21 - - -/* BATTERY */ -#define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ -#define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ -#define PALMTX_BAT_MAX_CURRENT 0 /* unknown */ -#define PALMTX_BAT_MIN_CURRENT 0 /* unknown */ -#define PALMTX_BAT_MAX_CHARGE 1 /* unknown */ -#define PALMTX_BAT_MIN_CHARGE 1 /* unknown */ -#define PALMTX_MAX_LIFE_MINS 360 /* on-life in minutes */ - -#define PALMTX_BAT_MEASURE_DELAY (HZ * 1) - -/* BACKLIGHT */ -#define PALMTX_MAX_INTENSITY 0xFE -#define PALMTX_DEFAULT_INTENSITY 0x7E -#define PALMTX_LIMIT_MASK 0x7F -#define PALMTX_PRESCALER 0x3F -#define PALMTX_PERIOD_NS 3500 - -#endif diff --git a/arch/arm/mach-pxa/include/mach/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h deleted file mode 100644 index 27926629f9c6..000000000000 --- a/arch/arm/mach-pxa/include/mach/trizeps4.h +++ /dev/null @@ -1,166 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/************************************************************************ - * Include file for TRIZEPS4 SoM and ConXS eval-board - * Copyright (c) Jürgen Schindele - * 2006 - ************************************************************************/ - -/* - * Includes/Defines - */ -#ifndef _TRIPEPS4_H_ -#define _TRIPEPS4_H_ - -#include -#include "irqs.h" /* PXA_GPIO_TO_IRQ */ - -/* physical memory regions */ -#define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ -#define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */ -#define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ -#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ -#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ - - /* Logic on ConXS-board CSFR register*/ -#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) - /* Logic on ConXS-board BOCR register*/ -#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) - /* Logic on ConXS-board IRCR register*/ -#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) - /* Logic on ConXS-board UPSR register*/ -#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) - /* Logic on ConXS-board DICR register*/ -#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) - -/* virtual memory regions */ -#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ - -#define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */ -#define TRIZEPS4_CFSR_VIRT 0xF0100000 -#define TRIZEPS4_BOCR_VIRT 0xF0200000 -#define TRIZEPS4_DICR_VIRT 0xF0300000 -#define TRIZEPS4_IRCR_VIRT 0xF0400000 -#define TRIZEPS4_UPSR_VIRT 0xF0500000 - -/* size of flash */ -#define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ - -/* Ethernet Controller Davicom DM9000 */ -#define GPIO_DM9000 101 -#define TRIZEPS4_ETH_IRQ PXA_GPIO_TO_IRQ(GPIO_DM9000) - -/* UCB1400 audio / TS-controller */ -#define GPIO_UCB1400 1 -#define TRIZEPS4_UCB1400_IRQ PXA_GPIO_TO_IRQ(GPIO_UCB1400) - -/* PCMCIA socket Compact Flash */ -#define GPIO_PCD 11 /* PCMCIA Card Detect */ -#define TRIZEPS4_CD_IRQ PXA_GPIO_TO_IRQ(GPIO_PCD) -#define GPIO_PRDY 13 /* READY / nINT */ -#define TRIZEPS4_READY_NINT PXA_GPIO_TO_IRQ(GPIO_PRDY) - -/* MMC socket */ -#define GPIO_MMC_DET 12 -#define TRIZEPS4_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO_MMC_DET) - -/* DOC NAND chip */ -#define GPIO_DOC_LOCK 94 -#define GPIO_DOC_IRQ 93 -#define TRIZEPS4_DOC_IRQ PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ) - -/* SPI interface */ -#define GPIO_SPI 53 -#define TRIZEPS4_SPI_IRQ PXA_GPIO_TO_IRQ(GPIO_SPI) - -/* LEDS using tx2 / rx2 */ -#define GPIO_SYS_BUSY_LED 46 -#define GPIO_HEARTBEAT_LED 47 - -/* Off-module PIC on ConXS board */ -#define GPIO_PIC 0 -#define TRIZEPS4_PIC_IRQ PXA_GPIO_TO_IRQ(GPIO_PIC) - -#ifdef CONFIG_MACH_TRIZEPS_CONXS -/* for CONXS base board define these registers */ -#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) -#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) - -#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) -#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) - -#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) -#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) - -#define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT) -#define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS) - -#ifndef __ASSEMBLY__ -static inline unsigned short CFSR_readw(void) -{ - /* [Compact Flash Status Register] is read only */ - return *((unsigned short *)CFSR_P2V(0x0C000000)); -} -static inline void BCR_writew(unsigned short value) -{ - /* [Board Control Regsiter] is write only */ - *((unsigned short *)BCR_P2V(0x0E000000)) = value; -} -static inline void DCR_writew(unsigned short value) -{ - /* [Display Control Register] is write only */ - *((unsigned short *)DCR_P2V(0x0E000000)) = value; -} -static inline void IRCR_writew(unsigned short value) -{ - /* [InfraRed data Control Register] is write only */ - *((unsigned short *)IRCR_P2V(0x0E000000)) = value; -} -#else -#define ConXS_CFSR CFSR_P2V(0x0C000000) -#define ConXS_BCR BCR_P2V(0x0E000000) -#define ConXS_DCR DCR_P2V(0x0F800000) -#define ConXS_IRCR IRCR_P2V(0x0F800000) -#endif -#else -/* for whatever baseboard define function registers */ -static inline unsigned short CFSR_readw(void) -{ - return 0; -} -static inline void BCR_writew(unsigned short value) -{ - ; -} -static inline void DCR_writew(unsigned short value) -{ - ; -} -static inline void IRCR_writew(unsigned short value) -{ - ; -} -#endif /* CONFIG_MACH_TRIZEPS_CONXS */ - -#define ConXS_CFSR_BVD_MASK 0x0003 -#define ConXS_CFSR_BVD1 (1 << 0) -#define ConXS_CFSR_BVD2 (1 << 1) -#define ConXS_CFSR_VS_MASK 0x000C -#define ConXS_CFSR_VS1 (1 << 2) -#define ConXS_CFSR_VS2 (1 << 3) -#define ConXS_CFSR_VS_5V (0x3 << 2) -#define ConXS_CFSR_VS_3V3 0x0 - -#define ConXS_BCR_S0_POW_EN0 (1 << 0) -#define ConXS_BCR_S0_POW_EN1 (1 << 1) -#define ConXS_BCR_L_DISP (1 << 4) -#define ConXS_BCR_CF_BUF_EN (1 << 5) -#define ConXS_BCR_CF_RESET (1 << 7) -#define ConXS_BCR_S0_VCC_3V3 0x1 -#define ConXS_BCR_S0_VCC_5V0 0x2 -#define ConXS_BCR_S0_VPP_12V 0x4 -#define ConXS_BCR_S0_VPP_3V3 0x8 - -#define ConXS_IRCR_MODE (1 << 0) -#define ConXS_IRCR_SD (1 << 1) - -#endif /* _TRIPEPS4_H_ */ diff --git a/arch/arm/mach-pxa/include/mach/vpac270.h b/arch/arm/mach-pxa/include/mach/vpac270.h deleted file mode 100644 index 0cd094d8c553..000000000000 --- a/arch/arm/mach-pxa/include/mach/vpac270.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIOs and interrupts for Voipac PXA270 - * - * Copyright (C) 2010 - * Marek Vasut - */ - -#ifndef _INCLUDE_VPAC270_H_ -#define _INCLUDE_VPAC270_H_ - -#define GPIO1_VPAC270_USER_BTN 1 - -#define GPIO15_VPAC270_LED_ORANGE 15 - -#define GPIO81_VPAC270_BKL_ON 81 -#define GPIO83_VPAC270_NL_ON 83 - -#define GPIO52_VPAC270_SD_READONLY 52 -#define GPIO53_VPAC270_SD_DETECT_N 53 - -#define GPIO84_VPAC270_PCMCIA_CD 84 -#define GPIO35_VPAC270_PCMCIA_RDY 35 -#define GPIO107_VPAC270_PCMCIA_PPEN 107 -#define GPIO11_VPAC270_PCMCIA_RESET 11 -#define GPIO17_VPAC270_CF_CD 17 -#define GPIO12_VPAC270_CF_RDY 12 -#define GPIO16_VPAC270_CF_RESET 16 - -#define GPIO41_VPAC270_UDC_DETECT 41 - -#define GPIO114_VPAC270_ETH_IRQ 114 - -#define GPIO36_VPAC270_IDE_IRQ 36 - -#define GPIO113_VPAC270_TS_IRQ 113 - -#endif diff --git a/arch/arm/mach-pxa/palmld-pcmcia.c b/arch/arm/mach-pxa/palmld-pcmcia.c new file mode 100644 index 000000000000..07e0f7438db1 --- /dev/null +++ b/arch/arm/mach-pxa/palmld-pcmcia.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/drivers/pcmcia/pxa2xx_palmld.c + * + * Driver for Palm LifeDrive PCMCIA + * + * Copyright (C) 2006 Alex Osborne + * Copyright (C) 2007-2011 Marek Vasut + */ + +#include +#include +#include + +#include +#include +#include + +static struct gpio palmld_pcmcia_gpios[] = { + { GPIO_NR_PALMLD_PCMCIA_POWER, GPIOF_INIT_LOW, "PCMCIA Power" }, + { GPIO_NR_PALMLD_PCMCIA_RESET, GPIOF_INIT_HIGH,"PCMCIA Reset" }, +}; + +static int palmld_pcmcia_hw_init(struct soc_pcmcia_socket *skt) +{ + int ret; + + ret = gpio_request_array(palmld_pcmcia_gpios, + ARRAY_SIZE(palmld_pcmcia_gpios)); + + skt->stat[SOC_STAT_RDY].gpio = GPIO_NR_PALMLD_PCMCIA_READY; + skt->stat[SOC_STAT_RDY].name = "PCMCIA Ready"; + + return ret; +} + +static void palmld_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) +{ + gpio_free_array(palmld_pcmcia_gpios, ARRAY_SIZE(palmld_pcmcia_gpios)); +} + +static void palmld_pcmcia_socket_state(struct soc_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + state->detect = 1; /* always inserted */ + state->vs_3v = 1; + state->vs_Xv = 0; +} + +static int palmld_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, + const socket_state_t *state) +{ + gpio_set_value(GPIO_NR_PALMLD_PCMCIA_POWER, 1); + gpio_set_value(GPIO_NR_PALMLD_PCMCIA_RESET, + !!(state->flags & SS_RESET)); + + return 0; +} + +static struct pcmcia_low_level palmld_pcmcia_ops = { + .owner = THIS_MODULE, + + .first = 1, + .nr = 1, + + .hw_init = palmld_pcmcia_hw_init, + .hw_shutdown = palmld_pcmcia_hw_shutdown, + + .socket_state = palmld_pcmcia_socket_state, + .configure_socket = palmld_pcmcia_configure_socket, +}; + +static struct platform_device *palmld_pcmcia_device; + +static int __init palmld_pcmcia_init(void) +{ + int ret; + + if (!machine_is_palmld()) + return -ENODEV; + + palmld_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); + if (!palmld_pcmcia_device) + return -ENOMEM; + + ret = platform_device_add_data(palmld_pcmcia_device, &palmld_pcmcia_ops, + sizeof(palmld_pcmcia_ops)); + + if (!ret) + ret = platform_device_add(palmld_pcmcia_device); + + if (ret) + platform_device_put(palmld_pcmcia_device); + + return ret; +} + +static void __exit palmld_pcmcia_exit(void) +{ + platform_device_unregister(palmld_pcmcia_device); +} + +module_init(palmld_pcmcia_init); +module_exit(palmld_pcmcia_exit); + +MODULE_AUTHOR("Alex Osborne ," + " Marek Vasut "); +MODULE_DESCRIPTION("PCMCIA support for Palm LifeDrive"); +MODULE_ALIAS("platform:pxa2xx-pcmcia"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-pxa/palmtc-pcmcia.c b/arch/arm/mach-pxa/palmtc-pcmcia.c new file mode 100644 index 000000000000..8e3f382343fe --- /dev/null +++ b/arch/arm/mach-pxa/palmtc-pcmcia.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/drivers/pcmcia/pxa2xx_palmtc.c + * + * Driver for Palm Tungsten|C PCMCIA + * + * Copyright (C) 2008 Alex Osborne + * Copyright (C) 2009-2011 Marek Vasut + */ + +#include +#include +#include +#include + +#include +#include "palmtc.h" +#include + +static struct gpio palmtc_pcmcia_gpios[] = { + { GPIO_NR_PALMTC_PCMCIA_POWER1, GPIOF_INIT_LOW, "PCMCIA Power 1" }, + { GPIO_NR_PALMTC_PCMCIA_POWER2, GPIOF_INIT_LOW, "PCMCIA Power 2" }, + { GPIO_NR_PALMTC_PCMCIA_POWER3, GPIOF_INIT_LOW, "PCMCIA Power 3" }, + { GPIO_NR_PALMTC_PCMCIA_RESET, GPIOF_INIT_HIGH,"PCMCIA Reset" }, + { GPIO_NR_PALMTC_PCMCIA_PWRREADY, GPIOF_IN, "PCMCIA Power Ready" }, +}; + +static int palmtc_pcmcia_hw_init(struct soc_pcmcia_socket *skt) +{ + int ret; + + ret = gpio_request_array(palmtc_pcmcia_gpios, + ARRAY_SIZE(palmtc_pcmcia_gpios)); + + skt->stat[SOC_STAT_RDY].gpio = GPIO_NR_PALMTC_PCMCIA_READY; + skt->stat[SOC_STAT_RDY].name = "PCMCIA Ready"; + + return ret; +} + +static void palmtc_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) +{ + gpio_free_array(palmtc_pcmcia_gpios, ARRAY_SIZE(palmtc_pcmcia_gpios)); +} + +static void palmtc_pcmcia_socket_state(struct soc_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + state->detect = 1; /* always inserted */ + state->vs_3v = 1; + state->vs_Xv = 0; +} + +static int palmtc_wifi_powerdown(void) +{ + gpio_set_value(GPIO_NR_PALMTC_PCMCIA_RESET, 1); + gpio_set_value(GPIO_NR_PALMTC_PCMCIA_POWER2, 0); + mdelay(40); + gpio_set_value(GPIO_NR_PALMTC_PCMCIA_POWER1, 0); + return 0; +} + +static int palmtc_wifi_powerup(void) +{ + int timeout = 50; + + gpio_set_value(GPIO_NR_PALMTC_PCMCIA_POWER3, 1); + mdelay(50); + + /* Power up the card, 1.8V first, after a while 3.3V */ + gpio_set_value(GPIO_NR_PALMTC_PCMCIA_POWER1, 1); + mdelay(100); + gpio_set_value(GPIO_NR_PALMTC_PCMCIA_POWER2, 1); + + /* Wait till the card is ready */ + while (!gpio_get_value(GPIO_NR_PALMTC_PCMCIA_PWRREADY) && + timeout) { + mdelay(1); + timeout--; + } + + /* Power down the WiFi in case of error */ + if (!timeout) { + palmtc_wifi_powerdown(); + return 1; + } + + /* Reset the card */ + gpio_set_value(GPIO_NR_PALMTC_PCMCIA_RESET, 1); + mdelay(20); + gpio_set_value(GPIO_NR_PALMTC_PCMCIA_RESET, 0); + mdelay(25); + + gpio_set_value(GPIO_NR_PALMTC_PCMCIA_POWER3, 0); + + return 0; +} + +static int palmtc_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, + const socket_state_t *state) +{ + int ret = 1; + + if (state->Vcc == 0) + ret = palmtc_wifi_powerdown(); + else if (state->Vcc == 33) + ret = palmtc_wifi_powerup(); + + return ret; +} + +static struct pcmcia_low_level palmtc_pcmcia_ops = { + .owner = THIS_MODULE, + + .first = 0, + .nr = 1, + + .hw_init = palmtc_pcmcia_hw_init, + .hw_shutdown = palmtc_pcmcia_hw_shutdown, + + .socket_state = palmtc_pcmcia_socket_state, + .configure_socket = palmtc_pcmcia_configure_socket, +}; + +static struct platform_device *palmtc_pcmcia_device; + +static int __init palmtc_pcmcia_init(void) +{ + int ret; + + if (!machine_is_palmtc()) + return -ENODEV; + + palmtc_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); + if (!palmtc_pcmcia_device) + return -ENOMEM; + + ret = platform_device_add_data(palmtc_pcmcia_device, &palmtc_pcmcia_ops, + sizeof(palmtc_pcmcia_ops)); + + if (!ret) + ret = platform_device_add(palmtc_pcmcia_device); + + if (ret) + platform_device_put(palmtc_pcmcia_device); + + return ret; +} + +static void __exit palmtc_pcmcia_exit(void) +{ + platform_device_unregister(palmtc_pcmcia_device); +} + +module_init(palmtc_pcmcia_init); +module_exit(palmtc_pcmcia_exit); + +MODULE_AUTHOR("Alex Osborne ," + " Marek Vasut "); +MODULE_DESCRIPTION("PCMCIA support for Palm Tungsten|C"); +MODULE_ALIAS("platform:pxa2xx-pcmcia"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index c59fc76c0c3d..3054ffa397ad 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -30,7 +30,7 @@ #include "pxa25x.h" #include -#include +#include "palmtc.h" #include #include #include diff --git a/arch/arm/mach-pxa/palmtc.h b/arch/arm/mach-pxa/palmtc.h new file mode 100644 index 000000000000..afec057c2857 --- /dev/null +++ b/arch/arm/mach-pxa/palmtc.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/include/asm-arm/arch-pxa/palmtc-gpio.h + * + * GPIOs and interrupts for Palm Tungsten|C Handheld Computer + * + * Authors: Alex Osborne + * Marek Vasut + * Holger Bocklet + */ + +#ifndef _INCLUDE_PALMTC_H_ +#define _INCLUDE_PALMTC_H_ + +#include /* PXA_GPIO_TO_IRQ */ + +/** HERE ARE GPIOs **/ + +/* GPIOs */ +#define GPIO_NR_PALMTC_EARPHONE_DETECT 2 +#define GPIO_NR_PALMTC_CRADLE_DETECT 5 +#define GPIO_NR_PALMTC_HOTSYNC_BUTTON 7 + +/* SD/MMC */ +#define GPIO_NR_PALMTC_SD_DETECT_N 12 +#define GPIO_NR_PALMTC_SD_POWER 32 +#define GPIO_NR_PALMTC_SD_READONLY 54 + +/* WLAN */ +#define GPIO_NR_PALMTC_PCMCIA_READY 13 +#define GPIO_NR_PALMTC_PCMCIA_PWRREADY 14 +#define GPIO_NR_PALMTC_PCMCIA_POWER1 15 +#define GPIO_NR_PALMTC_PCMCIA_POWER2 33 +#define GPIO_NR_PALMTC_PCMCIA_POWER3 55 +#define GPIO_NR_PALMTC_PCMCIA_RESET 78 + +/* UDC */ +#define GPIO_NR_PALMTC_USB_DETECT_N 4 +#define GPIO_NR_PALMTC_USB_POWER 36 + +/* LCD/BACKLIGHT */ +#define GPIO_NR_PALMTC_BL_POWER 16 +#define GPIO_NR_PALMTC_LCD_POWER 44 +#define GPIO_NR_PALMTC_LCD_BLANK 38 + +/* UART */ +#define GPIO_NR_PALMTC_RS232_POWER 37 + +/* IRDA */ +#define GPIO_NR_PALMTC_IR_DISABLE 45 + +/* IRQs */ +#define IRQ_GPIO_PALMTC_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_SD_DETECT_N) +#define IRQ_GPIO_PALMTC_WLAN_READY PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_WLAN_READY) + +/* UCB1400 GPIOs */ +#define GPIO_NR_PALMTC_POWER_DETECT (0x80 | 0x00) +#define GPIO_NR_PALMTC_HEADPHONE_DETECT (0x80 | 0x01) +#define GPIO_NR_PALMTC_SPEAKER_ENABLE (0x80 | 0x03) +#define GPIO_NR_PALMTC_VIBRA_POWER (0x80 | 0x05) +#define GPIO_NR_PALMTC_LED_POWER (0x80 | 0x07) + +/** HERE ARE INIT VALUES **/ +#define PALMTC_UCB1400_GPIO_OFFSET 0x80 + +/* BATTERY */ +#define PALMTC_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */ +#define PALMTC_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */ +#define PALMTC_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMTC_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMTC_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMTC_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMTC_MAX_LIFE_MINS 240 /* on-life in minutes */ + +#define PALMTC_BAT_MEASURE_DELAY (HZ * 1) + +/* BACKLIGHT */ +#define PALMTC_MAX_INTENSITY 0xFE +#define PALMTC_DEFAULT_INTENSITY 0x7E +#define PALMTC_LIMIT_MASK 0x7F +#define PALMTC_PRESCALER 0x3F +#define PALMTC_PERIOD_NS 3500 + +#endif diff --git a/arch/arm/mach-pxa/palmtx-pcmcia.c b/arch/arm/mach-pxa/palmtx-pcmcia.c new file mode 100644 index 000000000000..8c2aaad93043 --- /dev/null +++ b/arch/arm/mach-pxa/palmtx-pcmcia.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/drivers/pcmcia/pxa2xx_palmtx.c + * + * Driver for Palm T|X PCMCIA + * + * Copyright (C) 2007-2011 Marek Vasut + */ + +#include +#include +#include + +#include +#include "palmtx.h" +#include + +static struct gpio palmtx_pcmcia_gpios[] = { + { GPIO_NR_PALMTX_PCMCIA_POWER1, GPIOF_INIT_LOW, "PCMCIA Power 1" }, + { GPIO_NR_PALMTX_PCMCIA_POWER2, GPIOF_INIT_LOW, "PCMCIA Power 2" }, + { GPIO_NR_PALMTX_PCMCIA_RESET, GPIOF_INIT_HIGH,"PCMCIA Reset" }, +}; + +static int palmtx_pcmcia_hw_init(struct soc_pcmcia_socket *skt) +{ + int ret; + + ret = gpio_request_array(palmtx_pcmcia_gpios, + ARRAY_SIZE(palmtx_pcmcia_gpios)); + + skt->stat[SOC_STAT_RDY].gpio = GPIO_NR_PALMTX_PCMCIA_READY; + skt->stat[SOC_STAT_RDY].name = "PCMCIA Ready"; + + return ret; +} + +static void palmtx_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) +{ + gpio_free_array(palmtx_pcmcia_gpios, ARRAY_SIZE(palmtx_pcmcia_gpios)); +} + +static void palmtx_pcmcia_socket_state(struct soc_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + state->detect = 1; /* always inserted */ + state->vs_3v = 1; + state->vs_Xv = 0; +} + +static int +palmtx_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, + const socket_state_t *state) +{ + gpio_set_value(GPIO_NR_PALMTX_PCMCIA_POWER1, 1); + gpio_set_value(GPIO_NR_PALMTX_PCMCIA_POWER2, 1); + gpio_set_value(GPIO_NR_PALMTX_PCMCIA_RESET, + !!(state->flags & SS_RESET)); + + return 0; +} + +static struct pcmcia_low_level palmtx_pcmcia_ops = { + .owner = THIS_MODULE, + + .first = 0, + .nr = 1, + + .hw_init = palmtx_pcmcia_hw_init, + .hw_shutdown = palmtx_pcmcia_hw_shutdown, + + .socket_state = palmtx_pcmcia_socket_state, + .configure_socket = palmtx_pcmcia_configure_socket, +}; + +static struct platform_device *palmtx_pcmcia_device; + +static int __init palmtx_pcmcia_init(void) +{ + int ret; + + if (!machine_is_palmtx()) + return -ENODEV; + + palmtx_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); + if (!palmtx_pcmcia_device) + return -ENOMEM; + + ret = platform_device_add_data(palmtx_pcmcia_device, &palmtx_pcmcia_ops, + sizeof(palmtx_pcmcia_ops)); + + if (!ret) + ret = platform_device_add(palmtx_pcmcia_device); + + if (ret) + platform_device_put(palmtx_pcmcia_device); + + return ret; +} + +static void __exit palmtx_pcmcia_exit(void) +{ + platform_device_unregister(palmtx_pcmcia_device); +} + +module_init(palmtx_pcmcia_init); +module_exit(palmtx_pcmcia_exit); + +MODULE_AUTHOR("Marek Vasut "); +MODULE_DESCRIPTION("PCMCIA support for Palm T|X"); +MODULE_ALIAS("platform:pxa2xx-pcmcia"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index 097b88638863..86460d6ea721 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -33,7 +33,7 @@ #include "pxa27x.h" #include -#include +#include "palmtx.h" #include #include #include diff --git a/arch/arm/mach-pxa/palmtx.h b/arch/arm/mach-pxa/palmtx.h new file mode 100644 index 000000000000..a2bb993952d9 --- /dev/null +++ b/arch/arm/mach-pxa/palmtx.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * GPIOs and interrupts for Palm T|X Handheld Computer + * + * Based on palmld-gpio.h by Alex Osborne + * + * Authors: Marek Vasut + * Cristiano P. + * Jan Herman <2hp@seznam.cz> + */ + +#ifndef _INCLUDE_PALMTX_H_ +#define _INCLUDE_PALMTX_H_ + +#include /* PXA_GPIO_TO_IRQ */ + +/** HERE ARE GPIOs **/ + +/* GPIOs */ +#define GPIO_NR_PALMTX_GPIO_RESET 1 + +#define GPIO_NR_PALMTX_POWER_DETECT 12 /* 90 */ +#define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N 10 +#define GPIO_NR_PALMTX_EARPHONE_DETECT 107 + +/* SD/MMC */ +#define GPIO_NR_PALMTX_SD_DETECT_N 14 +#define GPIO_NR_PALMTX_SD_POWER 114 /* probably */ +#define GPIO_NR_PALMTX_SD_READONLY 115 /* probably */ + +/* TOUCHSCREEN */ +#define GPIO_NR_PALMTX_WM9712_IRQ 27 + +/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ +#define GPIO_NR_PALMTX_IR_DISABLE 40 + +/* USB */ +#define GPIO_NR_PALMTX_USB_DETECT_N 13 +#define GPIO_NR_PALMTX_USB_PULLUP 93 + +/* LCD/BACKLIGHT */ +#define GPIO_NR_PALMTX_BL_POWER 84 +#define GPIO_NR_PALMTX_LCD_POWER 96 + +/* LCD BORDER */ +#define GPIO_NR_PALMTX_BORDER_SWITCH 98 +#define GPIO_NR_PALMTX_BORDER_SELECT 22 + +/* BLUETOOTH */ +#define GPIO_NR_PALMTX_BT_POWER 17 +#define GPIO_NR_PALMTX_BT_RESET 83 + +/* PCMCIA (WiFi) */ +#define GPIO_NR_PALMTX_PCMCIA_POWER1 94 +#define GPIO_NR_PALMTX_PCMCIA_POWER2 108 +#define GPIO_NR_PALMTX_PCMCIA_RESET 79 +#define GPIO_NR_PALMTX_PCMCIA_READY 116 + +/* NAND Flash ... this GPIO may be incorrect! */ +#define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79 + +/* INTERRUPTS */ +#define IRQ_GPIO_PALMTX_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_SD_DETECT_N) +#define IRQ_GPIO_PALMTX_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_WM9712_IRQ) +#define IRQ_GPIO_PALMTX_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_USB_DETECT) +#define IRQ_GPIO_PALMTX_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_GPIO_RESET) + +/** HERE ARE INIT VALUES **/ + +/* Various addresses */ +#define PALMTX_PCMCIA_PHYS 0x28000000 +#define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000) +#define PALMTX_PCMCIA_SIZE 0x100000 + +#define PALMTX_PHYS_RAM_START 0xa0000000 +#define PALMTX_PHYS_IO_START 0x40000000 + +#define PALMTX_STR_BASE 0xa0200000 + +#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */ +#define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */ + +#define PALMTX_NAND_ALE_PHYS (PALMTX_PHYS_NAND_START | (1 << 24)) +#define PALMTX_NAND_CLE_PHYS (PALMTX_PHYS_NAND_START | (1 << 25)) +#define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000) +#define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000) + +/* TOUCHSCREEN */ +#define AC97_LINK_FRAME 21 + + +/* BATTERY */ +#define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ +#define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ +#define PALMTX_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMTX_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMTX_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMTX_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMTX_MAX_LIFE_MINS 360 /* on-life in minutes */ + +#define PALMTX_BAT_MEASURE_DELAY (HZ * 1) + +/* BACKLIGHT */ +#define PALMTX_MAX_INTENSITY 0xFE +#define PALMTX_DEFAULT_INTENSITY 0x7E +#define PALMTX_LIMIT_MASK 0x7F +#define PALMTX_PRESCALER 0x3F +#define PALMTX_PERIOD_NS 3500 + +#endif diff --git a/arch/arm/mach-pxa/trizeps4-pcmcia.c b/arch/arm/mach-pxa/trizeps4-pcmcia.c new file mode 100644 index 000000000000..02d7bb0c538f --- /dev/null +++ b/arch/arm/mach-pxa/trizeps4-pcmcia.c @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/drivers/pcmcia/pxa2xx_trizeps4.c + * + * TRIZEPS PCMCIA specific routines. + * + * Author: Jürgen Schindele + * Created: 20 02, 2006 + * Copyright: Jürgen Schindele + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include "trizeps4.h" + +#include + +extern void board_pcmcia_power(int power); + +static int trizeps_pcmcia_hw_init(struct soc_pcmcia_socket *skt) +{ + /* we dont have voltage/card/ready detection + * so we dont need interrupts for it + */ + switch (skt->nr) { + case 0: + skt->stat[SOC_STAT_CD].gpio = GPIO_PCD; + skt->stat[SOC_STAT_CD].name = "cs0_cd"; + skt->stat[SOC_STAT_RDY].gpio = GPIO_PRDY; + skt->stat[SOC_STAT_RDY].name = "cs0_rdy"; + break; + default: + break; + } + /* release the reset of this card */ + pr_debug("%s: sock %d irq %d\n", __func__, skt->nr, skt->socket.pci_irq); + + return 0; +} + +static unsigned long trizeps_pcmcia_status[2]; + +static void trizeps_pcmcia_socket_state(struct soc_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + unsigned short status = 0, change; + status = CFSR_readw(); + change = (status ^ trizeps_pcmcia_status[skt->nr]) & + ConXS_CFSR_BVD_MASK; + if (change) { + trizeps_pcmcia_status[skt->nr] = status; + if (status & ConXS_CFSR_BVD1) { + /* enable_irq empty */ + } else { + /* disable_irq empty */ + } + } + + switch (skt->nr) { + case 0: + /* just fill in fix states */ + state->bvd1 = (status & ConXS_CFSR_BVD1) ? 1 : 0; + state->bvd2 = (status & ConXS_CFSR_BVD2) ? 1 : 0; + state->vs_3v = (status & ConXS_CFSR_VS1) ? 0 : 1; + state->vs_Xv = (status & ConXS_CFSR_VS2) ? 0 : 1; + break; + +#ifndef CONFIG_MACH_TRIZEPS_CONXS + /* on ConXS we only have one slot. Second is inactive */ + case 1: + state->detect = 0; + state->ready = 0; + state->bvd1 = 0; + state->bvd2 = 0; + state->vs_3v = 0; + state->vs_Xv = 0; + break; + +#endif + } +} + +static int trizeps_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, + const socket_state_t *state) +{ + int ret = 0; + unsigned short power = 0; + + /* we do nothing here just check a bit */ + switch (state->Vcc) { + case 0: power &= 0xfc; break; + case 33: power |= ConXS_BCR_S0_VCC_3V3; break; + case 50: + pr_err("%s(): Vcc 5V not supported in socket\n", __func__); + break; + default: + pr_err("%s(): bad Vcc %u\n", __func__, state->Vcc); + ret = -1; + } + + switch (state->Vpp) { + case 0: power &= 0xf3; break; + case 33: power |= ConXS_BCR_S0_VPP_3V3; break; + case 120: + pr_err("%s(): Vpp 12V not supported in socket\n", __func__); + break; + default: + if (state->Vpp != state->Vcc) { + pr_err("%s(): bad Vpp %u\n", __func__, state->Vpp); + ret = -1; + } + } + + switch (skt->nr) { + case 0: /* we only have 3.3V */ + board_pcmcia_power(power); + break; + +#ifndef CONFIG_MACH_TRIZEPS_CONXS + /* on ConXS we only have one slot. Second is inactive */ + case 1: +#endif + default: + break; + } + + return ret; +} + +static void trizeps_pcmcia_socket_init(struct soc_pcmcia_socket *skt) +{ + /* default is on */ + board_pcmcia_power(0x9); +} + +static void trizeps_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) +{ + board_pcmcia_power(0x0); +} + +static struct pcmcia_low_level trizeps_pcmcia_ops = { + .owner = THIS_MODULE, + .hw_init = trizeps_pcmcia_hw_init, + .socket_state = trizeps_pcmcia_socket_state, + .configure_socket = trizeps_pcmcia_configure_socket, + .socket_init = trizeps_pcmcia_socket_init, + .socket_suspend = trizeps_pcmcia_socket_suspend, +#ifdef CONFIG_MACH_TRIZEPS_CONXS + .nr = 1, +#else + .nr = 2, +#endif + .first = 0, +}; + +static struct platform_device *trizeps_pcmcia_device; + +static int __init trizeps_pcmcia_init(void) +{ + int ret; + + if (!machine_is_trizeps4() && !machine_is_trizeps4wl()) + return -ENODEV; + + trizeps_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); + if (!trizeps_pcmcia_device) + return -ENOMEM; + + ret = platform_device_add_data(trizeps_pcmcia_device, + &trizeps_pcmcia_ops, sizeof(trizeps_pcmcia_ops)); + + if (ret == 0) + ret = platform_device_add(trizeps_pcmcia_device); + + if (ret) + platform_device_put(trizeps_pcmcia_device); + + return ret; +} + +static void __exit trizeps_pcmcia_exit(void) +{ + platform_device_unregister(trizeps_pcmcia_device); +} + +fs_initcall(trizeps_pcmcia_init); +module_exit(trizeps_pcmcia_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Juergen Schindele"); +MODULE_ALIAS("platform:pxa2xx-pcmcia"); diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 1337008cc760..fadfbb40cd6c 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -40,7 +40,7 @@ #include #include "pxa27x.h" -#include +#include "trizeps4.h" #include #include #include diff --git a/arch/arm/mach-pxa/trizeps4.h b/arch/arm/mach-pxa/trizeps4.h new file mode 100644 index 000000000000..7597b9de11e2 --- /dev/null +++ b/arch/arm/mach-pxa/trizeps4.h @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/************************************************************************ + * Include file for TRIZEPS4 SoM and ConXS eval-board + * Copyright (c) Jürgen Schindele + * 2006 + ************************************************************************/ + +/* + * Includes/Defines + */ +#ifndef _TRIPEPS4_H_ +#define _TRIPEPS4_H_ + +#include +#include /* PXA_GPIO_TO_IRQ */ + +/* physical memory regions */ +#define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ +#define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */ +#define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ +#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ +#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ + + /* Logic on ConXS-board CSFR register*/ +#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) + /* Logic on ConXS-board BOCR register*/ +#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) + /* Logic on ConXS-board IRCR register*/ +#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) + /* Logic on ConXS-board UPSR register*/ +#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) + /* Logic on ConXS-board DICR register*/ +#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) + +/* virtual memory regions */ +#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ + +#define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */ +#define TRIZEPS4_CFSR_VIRT 0xF0100000 +#define TRIZEPS4_BOCR_VIRT 0xF0200000 +#define TRIZEPS4_DICR_VIRT 0xF0300000 +#define TRIZEPS4_IRCR_VIRT 0xF0400000 +#define TRIZEPS4_UPSR_VIRT 0xF0500000 + +/* size of flash */ +#define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ + +/* Ethernet Controller Davicom DM9000 */ +#define GPIO_DM9000 101 +#define TRIZEPS4_ETH_IRQ PXA_GPIO_TO_IRQ(GPIO_DM9000) + +/* UCB1400 audio / TS-controller */ +#define GPIO_UCB1400 1 +#define TRIZEPS4_UCB1400_IRQ PXA_GPIO_TO_IRQ(GPIO_UCB1400) + +/* PCMCIA socket Compact Flash */ +#define GPIO_PCD 11 /* PCMCIA Card Detect */ +#define TRIZEPS4_CD_IRQ PXA_GPIO_TO_IRQ(GPIO_PCD) +#define GPIO_PRDY 13 /* READY / nINT */ +#define TRIZEPS4_READY_NINT PXA_GPIO_TO_IRQ(GPIO_PRDY) + +/* MMC socket */ +#define GPIO_MMC_DET 12 +#define TRIZEPS4_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO_MMC_DET) + +/* DOC NAND chip */ +#define GPIO_DOC_LOCK 94 +#define GPIO_DOC_IRQ 93 +#define TRIZEPS4_DOC_IRQ PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ) + +/* SPI interface */ +#define GPIO_SPI 53 +#define TRIZEPS4_SPI_IRQ PXA_GPIO_TO_IRQ(GPIO_SPI) + +/* LEDS using tx2 / rx2 */ +#define GPIO_SYS_BUSY_LED 46 +#define GPIO_HEARTBEAT_LED 47 + +/* Off-module PIC on ConXS board */ +#define GPIO_PIC 0 +#define TRIZEPS4_PIC_IRQ PXA_GPIO_TO_IRQ(GPIO_PIC) + +#ifdef CONFIG_MACH_TRIZEPS_CONXS +/* for CONXS base board define these registers */ +#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) +#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) + +#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) +#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) + +#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) +#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) + +#define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT) +#define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS) + +#ifndef __ASSEMBLY__ +static inline unsigned short CFSR_readw(void) +{ + /* [Compact Flash Status Register] is read only */ + return *((unsigned short *)CFSR_P2V(0x0C000000)); +} +static inline void BCR_writew(unsigned short value) +{ + /* [Board Control Regsiter] is write only */ + *((unsigned short *)BCR_P2V(0x0E000000)) = value; +} +static inline void DCR_writew(unsigned short value) +{ + /* [Display Control Register] is write only */ + *((unsigned short *)DCR_P2V(0x0E000000)) = value; +} +static inline void IRCR_writew(unsigned short value) +{ + /* [InfraRed data Control Register] is write only */ + *((unsigned short *)IRCR_P2V(0x0E000000)) = value; +} +#else +#define ConXS_CFSR CFSR_P2V(0x0C000000) +#define ConXS_BCR BCR_P2V(0x0E000000) +#define ConXS_DCR DCR_P2V(0x0F800000) +#define ConXS_IRCR IRCR_P2V(0x0F800000) +#endif +#else +/* for whatever baseboard define function registers */ +static inline unsigned short CFSR_readw(void) +{ + return 0; +} +static inline void BCR_writew(unsigned short value) +{ + ; +} +static inline void DCR_writew(unsigned short value) +{ + ; +} +static inline void IRCR_writew(unsigned short value) +{ + ; +} +#endif /* CONFIG_MACH_TRIZEPS_CONXS */ + +#define ConXS_CFSR_BVD_MASK 0x0003 +#define ConXS_CFSR_BVD1 (1 << 0) +#define ConXS_CFSR_BVD2 (1 << 1) +#define ConXS_CFSR_VS_MASK 0x000C +#define ConXS_CFSR_VS1 (1 << 2) +#define ConXS_CFSR_VS2 (1 << 3) +#define ConXS_CFSR_VS_5V (0x3 << 2) +#define ConXS_CFSR_VS_3V3 0x0 + +#define ConXS_BCR_S0_POW_EN0 (1 << 0) +#define ConXS_BCR_S0_POW_EN1 (1 << 1) +#define ConXS_BCR_L_DISP (1 << 4) +#define ConXS_BCR_CF_BUF_EN (1 << 5) +#define ConXS_BCR_CF_RESET (1 << 7) +#define ConXS_BCR_S0_VCC_3V3 0x1 +#define ConXS_BCR_S0_VCC_5V0 0x2 +#define ConXS_BCR_S0_VPP_12V 0x4 +#define ConXS_BCR_S0_VPP_3V3 0x8 + +#define ConXS_IRCR_MODE (1 << 0) +#define ConXS_IRCR_SD (1 << 1) + +#endif /* _TRIPEPS4_H_ */ diff --git a/arch/arm/mach-pxa/viper-pcmcia.c b/arch/arm/mach-pxa/viper-pcmcia.c new file mode 100644 index 000000000000..26599dcc49b3 --- /dev/null +++ b/arch/arm/mach-pxa/viper-pcmcia.c @@ -0,0 +1,180 @@ +/* + * Viper/Zeus PCMCIA support + * Copyright 2004 Arcom Control Systems + * + * Maintained by Marc Zyngier + * + * Based on: + * iPAQ h2200 PCMCIA support + * Copyright 2004 Koen Kooi + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "viper-pcmcia.h" + +static struct platform_device *arcom_pcmcia_dev; + +static inline struct arcom_pcmcia_pdata *viper_get_pdata(void) +{ + return arcom_pcmcia_dev->dev.platform_data; +} + +static int viper_pcmcia_hw_init(struct soc_pcmcia_socket *skt) +{ + struct arcom_pcmcia_pdata *pdata = viper_get_pdata(); + unsigned long flags; + + skt->stat[SOC_STAT_CD].gpio = pdata->cd_gpio; + skt->stat[SOC_STAT_CD].name = "PCMCIA_CD"; + skt->stat[SOC_STAT_RDY].gpio = pdata->rdy_gpio; + skt->stat[SOC_STAT_RDY].name = "CF ready"; + + if (gpio_request(pdata->pwr_gpio, "CF power")) + goto err_request_pwr; + + local_irq_save(flags); + + if (gpio_direction_output(pdata->pwr_gpio, 0)) { + local_irq_restore(flags); + goto err_dir; + } + + local_irq_restore(flags); + + return 0; + +err_dir: + gpio_free(pdata->pwr_gpio); +err_request_pwr: + dev_err(&arcom_pcmcia_dev->dev, "Failed to setup PCMCIA GPIOs\n"); + return -1; +} + +/* + * Release all resources. + */ +static void viper_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) +{ + struct arcom_pcmcia_pdata *pdata = viper_get_pdata(); + + gpio_free(pdata->pwr_gpio); +} + +static void viper_pcmcia_socket_state(struct soc_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + state->vs_3v = 1; /* Can only apply 3.3V */ + state->vs_Xv = 0; +} + +static int viper_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, + const socket_state_t *state) +{ + struct arcom_pcmcia_pdata *pdata = viper_get_pdata(); + + /* Silently ignore Vpp, output enable, speaker enable. */ + pdata->reset(state->flags & SS_RESET); + + /* Apply socket voltage */ + switch (state->Vcc) { + case 0: + gpio_set_value(pdata->pwr_gpio, 0); + break; + case 33: + gpio_set_value(pdata->pwr_gpio, 1); + break; + default: + dev_err(&arcom_pcmcia_dev->dev, "Unsupported Vcc:%d\n", state->Vcc); + return -1; + } + + return 0; +} + +static struct pcmcia_low_level viper_pcmcia_ops = { + .owner = THIS_MODULE, + .hw_init = viper_pcmcia_hw_init, + .hw_shutdown = viper_pcmcia_hw_shutdown, + .socket_state = viper_pcmcia_socket_state, + .configure_socket = viper_pcmcia_configure_socket, + .nr = 1, +}; + +static struct platform_device *viper_pcmcia_device; + +static int viper_pcmcia_probe(struct platform_device *pdev) +{ + int ret; + + /* I can't imagine more than one device, but you never know... */ + if (arcom_pcmcia_dev) + return -EEXIST; + + if (!pdev->dev.platform_data) + return -EINVAL; + + viper_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); + if (!viper_pcmcia_device) + return -ENOMEM; + + arcom_pcmcia_dev = pdev; + + viper_pcmcia_device->dev.parent = &pdev->dev; + + ret = platform_device_add_data(viper_pcmcia_device, + &viper_pcmcia_ops, + sizeof(viper_pcmcia_ops)); + + if (!ret) + ret = platform_device_add(viper_pcmcia_device); + + if (ret) { + platform_device_put(viper_pcmcia_device); + arcom_pcmcia_dev = NULL; + } + + return ret; +} + +static int viper_pcmcia_remove(struct platform_device *pdev) +{ + platform_device_unregister(viper_pcmcia_device); + arcom_pcmcia_dev = NULL; + return 0; +} + +static struct platform_device_id viper_pcmcia_id_table[] = { + { .name = "viper-pcmcia", }, + { .name = "zeus-pcmcia", }, + { }, +}; + +static struct platform_driver viper_pcmcia_driver = { + .probe = viper_pcmcia_probe, + .remove = viper_pcmcia_remove, + .driver = { + .name = "arcom-pcmcia", + }, + .id_table = viper_pcmcia_id_table, +}; + +module_platform_driver(viper_pcmcia_driver); + +MODULE_DEVICE_TABLE(platform, viper_pcmcia_id_table); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-pxa/viper-pcmcia.h b/arch/arm/mach-pxa/viper-pcmcia.h new file mode 100644 index 000000000000..a23b58aff9e1 --- /dev/null +++ b/arch/arm/mach-pxa/viper-pcmcia.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ARCOM_PCMCIA_H +#define __ARCOM_PCMCIA_H + +struct arcom_pcmcia_pdata { + int cd_gpio; + int rdy_gpio; + int pwr_gpio; + void (*reset)(int state); +}; + +#endif diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index ac94b10bf8c1..600d9e80b00c 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -49,7 +49,7 @@ #include #include #include "regs-uart.h" -#include +#include "viper-pcmcia.h" #include "viper.h" #include diff --git a/arch/arm/mach-pxa/vpac270-pcmcia.c b/arch/arm/mach-pxa/vpac270-pcmcia.c new file mode 100644 index 000000000000..9fd990c8a5fb --- /dev/null +++ b/arch/arm/mach-pxa/vpac270-pcmcia.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/drivers/pcmcia/pxa2xx_vpac270.c + * + * Driver for Voipac PXA270 PCMCIA and CF sockets + * + * Copyright (C) 2010-2011 Marek Vasut + */ + +#include +#include +#include + +#include + +#include "vpac270.h" + +#include + +static struct gpio vpac270_pcmcia_gpios[] = { + { GPIO107_VPAC270_PCMCIA_PPEN, GPIOF_INIT_LOW, "PCMCIA PPEN" }, + { GPIO11_VPAC270_PCMCIA_RESET, GPIOF_INIT_LOW, "PCMCIA Reset" }, +}; + +static struct gpio vpac270_cf_gpios[] = { + { GPIO16_VPAC270_CF_RESET, GPIOF_INIT_LOW, "CF Reset" }, +}; + +static int vpac270_pcmcia_hw_init(struct soc_pcmcia_socket *skt) +{ + int ret; + + if (skt->nr == 0) { + ret = gpio_request_array(vpac270_pcmcia_gpios, + ARRAY_SIZE(vpac270_pcmcia_gpios)); + + skt->stat[SOC_STAT_CD].gpio = GPIO84_VPAC270_PCMCIA_CD; + skt->stat[SOC_STAT_CD].name = "PCMCIA CD"; + skt->stat[SOC_STAT_RDY].gpio = GPIO35_VPAC270_PCMCIA_RDY; + skt->stat[SOC_STAT_RDY].name = "PCMCIA Ready"; + } else { + ret = gpio_request_array(vpac270_cf_gpios, + ARRAY_SIZE(vpac270_cf_gpios)); + + skt->stat[SOC_STAT_CD].gpio = GPIO17_VPAC270_CF_CD; + skt->stat[SOC_STAT_CD].name = "CF CD"; + skt->stat[SOC_STAT_RDY].gpio = GPIO12_VPAC270_CF_RDY; + skt->stat[SOC_STAT_RDY].name = "CF Ready"; + } + + return ret; +} + +static void vpac270_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) +{ + if (skt->nr == 0) + gpio_free_array(vpac270_pcmcia_gpios, + ARRAY_SIZE(vpac270_pcmcia_gpios)); + else + gpio_free_array(vpac270_cf_gpios, + ARRAY_SIZE(vpac270_cf_gpios)); +} + +static void vpac270_pcmcia_socket_state(struct soc_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + state->vs_3v = 1; + state->vs_Xv = 0; +} + +static int +vpac270_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, + const socket_state_t *state) +{ + if (skt->nr == 0) { + gpio_set_value(GPIO11_VPAC270_PCMCIA_RESET, + (state->flags & SS_RESET)); + gpio_set_value(GPIO107_VPAC270_PCMCIA_PPEN, + !(state->Vcc == 33 || state->Vcc == 50)); + } else { + gpio_set_value(GPIO16_VPAC270_CF_RESET, + (state->flags & SS_RESET)); + } + + return 0; +} + +static struct pcmcia_low_level vpac270_pcmcia_ops = { + .owner = THIS_MODULE, + + .first = 0, + .nr = 2, + + .hw_init = vpac270_pcmcia_hw_init, + .hw_shutdown = vpac270_pcmcia_hw_shutdown, + + .socket_state = vpac270_pcmcia_socket_state, + .configure_socket = vpac270_pcmcia_configure_socket, +}; + +static struct platform_device *vpac270_pcmcia_device; + +static int __init vpac270_pcmcia_init(void) +{ + int ret; + + if (!machine_is_vpac270()) + return -ENODEV; + + vpac270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); + if (!vpac270_pcmcia_device) + return -ENOMEM; + + ret = platform_device_add_data(vpac270_pcmcia_device, + &vpac270_pcmcia_ops, sizeof(vpac270_pcmcia_ops)); + + if (!ret) + ret = platform_device_add(vpac270_pcmcia_device); + + if (ret) + platform_device_put(vpac270_pcmcia_device); + + return ret; +} + +static void __exit vpac270_pcmcia_exit(void) +{ + platform_device_unregister(vpac270_pcmcia_device); +} + +module_init(vpac270_pcmcia_init); +module_exit(vpac270_pcmcia_exit); + +MODULE_AUTHOR("Marek Vasut "); +MODULE_DESCRIPTION("PCMCIA support for Voipac PXA270"); +MODULE_ALIAS("platform:pxa2xx-pcmcia"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index 7067d1464689..8f74bafcf1f9 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c @@ -30,7 +30,7 @@ #include "pxa27x.h" #include -#include +#include "vpac270.h" #include #include #include diff --git a/arch/arm/mach-pxa/vpac270.h b/arch/arm/mach-pxa/vpac270.h new file mode 100644 index 000000000000..0cd094d8c553 --- /dev/null +++ b/arch/arm/mach-pxa/vpac270.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * GPIOs and interrupts for Voipac PXA270 + * + * Copyright (C) 2010 + * Marek Vasut + */ + +#ifndef _INCLUDE_VPAC270_H_ +#define _INCLUDE_VPAC270_H_ + +#define GPIO1_VPAC270_USER_BTN 1 + +#define GPIO15_VPAC270_LED_ORANGE 15 + +#define GPIO81_VPAC270_BKL_ON 81 +#define GPIO83_VPAC270_NL_ON 83 + +#define GPIO52_VPAC270_SD_READONLY 52 +#define GPIO53_VPAC270_SD_DETECT_N 53 + +#define GPIO84_VPAC270_PCMCIA_CD 84 +#define GPIO35_VPAC270_PCMCIA_RDY 35 +#define GPIO107_VPAC270_PCMCIA_PPEN 107 +#define GPIO11_VPAC270_PCMCIA_RESET 11 +#define GPIO17_VPAC270_CF_CD 17 +#define GPIO12_VPAC270_CF_RDY 12 +#define GPIO16_VPAC270_CF_RESET 16 + +#define GPIO41_VPAC270_UDC_DETECT 41 + +#define GPIO114_VPAC270_ETH_IRQ 114 + +#define GPIO36_VPAC270_IDE_IRQ 36 + +#define GPIO113_VPAC270_TS_IRQ 113 + +#endif diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 67396e85bb66..2e6c8d156d77 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -47,7 +47,7 @@ #include #include "pm.h" #include -#include +#include "viper-pcmcia.h" #include "zeus.h" #include -- cgit From 225b5d376e53543a66fc9b824a05cfcdf74c763a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 10 Sep 2019 22:22:03 +0200 Subject: ARM: pxa: make addr-map.h header local Drivers should not rely on the contents of this file, so move it into the platform directory directly. Cc: Philipp Zabel Cc: Paul Parsons Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/lkml/87mudkmx8g.fsf@belgarion.home/ --- arch/arm/mach-pxa/addr-map.h | 61 +++++++++++++++++++++++++++++++ arch/arm/mach-pxa/generic.c | 2 +- arch/arm/mach-pxa/hx4700.c | 2 +- arch/arm/mach-pxa/include/mach/addr-map.h | 61 ------------------------------- arch/arm/mach-pxa/lpd270.c | 2 +- arch/arm/mach-pxa/magician.c | 2 +- arch/arm/mach-pxa/mainstone.c | 2 +- arch/arm/mach-pxa/pxa25x.c | 2 +- arch/arm/mach-pxa/pxa25x.h | 2 +- arch/arm/mach-pxa/pxa27x.c | 2 +- arch/arm/mach-pxa/pxa27x.h | 2 +- arch/arm/mach-pxa/pxa3xx.c | 2 +- arch/arm/mach-pxa/pxa3xx.h | 2 +- arch/arm/mach-pxa/trizeps4.h | 2 +- arch/arm/mach-pxa/xcep.c | 2 +- 15 files changed, 74 insertions(+), 74 deletions(-) create mode 100644 arch/arm/mach-pxa/addr-map.h delete mode 100644 arch/arm/mach-pxa/include/mach/addr-map.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/addr-map.h b/arch/arm/mach-pxa/addr-map.h new file mode 100644 index 000000000000..93cfe7dbfec6 --- /dev/null +++ b/arch/arm/mach-pxa/addr-map.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_ADDR_MAP_H +#define __ASM_MACH_ADDR_MAP_H + +/* + * Chip Selects + */ +#define PXA_CS0_PHYS 0x00000000 +#define PXA_CS1_PHYS 0x04000000 +#define PXA_CS2_PHYS 0x08000000 +#define PXA_CS3_PHYS 0x0C000000 +#define PXA_CS4_PHYS 0x10000000 +#define PXA_CS5_PHYS 0x14000000 + +#define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */ +#define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */ +#define PXA3xx_CS2_PHYS 0x10000000 +#define PXA3xx_CS3_PHYS 0x14000000 + +/* + * Peripheral Bus + */ +#define PERIPH_PHYS 0x40000000 +#define PERIPH_VIRT IOMEM(0xf2000000) +#define PERIPH_SIZE 0x02000000 + +/* + * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x) + */ +#define PXA2XX_SMEMC_PHYS 0x48000000 +#define PXA3XX_SMEMC_PHYS 0x4a000000 +#define SMEMC_VIRT IOMEM(0xf6000000) +#define SMEMC_SIZE 0x00100000 + +/* + * Dynamic Memory Controller (only on PXA3xx) + */ +#define DMEMC_PHYS 0x48100000 +#define DMEMC_VIRT IOMEM(0xf6100000) +#define DMEMC_SIZE 0x00100000 + +/* + * Reserved space for low level debug virtual addresses within + * 0xf6200000..0xf6201000 + */ + +/* + * DFI Bus for NAND, PXA3xx only + */ +#define NAND_PHYS 0x43100000 +#define NAND_VIRT IOMEM(0xf6300000) +#define NAND_SIZE 0x00100000 + +/* + * Internal Memory Controller (PXA27x and later) + */ +#define IMEMC_PHYS 0x58000000 +#define IMEMC_VIRT IOMEM(0xfe000000) +#define IMEMC_SIZE 0x00100000 + +#endif /* __ASM_MACH_ADDR_MAP_H */ diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 3c3cd90bb9b4..f9083c4f0aea 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -22,7 +22,7 @@ #include #include -#include +#include "addr-map.h" #include #include #include diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 191a6c24fe19..140a44cb2989 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -40,7 +40,7 @@ #include #include "pxa27x.h" -#include +#include "addr-map.h" #include #include diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/include/mach/addr-map.h deleted file mode 100644 index 93cfe7dbfec6..000000000000 --- a/arch/arm/mach-pxa/include/mach/addr-map.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_MACH_ADDR_MAP_H -#define __ASM_MACH_ADDR_MAP_H - -/* - * Chip Selects - */ -#define PXA_CS0_PHYS 0x00000000 -#define PXA_CS1_PHYS 0x04000000 -#define PXA_CS2_PHYS 0x08000000 -#define PXA_CS3_PHYS 0x0C000000 -#define PXA_CS4_PHYS 0x10000000 -#define PXA_CS5_PHYS 0x14000000 - -#define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */ -#define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */ -#define PXA3xx_CS2_PHYS 0x10000000 -#define PXA3xx_CS3_PHYS 0x14000000 - -/* - * Peripheral Bus - */ -#define PERIPH_PHYS 0x40000000 -#define PERIPH_VIRT IOMEM(0xf2000000) -#define PERIPH_SIZE 0x02000000 - -/* - * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x) - */ -#define PXA2XX_SMEMC_PHYS 0x48000000 -#define PXA3XX_SMEMC_PHYS 0x4a000000 -#define SMEMC_VIRT IOMEM(0xf6000000) -#define SMEMC_SIZE 0x00100000 - -/* - * Dynamic Memory Controller (only on PXA3xx) - */ -#define DMEMC_PHYS 0x48100000 -#define DMEMC_VIRT IOMEM(0xf6100000) -#define DMEMC_SIZE 0x00100000 - -/* - * Reserved space for low level debug virtual addresses within - * 0xf6200000..0xf6201000 - */ - -/* - * DFI Bus for NAND, PXA3xx only - */ -#define NAND_PHYS 0x43100000 -#define NAND_VIRT IOMEM(0xf6300000) -#define NAND_SIZE 0x00100000 - -/* - * Internal Memory Controller (PXA27x and later) - */ -#define IMEMC_PHYS 0x58000000 -#define IMEMC_VIRT IOMEM(0xfe000000) -#define IMEMC_SIZE 0x00100000 - -#endif /* __ASM_MACH_ADDR_MAP_H */ diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 7f10b86f85fd..e03436710752 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -38,7 +38,7 @@ #include "pxa27x.h" #include "lpd270.h" -#include +#include "addr-map.h" #include #include #include diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 345a44d15a2c..20ca3e28c7fb 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -34,7 +34,7 @@ #include #include "pxa27x.h" -#include +#include "addr-map.h" #include #include #include diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index c8200fc2159d..f0072e63b456 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -51,7 +51,7 @@ #include #include #include -#include +#include "addr-map.h" #include #include "generic.h" diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index dfc90b41fba3..8d21c7eef1d2 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -34,7 +34,7 @@ #include "pxa25x.h" #include #include "pm.h" -#include +#include "addr-map.h" #include #include "generic.h" diff --git a/arch/arm/mach-pxa/pxa25x.h b/arch/arm/mach-pxa/pxa25x.h index 403bc16c2ed2..4699ebf7b486 100644 --- a/arch/arm/mach-pxa/pxa25x.h +++ b/arch/arm/mach-pxa/pxa25x.h @@ -2,7 +2,7 @@ #ifndef __MACH_PXA25x_H #define __MACH_PXA25x_H -#include +#include "addr-map.h" #include #include "mfp-pxa25x.h" #include diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 38fdd22c4dc5..c36a9784fab8 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -33,7 +33,7 @@ #include #include #include "pm.h" -#include +#include "addr-map.h" #include #include "generic.h" diff --git a/arch/arm/mach-pxa/pxa27x.h b/arch/arm/mach-pxa/pxa27x.h index 6c99090647d2..bf2755561fe5 100644 --- a/arch/arm/mach-pxa/pxa27x.h +++ b/arch/arm/mach-pxa/pxa27x.h @@ -3,7 +3,7 @@ #define __MACH_PXA27x_H #include -#include +#include "addr-map.h" #include #include "mfp-pxa27x.h" #include diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 7c569fa2a6da..7881888107c7 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -32,7 +32,7 @@ #include #include #include "pm.h" -#include +#include "addr-map.h" #include #include diff --git a/arch/arm/mach-pxa/pxa3xx.h b/arch/arm/mach-pxa/pxa3xx.h index 22ace053ea25..6b424d328680 100644 --- a/arch/arm/mach-pxa/pxa3xx.h +++ b/arch/arm/mach-pxa/pxa3xx.h @@ -2,7 +2,7 @@ #ifndef __MACH_PXA3XX_H #define __MACH_PXA3XX_H -#include +#include "addr-map.h" #include #include diff --git a/arch/arm/mach-pxa/trizeps4.h b/arch/arm/mach-pxa/trizeps4.h index 7597b9de11e2..e0f37c0ff06f 100644 --- a/arch/arm/mach-pxa/trizeps4.h +++ b/arch/arm/mach-pxa/trizeps4.h @@ -11,7 +11,7 @@ #ifndef _TRIPEPS4_H_ #define _TRIPEPS4_H_ -#include +#include "addr-map.h" #include /* PXA_GPIO_TO_IRQ */ /* physical memory regions */ diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c index e6ab428287ae..7389e0199144 100644 --- a/arch/arm/mach-pxa/xcep.c +++ b/arch/arm/mach-pxa/xcep.c @@ -25,7 +25,7 @@ #include #include "pxa25x.h" -#include +#include "addr-map.h" #include #include "generic.h" -- cgit From 57bf0f5a162d386cc1a33f8dd492bb7a2cf8e8ac Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 11 Sep 2019 09:36:03 +0200 Subject: ARM: pxa: use pdev resource for palmld mmio The palmld header is almost unused in drivers, the only remaining thing now is the PATA device address, which should really be passed as a resource. Cc: linux-ide@vger.kernel.org Acked-by: Robert Jarzmik Acked-by: Bartlomiej Zolnierkiewicz Acked-by: Damien Le Moal Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/include/mach/palmld.h | 107 -------------------------------- arch/arm/mach-pxa/palmld-pcmcia.c | 3 +- arch/arm/mach-pxa/palmld.c | 12 +++- arch/arm/mach-pxa/palmld.h | 107 ++++++++++++++++++++++++++++++++ 4 files changed, 118 insertions(+), 111 deletions(-) delete mode 100644 arch/arm/mach-pxa/include/mach/palmld.h create mode 100644 arch/arm/mach-pxa/palmld.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/palmld.h b/arch/arm/mach-pxa/include/mach/palmld.h deleted file mode 100644 index 99a6d8b3a1e3..000000000000 --- a/arch/arm/mach-pxa/include/mach/palmld.h +++ /dev/null @@ -1,107 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIOs and interrupts for Palm LifeDrive Handheld Computer - * - * Authors: Alex Osborne - * Marek Vasut - */ - -#ifndef _INCLUDE_PALMLD_H_ -#define _INCLUDE_PALMLD_H_ - -#include "irqs.h" /* PXA_GPIO_TO_IRQ */ - -/** HERE ARE GPIOs **/ - -/* GPIOs */ -#define GPIO_NR_PALMLD_GPIO_RESET 1 -#define GPIO_NR_PALMLD_POWER_DETECT 4 -#define GPIO_NR_PALMLD_HOTSYNC_BUTTON_N 10 -#define GPIO_NR_PALMLD_POWER_SWITCH 12 -#define GPIO_NR_PALMLD_EARPHONE_DETECT 13 -#define GPIO_NR_PALMLD_LOCK_SWITCH 15 - -/* SD/MMC */ -#define GPIO_NR_PALMLD_SD_DETECT_N 14 -#define GPIO_NR_PALMLD_SD_POWER 114 -#define GPIO_NR_PALMLD_SD_READONLY 116 - -/* TOUCHSCREEN */ -#define GPIO_NR_PALMLD_WM9712_IRQ 27 - -/* IRDA */ -#define GPIO_NR_PALMLD_IR_DISABLE 108 - -/* LCD/BACKLIGHT */ -#define GPIO_NR_PALMLD_BL_POWER 19 -#define GPIO_NR_PALMLD_LCD_POWER 96 - -/* LCD BORDER */ -#define GPIO_NR_PALMLD_BORDER_SWITCH 21 -#define GPIO_NR_PALMLD_BORDER_SELECT 22 - -/* BLUETOOTH */ -#define GPIO_NR_PALMLD_BT_POWER 17 -#define GPIO_NR_PALMLD_BT_RESET 83 - -/* PCMCIA (WiFi) */ -#define GPIO_NR_PALMLD_PCMCIA_READY 38 -#define GPIO_NR_PALMLD_PCMCIA_POWER 36 -#define GPIO_NR_PALMLD_PCMCIA_RESET 81 - -/* LEDs */ -#define GPIO_NR_PALMLD_LED_GREEN 52 -#define GPIO_NR_PALMLD_LED_AMBER 94 - -/* IDE */ -#define GPIO_NR_PALMLD_IDE_RESET 98 -#define GPIO_NR_PALMLD_IDE_PWEN 115 - -/* USB */ -#define GPIO_NR_PALMLD_USB_DETECT_N 3 -#define GPIO_NR_PALMLD_USB_READY 86 -#define GPIO_NR_PALMLD_USB_RESET 88 -#define GPIO_NR_PALMLD_USB_INT 106 -#define GPIO_NR_PALMLD_USB_POWER 118 -/* 20, 53 and 86 are usb related too */ - -/* INTERRUPTS */ -#define IRQ_GPIO_PALMLD_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_GPIO_RESET) -#define IRQ_GPIO_PALMLD_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_SD_DETECT_N) -#define IRQ_GPIO_PALMLD_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_WM9712_IRQ) -#define IRQ_GPIO_PALMLD_IDE_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_IDE_IRQ) - - -/** HERE ARE INIT VALUES **/ - -/* IO mappings */ -#define PALMLD_USB_PHYS PXA_CS2_PHYS -#define PALMLD_USB_VIRT 0xf0000000 -#define PALMLD_USB_SIZE 0x00100000 - -#define PALMLD_IDE_PHYS 0x20000000 -#define PALMLD_IDE_VIRT 0xf1000000 -#define PALMLD_IDE_SIZE 0x00100000 - -#define PALMLD_PHYS_IO_START 0x40000000 -#define PALMLD_STR_BASE 0xa0200000 - -/* BATTERY */ -#define PALMLD_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */ -#define PALMLD_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */ -#define PALMLD_BAT_MAX_CURRENT 0 /* unknown */ -#define PALMLD_BAT_MIN_CURRENT 0 /* unknown */ -#define PALMLD_BAT_MAX_CHARGE 1 /* unknown */ -#define PALMLD_BAT_MIN_CHARGE 1 /* unknown */ -#define PALMLD_MAX_LIFE_MINS 240 /* on-life in minutes */ - -#define PALMLD_BAT_MEASURE_DELAY (HZ * 1) - -/* BACKLIGHT */ -#define PALMLD_MAX_INTENSITY 0xFE -#define PALMLD_DEFAULT_INTENSITY 0x7E -#define PALMLD_LIMIT_MASK 0x7F -#define PALMLD_PRESCALER 0x3F -#define PALMLD_PERIOD_NS 3500 - -#endif diff --git a/arch/arm/mach-pxa/palmld-pcmcia.c b/arch/arm/mach-pxa/palmld-pcmcia.c index 07e0f7438db1..720294a50864 100644 --- a/arch/arm/mach-pxa/palmld-pcmcia.c +++ b/arch/arm/mach-pxa/palmld-pcmcia.c @@ -13,9 +13,10 @@ #include #include -#include #include +#include "palmld.h" + static struct gpio palmld_pcmcia_gpios[] = { { GPIO_NR_PALMLD_PCMCIA_POWER, GPIOF_INIT_LOW, "PCMCIA Power" }, { GPIO_NR_PALMLD_PCMCIA_RESET, GPIOF_INIT_HIGH,"PCMCIA Reset" }, diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index d85146957004..d821606ce0b5 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -29,8 +29,8 @@ #include #include "pxa27x.h" +#include "palmld.h" #include -#include #include #include #include @@ -279,9 +279,15 @@ static inline void palmld_leds_init(void) {} * HDD ******************************************************************************/ #if defined(CONFIG_PATA_PALMLD) || defined(CONFIG_PATA_PALMLD_MODULE) +static struct resource palmld_ide_resources[] = { + DEFINE_RES_MEM(PALMLD_IDE_PHYS, 0x1000), +}; + static struct platform_device palmld_ide_device = { - .name = "pata_palmld", - .id = -1, + .name = "pata_palmld", + .id = -1, + .resource = palmld_ide_resources, + .num_resources = ARRAY_SIZE(palmld_ide_resources), }; static struct gpiod_lookup_table palmld_ide_gpio_table = { diff --git a/arch/arm/mach-pxa/palmld.h b/arch/arm/mach-pxa/palmld.h new file mode 100644 index 000000000000..ee3bc15b71a2 --- /dev/null +++ b/arch/arm/mach-pxa/palmld.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * GPIOs and interrupts for Palm LifeDrive Handheld Computer + * + * Authors: Alex Osborne + * Marek Vasut + */ + +#ifndef _INCLUDE_PALMLD_H_ +#define _INCLUDE_PALMLD_H_ + +#include /* PXA_GPIO_TO_IRQ */ + +/** HERE ARE GPIOs **/ + +/* GPIOs */ +#define GPIO_NR_PALMLD_GPIO_RESET 1 +#define GPIO_NR_PALMLD_POWER_DETECT 4 +#define GPIO_NR_PALMLD_HOTSYNC_BUTTON_N 10 +#define GPIO_NR_PALMLD_POWER_SWITCH 12 +#define GPIO_NR_PALMLD_EARPHONE_DETECT 13 +#define GPIO_NR_PALMLD_LOCK_SWITCH 15 + +/* SD/MMC */ +#define GPIO_NR_PALMLD_SD_DETECT_N 14 +#define GPIO_NR_PALMLD_SD_POWER 114 +#define GPIO_NR_PALMLD_SD_READONLY 116 + +/* TOUCHSCREEN */ +#define GPIO_NR_PALMLD_WM9712_IRQ 27 + +/* IRDA */ +#define GPIO_NR_PALMLD_IR_DISABLE 108 + +/* LCD/BACKLIGHT */ +#define GPIO_NR_PALMLD_BL_POWER 19 +#define GPIO_NR_PALMLD_LCD_POWER 96 + +/* LCD BORDER */ +#define GPIO_NR_PALMLD_BORDER_SWITCH 21 +#define GPIO_NR_PALMLD_BORDER_SELECT 22 + +/* BLUETOOTH */ +#define GPIO_NR_PALMLD_BT_POWER 17 +#define GPIO_NR_PALMLD_BT_RESET 83 + +/* PCMCIA (WiFi) */ +#define GPIO_NR_PALMLD_PCMCIA_READY 38 +#define GPIO_NR_PALMLD_PCMCIA_POWER 36 +#define GPIO_NR_PALMLD_PCMCIA_RESET 81 + +/* LEDs */ +#define GPIO_NR_PALMLD_LED_GREEN 52 +#define GPIO_NR_PALMLD_LED_AMBER 94 + +/* IDE */ +#define GPIO_NR_PALMLD_IDE_RESET 98 +#define GPIO_NR_PALMLD_IDE_PWEN 115 + +/* USB */ +#define GPIO_NR_PALMLD_USB_DETECT_N 3 +#define GPIO_NR_PALMLD_USB_READY 86 +#define GPIO_NR_PALMLD_USB_RESET 88 +#define GPIO_NR_PALMLD_USB_INT 106 +#define GPIO_NR_PALMLD_USB_POWER 118 +/* 20, 53 and 86 are usb related too */ + +/* INTERRUPTS */ +#define IRQ_GPIO_PALMLD_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_GPIO_RESET) +#define IRQ_GPIO_PALMLD_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_SD_DETECT_N) +#define IRQ_GPIO_PALMLD_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_WM9712_IRQ) +#define IRQ_GPIO_PALMLD_IDE_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_IDE_IRQ) + + +/** HERE ARE INIT VALUES **/ + +/* IO mappings */ +#define PALMLD_USB_PHYS PXA_CS2_PHYS +#define PALMLD_USB_VIRT 0xf0000000 +#define PALMLD_USB_SIZE 0x00100000 + +#define PALMLD_IDE_PHYS 0x20000000 +#define PALMLD_IDE_VIRT 0xf1000000 +#define PALMLD_IDE_SIZE 0x00100000 + +#define PALMLD_PHYS_IO_START 0x40000000 +#define PALMLD_STR_BASE 0xa0200000 + +/* BATTERY */ +#define PALMLD_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */ +#define PALMLD_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */ +#define PALMLD_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMLD_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMLD_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMLD_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMLD_MAX_LIFE_MINS 240 /* on-life in minutes */ + +#define PALMLD_BAT_MEASURE_DELAY (HZ * 1) + +/* BACKLIGHT */ +#define PALMLD_MAX_INTENSITY 0xFE +#define PALMLD_DEFAULT_INTENSITY 0x7E +#define PALMLD_LIMIT_MASK 0x7F +#define PALMLD_PRESCALER 0x3F +#define PALMLD_PERIOD_NS 3500 + +#endif -- cgit From 2672a4bff6c03a20d5ae460a091f67ee782c3eff Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 11 Sep 2019 22:31:51 +0200 Subject: ARM: pxa: maybe fix gpio lookup tables From inspection I found a couple of GPIO lookups that are listed with device "gpio-pxa", but actually have a number from a different gpio controller. Try to rectify that here, with a guess of what the actual device name is. Acked-by: Robert Jarzmik Reviewed-by: Linus Walleij Cc: stable@vger.kernel.org Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/cm-x300.c | 8 ++++---- arch/arm/mach-pxa/magician.c | 2 +- arch/arm/mach-pxa/tosa.c | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 09a5264a27c8..01f364a66446 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -356,13 +356,13 @@ static struct platform_device cm_x300_spi_gpio = { static struct gpiod_lookup_table cm_x300_spi_gpiod_table = { .dev_id = "spi_gpio", .table = { - GPIO_LOOKUP("gpio-pxa", GPIO_LCD_SCL, + GPIO_LOOKUP("pca9555.1", GPIO_LCD_SCL - GPIO_LCD_BASE, "sck", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("gpio-pxa", GPIO_LCD_DIN, + GPIO_LOOKUP("pca9555.1", GPIO_LCD_DIN - GPIO_LCD_BASE, "mosi", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("gpio-pxa", GPIO_LCD_DOUT, + GPIO_LOOKUP("pca9555.1", GPIO_LCD_DOUT - GPIO_LCD_BASE, "miso", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("gpio-pxa", GPIO_LCD_CS, + GPIO_LOOKUP("pca9555.1", GPIO_LCD_CS - GPIO_LCD_BASE, "cs", GPIO_ACTIVE_HIGH), { }, }, diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 20ca3e28c7fb..d105deb1e098 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -681,7 +681,7 @@ static struct platform_device bq24022 = { static struct gpiod_lookup_table bq24022_gpiod_table = { .dev_id = "gpio-regulator", .table = { - GPIO_LOOKUP("gpio-pxa", EGPIO_MAGICIAN_BQ24022_ISET2, + GPIO_LOOKUP("htc-egpio-0", EGPIO_MAGICIAN_BQ24022_ISET2 - MAGICIAN_EGPIO_BASE, NULL, GPIO_ACTIVE_HIGH), GPIO_LOOKUP("gpio-pxa", GPIO30_MAGICIAN_BQ24022_nCHARGE_EN, "enable", GPIO_ACTIVE_LOW), diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 5af980d77d39..9476ed0f55e9 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -296,9 +296,9 @@ static struct gpiod_lookup_table tosa_mci_gpio_table = { .table = { GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_nSD_DETECT, "cd", GPIO_ACTIVE_LOW), - GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_SD_WP, + GPIO_LOOKUP("sharp-scoop.0", TOSA_GPIO_SD_WP - TOSA_SCOOP_GPIO_BASE, "wp", GPIO_ACTIVE_LOW), - GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_PWR_ON, + GPIO_LOOKUP("sharp-scoop.0", TOSA_GPIO_PWR_ON - TOSA_SCOOP_GPIO_BASE, "power", GPIO_ACTIVE_HIGH), { }, }, -- cgit From 813c2aee51dd7d7d9092251851e33f66719513cc Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 7 May 2022 14:33:31 +0200 Subject: ARM/pxa/mfd/power/sound: Switch Tosa to GPIO descriptors The Tosa device (Sharp SL-6000) has a mishmash driver set-up for the Toshiba TC6393xb MFD that includes a battery charger and touchscreen and has some kind of relationship to the SoC sound driver for the AC97 codec. Other devices define a chip like this but seem only half-implemented, not really handling battery charging etc. This patch switches the Toshiba MFD device to provide GPIO descriptors to the battery charger and SoC codec. As a result some descriptors need to be moved out of the Tosa boardfile and new one added: all SoC GPIO resources to these drivers now comes from the main boardfile, while the MFD provide GPIOs for its portions. As a result we can request one GPIO from our own GPIO chip and drop two hairy callbacks into the board file. This platform badly needs to have its drivers split up and converted to device tree probing to handle this quite complex relationship in an orderly manner. I just do my best in solving the GPIO descriptor part of the puzzle. Please don't ask me to fix everything that is wrong with these driver to todays standards, I am just trying to fix one aspect. I do try to use modern devres resource management and handle deferred probe using new functions where appropriate. Cc: Dmitry Eremin-Solenikov Cc: Dirk Opfer Cc: Robert Jarzmik Cc: Daniel Mack Cc: Haojian Zhuang Cc: Lee Jones Cc: Liam Girdwood Reviewed-by: Dmitry Baryshkov Acked-by: Mark Brown Acked-by: Sebastian Reichel Signed-off-by: Linus Walleij Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/eseries.c | 2 -- arch/arm/mach-pxa/include/mach/tosa.h | 18 ---------- arch/arm/mach-pxa/tosa.c | 68 ++++++++++------------------------- 3 files changed, 18 insertions(+), 70 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index a8b6483ff665..1e9d6bbf4555 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -699,7 +699,6 @@ static struct tc6393xb_platform_data e750_tc6393xb_info = { .irq_base = IRQ_BOARD_START, .scr_pll2cr = 0x0cc1, .scr_gper = 0, - .gpio_base = -1, .suspend = &eseries_tmio_suspend, .resume = &eseries_tmio_resume, .enable = &eseries_tmio_enable, @@ -918,7 +917,6 @@ static struct tc6393xb_platform_data e800_tc6393xb_info = { .irq_base = IRQ_BOARD_START, .scr_pll2cr = 0x0cc1, .scr_gper = 0, - .gpio_base = -1, .suspend = &eseries_tmio_suspend, .resume = &eseries_tmio_resume, .enable = &eseries_tmio_enable, diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h index 8bfaca3a8b64..3b3efa0a0e22 100644 --- a/arch/arm/mach-pxa/include/mach/tosa.h +++ b/arch/arm/mach-pxa/include/mach/tosa.h @@ -54,24 +54,6 @@ /* GPIO Direction 1 : output mode / 0:input mode */ #define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL) -/* - * TC6393XB GPIOs - */ -#define TOSA_TC6393XB_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 2 * 12) - -#define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0) -#define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1) -#define TOSA_GPIO_BL_C20MA (TOSA_TC6393XB_GPIO_BASE + 3) -#define TOSA_GPIO_CARD_VCC_ON (TOSA_TC6393XB_GPIO_BASE + 4) -#define TOSA_GPIO_CHARGE_OFF (TOSA_TC6393XB_GPIO_BASE + 6) -#define TOSA_GPIO_CHARGE_OFF_JC (TOSA_TC6393XB_GPIO_BASE + 7) -#define TOSA_GPIO_BAT0_V_ON (TOSA_TC6393XB_GPIO_BASE + 9) -#define TOSA_GPIO_BAT1_V_ON (TOSA_TC6393XB_GPIO_BASE + 10) -#define TOSA_GPIO_BU_CHRG_ON (TOSA_TC6393XB_GPIO_BASE + 11) -#define TOSA_GPIO_BAT_SW_ON (TOSA_TC6393XB_GPIO_BASE + 12) -#define TOSA_GPIO_BAT0_TH_ON (TOSA_TC6393XB_GPIO_BASE + 14) -#define TOSA_GPIO_BAT1_TH_ON (TOSA_TC6393XB_GPIO_BASE + 15) - /* * PXA GPIOs */ diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 9476ed0f55e9..ee0e38a8f96e 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -616,6 +616,22 @@ static struct resource tc6393xb_resources[] = { }, }; +static struct gpiod_lookup_table tosa_battery_gpio_table = { + .dev_id = "wm97xx-battery", + .table = { + GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_BAT0_CRG, + "main battery full", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_BAT1_CRG, + "jacket battery full", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_BAT0_LOW, + "main battery low", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_BAT1_LOW, + "jacket battery low", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_JACKET_DETECT, + "jacket detect", GPIO_ACTIVE_HIGH), + { }, + }, +}; static int tosa_tc6393xb_enable(struct platform_device *dev) { @@ -709,31 +725,6 @@ static struct tmio_nand_data tosa_tc6393xb_nand_config = { .part_parsers = probes, }; -static int tosa_tc6393xb_setup(struct platform_device *dev) -{ - int rc; - - rc = gpio_request(TOSA_GPIO_CARD_VCC_ON, "CARD_VCC_ON"); - if (rc) - goto err_req; - - rc = gpio_direction_output(TOSA_GPIO_CARD_VCC_ON, 1); - if (rc) - goto err_dir; - - return rc; - -err_dir: - gpio_free(TOSA_GPIO_CARD_VCC_ON); -err_req: - return rc; -} - -static void tosa_tc6393xb_teardown(struct platform_device *dev) -{ - gpio_free(TOSA_GPIO_CARD_VCC_ON); -} - #ifdef CONFIG_MFD_TC6393XB static struct fb_videomode tosa_tc6393xb_lcd_mode[] = { { @@ -778,9 +769,6 @@ static struct tc6393xb_platform_data tosa_tc6393xb_data = { .scr_gper = 0x3300, .irq_base = IRQ_BOARD_START, - .gpio_base = TOSA_TC6393XB_GPIO_BASE, - .setup = tosa_tc6393xb_setup, - .teardown = tosa_tc6393xb_teardown, .enable = tosa_tc6393xb_enable, .disable = tosa_tc6393xb_disable, @@ -821,26 +809,6 @@ static struct pxa2xx_spi_controller pxa_ssp_master_info = { .num_chipselect = 1, }; -static struct gpiod_lookup_table tosa_lcd_gpio_table = { - .dev_id = "spi2.0", - .table = { - GPIO_LOOKUP("tc6393xb", - TOSA_GPIO_TG_ON - TOSA_TC6393XB_GPIO_BASE, - "tg #pwr", GPIO_ACTIVE_HIGH), - { }, - }, -}; - -static struct gpiod_lookup_table tosa_lcd_bl_gpio_table = { - .dev_id = "i2c-tosa-bl", - .table = { - GPIO_LOOKUP("tc6393xb", - TOSA_GPIO_BL_C20MA - TOSA_TC6393XB_GPIO_BASE, - "backlight", GPIO_ACTIVE_HIGH), - { }, - }, -}; - static struct spi_board_info spi_board_info[] __initdata = { { .modalias = "tosa-lcd", @@ -943,6 +911,8 @@ static void __init tosa_init(void) /* enable batt_fault */ PMCR = 0x01; + gpiod_add_lookup_table(&tosa_battery_gpio_table); + gpiod_add_lookup_table(&tosa_mci_gpio_table); pxa_set_mci_info(&tosa_mci_platform_data); pxa_set_ficp_info(&tosa_ficp_platform_data); @@ -951,8 +921,6 @@ static void __init tosa_init(void) platform_scoop_config = &tosa_pcmcia_config; pxa2xx_set_spi_info(2, &pxa_ssp_master_info); - gpiod_add_lookup_table(&tosa_lcd_gpio_table); - gpiod_add_lookup_table(&tosa_lcd_bl_gpio_table); spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); clk_add_alias("CLK_CK3P6MI", tc6393xb_device.name, "GPIO11_CLK", NULL); -- cgit From ac70f4d80df414223130b04d9b4435bf56dda654 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 11 Sep 2019 10:58:26 +0200 Subject: ARM: pxa: poodle: use platform data for poodle asoc driver The poodle audio driver shows its age by using a custom gpio api for the "locomo" support chip. In a perfect world, this would get converted to use gpiolib and a gpio lookup table. As the world is not perfect, just pass all the required data in a custom platform_data structure. to avoid the globally visible mach/poodle.h header. Acked-by: Mark Brown Acked-by: Robert Jarzmik Cc: alsa-devel@alsa-project.org Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/include/mach/poodle.h | 94 --------------------------------- arch/arm/mach-pxa/poodle.c | 30 +++++++---- arch/arm/mach-pxa/poodle.h | 92 ++++++++++++++++++++++++++++++++ 3 files changed, 112 insertions(+), 104 deletions(-) delete mode 100644 arch/arm/mach-pxa/include/mach/poodle.h create mode 100644 arch/arm/mach-pxa/poodle.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h deleted file mode 100644 index b56b19351a03..000000000000 --- a/arch/arm/mach-pxa/include/mach/poodle.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/poodle.h - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * Based on: - * arch/arm/mach-sa1100/include/mach/collie.h - * - * ChangeLog: - * 04-06-2001 Lineo Japan, Inc. - * 04-16-2001 SHARP Corporation - * Update to 2.6 John Lenz - */ -#ifndef __ASM_ARCH_POODLE_H -#define __ASM_ARCH_POODLE_H 1 - -#include "irqs.h" /* PXA_GPIO_TO_IRQ */ - -/* - * GPIOs - */ -/* PXA GPIOs */ -#define POODLE_GPIO_ON_KEY (0) -#define POODLE_GPIO_AC_IN (1) -#define POODLE_GPIO_CO 16 -#define POODLE_GPIO_TP_INT (5) -#define POODLE_GPIO_TP_CS (24) -#define POODLE_GPIO_WAKEUP (11) /* change battery */ -#define POODLE_GPIO_GA_INT (10) -#define POODLE_GPIO_IR_ON (22) -#define POODLE_GPIO_HP_IN (4) -#define POODLE_GPIO_CF_IRQ (17) -#define POODLE_GPIO_CF_CD (14) -#define POODLE_GPIO_CF_STSCHG (14) -#define POODLE_GPIO_SD_PWR (33) -#define POODLE_GPIO_SD_PWR1 (3) -#define POODLE_GPIO_nSD_CLK (6) -#define POODLE_GPIO_nSD_WP (7) -#define POODLE_GPIO_nSD_INT (8) -#define POODLE_GPIO_nSD_DETECT (9) -#define POODLE_GPIO_MAIN_BAT_LOW (13) -#define POODLE_GPIO_BAT_COVER (13) -#define POODLE_GPIO_USB_PULLUP (20) -#define POODLE_GPIO_ADC_TEMP_ON (21) -#define POODLE_GPIO_BYPASS_ON (36) -#define POODLE_GPIO_CHRG_ON (38) -#define POODLE_GPIO_CHRG_FULL (16) -#define POODLE_GPIO_DISCHARGE_ON (42) /* Enable battery discharge */ - -/* PXA GPIOs */ -#define POODLE_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(0) -#define POODLE_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1) -#define POODLE_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(4) -#define POODLE_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(16) -#define POODLE_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5) -#define POODLE_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(11) -#define POODLE_IRQ_GPIO_GA_INT PXA_GPIO_TO_IRQ(10) -#define POODLE_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17) -#define POODLE_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14) -#define POODLE_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(8) -#define POODLE_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9) -#define POODLE_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(13) - -/* SCOOP GPIOs */ -#define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11 -#define POODLE_SCOOP_CP401 SCOOP_GPCR_PA13 -#define POODLE_SCOOP_VPEN SCOOP_GPCR_PA18 -#define POODLE_SCOOP_L_PCLK SCOOP_GPCR_PA20 -#define POODLE_SCOOP_L_LCLK SCOOP_GPCR_PA21 -#define POODLE_SCOOP_HS_OUT SCOOP_GPCR_PA22 - -#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT ) -#define POODLE_SCOOP_IO_OUT ( 0 ) - -#define POODLE_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) -#define POODLE_GPIO_CHARGE_ON (POODLE_SCOOP_GPIO_BASE + 0) -#define POODLE_GPIO_CP401 (POODLE_SCOOP_GPIO_BASE + 2) -#define POODLE_GPIO_VPEN (POODLE_SCOOP_GPIO_BASE + 7) -#define POODLE_GPIO_L_PCLK (POODLE_SCOOP_GPIO_BASE + 9) -#define POODLE_GPIO_L_LCLK (POODLE_SCOOP_GPIO_BASE + 10) -#define POODLE_GPIO_HS_OUT (POODLE_SCOOP_GPIO_BASE + 11) - -#define POODLE_LOCOMO_GPIO_AMP_ON LOCOMO_GPIO(8) -#define POODLE_LOCOMO_GPIO_MUTE_L LOCOMO_GPIO(10) -#define POODLE_LOCOMO_GPIO_MUTE_R LOCOMO_GPIO(11) -#define POODLE_LOCOMO_GPIO_232VCC_ON LOCOMO_GPIO(12) -#define POODLE_LOCOMO_GPIO_JK_B LOCOMO_GPIO(13) - -#define POODLE_NR_IRQS (IRQ_BOARD_START + 4) /* 4 for LoCoMo */ - -extern struct platform_device poodle_locomo_device; - -#endif /* __ASM_ARCH_POODLE_H */ diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index ca52882433d4..7772a39430ed 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -39,11 +39,13 @@ #include #include "pxa25x.h" -#include #include "udc.h" +#include "poodle.h" + +#include #include -#include #include +#include #include #include @@ -155,12 +157,6 @@ static struct scoop_pcmcia_config poodle_pcmcia_config = { EXPORT_SYMBOL(poodle_scoop_device); - -static struct platform_device poodle_audio_device = { - .name = "poodle-audio", - .id = -1, -}; - /* LoCoMo device */ static struct resource locomo_resources[] = { [0] = { @@ -179,7 +175,7 @@ static struct locomo_platform_data locomo_info = { .irq_base = IRQ_BOARD_START, }; -struct platform_device poodle_locomo_device = { +static struct platform_device poodle_locomo_device = { .name = "locomo", .id = 0, .num_resources = ARRAY_SIZE(locomo_resources), @@ -189,7 +185,21 @@ struct platform_device poodle_locomo_device = { }, }; -EXPORT_SYMBOL(poodle_locomo_device); +static struct poodle_audio_platform_data poodle_audio_pdata = { + .locomo_dev = &poodle_locomo_device.dev, + + .gpio_amp_on = POODLE_LOCOMO_GPIO_AMP_ON, + .gpio_mute_l = POODLE_LOCOMO_GPIO_MUTE_L, + .gpio_mute_r = POODLE_LOCOMO_GPIO_MUTE_R, + .gpio_232vcc_on = POODLE_LOCOMO_GPIO_232VCC_ON, + .gpio_jk_b = POODLE_LOCOMO_GPIO_JK_B, +}; + +static struct platform_device poodle_audio_device = { + .name = "poodle-audio", + .id = -1, + .dev.platform_data = &poodle_audio_pdata, +}; #if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE) static struct pxa2xx_spi_controller poodle_spi_info = { diff --git a/arch/arm/mach-pxa/poodle.h b/arch/arm/mach-pxa/poodle.h new file mode 100644 index 000000000000..e675a3d1aa18 --- /dev/null +++ b/arch/arm/mach-pxa/poodle.h @@ -0,0 +1,92 @@ +/* + * arch/arm/mach-pxa/include/mach/poodle.h + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * Based on: + * arch/arm/mach-sa1100/include/mach/collie.h + * + * ChangeLog: + * 04-06-2001 Lineo Japan, Inc. + * 04-16-2001 SHARP Corporation + * Update to 2.6 John Lenz + */ +#ifndef __ASM_ARCH_POODLE_H +#define __ASM_ARCH_POODLE_H 1 + +#include /* PXA_GPIO_TO_IRQ */ + +/* + * GPIOs + */ +/* PXA GPIOs */ +#define POODLE_GPIO_ON_KEY (0) +#define POODLE_GPIO_AC_IN (1) +#define POODLE_GPIO_CO 16 +#define POODLE_GPIO_TP_INT (5) +#define POODLE_GPIO_TP_CS (24) +#define POODLE_GPIO_WAKEUP (11) /* change battery */ +#define POODLE_GPIO_GA_INT (10) +#define POODLE_GPIO_IR_ON (22) +#define POODLE_GPIO_HP_IN (4) +#define POODLE_GPIO_CF_IRQ (17) +#define POODLE_GPIO_CF_CD (14) +#define POODLE_GPIO_CF_STSCHG (14) +#define POODLE_GPIO_SD_PWR (33) +#define POODLE_GPIO_SD_PWR1 (3) +#define POODLE_GPIO_nSD_CLK (6) +#define POODLE_GPIO_nSD_WP (7) +#define POODLE_GPIO_nSD_INT (8) +#define POODLE_GPIO_nSD_DETECT (9) +#define POODLE_GPIO_MAIN_BAT_LOW (13) +#define POODLE_GPIO_BAT_COVER (13) +#define POODLE_GPIO_USB_PULLUP (20) +#define POODLE_GPIO_ADC_TEMP_ON (21) +#define POODLE_GPIO_BYPASS_ON (36) +#define POODLE_GPIO_CHRG_ON (38) +#define POODLE_GPIO_CHRG_FULL (16) +#define POODLE_GPIO_DISCHARGE_ON (42) /* Enable battery discharge */ + +/* PXA GPIOs */ +#define POODLE_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(0) +#define POODLE_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1) +#define POODLE_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(4) +#define POODLE_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(16) +#define POODLE_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5) +#define POODLE_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(11) +#define POODLE_IRQ_GPIO_GA_INT PXA_GPIO_TO_IRQ(10) +#define POODLE_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17) +#define POODLE_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14) +#define POODLE_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(8) +#define POODLE_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9) +#define POODLE_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(13) + +/* SCOOP GPIOs */ +#define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11 +#define POODLE_SCOOP_CP401 SCOOP_GPCR_PA13 +#define POODLE_SCOOP_VPEN SCOOP_GPCR_PA18 +#define POODLE_SCOOP_L_PCLK SCOOP_GPCR_PA20 +#define POODLE_SCOOP_L_LCLK SCOOP_GPCR_PA21 +#define POODLE_SCOOP_HS_OUT SCOOP_GPCR_PA22 + +#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT ) +#define POODLE_SCOOP_IO_OUT ( 0 ) + +#define POODLE_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) +#define POODLE_GPIO_CHARGE_ON (POODLE_SCOOP_GPIO_BASE + 0) +#define POODLE_GPIO_CP401 (POODLE_SCOOP_GPIO_BASE + 2) +#define POODLE_GPIO_VPEN (POODLE_SCOOP_GPIO_BASE + 7) +#define POODLE_GPIO_L_PCLK (POODLE_SCOOP_GPIO_BASE + 9) +#define POODLE_GPIO_L_LCLK (POODLE_SCOOP_GPIO_BASE + 10) +#define POODLE_GPIO_HS_OUT (POODLE_SCOOP_GPIO_BASE + 11) + +#define POODLE_LOCOMO_GPIO_AMP_ON LOCOMO_GPIO(8) +#define POODLE_LOCOMO_GPIO_MUTE_L LOCOMO_GPIO(10) +#define POODLE_LOCOMO_GPIO_MUTE_R LOCOMO_GPIO(11) +#define POODLE_LOCOMO_GPIO_232VCC_ON LOCOMO_GPIO(12) +#define POODLE_LOCOMO_GPIO_JK_B LOCOMO_GPIO(13) + +#define POODLE_NR_IRQS (IRQ_BOARD_START + 4) /* 4 for LoCoMo */ + +#endif /* __ASM_ARCH_POODLE_H */ -- cgit From 2f361e9459559d4ea97f6645ea6d2f814fb5f2e9 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 11 Sep 2019 13:57:45 +0200 Subject: ARM: pxa: corgi: use gpio descriptors for audio The audio driver should not use a hardwired gpio number from the header. Change it to use a lookup table. Acked-by: Mark Brown Cc: alsa-devel@alsa-project.org Acked-by: Robert Jarzmik Reviewed-by: Linus Walleij Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/corgi.c | 22 ++++++- arch/arm/mach-pxa/corgi.h | 110 +++++++++++++++++++++++++++++++++ arch/arm/mach-pxa/corgi_pm.c | 2 +- arch/arm/mach-pxa/include/mach/corgi.h | 110 --------------------------------- 4 files changed, 132 insertions(+), 112 deletions(-) create mode 100644 arch/arm/mach-pxa/corgi.h delete mode 100644 arch/arm/mach-pxa/include/mach/corgi.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index f897762c8b58..c546356d0f02 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -49,7 +49,7 @@ #include #include #include "udc.h" -#include +#include "corgi.h" #include "sharpsl_pm.h" #include @@ -472,6 +472,25 @@ static struct platform_device corgiled_device = { }, }; +static struct gpiod_lookup_table corgi_audio_gpio_table = { + .dev_id = "corgi-audio", + .table = { + GPIO_LOOKUP("sharp-scoop", + CORGI_GPIO_MUTE_L - CORGI_SCOOP_GPIO_BASE, + "mute-l", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("sharp-scoop", + CORGI_GPIO_MUTE_R - CORGI_SCOOP_GPIO_BASE, + "mute-r", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("sharp-scoop", + CORGI_GPIO_APM_ON - CORGI_SCOOP_GPIO_BASE, + "apm-on", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("sharp-scoop", + CORGI_GPIO_MIC_BIAS - CORGI_SCOOP_GPIO_BASE, + "mic-bias", GPIO_ACTIVE_HIGH), + { }, + }, +}; + /* * Corgi Audio */ @@ -744,6 +763,7 @@ static void __init corgi_init(void) pxa_set_udc_info(&udc_info); gpiod_add_lookup_table(&corgi_mci_gpio_table); + gpiod_add_lookup_table(&corgi_audio_gpio_table); pxa_set_mci_info(&corgi_mci_platform_data); pxa_set_ficp_info(&corgi_ficp_platform_data); pxa_set_i2c_info(NULL); diff --git a/arch/arm/mach-pxa/corgi.h b/arch/arm/mach-pxa/corgi.h new file mode 100644 index 000000000000..fe2fcf6532b9 --- /dev/null +++ b/arch/arm/mach-pxa/corgi.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Hardware specific definitions for SL-C7xx series of PDAs + * + * Copyright (c) 2004-2005 Richard Purdie + * + * Based on Sharp's 2.4 kernel patches + */ +#ifndef __ASM_ARCH_CORGI_H +#define __ASM_ARCH_CORGI_H 1 + +#include /* PXA_NR_BUILTIN_GPIO */ + +/* + * Corgi (Non Standard) GPIO Definitions + */ +#define CORGI_GPIO_KEY_INT (0) /* Keyboard Interrupt */ +#define CORGI_GPIO_AC_IN (1) /* Charger Detection */ +#define CORGI_GPIO_WAKEUP (3) /* System wakeup notification? */ +#define CORGI_GPIO_AK_INT (4) /* Headphone Jack Control Interrupt */ +#define CORGI_GPIO_TP_INT (5) /* Touch Panel Interrupt */ +#define CORGI_GPIO_nSD_WP (7) /* SD Write Protect? */ +#define CORGI_GPIO_nSD_DETECT (9) /* MMC/SD Card Detect */ +#define CORGI_GPIO_nSD_INT (10) /* SD Interrupt for SDIO? */ +#define CORGI_GPIO_MAIN_BAT_LOW (11) /* Main Battery Low Notification */ +#define CORGI_GPIO_BAT_COVER (11) /* Battery Cover Detect */ +#define CORGI_GPIO_LED_ORANGE (13) /* Orange LED Control */ +#define CORGI_GPIO_CF_CD (14) /* Compact Flash Card Detect */ +#define CORGI_GPIO_CHRG_FULL (16) /* Charging Complete Notification */ +#define CORGI_GPIO_CF_IRQ (17) /* Compact Flash Interrupt */ +#define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */ +#define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */ +#define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */ +#define CORGI_GPIO_IR_ON (22) /* Enable IR Transceiver */ +#define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */ +#define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */ +#define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */ +#define CORGI_GPIO_DISCHARGE_ON (42) /* Enable battery Discharge */ +#define CORGI_GPIO_CHRG_UKN (43) /* Unknown Charging (Bypass Control?) */ +#define CORGI_GPIO_HSYNC (44) /* LCD HSync Pulse */ +#define CORGI_GPIO_USB_PULLUP (45) /* USB show presence to host */ + + +/* + * Corgi Keyboard Definitions + */ +#define CORGI_KEY_STROBE_NUM (12) +#define CORGI_KEY_SENSE_NUM (8) +#define CORGI_GPIO_ALL_STROBE_BIT (0x00003ffc) +#define CORGI_GPIO_HIGH_SENSE_BIT (0xfc000000) +#define CORGI_GPIO_HIGH_SENSE_RSHIFT (26) +#define CORGI_GPIO_LOW_SENSE_BIT (0x00000003) +#define CORGI_GPIO_LOW_SENSE_LSHIFT (6) +#define CORGI_GPIO_STROBE_BIT(a) GPIO_bit(66+(a)) +#define CORGI_GPIO_SENSE_BIT(a) GPIO_bit(58+(a)) +#define CORGI_GAFR_ALL_STROBE_BIT (0x0ffffff0) +#define CORGI_GAFR_HIGH_SENSE_BIT (0xfff00000) +#define CORGI_GAFR_LOW_SENSE_BIT (0x0000000f) +#define CORGI_GPIO_KEY_SENSE(a) (58+(a)) +#define CORGI_GPIO_KEY_STROBE(a) (66+(a)) + + +/* + * Corgi Interrupts + */ +#define CORGI_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(0) +#define CORGI_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1) +#define CORGI_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(3) +#define CORGI_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(4) +#define CORGI_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5) +#define CORGI_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9) +#define CORGI_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(10) +#define CORGI_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(11) +#define CORGI_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14) +#define CORGI_IRQ_GPIO_CHRG_FULL PXA_GPIO_TO_IRQ(16) /* Battery fully charged */ +#define CORGI_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17) +#define CORGI_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(58+(a)) /* Keyboard Sense lines */ + + +/* + * Corgi SCOOP GPIOs and Config + */ +#define CORGI_SCP_LED_GREEN SCOOP_GPCR_PA11 +#define CORGI_SCP_SWA SCOOP_GPCR_PA12 /* Hinge Switch A */ +#define CORGI_SCP_SWB SCOOP_GPCR_PA13 /* Hinge Switch B */ +#define CORGI_SCP_MUTE_L SCOOP_GPCR_PA14 +#define CORGI_SCP_MUTE_R SCOOP_GPCR_PA15 +#define CORGI_SCP_AKIN_PULLUP SCOOP_GPCR_PA16 +#define CORGI_SCP_APM_ON SCOOP_GPCR_PA17 +#define CORGI_SCP_BACKLIGHT_CONT SCOOP_GPCR_PA18 +#define CORGI_SCP_MIC_BIAS SCOOP_GPCR_PA19 + +#define CORGI_SCOOP_IO_DIR ( CORGI_SCP_LED_GREEN | CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R | \ + CORGI_SCP_AKIN_PULLUP | CORGI_SCP_APM_ON | CORGI_SCP_BACKLIGHT_CONT | \ + CORGI_SCP_MIC_BIAS ) +#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R ) + +#define CORGI_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) +#define CORGI_GPIO_LED_GREEN (CORGI_SCOOP_GPIO_BASE + 0) +#define CORGI_GPIO_SWA (CORGI_SCOOP_GPIO_BASE + 1) /* Hinge Switch A */ +#define CORGI_GPIO_SWB (CORGI_SCOOP_GPIO_BASE + 2) /* Hinge Switch B */ +#define CORGI_GPIO_MUTE_L (CORGI_SCOOP_GPIO_BASE + 3) +#define CORGI_GPIO_MUTE_R (CORGI_SCOOP_GPIO_BASE + 4) +#define CORGI_GPIO_AKIN_PULLUP (CORGI_SCOOP_GPIO_BASE + 5) +#define CORGI_GPIO_APM_ON (CORGI_SCOOP_GPIO_BASE + 6) +#define CORGI_GPIO_BACKLIGHT_CONT (CORGI_SCOOP_GPIO_BASE + 7) +#define CORGI_GPIO_MIC_BIAS (CORGI_SCOOP_GPIO_BASE + 8) + +#endif /* __ASM_ARCH_CORGI_H */ + diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index ff1ac9bf37cb..c6ddfc737644 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c @@ -20,7 +20,7 @@ #include #include -#include +#include "corgi.h" #include #include "sharpsl_pm.h" diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h deleted file mode 100644 index b565ca7b8cda..000000000000 --- a/arch/arm/mach-pxa/include/mach/corgi.h +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Hardware specific definitions for SL-C7xx series of PDAs - * - * Copyright (c) 2004-2005 Richard Purdie - * - * Based on Sharp's 2.4 kernel patches - */ -#ifndef __ASM_ARCH_CORGI_H -#define __ASM_ARCH_CORGI_H 1 - -#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ - -/* - * Corgi (Non Standard) GPIO Definitions - */ -#define CORGI_GPIO_KEY_INT (0) /* Keyboard Interrupt */ -#define CORGI_GPIO_AC_IN (1) /* Charger Detection */ -#define CORGI_GPIO_WAKEUP (3) /* System wakeup notification? */ -#define CORGI_GPIO_AK_INT (4) /* Headphone Jack Control Interrupt */ -#define CORGI_GPIO_TP_INT (5) /* Touch Panel Interrupt */ -#define CORGI_GPIO_nSD_WP (7) /* SD Write Protect? */ -#define CORGI_GPIO_nSD_DETECT (9) /* MMC/SD Card Detect */ -#define CORGI_GPIO_nSD_INT (10) /* SD Interrupt for SDIO? */ -#define CORGI_GPIO_MAIN_BAT_LOW (11) /* Main Battery Low Notification */ -#define CORGI_GPIO_BAT_COVER (11) /* Battery Cover Detect */ -#define CORGI_GPIO_LED_ORANGE (13) /* Orange LED Control */ -#define CORGI_GPIO_CF_CD (14) /* Compact Flash Card Detect */ -#define CORGI_GPIO_CHRG_FULL (16) /* Charging Complete Notification */ -#define CORGI_GPIO_CF_IRQ (17) /* Compact Flash Interrupt */ -#define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */ -#define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */ -#define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */ -#define CORGI_GPIO_IR_ON (22) /* Enable IR Transceiver */ -#define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */ -#define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */ -#define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */ -#define CORGI_GPIO_DISCHARGE_ON (42) /* Enable battery Discharge */ -#define CORGI_GPIO_CHRG_UKN (43) /* Unknown Charging (Bypass Control?) */ -#define CORGI_GPIO_HSYNC (44) /* LCD HSync Pulse */ -#define CORGI_GPIO_USB_PULLUP (45) /* USB show presence to host */ - - -/* - * Corgi Keyboard Definitions - */ -#define CORGI_KEY_STROBE_NUM (12) -#define CORGI_KEY_SENSE_NUM (8) -#define CORGI_GPIO_ALL_STROBE_BIT (0x00003ffc) -#define CORGI_GPIO_HIGH_SENSE_BIT (0xfc000000) -#define CORGI_GPIO_HIGH_SENSE_RSHIFT (26) -#define CORGI_GPIO_LOW_SENSE_BIT (0x00000003) -#define CORGI_GPIO_LOW_SENSE_LSHIFT (6) -#define CORGI_GPIO_STROBE_BIT(a) GPIO_bit(66+(a)) -#define CORGI_GPIO_SENSE_BIT(a) GPIO_bit(58+(a)) -#define CORGI_GAFR_ALL_STROBE_BIT (0x0ffffff0) -#define CORGI_GAFR_HIGH_SENSE_BIT (0xfff00000) -#define CORGI_GAFR_LOW_SENSE_BIT (0x0000000f) -#define CORGI_GPIO_KEY_SENSE(a) (58+(a)) -#define CORGI_GPIO_KEY_STROBE(a) (66+(a)) - - -/* - * Corgi Interrupts - */ -#define CORGI_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(0) -#define CORGI_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1) -#define CORGI_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(3) -#define CORGI_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(4) -#define CORGI_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5) -#define CORGI_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9) -#define CORGI_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(10) -#define CORGI_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(11) -#define CORGI_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14) -#define CORGI_IRQ_GPIO_CHRG_FULL PXA_GPIO_TO_IRQ(16) /* Battery fully charged */ -#define CORGI_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17) -#define CORGI_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(58+(a)) /* Keyboard Sense lines */ - - -/* - * Corgi SCOOP GPIOs and Config - */ -#define CORGI_SCP_LED_GREEN SCOOP_GPCR_PA11 -#define CORGI_SCP_SWA SCOOP_GPCR_PA12 /* Hinge Switch A */ -#define CORGI_SCP_SWB SCOOP_GPCR_PA13 /* Hinge Switch B */ -#define CORGI_SCP_MUTE_L SCOOP_GPCR_PA14 -#define CORGI_SCP_MUTE_R SCOOP_GPCR_PA15 -#define CORGI_SCP_AKIN_PULLUP SCOOP_GPCR_PA16 -#define CORGI_SCP_APM_ON SCOOP_GPCR_PA17 -#define CORGI_SCP_BACKLIGHT_CONT SCOOP_GPCR_PA18 -#define CORGI_SCP_MIC_BIAS SCOOP_GPCR_PA19 - -#define CORGI_SCOOP_IO_DIR ( CORGI_SCP_LED_GREEN | CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R | \ - CORGI_SCP_AKIN_PULLUP | CORGI_SCP_APM_ON | CORGI_SCP_BACKLIGHT_CONT | \ - CORGI_SCP_MIC_BIAS ) -#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R ) - -#define CORGI_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) -#define CORGI_GPIO_LED_GREEN (CORGI_SCOOP_GPIO_BASE + 0) -#define CORGI_GPIO_SWA (CORGI_SCOOP_GPIO_BASE + 1) /* Hinge Switch A */ -#define CORGI_GPIO_SWB (CORGI_SCOOP_GPIO_BASE + 2) /* Hinge Switch B */ -#define CORGI_GPIO_MUTE_L (CORGI_SCOOP_GPIO_BASE + 3) -#define CORGI_GPIO_MUTE_R (CORGI_SCOOP_GPIO_BASE + 4) -#define CORGI_GPIO_AKIN_PULLUP (CORGI_SCOOP_GPIO_BASE + 5) -#define CORGI_GPIO_APM_ON (CORGI_SCOOP_GPIO_BASE + 6) -#define CORGI_GPIO_BACKLIGHT_CONT (CORGI_SCOOP_GPIO_BASE + 7) -#define CORGI_GPIO_MIC_BIAS (CORGI_SCOOP_GPIO_BASE + 8) - -#endif /* __ASM_ARCH_CORGI_H */ - -- cgit From e6c91e1adfd385e99cbe5d1b90684ebeb96540ea Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 11 Sep 2019 14:27:13 +0200 Subject: ARM: pxa: hx4700: use gpio descriptors for audio The audio driver should not use a hardwired gpio number from the header. Change it to use a lookup table. Cc: Philipp Zabel Cc: Paul Parsons Acked-by: Mark Brown Acked-by: Robert Jarzmik Cc: alsa-devel@alsa-project.org Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/hx4700-pcmcia.c | 2 +- arch/arm/mach-pxa/hx4700.c | 16 +++- arch/arm/mach-pxa/hx4700.h | 129 ++++++++++++++++++++++++++++++++ arch/arm/mach-pxa/include/mach/hx4700.h | 129 -------------------------------- 4 files changed, 145 insertions(+), 131 deletions(-) create mode 100644 arch/arm/mach-pxa/hx4700.h delete mode 100644 arch/arm/mach-pxa/include/mach/hx4700.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/hx4700-pcmcia.c b/arch/arm/mach-pxa/hx4700-pcmcia.c index e8acbfc9ef6c..e2331dfe427d 100644 --- a/arch/arm/mach-pxa/hx4700-pcmcia.c +++ b/arch/arm/mach-pxa/hx4700-pcmcia.c @@ -10,7 +10,7 @@ #include #include -#include +#include "hx4700.h" #include diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 140a44cb2989..2ae06edf413c 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -41,7 +41,7 @@ #include "pxa27x.h" #include "addr-map.h" -#include +#include "hx4700.h" #include #include @@ -834,6 +834,19 @@ static struct i2c_board_info i2c_board_info[] __initdata = { }, }; +static struct gpiod_lookup_table hx4700_audio_gpio_table = { + .dev_id = "hx4700-audio", + .table = { + GPIO_LOOKUP("gpio-pxa", GPIO75_HX4700_EARPHONE_nDET, + "earphone-det", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("gpio-pxa", GPIO92_HX4700_HP_DRIVER, + "hp-driver", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio-pxa", GPIO107_HX4700_SPK_nSD, + "spk-sd", GPIO_ACTIVE_LOW), + { }, + }, +}; + static struct platform_device audio = { .name = "hx4700-audio", .id = -1, @@ -895,6 +908,7 @@ static void __init hx4700_init(void) gpiod_add_lookup_table(&bq24022_gpiod_table); gpiod_add_lookup_table(&gpio_vbus_gpiod_table); + gpiod_add_lookup_table(&hx4700_audio_gpio_table); platform_add_devices(devices, ARRAY_SIZE(devices)); pwm_add_table(hx4700_pwm_lookup, ARRAY_SIZE(hx4700_pwm_lookup)); diff --git a/arch/arm/mach-pxa/hx4700.h b/arch/arm/mach-pxa/hx4700.h new file mode 100644 index 000000000000..ce2db33989e1 --- /dev/null +++ b/arch/arm/mach-pxa/hx4700.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * GPIO and IRQ definitions for HP iPAQ hx4700 + * + * Copyright (c) 2008 Philipp Zabel + */ + +#ifndef _HX4700_H_ +#define _HX4700_H_ + +#include +#include +#include /* PXA_NR_BUILTIN_GPIO */ + +#define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO +#define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS) +#define HX4700_NR_IRQS (IRQ_BOARD_START + 70) + +/* + * PXA GPIOs + */ + +#define GPIO0_HX4700_nKEY_POWER 0 +#define GPIO12_HX4700_ASIC3_IRQ 12 +#define GPIO13_HX4700_W3220_IRQ 13 +#define GPIO14_HX4700_nWLAN_IRQ 14 +#define GPIO18_HX4700_RDY 18 +#define GPIO22_HX4700_LCD_RL 22 +#define GPIO27_HX4700_CODEC_ON 27 +#define GPIO32_HX4700_RS232_ON 32 +#define GPIO52_HX4700_CPU_nBATT_FAULT 52 +#define GPIO58_HX4700_TSC2046_nPENIRQ 58 +#define GPIO59_HX4700_LCD_PC1 59 +#define GPIO60_HX4700_CF_RNB 60 +#define GPIO61_HX4700_W3220_nRESET 61 +#define GPIO62_HX4700_LCD_nRESET 62 +#define GPIO63_HX4700_CPU_SS_nRESET 63 +#define GPIO65_HX4700_TSC2046_PEN_PU 65 +#define GPIO66_HX4700_ASIC3_nSDIO_IRQ 66 +#define GPIO67_HX4700_EUART_PS 67 +#define GPIO70_HX4700_LCD_SLIN1 70 +#define GPIO71_HX4700_ASIC3_nRESET 71 +#define GPIO72_HX4700_BQ24022_nCHARGE_EN 72 +#define GPIO73_HX4700_LCD_UD_1 73 +#define GPIO75_HX4700_EARPHONE_nDET 75 +#define GPIO76_HX4700_USBC_PUEN 76 +#define GPIO81_HX4700_CPU_GP_nRESET 81 +#define GPIO82_HX4700_EUART_RESET 82 +#define GPIO83_HX4700_WLAN_nRESET 83 +#define GPIO84_HX4700_LCD_SQN 84 +#define GPIO85_HX4700_nPCE1 85 +#define GPIO88_HX4700_TSC2046_CS 88 +#define GPIO91_HX4700_FLASH_VPEN 91 +#define GPIO92_HX4700_HP_DRIVER 92 +#define GPIO93_HX4700_EUART_INT 93 +#define GPIO94_HX4700_KEY_MAIL 94 +#define GPIO95_HX4700_BATT_OFF 95 +#define GPIO96_HX4700_BQ24022_ISET2 96 +#define GPIO97_HX4700_nBL_DETECT 97 +#define GPIO99_HX4700_KEY_CONTACTS 99 +#define GPIO100_HX4700_AUTO_SENSE 100 /* BL auto brightness */ +#define GPIO102_HX4700_SYNAPTICS_POWER_ON 102 +#define GPIO103_HX4700_SYNAPTICS_INT 103 +#define GPIO105_HX4700_nIR_ON 105 +#define GPIO106_HX4700_CPU_BT_nRESET 106 +#define GPIO107_HX4700_SPK_nSD 107 +#define GPIO109_HX4700_CODEC_nPDN 109 +#define GPIO110_HX4700_LCD_LVDD_3V3_ON 110 +#define GPIO111_HX4700_LCD_AVDD_3V3_ON 111 +#define GPIO112_HX4700_LCD_N2V7_7V3_ON 112 +#define GPIO114_HX4700_CF_RESET 114 +#define GPIO116_HX4700_CPU_HW_nRESET 116 + +/* + * ASIC3 GPIOs + */ + +#define GPIOC_BASE (HX4700_ASIC3_GPIO_BASE + 32) +#define GPIOD_BASE (HX4700_ASIC3_GPIO_BASE + 48) + +#define GPIOC0_LED_RED (GPIOC_BASE + 0) +#define GPIOC1_LED_GREEN (GPIOC_BASE + 1) +#define GPIOC2_LED_BLUE (GPIOC_BASE + 2) +#define GPIOC3_nSD_CS (GPIOC_BASE + 3) +#define GPIOC4_CF_nCD (GPIOC_BASE + 4) /* Input */ +#define GPIOC5_nCIOW (GPIOC_BASE + 5) /* Output, to CF */ +#define GPIOC6_nCIOR (GPIOC_BASE + 6) /* Output, to CF */ +#define GPIOC7_nPCE1 (GPIOC_BASE + 7) /* Input, from CPU */ +#define GPIOC8_nPCE2 (GPIOC_BASE + 8) /* Input, from CPU */ +#define GPIOC9_nPOE (GPIOC_BASE + 9) /* Input, from CPU */ +#define GPIOC10_CF_nPWE (GPIOC_BASE + 10) /* Input */ +#define GPIOC11_PSKTSEL (GPIOC_BASE + 11) /* Input, from CPU */ +#define GPIOC12_nPREG (GPIOC_BASE + 12) /* Input, from CPU */ +#define GPIOC13_nPWAIT (GPIOC_BASE + 13) /* Output, to CPU */ +#define GPIOC14_nPIOIS16 (GPIOC_BASE + 14) /* Output, to CPU */ +#define GPIOC15_nPIOR (GPIOC_BASE + 15) /* Input, from CPU */ + +#define GPIOD0_CPU_SS_INT (GPIOD_BASE + 0) /* Input */ +#define GPIOD1_nKEY_CALENDAR (GPIOD_BASE + 1) +#define GPIOD2_BLUETOOTH_WAKEUP (GPIOD_BASE + 2) +#define GPIOD3_nKEY_HOME (GPIOD_BASE + 3) +#define GPIOD4_CF_nCD (GPIOD_BASE + 4) /* Input, from CF */ +#define GPIOD5_nPIO (GPIOD_BASE + 5) /* Input */ +#define GPIOD6_nKEY_RECORD (GPIOD_BASE + 6) +#define GPIOD7_nSDIO_DETECT (GPIOD_BASE + 7) +#define GPIOD8_COM_DCD (GPIOD_BASE + 8) /* Input */ +#define GPIOD9_nAC_IN (GPIOD_BASE + 9) +#define GPIOD10_nSDIO_IRQ (GPIOD_BASE + 10) /* Input */ +#define GPIOD11_nCIOIS16 (GPIOD_BASE + 11) /* Input, from CF */ +#define GPIOD12_nCWAIT (GPIOD_BASE + 12) /* Input, from CF */ +#define GPIOD13_CF_RNB (GPIOD_BASE + 13) /* Input */ +#define GPIOD14_nUSBC_DETECT (GPIOD_BASE + 14) +#define GPIOD15_nPIOW (GPIOD_BASE + 15) /* Input, from CPU */ + +/* + * EGPIOs + */ + +#define EGPIO0_VCC_3V3_EN (HX4700_EGPIO_BASE + 0) /* WLAN support chip */ +#define EGPIO1_WL_VREG_EN (HX4700_EGPIO_BASE + 1) /* WLAN power */ +#define EGPIO2_VCC_2V1_WL_EN (HX4700_EGPIO_BASE + 2) /* unused */ +#define EGPIO3_SS_PWR_ON (HX4700_EGPIO_BASE + 3) /* smart slot power */ +#define EGPIO4_CF_3V3_ON (HX4700_EGPIO_BASE + 4) /* CF 3.3V enable */ +#define EGPIO5_BT_3V3_ON (HX4700_EGPIO_BASE + 5) /* BT 3.3V enable */ +#define EGPIO6_WL1V8_EN (HX4700_EGPIO_BASE + 6) /* WLAN 1.8V enable */ +#define EGPIO7_VCC_3V3_WL_EN (HX4700_EGPIO_BASE + 7) /* WLAN 3.3V enable */ +#define EGPIO8_USB_3V3_ON (HX4700_EGPIO_BASE + 8) /* unused */ + +#endif /* _HX4700_H_ */ diff --git a/arch/arm/mach-pxa/include/mach/hx4700.h b/arch/arm/mach-pxa/include/mach/hx4700.h deleted file mode 100644 index 0c30e6d9c660..000000000000 --- a/arch/arm/mach-pxa/include/mach/hx4700.h +++ /dev/null @@ -1,129 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO and IRQ definitions for HP iPAQ hx4700 - * - * Copyright (c) 2008 Philipp Zabel - */ - -#ifndef _HX4700_H_ -#define _HX4700_H_ - -#include -#include -#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ - -#define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO -#define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS) -#define HX4700_NR_IRQS (IRQ_BOARD_START + 70) - -/* - * PXA GPIOs - */ - -#define GPIO0_HX4700_nKEY_POWER 0 -#define GPIO12_HX4700_ASIC3_IRQ 12 -#define GPIO13_HX4700_W3220_IRQ 13 -#define GPIO14_HX4700_nWLAN_IRQ 14 -#define GPIO18_HX4700_RDY 18 -#define GPIO22_HX4700_LCD_RL 22 -#define GPIO27_HX4700_CODEC_ON 27 -#define GPIO32_HX4700_RS232_ON 32 -#define GPIO52_HX4700_CPU_nBATT_FAULT 52 -#define GPIO58_HX4700_TSC2046_nPENIRQ 58 -#define GPIO59_HX4700_LCD_PC1 59 -#define GPIO60_HX4700_CF_RNB 60 -#define GPIO61_HX4700_W3220_nRESET 61 -#define GPIO62_HX4700_LCD_nRESET 62 -#define GPIO63_HX4700_CPU_SS_nRESET 63 -#define GPIO65_HX4700_TSC2046_PEN_PU 65 -#define GPIO66_HX4700_ASIC3_nSDIO_IRQ 66 -#define GPIO67_HX4700_EUART_PS 67 -#define GPIO70_HX4700_LCD_SLIN1 70 -#define GPIO71_HX4700_ASIC3_nRESET 71 -#define GPIO72_HX4700_BQ24022_nCHARGE_EN 72 -#define GPIO73_HX4700_LCD_UD_1 73 -#define GPIO75_HX4700_EARPHONE_nDET 75 -#define GPIO76_HX4700_USBC_PUEN 76 -#define GPIO81_HX4700_CPU_GP_nRESET 81 -#define GPIO82_HX4700_EUART_RESET 82 -#define GPIO83_HX4700_WLAN_nRESET 83 -#define GPIO84_HX4700_LCD_SQN 84 -#define GPIO85_HX4700_nPCE1 85 -#define GPIO88_HX4700_TSC2046_CS 88 -#define GPIO91_HX4700_FLASH_VPEN 91 -#define GPIO92_HX4700_HP_DRIVER 92 -#define GPIO93_HX4700_EUART_INT 93 -#define GPIO94_HX4700_KEY_MAIL 94 -#define GPIO95_HX4700_BATT_OFF 95 -#define GPIO96_HX4700_BQ24022_ISET2 96 -#define GPIO97_HX4700_nBL_DETECT 97 -#define GPIO99_HX4700_KEY_CONTACTS 99 -#define GPIO100_HX4700_AUTO_SENSE 100 /* BL auto brightness */ -#define GPIO102_HX4700_SYNAPTICS_POWER_ON 102 -#define GPIO103_HX4700_SYNAPTICS_INT 103 -#define GPIO105_HX4700_nIR_ON 105 -#define GPIO106_HX4700_CPU_BT_nRESET 106 -#define GPIO107_HX4700_SPK_nSD 107 -#define GPIO109_HX4700_CODEC_nPDN 109 -#define GPIO110_HX4700_LCD_LVDD_3V3_ON 110 -#define GPIO111_HX4700_LCD_AVDD_3V3_ON 111 -#define GPIO112_HX4700_LCD_N2V7_7V3_ON 112 -#define GPIO114_HX4700_CF_RESET 114 -#define GPIO116_HX4700_CPU_HW_nRESET 116 - -/* - * ASIC3 GPIOs - */ - -#define GPIOC_BASE (HX4700_ASIC3_GPIO_BASE + 32) -#define GPIOD_BASE (HX4700_ASIC3_GPIO_BASE + 48) - -#define GPIOC0_LED_RED (GPIOC_BASE + 0) -#define GPIOC1_LED_GREEN (GPIOC_BASE + 1) -#define GPIOC2_LED_BLUE (GPIOC_BASE + 2) -#define GPIOC3_nSD_CS (GPIOC_BASE + 3) -#define GPIOC4_CF_nCD (GPIOC_BASE + 4) /* Input */ -#define GPIOC5_nCIOW (GPIOC_BASE + 5) /* Output, to CF */ -#define GPIOC6_nCIOR (GPIOC_BASE + 6) /* Output, to CF */ -#define GPIOC7_nPCE1 (GPIOC_BASE + 7) /* Input, from CPU */ -#define GPIOC8_nPCE2 (GPIOC_BASE + 8) /* Input, from CPU */ -#define GPIOC9_nPOE (GPIOC_BASE + 9) /* Input, from CPU */ -#define GPIOC10_CF_nPWE (GPIOC_BASE + 10) /* Input */ -#define GPIOC11_PSKTSEL (GPIOC_BASE + 11) /* Input, from CPU */ -#define GPIOC12_nPREG (GPIOC_BASE + 12) /* Input, from CPU */ -#define GPIOC13_nPWAIT (GPIOC_BASE + 13) /* Output, to CPU */ -#define GPIOC14_nPIOIS16 (GPIOC_BASE + 14) /* Output, to CPU */ -#define GPIOC15_nPIOR (GPIOC_BASE + 15) /* Input, from CPU */ - -#define GPIOD0_CPU_SS_INT (GPIOD_BASE + 0) /* Input */ -#define GPIOD1_nKEY_CALENDAR (GPIOD_BASE + 1) -#define GPIOD2_BLUETOOTH_WAKEUP (GPIOD_BASE + 2) -#define GPIOD3_nKEY_HOME (GPIOD_BASE + 3) -#define GPIOD4_CF_nCD (GPIOD_BASE + 4) /* Input, from CF */ -#define GPIOD5_nPIO (GPIOD_BASE + 5) /* Input */ -#define GPIOD6_nKEY_RECORD (GPIOD_BASE + 6) -#define GPIOD7_nSDIO_DETECT (GPIOD_BASE + 7) -#define GPIOD8_COM_DCD (GPIOD_BASE + 8) /* Input */ -#define GPIOD9_nAC_IN (GPIOD_BASE + 9) -#define GPIOD10_nSDIO_IRQ (GPIOD_BASE + 10) /* Input */ -#define GPIOD11_nCIOIS16 (GPIOD_BASE + 11) /* Input, from CF */ -#define GPIOD12_nCWAIT (GPIOD_BASE + 12) /* Input, from CF */ -#define GPIOD13_CF_RNB (GPIOD_BASE + 13) /* Input */ -#define GPIOD14_nUSBC_DETECT (GPIOD_BASE + 14) -#define GPIOD15_nPIOW (GPIOD_BASE + 15) /* Input, from CPU */ - -/* - * EGPIOs - */ - -#define EGPIO0_VCC_3V3_EN (HX4700_EGPIO_BASE + 0) /* WLAN support chip */ -#define EGPIO1_WL_VREG_EN (HX4700_EGPIO_BASE + 1) /* WLAN power */ -#define EGPIO2_VCC_2V1_WL_EN (HX4700_EGPIO_BASE + 2) /* unused */ -#define EGPIO3_SS_PWR_ON (HX4700_EGPIO_BASE + 3) /* smart slot power */ -#define EGPIO4_CF_3V3_ON (HX4700_EGPIO_BASE + 4) /* CF 3.3V enable */ -#define EGPIO5_BT_3V3_ON (HX4700_EGPIO_BASE + 5) /* BT 3.3V enable */ -#define EGPIO6_WL1V8_EN (HX4700_EGPIO_BASE + 6) /* WLAN 1.8V enable */ -#define EGPIO7_VCC_3V3_WL_EN (HX4700_EGPIO_BASE + 7) /* WLAN 3.3V enable */ -#define EGPIO8_USB_3V3_ON (HX4700_EGPIO_BASE + 8) /* unused */ - -#endif /* _HX4700_H_ */ -- cgit From 047dc2a21ed01437f99bc78c55a8ff86dfe3493e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 11 Sep 2019 16:10:33 +0200 Subject: ARM: pxa: lubbock: pass udc irqs as resource Lubbock is the only machine that has three IRQs for the UDC. These are currently hardcoded in the driver based on a machine header file. Change this to use platform device resources as we use for the generic IRQ anyway. Cc: Felipe Balbi Cc: Greg Kroah-Hartman Cc: linux-usb@vger.kernel.org Acked-by: Robert Jarzmik Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/include/mach/lubbock.h | 49 -------------------------------- arch/arm/mach-pxa/lubbock.c | 12 +++++++- arch/arm/mach-pxa/lubbock.h | 47 ++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+), 50 deletions(-) delete mode 100644 arch/arm/mach-pxa/include/mach/lubbock.h create mode 100644 arch/arm/mach-pxa/lubbock.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h deleted file mode 100644 index a3af4a2f9446..000000000000 --- a/arch/arm/mach-pxa/include/mach/lubbock.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-pxa/include/mach/lubbock.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - */ - -#include - -#define LUBBOCK_ETH_PHYS PXA_CS3_PHYS - -#define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS -#define LUBBOCK_FPGA_VIRT (0xf0000000) -#define LUB_P2V(x) ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT) -#define LUB_V2P(x) ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS) - -#ifndef __ASSEMBLY__ -# define __LUB_REG(x) (*((volatile unsigned long *)LUB_P2V(x))) -#else -# define __LUB_REG(x) LUB_P2V(x) -#endif - -/* FPGA register virtual addresses */ -#define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000) -#define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040) -#define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050) -#define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060) -#define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) -#define LUB_MISC_RD __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090) -#define LUB_IRQ_MASK_EN __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0) -#define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0) -#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) - -/* Board specific IRQs */ -#define LUBBOCK_NR_IRQS IRQ_BOARD_START - -#define LUBBOCK_IRQ(x) (LUBBOCK_NR_IRQS + (x)) -#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) -#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) -#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ -#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) -#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) -#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) -#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ -#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) - -#define LUBBOCK_SA1111_IRQ_BASE (LUBBOCK_NR_IRQS + 32) diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 46aef93c0615..201f89f49642 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -46,7 +46,7 @@ #include "pxa25x.h" #include -#include +#include "lubbock.h" #include "udc.h" #include #include @@ -131,6 +131,13 @@ static struct pxa2xx_udc_mach_info udc_info __initdata = { // no D+ pullup; lubbock can't connect/disconnect in software }; +static struct resource lubbock_udc_resources[] = { + DEFINE_RES_MEM(0x40600000, 0x10000), + DEFINE_RES_IRQ(IRQ_USB), + DEFINE_RES_IRQ(LUBBOCK_USB_IRQ), + DEFINE_RES_IRQ(LUBBOCK_USB_DISC_IRQ), +}; + /* GPIOs for SA1111 PCMCIA */ static struct gpiod_lookup_table sa1111_pcmcia_gpio_table = { .dev_id = "1800", @@ -496,6 +503,9 @@ static void __init lubbock_init(void) lubbock_init_pcmcia(); clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL); + /* lubbock has two extra IRQs */ + pxa25x_device_udc.resource = lubbock_udc_resources; + pxa25x_device_udc.num_resources = ARRAY_SIZE(lubbock_udc_resources); pxa_set_udc_info(&udc_info); pxa_set_fb_info(NULL, &sharp_lm8v31); pxa_set_mci_info(&lubbock_mci_platform_data); diff --git a/arch/arm/mach-pxa/lubbock.h b/arch/arm/mach-pxa/lubbock.h new file mode 100644 index 000000000000..8e3ff7d57121 --- /dev/null +++ b/arch/arm/mach-pxa/lubbock.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + */ + +#include + +#define LUBBOCK_ETH_PHYS PXA_CS3_PHYS + +#define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS +#define LUBBOCK_FPGA_VIRT (0xf0000000) +#define LUB_P2V(x) ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT) +#define LUB_V2P(x) ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS) + +#ifndef __ASSEMBLY__ +# define __LUB_REG(x) (*((volatile unsigned long *)LUB_P2V(x))) +#else +# define __LUB_REG(x) LUB_P2V(x) +#endif + +/* FPGA register virtual addresses */ +#define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000) +#define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040) +#define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050) +#define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060) +#define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) +#define LUB_MISC_RD __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090) +#define LUB_IRQ_MASK_EN __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0) +#define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0) +#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) + +/* Board specific IRQs */ +#define LUBBOCK_NR_IRQS IRQ_BOARD_START + +#define LUBBOCK_IRQ(x) (LUBBOCK_NR_IRQS + (x)) +#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) +#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) +#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ +#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) +#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) +#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) +#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ +#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) + +#define LUBBOCK_SA1111_IRQ_BASE (LUBBOCK_NR_IRQS + 32) -- cgit From 726d8c965bae2d7468445d990849e281dca8cbf7 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 11 Sep 2019 16:43:59 +0200 Subject: ARM: pxa: spitz: use gpio descriptors for audio The audio driver should not use a hardwired gpio number from the header. Change it to use a lookup table. Acked-by: Mark Brown Cc: alsa-devel@alsa-project.org Reviewed-by: Linus Walleij Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/include/mach/spitz.h | 185 --------------------------------- arch/arm/mach-pxa/spitz.c | 33 +++++- arch/arm/mach-pxa/spitz.h | 185 +++++++++++++++++++++++++++++++++ arch/arm/mach-pxa/spitz_pm.c | 2 +- 4 files changed, 218 insertions(+), 187 deletions(-) delete mode 100644 arch/arm/mach-pxa/include/mach/spitz.h create mode 100644 arch/arm/mach-pxa/spitz.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h deleted file mode 100644 index 04828d8918aa..000000000000 --- a/arch/arm/mach-pxa/include/mach/spitz.h +++ /dev/null @@ -1,185 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Hardware specific definitions for SL-Cx000 series of PDAs - * - * Copyright (c) 2005 Alexander Wykes - * Copyright (c) 2005 Richard Purdie - * - * Based on Sharp's 2.4 kernel patches - */ -#ifndef __ASM_ARCH_SPITZ_H -#define __ASM_ARCH_SPITZ_H 1 -#endif - -#include "irqs.h" /* PXA_NR_BUILTIN_GPIO, PXA_GPIO_TO_IRQ */ -#include - -/* Spitz/Akita GPIOs */ - -#define SPITZ_GPIO_KEY_INT (0) /* Key Interrupt */ -#define SPITZ_GPIO_RESET (1) -#define SPITZ_GPIO_nSD_DETECT (9) -#define SPITZ_GPIO_TP_INT (11) /* Touch Panel interrupt */ -#define SPITZ_GPIO_AK_INT (13) /* Remote Control */ -#define SPITZ_GPIO_ADS7846_CS (14) -#define SPITZ_GPIO_SYNC (16) -#define SPITZ_GPIO_MAX1111_CS (20) -#define SPITZ_GPIO_FATAL_BAT (21) -#define SPITZ_GPIO_HSYNC (22) -#define SPITZ_GPIO_nSD_CLK (32) -#define SPITZ_GPIO_USB_DEVICE (35) -#define SPITZ_GPIO_USB_HOST (37) -#define SPITZ_GPIO_USB_CONNECT (41) -#define SPITZ_GPIO_LCDCON_CS (53) -#define SPITZ_GPIO_nPCE (54) -#define SPITZ_GPIO_nSD_WP (81) -#define SPITZ_GPIO_ON_RESET (89) -#define SPITZ_GPIO_BAT_COVER (90) -#define SPITZ_GPIO_CF_CD (94) -#define SPITZ_GPIO_ON_KEY (95) -#define SPITZ_GPIO_SWA (97) -#define SPITZ_GPIO_SWB (96) -#define SPITZ_GPIO_CHRG_FULL (101) -#define SPITZ_GPIO_CO (101) -#define SPITZ_GPIO_CF_IRQ (105) -#define SPITZ_GPIO_AC_IN (115) -#define SPITZ_GPIO_HP_IN (116) - -/* Spitz Only GPIOs */ - -#define SPITZ_GPIO_CF2_IRQ (106) /* CF slot1 Ready */ -#define SPITZ_GPIO_CF2_CD (93) - - -/* Spitz/Akita Keyboard Definitions */ - -#define SPITZ_KEY_STROBE_NUM (11) -#define SPITZ_KEY_SENSE_NUM (7) -#define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000 -#define SPITZ_GPIO_G1_STROBE_BIT 0x00100000 -#define SPITZ_GPIO_G2_STROBE_BIT 0x01000000 -#define SPITZ_GPIO_G3_STROBE_BIT 0x00041880 -#define SPITZ_GPIO_G0_SENSE_BIT 0x00021000 -#define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4 -#define SPITZ_GPIO_G2_SENSE_BIT 0x08000000 -#define SPITZ_GPIO_G3_SENSE_BIT 0x00000000 - -#define SPITZ_GPIO_KEY_STROBE0 88 -#define SPITZ_GPIO_KEY_STROBE1 23 -#define SPITZ_GPIO_KEY_STROBE2 24 -#define SPITZ_GPIO_KEY_STROBE3 25 -#define SPITZ_GPIO_KEY_STROBE4 26 -#define SPITZ_GPIO_KEY_STROBE5 27 -#define SPITZ_GPIO_KEY_STROBE6 52 -#define SPITZ_GPIO_KEY_STROBE7 103 -#define SPITZ_GPIO_KEY_STROBE8 107 -#define SPITZ_GPIO_KEY_STROBE9 108 -#define SPITZ_GPIO_KEY_STROBE10 114 - -#define SPITZ_GPIO_KEY_SENSE0 12 -#define SPITZ_GPIO_KEY_SENSE1 17 -#define SPITZ_GPIO_KEY_SENSE2 91 -#define SPITZ_GPIO_KEY_SENSE3 34 -#define SPITZ_GPIO_KEY_SENSE4 36 -#define SPITZ_GPIO_KEY_SENSE5 38 -#define SPITZ_GPIO_KEY_SENSE6 39 - - -/* Spitz Scoop Device (No. 1) GPIOs */ -/* Suspend States in comments */ -#define SPITZ_SCP_LED_GREEN SCOOP_GPCR_PA11 /* Keep */ -#define SPITZ_SCP_JK_B SCOOP_GPCR_PA12 /* Keep */ -#define SPITZ_SCP_CHRG_ON SCOOP_GPCR_PA13 /* Keep */ -#define SPITZ_SCP_MUTE_L SCOOP_GPCR_PA14 /* Low */ -#define SPITZ_SCP_MUTE_R SCOOP_GPCR_PA15 /* Low */ -#define SPITZ_SCP_CF_POWER SCOOP_GPCR_PA16 /* Keep */ -#define SPITZ_SCP_LED_ORANGE SCOOP_GPCR_PA17 /* Keep */ -#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */ -#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */ - -#define SPITZ_SCP_IO_DIR (SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \ - SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | \ - SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) -#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R) -#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) -#define SPITZ_SCP_SUS_SET 0 - -#define SPITZ_SCP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) -#define SPITZ_GPIO_LED_GREEN (SPITZ_SCP_GPIO_BASE + 0) -#define SPITZ_GPIO_JK_B (SPITZ_SCP_GPIO_BASE + 1) -#define SPITZ_GPIO_CHRG_ON (SPITZ_SCP_GPIO_BASE + 2) -#define SPITZ_GPIO_MUTE_L (SPITZ_SCP_GPIO_BASE + 3) -#define SPITZ_GPIO_MUTE_R (SPITZ_SCP_GPIO_BASE + 4) -#define SPITZ_GPIO_CF_POWER (SPITZ_SCP_GPIO_BASE + 5) -#define SPITZ_GPIO_LED_ORANGE (SPITZ_SCP_GPIO_BASE + 6) -#define SPITZ_GPIO_JK_A (SPITZ_SCP_GPIO_BASE + 7) -#define SPITZ_GPIO_ADC_TEMP_ON (SPITZ_SCP_GPIO_BASE + 8) - -/* Spitz Scoop Device (No. 2) GPIOs */ -/* Suspend States in comments */ -#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */ -#define SPITZ_SCP2_AKIN_PULLUP SCOOP_GPCR_PA12 /* Keep */ -#define SPITZ_SCP2_RESERVED_1 SCOOP_GPCR_PA13 /* High */ -#define SPITZ_SCP2_RESERVED_2 SCOOP_GPCR_PA14 /* Low */ -#define SPITZ_SCP2_RESERVED_3 SCOOP_GPCR_PA15 /* Low */ -#define SPITZ_SCP2_RESERVED_4 SCOOP_GPCR_PA16 /* Low */ -#define SPITZ_SCP2_BACKLIGHT_CONT SCOOP_GPCR_PA17 /* Low */ -#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */ -#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */ - -#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \ - SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ - SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) - -#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1) -#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ - SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) -#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1) - -#define SPITZ_SCP2_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) -#define SPITZ_GPIO_IR_ON (SPITZ_SCP2_GPIO_BASE + 0) -#define SPITZ_GPIO_AKIN_PULLUP (SPITZ_SCP2_GPIO_BASE + 1) -#define SPITZ_GPIO_RESERVED_1 (SPITZ_SCP2_GPIO_BASE + 2) -#define SPITZ_GPIO_RESERVED_2 (SPITZ_SCP2_GPIO_BASE + 3) -#define SPITZ_GPIO_RESERVED_3 (SPITZ_SCP2_GPIO_BASE + 4) -#define SPITZ_GPIO_RESERVED_4 (SPITZ_SCP2_GPIO_BASE + 5) -#define SPITZ_GPIO_BACKLIGHT_CONT (SPITZ_SCP2_GPIO_BASE + 6) -#define SPITZ_GPIO_BACKLIGHT_ON (SPITZ_SCP2_GPIO_BASE + 7) -#define SPITZ_GPIO_MIC_BIAS (SPITZ_SCP2_GPIO_BASE + 8) - -/* Akita IO Expander GPIOs */ -#define AKITA_IOEXP_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) -#define AKITA_GPIO_RESERVED_0 (AKITA_IOEXP_GPIO_BASE + 0) -#define AKITA_GPIO_RESERVED_1 (AKITA_IOEXP_GPIO_BASE + 1) -#define AKITA_GPIO_MIC_BIAS (AKITA_IOEXP_GPIO_BASE + 2) -#define AKITA_GPIO_BACKLIGHT_ON (AKITA_IOEXP_GPIO_BASE + 3) -#define AKITA_GPIO_BACKLIGHT_CONT (AKITA_IOEXP_GPIO_BASE + 4) -#define AKITA_GPIO_AKIN_PULLUP (AKITA_IOEXP_GPIO_BASE + 5) -#define AKITA_GPIO_IR_ON (AKITA_IOEXP_GPIO_BASE + 6) -#define AKITA_GPIO_RESERVED_7 (AKITA_IOEXP_GPIO_BASE + 7) - -/* Spitz IRQ Definitions */ - -#define SPITZ_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_KEY_INT) -#define SPITZ_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_AC_IN) -#define SPITZ_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_AK_INT) -#define SPITZ_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_HP_IN) -#define SPITZ_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT) -#define SPITZ_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(SPITZ_GPIO_SYNC) -#define SPITZ_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(SPITZ_GPIO_ON_KEY) -#define SPITZ_IRQ_GPIO_SWA PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWA) -#define SPITZ_IRQ_GPIO_SWB PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWB) -#define SPITZ_IRQ_GPIO_BAT_COVER PXA_GPIO_TO_IRQ(SPITZ_GPIO_BAT_COVER) -#define SPITZ_IRQ_GPIO_FATAL_BAT PXA_GPIO_TO_IRQ(SPITZ_GPIO_FATAL_BAT) -#define SPITZ_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(SPITZ_GPIO_CO) -#define SPITZ_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_IRQ) -#define SPITZ_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_CD) -#define SPITZ_IRQ_GPIO_CF2_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF2_IRQ) -#define SPITZ_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_INT) -#define SPITZ_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_DETECT) - -/* - * Shared data structures - */ -extern struct platform_device spitzssp_device; -extern struct sharpsl_charger_machinfo spitz_pm_machinfo; diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index a648e7094e84..cd8f00945373 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -44,7 +44,7 @@ #include #include #include -#include +#include "spitz.h" #include "sharpsl_pm.h" #include @@ -962,11 +962,42 @@ static void __init spitz_i2c_init(void) static inline void spitz_i2c_init(void) {} #endif +static struct gpiod_lookup_table spitz_audio_gpio_table = { + .dev_id = "spitz-audio", + .table = { + GPIO_LOOKUP("sharp-scoop.0", SPITZ_GPIO_MUTE_L - SPITZ_SCP_GPIO_BASE, + "mute-l", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("sharp-scoop.0", SPITZ_GPIO_MUTE_R - SPITZ_SCP_GPIO_BASE, + "mute-r", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("sharp-scoop.1", SPITZ_GPIO_MIC_BIAS - SPITZ_SCP2_GPIO_BASE, + "mic", GPIO_ACTIVE_HIGH), + { }, + }, +}; + +static struct gpiod_lookup_table akita_audio_gpio_table = { + .dev_id = "spitz-audio", + .table = { + GPIO_LOOKUP("sharp-scoop.0", SPITZ_GPIO_MUTE_L - SPITZ_SCP_GPIO_BASE, + "mute-l", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("sharp-scoop.0", SPITZ_GPIO_MUTE_R - SPITZ_SCP_GPIO_BASE, + "mute-r", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("i2c-max7310", AKITA_GPIO_MIC_BIAS - AKITA_IOEXP_GPIO_BASE, + "mic", GPIO_ACTIVE_HIGH), + { }, + }, +}; + /****************************************************************************** * Audio devices ******************************************************************************/ static inline void spitz_audio_init(void) { + if (machine_is_akita()) + gpiod_add_lookup_table(&akita_audio_gpio_table); + else + gpiod_add_lookup_table(&spitz_audio_gpio_table); + platform_device_register_simple("spitz-audio", -1, NULL, 0); } diff --git a/arch/arm/mach-pxa/spitz.h b/arch/arm/mach-pxa/spitz.h new file mode 100644 index 000000000000..f97e3ebd762d --- /dev/null +++ b/arch/arm/mach-pxa/spitz.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Hardware specific definitions for SL-Cx000 series of PDAs + * + * Copyright (c) 2005 Alexander Wykes + * Copyright (c) 2005 Richard Purdie + * + * Based on Sharp's 2.4 kernel patches + */ +#ifndef __ASM_ARCH_SPITZ_H +#define __ASM_ARCH_SPITZ_H 1 +#endif + +#include /* PXA_NR_BUILTIN_GPIO, PXA_GPIO_TO_IRQ */ +#include + +/* Spitz/Akita GPIOs */ + +#define SPITZ_GPIO_KEY_INT (0) /* Key Interrupt */ +#define SPITZ_GPIO_RESET (1) +#define SPITZ_GPIO_nSD_DETECT (9) +#define SPITZ_GPIO_TP_INT (11) /* Touch Panel interrupt */ +#define SPITZ_GPIO_AK_INT (13) /* Remote Control */ +#define SPITZ_GPIO_ADS7846_CS (14) +#define SPITZ_GPIO_SYNC (16) +#define SPITZ_GPIO_MAX1111_CS (20) +#define SPITZ_GPIO_FATAL_BAT (21) +#define SPITZ_GPIO_HSYNC (22) +#define SPITZ_GPIO_nSD_CLK (32) +#define SPITZ_GPIO_USB_DEVICE (35) +#define SPITZ_GPIO_USB_HOST (37) +#define SPITZ_GPIO_USB_CONNECT (41) +#define SPITZ_GPIO_LCDCON_CS (53) +#define SPITZ_GPIO_nPCE (54) +#define SPITZ_GPIO_nSD_WP (81) +#define SPITZ_GPIO_ON_RESET (89) +#define SPITZ_GPIO_BAT_COVER (90) +#define SPITZ_GPIO_CF_CD (94) +#define SPITZ_GPIO_ON_KEY (95) +#define SPITZ_GPIO_SWA (97) +#define SPITZ_GPIO_SWB (96) +#define SPITZ_GPIO_CHRG_FULL (101) +#define SPITZ_GPIO_CO (101) +#define SPITZ_GPIO_CF_IRQ (105) +#define SPITZ_GPIO_AC_IN (115) +#define SPITZ_GPIO_HP_IN (116) + +/* Spitz Only GPIOs */ + +#define SPITZ_GPIO_CF2_IRQ (106) /* CF slot1 Ready */ +#define SPITZ_GPIO_CF2_CD (93) + + +/* Spitz/Akita Keyboard Definitions */ + +#define SPITZ_KEY_STROBE_NUM (11) +#define SPITZ_KEY_SENSE_NUM (7) +#define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000 +#define SPITZ_GPIO_G1_STROBE_BIT 0x00100000 +#define SPITZ_GPIO_G2_STROBE_BIT 0x01000000 +#define SPITZ_GPIO_G3_STROBE_BIT 0x00041880 +#define SPITZ_GPIO_G0_SENSE_BIT 0x00021000 +#define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4 +#define SPITZ_GPIO_G2_SENSE_BIT 0x08000000 +#define SPITZ_GPIO_G3_SENSE_BIT 0x00000000 + +#define SPITZ_GPIO_KEY_STROBE0 88 +#define SPITZ_GPIO_KEY_STROBE1 23 +#define SPITZ_GPIO_KEY_STROBE2 24 +#define SPITZ_GPIO_KEY_STROBE3 25 +#define SPITZ_GPIO_KEY_STROBE4 26 +#define SPITZ_GPIO_KEY_STROBE5 27 +#define SPITZ_GPIO_KEY_STROBE6 52 +#define SPITZ_GPIO_KEY_STROBE7 103 +#define SPITZ_GPIO_KEY_STROBE8 107 +#define SPITZ_GPIO_KEY_STROBE9 108 +#define SPITZ_GPIO_KEY_STROBE10 114 + +#define SPITZ_GPIO_KEY_SENSE0 12 +#define SPITZ_GPIO_KEY_SENSE1 17 +#define SPITZ_GPIO_KEY_SENSE2 91 +#define SPITZ_GPIO_KEY_SENSE3 34 +#define SPITZ_GPIO_KEY_SENSE4 36 +#define SPITZ_GPIO_KEY_SENSE5 38 +#define SPITZ_GPIO_KEY_SENSE6 39 + + +/* Spitz Scoop Device (No. 1) GPIOs */ +/* Suspend States in comments */ +#define SPITZ_SCP_LED_GREEN SCOOP_GPCR_PA11 /* Keep */ +#define SPITZ_SCP_JK_B SCOOP_GPCR_PA12 /* Keep */ +#define SPITZ_SCP_CHRG_ON SCOOP_GPCR_PA13 /* Keep */ +#define SPITZ_SCP_MUTE_L SCOOP_GPCR_PA14 /* Low */ +#define SPITZ_SCP_MUTE_R SCOOP_GPCR_PA15 /* Low */ +#define SPITZ_SCP_CF_POWER SCOOP_GPCR_PA16 /* Keep */ +#define SPITZ_SCP_LED_ORANGE SCOOP_GPCR_PA17 /* Keep */ +#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */ +#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */ + +#define SPITZ_SCP_IO_DIR (SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \ + SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | \ + SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) +#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R) +#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) +#define SPITZ_SCP_SUS_SET 0 + +#define SPITZ_SCP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) +#define SPITZ_GPIO_LED_GREEN (SPITZ_SCP_GPIO_BASE + 0) +#define SPITZ_GPIO_JK_B (SPITZ_SCP_GPIO_BASE + 1) +#define SPITZ_GPIO_CHRG_ON (SPITZ_SCP_GPIO_BASE + 2) +#define SPITZ_GPIO_MUTE_L (SPITZ_SCP_GPIO_BASE + 3) +#define SPITZ_GPIO_MUTE_R (SPITZ_SCP_GPIO_BASE + 4) +#define SPITZ_GPIO_CF_POWER (SPITZ_SCP_GPIO_BASE + 5) +#define SPITZ_GPIO_LED_ORANGE (SPITZ_SCP_GPIO_BASE + 6) +#define SPITZ_GPIO_JK_A (SPITZ_SCP_GPIO_BASE + 7) +#define SPITZ_GPIO_ADC_TEMP_ON (SPITZ_SCP_GPIO_BASE + 8) + +/* Spitz Scoop Device (No. 2) GPIOs */ +/* Suspend States in comments */ +#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */ +#define SPITZ_SCP2_AKIN_PULLUP SCOOP_GPCR_PA12 /* Keep */ +#define SPITZ_SCP2_RESERVED_1 SCOOP_GPCR_PA13 /* High */ +#define SPITZ_SCP2_RESERVED_2 SCOOP_GPCR_PA14 /* Low */ +#define SPITZ_SCP2_RESERVED_3 SCOOP_GPCR_PA15 /* Low */ +#define SPITZ_SCP2_RESERVED_4 SCOOP_GPCR_PA16 /* Low */ +#define SPITZ_SCP2_BACKLIGHT_CONT SCOOP_GPCR_PA17 /* Low */ +#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */ +#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */ + +#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \ + SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ + SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) + +#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1) +#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ + SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) +#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1) + +#define SPITZ_SCP2_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) +#define SPITZ_GPIO_IR_ON (SPITZ_SCP2_GPIO_BASE + 0) +#define SPITZ_GPIO_AKIN_PULLUP (SPITZ_SCP2_GPIO_BASE + 1) +#define SPITZ_GPIO_RESERVED_1 (SPITZ_SCP2_GPIO_BASE + 2) +#define SPITZ_GPIO_RESERVED_2 (SPITZ_SCP2_GPIO_BASE + 3) +#define SPITZ_GPIO_RESERVED_3 (SPITZ_SCP2_GPIO_BASE + 4) +#define SPITZ_GPIO_RESERVED_4 (SPITZ_SCP2_GPIO_BASE + 5) +#define SPITZ_GPIO_BACKLIGHT_CONT (SPITZ_SCP2_GPIO_BASE + 6) +#define SPITZ_GPIO_BACKLIGHT_ON (SPITZ_SCP2_GPIO_BASE + 7) +#define SPITZ_GPIO_MIC_BIAS (SPITZ_SCP2_GPIO_BASE + 8) + +/* Akita IO Expander GPIOs */ +#define AKITA_IOEXP_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) +#define AKITA_GPIO_RESERVED_0 (AKITA_IOEXP_GPIO_BASE + 0) +#define AKITA_GPIO_RESERVED_1 (AKITA_IOEXP_GPIO_BASE + 1) +#define AKITA_GPIO_MIC_BIAS (AKITA_IOEXP_GPIO_BASE + 2) +#define AKITA_GPIO_BACKLIGHT_ON (AKITA_IOEXP_GPIO_BASE + 3) +#define AKITA_GPIO_BACKLIGHT_CONT (AKITA_IOEXP_GPIO_BASE + 4) +#define AKITA_GPIO_AKIN_PULLUP (AKITA_IOEXP_GPIO_BASE + 5) +#define AKITA_GPIO_IR_ON (AKITA_IOEXP_GPIO_BASE + 6) +#define AKITA_GPIO_RESERVED_7 (AKITA_IOEXP_GPIO_BASE + 7) + +/* Spitz IRQ Definitions */ + +#define SPITZ_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_KEY_INT) +#define SPITZ_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_AC_IN) +#define SPITZ_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_AK_INT) +#define SPITZ_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_HP_IN) +#define SPITZ_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT) +#define SPITZ_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(SPITZ_GPIO_SYNC) +#define SPITZ_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(SPITZ_GPIO_ON_KEY) +#define SPITZ_IRQ_GPIO_SWA PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWA) +#define SPITZ_IRQ_GPIO_SWB PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWB) +#define SPITZ_IRQ_GPIO_BAT_COVER PXA_GPIO_TO_IRQ(SPITZ_GPIO_BAT_COVER) +#define SPITZ_IRQ_GPIO_FATAL_BAT PXA_GPIO_TO_IRQ(SPITZ_GPIO_FATAL_BAT) +#define SPITZ_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(SPITZ_GPIO_CO) +#define SPITZ_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_IRQ) +#define SPITZ_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_CD) +#define SPITZ_IRQ_GPIO_CF2_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF2_IRQ) +#define SPITZ_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_INT) +#define SPITZ_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_DETECT) + +/* + * Shared data structures + */ +extern struct platform_device spitzssp_device; +extern struct sharpsl_charger_machinfo spitz_pm_machinfo; diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 201dabe883b6..6689b67f9ce5 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c @@ -19,7 +19,7 @@ #include #include -#include +#include "spitz.h" #include "pxa27x.h" #include "sharpsl_pm.h" -- cgit From 216459838355b66a7dc617bfb727878dd8631431 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 17 Sep 2019 14:25:44 +0200 Subject: ARM: pxa: eseries: use gpio lookup for audio The three eseries machines have very similar drivers for audio, all using the mach/eseries-gpio.h header for finding the gpio numbers. Change these to use gpio descriptors to avoid the header file dependency. I convert the _OFF gpio numbers into GPIO_ACTIVE_LOW ones for consistency here. Acked-by: Mark Brown Acked-by: Robert Jarzmik Reviewed-by: Linus Walleij Cc: alsa-devel@alsa-project.org Signed-off-by: Arnd Bergmann --- arch/arm/mach-pxa/eseries.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index 1e9d6bbf4555..0955c7b23014 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -24,6 +24,7 @@ #include #include #include +#include #include