From 3f2870989f10ddb276063097d8e44e543277694a Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Mon, 10 May 2021 20:51:59 +0800 Subject: bpf, arm64: Replace STACK_ALIGN() with round_up() to align stack size Use the common function round_up() directly to show the align size explicitly, the function STACK_ALIGN() is needless, remove it. Other JITs also just rely on round_up(). Signed-off-by: Tiezhu Yang Signed-off-by: Daniel Borkmann Link: https://lore.kernel.org/bpf/1620651119-5663-1-git-send-email-yangtiezhu@loongson.cn --- arch/arm64/net/bpf_jit_comp.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index f7b194878a99..978502629f4e 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -178,9 +178,6 @@ static bool is_addsub_imm(u32 imm) return !(imm & ~0xfff) || !(imm & ~0xfff000); } -/* Stack must be multiples of 16B */ -#define STACK_ALIGN(sz) (((sz) + 15) & ~15) - /* Tail call offset to jump into */ #if IS_ENABLED(CONFIG_ARM64_BTI_KERNEL) #define PROLOGUE_OFFSET 8 @@ -255,7 +252,8 @@ static int build_prologue(struct jit_ctx *ctx, bool ebpf_from_cbpf) emit(A64_BTI_J, ctx); } - ctx->stack_size = STACK_ALIGN(prog->aux->stack_depth); + /* Stack must be multiples of 16B */ + ctx->stack_size = round_up(prog->aux->stack_depth, 16); /* Set up function call stack */ emit(A64_SUB_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); -- cgit From 8d1a81f21a9e0c5967bbec1918a777369dc07856 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 13:38:13 +0200 Subject: arm64: dts: rockchip: add gmac to rk3308 dts The RK3308 SoC has a gmac with only the RMII interface exposed. This commit adds it to the RK3308 dtsi. Signed-off-by: Tobias Schramm Signed-off-by: David S. Miller --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 0c5fa9801e6f..b815ce73e5c6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -637,6 +637,28 @@ status = "disabled"; }; + gmac: ethernet@ff4e0000 { + compatible = "rockchip,rk3308-gmac"; + reg = <0x0 0xff4e0000 0x0 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, + <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, + <&cru SCLK_MAC>, <&cru ACLK_MAC>, + <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac", "clk_mac_speed"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; + resets = <&cru SRST_MAC_A>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + cru: clock-controller@ff500000 { compatible = "rockchip,rk3308-cru"; reg = <0x0 0xff500000 0x0 0x1000>; -- cgit From 119220d81258c1e79db9aa7b52ef09b945aaf46f Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 18 May 2021 16:56:10 +0800 Subject: bpf, arm64: Remove redundant switch case about BPF_DIV and BPF_MOD After commit 96a71005bdcb ("bpf, arm64: remove obsolete exception handling from div/mod"), there is no need to check twice about BPF_DIV and BPF_MOD, remove the redundant switch case. Signed-off-by: Tiezhu Yang Signed-off-by: Daniel Borkmann Link: https://lore.kernel.org/bpf/1621328170-17583-1-git-send-email-yangtiezhu@loongson.cn --- arch/arm64/net/bpf_jit_comp.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index 978502629f4e..be873a7da62b 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -485,17 +485,12 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, break; case BPF_ALU | BPF_DIV | BPF_X: case BPF_ALU64 | BPF_DIV | BPF_X: + emit(A64_UDIV(is64, dst, dst, src), ctx); + break; case BPF_ALU | BPF_MOD | BPF_X: case BPF_ALU64 | BPF_MOD | BPF_X: - switch (BPF_OP(code)) { - case BPF_DIV: - emit(A64_UDIV(is64, dst, dst, src), ctx); - break; - case BPF_MOD: - emit(A64_UDIV(is64, tmp, dst, src), ctx); - emit(A64_MSUB(is64, dst, dst, tmp, src), ctx); - break; - } + emit(A64_UDIV(is64, tmp, dst, src), ctx); + emit(A64_MSUB(is64, dst, dst, tmp, src), ctx); break; case BPF_ALU | BPF_LSH | BPF_X: case BPF_ALU64 | BPF_LSH | BPF_X: -- cgit From 838e4cc80814aad973fbfdd836b2b25eb27681f1 Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Fri, 11 Jun 2021 09:33:38 +0200 Subject: s390/qeth: remove QAOB's pointer to its TX buffer Maintaining a pointer inside the aob's user-definable area is fragile and unnecessary. At this stage we only need it to overload the buffer's state field, and to access the buffer's TX queue. The first part is easily solved by tracking the aob's state within the aob itself. This also feels much cleaner and self-contained. For enabling the access to the associated TX queue, we can store the queue's index in the aob. Signed-off-by: Julian Wiedmann Signed-off-by: David S. Miller --- arch/s390/include/asm/qdio.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index 8fc52679543d..cb4f73c7228d 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -137,7 +137,6 @@ struct slibe { * @user0: user defineable value * @res4: reserved paramater * @user1: user defineable value - * @user2: user defineable value */ struct qaob { u64 res0[6]; @@ -152,8 +151,7 @@ struct qaob { u16 dcount[QDIO_MAX_ELEMENTS_PER_BUFFER]; u64 user0; u64 res4[2]; - u64 user1; - u64 user2; + u8 user1[16]; } __attribute__ ((packed, aligned(256))); /** -- cgit From f8a11425075ff11b4b5784f077cb84f3d2dfb3f0 Mon Sep 17 00:00:00 2001 From: Qing Zhang Date: Fri, 18 Jun 2021 10:53:35 +0800 Subject: MIPS: Loongson64: Add GMAC support for Loongson-2K1000 The GMAC module is now supported, enable it. Signed-off-by: Qing Zhang Signed-off-by: David S. Miller --- arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch') diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi index 569e814def83..5747f171de29 100644 --- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi +++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi @@ -114,6 +114,52 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000 0x0 0x00010000>, <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; + gmac@3,0 { + compatible = "pci0014,7a03.0", + "pci0014,7a03", + "pciclass0c0320", + "pciclass0c03", + "loongson, pci-gmac"; + + reg = <0x1800 0x0 0x0 0x0 0x0>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>, + <13 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "macirq", "eth_lpi"; + interrupt-parent = <&liointc0>; + phy-mode = "rgmii"; + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + + gmac@3,1 { + compatible = "pci0014,7a03.0", + "pci0014,7a03", + "pciclass0c0320", + "pciclass0c03", + "loongson, pci-gmac"; + + reg = <0x1900 0x0 0x0 0x0 0x0>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>, + <15 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "macirq", "eth_lpi"; + interrupt-parent = <&liointc0>; + phy-mode = "rgmii"; + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1: ethernet-phy@1 { + reg = <0>; + }; + }; + }; + ehci@4,1 { compatible = "pci0014,7a14.0", "pci0014,7a14", -- cgit From 47a311c31a51e44130c92dc11f9f0d7c8c1f9be0 Mon Sep 17 00:00:00 2001 From: Qing Zhang Date: Fri, 18 Jun 2021 10:53:36 +0800 Subject: MIPS: Loongson64: DTS: Add GMAC support for LS7A PCH The GMAC module is now supported, enable it. Signed-off-by: Qing Zhang Signed-off-by: David S. Miller --- arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi index f99a7a11fded..58b9bb47c58a 100644 --- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi +++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi @@ -186,7 +186,8 @@ compatible = "pci0014,7a03.0", "pci0014,7a03", "pciclass020000", - "pciclass0200"; + "pciclass0200", + "loongson, pci-gmac"; reg = <0x1800 0x0 0x0 0x0 0x0>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, @@ -208,7 +209,8 @@ compatible = "pci0014,7a03.0", "pci0014,7a03", "pciclass020000", - "pciclass0200"; + "pciclass0200", + "loongson, pci-gmac"; reg = <0x1900 0x0 0x0 0x0 0x0>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, -- cgit From ced50fc49f3bde2892c3d7fad7b3b6bfbc6ef90e Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Wed, 23 Jun 2021 13:25:04 +0200 Subject: bpf, x86: Remove unused cnt increase from EMIT macro Removing unused cnt increase from EMIT macro together with cnt declarations. This was introduced in commit [1] to ensure proper code generation. But that code was removed in commit [2] and this extra code was left in. [1] b52f00e6a715 ("x86: bpf_jit: implement bpf_tail_call() helper") [2] ebf7d1f508a7 ("bpf, x64: rework pro/epilogue and tailcall handling in JIT") Signed-off-by: Jiri Olsa Signed-off-by: Daniel Borkmann Link: https://lore.kernel.org/bpf/20210623112504.709856-1-jolsa@kernel.org --- arch/x86/net/bpf_jit_comp.c | 44 ++++++++++++-------------------------------- 1 file changed, 12 insertions(+), 32 deletions(-) (limited to 'arch') diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index 2a2e290fa5d8..db1e83813db5 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -31,7 +31,7 @@ static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len) } #define EMIT(bytes, len) \ - do { prog = emit_code(prog, bytes, len); cnt += len; } while (0) + do { prog = emit_code(prog, bytes, len); } while (0) #define EMIT1(b1) EMIT(b1, 1) #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2) @@ -239,7 +239,6 @@ struct jit_context { static void push_callee_regs(u8 **pprog, bool *callee_regs_used) { u8 *prog = *pprog; - int cnt = 0; if (callee_regs_used[0]) EMIT1(0x53); /* push rbx */ @@ -255,7 +254,6 @@ static void push_callee_regs(u8 **pprog, bool *callee_regs_used) static void pop_callee_regs(u8 **pprog, bool *callee_regs_used) { u8 *prog = *pprog; - int cnt = 0; if (callee_regs_used[3]) EMIT2(0x41, 0x5F); /* pop r15 */ @@ -277,13 +275,12 @@ static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf, bool tail_call_reachable, bool is_subprog) { u8 *prog = *pprog; - int cnt = X86_PATCH_SIZE; /* BPF trampoline can be made to work without these nops, * but let's waste 5 bytes for now and optimize later */ - memcpy(prog, x86_nops[5], cnt); - prog += cnt; + memcpy(prog, x86_nops[5], X86_PATCH_SIZE); + prog += X86_PATCH_SIZE; if (!ebpf_from_cbpf) { if (tail_call_reachable && !is_subprog) EMIT2(0x31, 0xC0); /* xor eax, eax */ @@ -303,7 +300,6 @@ static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf, static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode) { u8 *prog = *pprog; - int cnt = 0; s64 offset; offset = func - (ip + X86_PATCH_SIZE); @@ -423,7 +419,6 @@ static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used, int off1 = 42; int off2 = 31; int off3 = 9; - int cnt = 0; /* count the additional bytes used for popping callee regs from stack * that need to be taken into account for each of the offsets that @@ -513,7 +508,6 @@ static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke, int pop_bytes = 0; int off1 = 20; int poke_off; - int cnt = 0; /* count the additional bytes used for popping callee regs to stack * that need to be taken into account for jump offset that is used for @@ -615,7 +609,6 @@ static void emit_mov_imm32(u8 **pprog, bool sign_propagate, { u8 *prog = *pprog; u8 b1, b2, b3; - int cnt = 0; /* * Optimization: if imm32 is positive, use 'mov %eax, imm32' @@ -655,7 +648,6 @@ static void emit_mov_imm64(u8 **pprog, u32 dst_reg, const u32 imm32_hi, const u32 imm32_lo) { u8 *prog = *pprog; - int cnt = 0; if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) { /* @@ -678,7 +670,6 @@ static void emit_mov_imm64(u8 **pprog, u32 dst_reg, static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg) { u8 *prog = *pprog; - int cnt = 0; if (is64) { /* mov dst, src */ @@ -697,7 +688,6 @@ static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg) static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off) { u8 *prog = *pprog; - int cnt = 0; if (is_imm8(off)) { /* 1-byte signed displacement. @@ -720,7 +710,6 @@ static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off) static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64) { u8 *prog = *pprog; - int cnt = 0; if (is64) EMIT1(add_2mod(0x48, dst_reg, src_reg)); @@ -733,7 +722,6 @@ static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64) static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) { u8 *prog = *pprog; - int cnt = 0; switch (size) { case BPF_B: @@ -764,7 +752,6 @@ static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) { u8 *prog = *pprog; - int cnt = 0; switch (size) { case BPF_B: @@ -799,7 +786,6 @@ static int emit_atomic(u8 **pprog, u8 atomic_op, u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size) { u8 *prog = *pprog; - int cnt = 0; EMIT1(0xF0); /* lock prefix */ @@ -869,10 +855,10 @@ static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt, } } -static int emit_nops(u8 **pprog, int len) +static void emit_nops(u8 **pprog, int len) { u8 *prog = *pprog; - int i, noplen, cnt = 0; + int i, noplen; while (len > 0) { noplen = len; @@ -886,8 +872,6 @@ static int emit_nops(u8 **pprog, int len) } *pprog = prog; - - return cnt; } #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp))) @@ -902,7 +886,7 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, bool tail_call_seen = false; bool seen_exit = false; u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY]; - int i, cnt = 0, excnt = 0; + int i, excnt = 0; int ilen, proglen = 0; u8 *prog = temp; int err; @@ -1576,7 +1560,7 @@ emit_cond_jmp: /* Convert BPF opcode to x86 */ nops); return -EFAULT; } - cnt += emit_nops(&prog, nops); + emit_nops(&prog, nops); } EMIT2(jmp_cond, jmp_offset); } else if (is_simm32(jmp_offset)) { @@ -1622,7 +1606,7 @@ emit_cond_jmp: /* Convert BPF opcode to x86 */ nops); return -EFAULT; } - cnt += emit_nops(&prog, nops); + emit_nops(&prog, nops); } break; } @@ -1647,7 +1631,7 @@ emit_jmp: nops); return -EFAULT; } - cnt += emit_nops(&prog, INSN_SZ_DIFF - 2); + emit_nops(&prog, INSN_SZ_DIFF - 2); } EMIT2(0xEB, jmp_offset); } else if (is_simm32(jmp_offset)) { @@ -1754,7 +1738,6 @@ static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog, { u8 *prog = *pprog; u8 *jmp_insn; - int cnt = 0; /* arg1: mov rdi, progs[i] */ emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); @@ -1822,7 +1805,6 @@ static void emit_align(u8 **pprog, u32 align) static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond) { u8 *prog = *pprog; - int cnt = 0; s64 offset; offset = func - (ip + 2 + 4); @@ -1854,7 +1836,7 @@ static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog, u8 **branches) { u8 *prog = *pprog; - int i, cnt = 0; + int i; /* The first fmod_ret program will receive a garbage return value. * Set this to 0 to avoid confusing the program. @@ -1950,7 +1932,7 @@ int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *i struct bpf_tramp_progs *tprogs, void *orig_call) { - int ret, i, cnt = 0, nr_args = m->nr_args; + int ret, i, nr_args = m->nr_args; int stack_size = nr_args * 8; struct bpf_tramp_progs *fentry = &tprogs[BPF_TRAMP_FENTRY]; struct bpf_tramp_progs *fexit = &tprogs[BPF_TRAMP_FEXIT]; @@ -2095,8 +2077,6 @@ static int emit_fallback_jump(u8 **pprog) */ err = emit_jump(&prog, __x86_indirect_thunk_rdx, prog); #else - int cnt = 0; - EMIT2(0xFF, 0xE2); /* jmp rdx */ #endif *pprog = prog; @@ -2106,7 +2086,7 @@ static int emit_fallback_jump(u8 **pprog) static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs) { u8 *jg_reloc, *prog = *pprog; - int pivot, err, jg_bytes = 1, cnt = 0; + int pivot, err, jg_bytes = 1; s64 jg_offset; if (a == b) { -- cgit From e8b9eab99232c4e62ada9d7976c80fd5e8118289 Mon Sep 17 00:00:00 2001 From: Martynas Pumputis Date: Wed, 23 Jun 2021 15:56:45 +0200 Subject: net: retrieve netns cookie via getsocketopt It's getting more common to run nested container environments for testing cloud software. One of such examples is Kind [1] which runs a Kubernetes cluster in Docker containers on a single host. Each container acts as a Kubernetes node, and thus can run any Pod (aka container) inside the former. This approach simplifies testing a lot, as it eliminates complicated VM setups. Unfortunately, such a setup breaks some functionality when cgroupv2 BPF programs are used for load-balancing. The load-balancer BPF program needs to detect whether a request originates from the host netns or a container netns in order to allow some access, e.g. to a service via a loopback IP address. Typically, the programs detect this by comparing netns cookies with the one of the init ns via a call to bpf_get_netns_cookie(NULL). However, in nested environments the latter cannot be used given the Kubernetes node's netns is outside the init ns. To fix this, we need to pass the Kubernetes node netns cookie to the program in a different way: by extending getsockopt() with a SO_NETNS_COOKIE option, the orchestrator which runs in the Kubernetes node netns can retrieve the cookie and pass it to the program instead. Thus, this is following up on Eric's commit 3d368ab87cf6 ("net: initialize net->net_cookie at netns setup") to allow retrieval via SO_NETNS_COOKIE. This is also in line in how we retrieve socket cookie via SO_COOKIE. [1] https://kind.sigs.k8s.io/ Signed-off-by: Lorenz Bauer Signed-off-by: Martynas Pumputis Cc: Eric Dumazet Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller --- arch/alpha/include/uapi/asm/socket.h | 2 ++ arch/mips/include/uapi/asm/socket.h | 2 ++ arch/parisc/include/uapi/asm/socket.h | 2 ++ arch/sparc/include/uapi/asm/socket.h | 2 ++ 4 files changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/alpha/include/uapi/asm/socket.h b/arch/alpha/include/uapi/asm/socket.h index 57420356ce4c..6b3daba60987 100644 --- a/arch/alpha/include/uapi/asm/socket.h +++ b/arch/alpha/include/uapi/asm/socket.h @@ -127,6 +127,8 @@ #define SO_PREFER_BUSY_POLL 69 #define SO_BUSY_POLL_BUDGET 70 +#define SO_NETNS_COOKIE 71 + #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h index 2d949969313b..cdf404a831b2 100644 --- a/arch/mips/include/uapi/asm/socket.h +++ b/arch/mips/include/uapi/asm/socket.h @@ -138,6 +138,8 @@ #define SO_PREFER_BUSY_POLL 69 #define SO_BUSY_POLL_BUDGET 70 +#define SO_NETNS_COOKIE 71 + #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 diff --git a/arch/parisc/include/uapi/asm/socket.h b/arch/parisc/include/uapi/asm/socket.h index f60904329bbc..5b5351cdcb33 100644 --- a/arch/parisc/include/uapi/asm/socket.h +++ b/arch/parisc/include/uapi/asm/socket.h @@ -119,6 +119,8 @@ #define SO_PREFER_BUSY_POLL 0x4043 #define SO_BUSY_POLL_BUDGET 0x4044 +#define SO_NETNS_COOKIE 0x4045 + #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 diff --git a/arch/sparc/include/uapi/asm/socket.h b/arch/sparc/include/uapi/asm/socket.h index 848a22fbac20..92675dc380fa 100644 --- a/arch/sparc/include/uapi/asm/socket.h +++ b/arch/sparc/include/uapi/asm/socket.h @@ -120,6 +120,8 @@ #define SO_PREFER_BUSY_POLL 0x0048 #define SO_BUSY_POLL_BUDGET 0x0049 +#define SO_NETNS_COOKIE 0x0050 + #if !defined(__KERNEL__) -- cgit From d0f482bb06f9447d44d2cae0386a0bd768c3cc16 Mon Sep 17 00:00:00 2001 From: Steen Hegelund Date: Thu, 24 Jun 2021 09:07:58 +0200 Subject: arm64: dts: sparx5: Add the Sparx5 switch node This provides the configuration for the currently available evaluation boards PCB134 and PCB135. The series depends on the following series currently on its way into the kernel: - Sparx5 Reset Driver Link: https://lore.kernel.org/r/20210416084054.2922327-1-steen.hegelund@microchip.com/ Signed-off-by: Steen Hegelund Signed-off-by: Lars Povlsen Signed-off-by: Bjarni Jonasson Signed-off-by: David S. Miller --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 94 +++- .../boot/dts/microchip/sparx5_pcb134_board.dtsi | 481 ++++++++++++++-- .../boot/dts/microchip/sparx5_pcb135_board.dtsi | 621 ++++++++++++++++++++- 3 files changed, 1112 insertions(+), 84 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index d64621d1213b..ad07fff40544 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -135,9 +135,12 @@ }; }; - reset@611010008 { - compatible = "microchip,sparx5-chip-reset"; + reset: reset-controller@611010008 { + compatible = "microchip,sparx5-switch-reset"; reg = <0x6 0x11010008 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; }; uart0: serial@600100000 { @@ -275,6 +278,21 @@ "GPIO_46", "GPIO_47"; function = "emmc"; }; + + miim1_pins: miim1-pins { + pins = "GPIO_56", "GPIO_57"; + function = "miim"; + }; + + miim2_pins: miim2-pins { + pins = "GPIO_58", "GPIO_59"; + function = "miim"; + }; + + miim3_pins: miim3-pins { + pins = "GPIO_52", "GPIO_53"; + function = "miim"; + }; }; sgpio0: gpio@61101036c { @@ -285,6 +303,8 @@ clocks = <&sys_clk>; pinctrl-0 = <&sgpio0_pins>; pinctrl-names = "default"; + resets = <&reset 0>; + reset-names = "switch"; reg = <0x6 0x1101036c 0x100>; sgpio_in0: gpio@0 { compatible = "microchip,sparx5-sgpio-bank"; @@ -292,6 +312,9 @@ gpio-controller; #gpio-cells = <3>; ngpios = <96>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; }; sgpio_out0: gpio@1 { compatible = "microchip,sparx5-sgpio-bank"; @@ -310,6 +333,8 @@ clocks = <&sys_clk>; pinctrl-0 = <&sgpio1_pins>; pinctrl-names = "default"; + resets = <&reset 0>; + reset-names = "switch"; reg = <0x6 0x11010484 0x100>; sgpio_in1: gpio@0 { compatible = "microchip,sparx5-sgpio-bank"; @@ -317,6 +342,9 @@ gpio-controller; #gpio-cells = <3>; ngpios = <96>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; }; sgpio_out1: gpio@1 { compatible = "microchip,sparx5-sgpio-bank"; @@ -335,6 +363,8 @@ clocks = <&sys_clk>; pinctrl-0 = <&sgpio2_pins>; pinctrl-names = "default"; + resets = <&reset 0>; + reset-names = "switch"; reg = <0x6 0x1101059c 0x100>; sgpio_in2: gpio@0 { reg = <0>; @@ -342,6 +372,9 @@ gpio-controller; #gpio-cells = <3>; ngpios = <96>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; }; sgpio_out2: gpio@1 { compatible = "microchip,sparx5-sgpio-bank"; @@ -386,5 +419,62 @@ #thermal-sensor-cells = <0>; clocks = <&ahb_clk>; }; + + mdio0: mdio@6110102b0 { + compatible = "mscc,ocelot-miim"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6 0x110102b0 0x24>; + }; + + mdio1: mdio@6110102d4 { + compatible = "mscc,ocelot-miim"; + status = "disabled"; + pinctrl-0 = <&miim1_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6 0x110102d4 0x24>; + }; + + mdio2: mdio@6110102f8 { + compatible = "mscc,ocelot-miim"; + status = "disabled"; + pinctrl-0 = <&miim2_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6 0x110102d4 0x24>; + }; + + mdio3: mdio@61101031c { + compatible = "mscc,ocelot-miim"; + status = "disabled"; + pinctrl-0 = <&miim3_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6 0x1101031c 0x24>; + }; + + serdes: serdes@10808000 { + compatible = "microchip,sparx5-serdes"; + #phy-cells = <1>; + clocks = <&sys_clk>; + reg = <0x6 0x10808000 0x5d0000>; + }; + + switch: switch@0x600000000 { + compatible = "microchip,sparx5-switch"; + reg = <0x6 0 0x401000>, + <0x6 0x10004000 0x7fc000>, + <0x6 0x11010000 0xaf0000>; + reg-names = "cpu", "dev", "gcb"; + interrupt-names = "xtr"; + interrupts = ; + resets = <&reset 0>; + reset-names = "switch"; + }; }; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index f0c915160990..33faf1f3264f 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -7,30 +7,6 @@ #include "sparx5_pcb_common.dtsi" /{ - aliases { - i2c0 = &i2c0; - i2c100 = &i2c100; - i2c101 = &i2c101; - i2c102 = &i2c102; - i2c103 = &i2c103; - i2c104 = &i2c104; - i2c105 = &i2c105; - i2c106 = &i2c106; - i2c107 = &i2c107; - i2c108 = &i2c108; - i2c109 = &i2c109; - i2c110 = &i2c110; - i2c111 = &i2c111; - i2c112 = &i2c112; - i2c113 = &i2c113; - i2c114 = &i2c114; - i2c115 = &i2c115; - i2c116 = &i2c116; - i2c117 = &i2c117; - i2c118 = &i2c118; - i2c119 = &i2c119; - }; - gpio-restart { compatible = "gpio-restart"; gpios = <&gpio 37 GPIO_ACTIVE_LOW>; @@ -298,17 +274,10 @@ &spi0 { status = "okay"; - spi@0 { - compatible = "spi-mux"; - mux-controls = <&mux>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; /* CS0 */ - spi-flash@9 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <8000000>; - reg = <0x9>; /* SPI */ - }; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0>; }; }; @@ -328,6 +297,33 @@ }; }; +&sgpio0 { + status = "okay"; + microchip,sgpio-port-ranges = <8 15>; + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + +&sgpio1 { + status = "okay"; + microchip,sgpio-port-ranges = <24 31>; + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + +&sgpio2 { + status = "okay"; + microchip,sgpio-port-ranges = <0 0>, <11 31>; +}; + &gpio { i2cmux_pins_i: i2cmux-pins-i { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", @@ -415,9 +411,9 @@ &i2c0_imux { pinctrl-names = - "i2c100", "i2c101", "i2c102", "i2c103", - "i2c104", "i2c105", "i2c106", "i2c107", - "i2c108", "i2c109", "i2c110", "i2c111", "idle"; + "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4", + "i2c_sfp5", "i2c_sfp6", "i2c_sfp7", "i2c_sfp8", + "i2c_sfp9", "i2c_sfp10", "i2c_sfp11", "i2c_sfp12", "idle"; pinctrl-0 = <&i2cmux_0>; pinctrl-1 = <&i2cmux_1>; pinctrl-2 = <&i2cmux_2>; @@ -431,62 +427,62 @@ pinctrl-10 = <&i2cmux_10>; pinctrl-11 = <&i2cmux_11>; pinctrl-12 = <&i2cmux_pins_i>; - i2c100: i2c_sfp1 { + i2c_sfp1: i2c_sfp1 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; }; - i2c101: i2c_sfp2 { + i2c_sfp2: i2c_sfp2 { reg = <0x1>; #address-cells = <1>; #size-cells = <0>; }; - i2c102: i2c_sfp3 { + i2c_sfp3: i2c_sfp3 { reg = <0x2>; #address-cells = <1>; #size-cells = <0>; }; - i2c103: i2c_sfp4 { + i2c_sfp4: i2c_sfp4 { reg = <0x3>; #address-cells = <1>; #size-cells = <0>; }; - i2c104: i2c_sfp5 { + i2c_sfp5: i2c_sfp5 { reg = <0x4>; #address-cells = <1>; #size-cells = <0>; }; - i2c105: i2c_sfp6 { + i2c_sfp6: i2c_sfp6 { reg = <0x5>; #address-cells = <1>; #size-cells = <0>; }; - i2c106: i2c_sfp7 { + i2c_sfp7: i2c_sfp7 { reg = <0x6>; #address-cells = <1>; #size-cells = <0>; }; - i2c107: i2c_sfp8 { + i2c_sfp8: i2c_sfp8 { reg = <0x7>; #address-cells = <1>; #size-cells = <0>; }; - i2c108: i2c_sfp9 { + i2c_sfp9: i2c_sfp9 { reg = <0x8>; #address-cells = <1>; #size-cells = <0>; }; - i2c109: i2c_sfp10 { + i2c_sfp10: i2c_sfp10 { reg = <0x9>; #address-cells = <1>; #size-cells = <0>; }; - i2c110: i2c_sfp11 { + i2c_sfp11: i2c_sfp11 { reg = <0xa>; #address-cells = <1>; #size-cells = <0>; }; - i2c111: i2c_sfp12 { + i2c_sfp12: i2c_sfp12 { reg = <0xb>; #address-cells = <1>; #size-cells = <0>; @@ -499,44 +495,413 @@ &gpio 61 GPIO_ACTIVE_HIGH &gpio 54 GPIO_ACTIVE_HIGH>; idle-state = <0x8>; - i2c112: i2c_sfp13 { + i2c_sfp13: i2c_sfp13 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; }; - i2c113: i2c_sfp14 { + i2c_sfp14: i2c_sfp14 { reg = <0x1>; #address-cells = <1>; #size-cells = <0>; }; - i2c114: i2c_sfp15 { + i2c_sfp15: i2c_sfp15 { reg = <0x2>; #address-cells = <1>; #size-cells = <0>; }; - i2c115: i2c_sfp16 { + i2c_sfp16: i2c_sfp16 { reg = <0x3>; #address-cells = <1>; #size-cells = <0>; }; - i2c116: i2c_sfp17 { + i2c_sfp17: i2c_sfp17 { reg = <0x4>; #address-cells = <1>; #size-cells = <0>; }; - i2c117: i2c_sfp18 { + i2c_sfp18: i2c_sfp18 { reg = <0x5>; #address-cells = <1>; #size-cells = <0>; }; - i2c118: i2c_sfp19 { + i2c_sfp19: i2c_sfp19 { reg = <0x6>; #address-cells = <1>; #size-cells = <0>; }; - i2c119: i2c_sfp20 { + i2c_sfp20: i2c_sfp20 { reg = <0x7>; #address-cells = <1>; #size-cells = <0>; }; }; + +&mdio3 { + status = "ok"; + phy64: ethernet-phy@64 { + reg = <28>; + }; +}; + +&axi { + sfp_eth12: sfp-eth12 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth13: sfp-eth13 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth14: sfp-eth14 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp3>; + tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth15: sfp-eth15 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp4>; + tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth48: sfp-eth48 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp5>; + tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth49: sfp-eth49 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp6>; + tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth50: sfp-eth50 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp7>; + tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth51: sfp-eth51 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp8>; + tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth52: sfp-eth52 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp9>; + tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth53: sfp-eth53 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp10>; + tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth54: sfp-eth54 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp11>; + tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth55: sfp-eth55 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp12>; + tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth56: sfp-eth56 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp13>; + tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth57: sfp-eth57 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp14>; + tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth58: sfp-eth58 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp15>; + tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth59: sfp-eth59 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp16>; + tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth60: sfp-eth60 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp17>; + tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth61: sfp-eth61 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp18>; + tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth62: sfp-eth62 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp19>; + tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; + }; + sfp_eth63: sfp-eth63 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp20>; + tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; + }; +}; + +&switch { + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* 10G SFPs */ + port12: port@12 { + reg = <12>; + microchip,bandwidth = <10000>; + phys = <&serdes 13>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth12>; + microchip,sd-sgpio = <301>; + managed = "in-band-status"; + }; + port13: port@13 { + reg = <13>; + /* Example: CU SFP, 1G speed */ + microchip,bandwidth = <10000>; + phys = <&serdes 14>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth13>; + microchip,sd-sgpio = <305>; + managed = "in-band-status"; + }; + port14: port@14 { + reg = <14>; + microchip,bandwidth = <10000>; + phys = <&serdes 15>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth14>; + microchip,sd-sgpio = <309>; + managed = "in-band-status"; + }; + port15: port@15 { + reg = <15>; + microchip,bandwidth = <10000>; + phys = <&serdes 16>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth15>; + microchip,sd-sgpio = <313>; + managed = "in-band-status"; + }; + port48: port@48 { + reg = <48>; + microchip,bandwidth = <10000>; + phys = <&serdes 17>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth48>; + microchip,sd-sgpio = <317>; + managed = "in-band-status"; + }; + port49: port@49 { + reg = <49>; + microchip,bandwidth = <10000>; + phys = <&serdes 18>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth49>; + microchip,sd-sgpio = <321>; + managed = "in-band-status"; + }; + port50: port@50 { + reg = <50>; + microchip,bandwidth = <10000>; + phys = <&serdes 19>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth50>; + microchip,sd-sgpio = <325>; + managed = "in-band-status"; + }; + port51: port@51 { + reg = <51>; + microchip,bandwidth = <10000>; + phys = <&serdes 20>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth51>; + microchip,sd-sgpio = <329>; + managed = "in-band-status"; + }; + port52: port@52 { + reg = <52>; + microchip,bandwidth = <10000>; + phys = <&serdes 21>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth52>; + microchip,sd-sgpio = <333>; + managed = "in-band-status"; + }; + port53: port@53 { + reg = <53>; + microchip,bandwidth = <10000>; + phys = <&serdes 22>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth53>; + microchip,sd-sgpio = <337>; + managed = "in-band-status"; + }; + port54: port@54 { + reg = <54>; + microchip,bandwidth = <10000>; + phys = <&serdes 23>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth54>; + microchip,sd-sgpio = <341>; + managed = "in-band-status"; + }; + port55: port@55 { + reg = <55>; + microchip,bandwidth = <10000>; + phys = <&serdes 24>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth55>; + microchip,sd-sgpio = <345>; + managed = "in-band-status"; + }; + /* 25G SFPs */ + port56: port@56 { + reg = <56>; + microchip,bandwidth = <10000>; + phys = <&serdes 25>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth56>; + microchip,sd-sgpio = <349>; + managed = "in-band-status"; + }; + port57: port@57 { + reg = <57>; + microchip,bandwidth = <10000>; + phys = <&serdes 26>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth57>; + microchip,sd-sgpio = <353>; + managed = "in-band-status"; + }; + port58: port@58 { + reg = <58>; + microchip,bandwidth = <10000>; + phys = <&serdes 27>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth58>; + microchip,sd-sgpio = <357>; + managed = "in-band-status"; + }; + port59: port@59 { + reg = <59>; + microchip,bandwidth = <10000>; + phys = <&serdes 28>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth59>; + microchip,sd-sgpio = <361>; + managed = "in-band-status"; + }; + port60: port@60 { + reg = <60>; + microchip,bandwidth = <10000>; + phys = <&serdes 29>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth60>; + microchip,sd-sgpio = <365>; + managed = "in-band-status"; + }; + port61: port@61 { + reg = <61>; + microchip,bandwidth = <10000>; + phys = <&serdes 30>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth61>; + microchip,sd-sgpio = <369>; + managed = "in-band-status"; + }; + port62: port@62 { + reg = <62>; + microchip,bandwidth = <10000>; + phys = <&serdes 31>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth62>; + microchip,sd-sgpio = <373>; + managed = "in-band-status"; + }; + port63: port@63 { + reg = <63>; + microchip,bandwidth = <10000>; + phys = <&serdes 32>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth63>; + microchip,sd-sgpio = <377>; + managed = "in-band-status"; + }; + /* Finally the Management interface */ + port64: port@64 { + reg = <64>; + microchip,bandwidth = <1000>; + phys = <&serdes 0>; + phy-handle = <&phy64>; + phy-mode = "sgmii"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index e28c6dd16377..ef96e6d8c6b3 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -7,14 +7,6 @@ #include "sparx5_pcb_common.dtsi" /{ - aliases { - i2c0 = &i2c0; - i2c152 = &i2c152; - i2c153 = &i2c153; - i2c154 = &i2c154; - i2c155 = &i2c155; - }; - gpio-restart { compatible = "gpio-restart"; gpios = <&gpio 37 GPIO_ACTIVE_LOW>; @@ -97,17 +89,10 @@ &spi0 { status = "okay"; - spi@0 { - compatible = "spi-mux"; - mux-controls = <&mux>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; /* CS0 */ - spi-flash@9 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <8000000>; - reg = <0x9>; /* SPI */ - }; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0>; }; }; @@ -138,6 +123,11 @@ }; }; +&sgpio2 { + status = "okay"; + microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; +}; + &axi { i2c0_imux: i2c0-imux@0 { compatible = "i2c-mux-pinctrl"; @@ -149,31 +139,614 @@ &i2c0_imux { pinctrl-names = - "i2c152", "i2c153", "i2c154", "i2c155", + "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4", "idle"; pinctrl-0 = <&i2cmux_s29>; pinctrl-1 = <&i2cmux_s30>; pinctrl-2 = <&i2cmux_s31>; pinctrl-3 = <&i2cmux_s32>; pinctrl-4 = <&i2cmux_pins_i>; - i2c152: i2c_sfp1 { + i2c_sfp1: i2c_sfp1 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; }; - i2c153: i2c_sfp2 { + i2c_sfp2: i2c_sfp2 { reg = <0x1>; #address-cells = <1>; #size-cells = <0>; }; - i2c154: i2c_sfp3 { + i2c_sfp3: i2c_sfp3 { reg = <0x2>; #address-cells = <1>; #size-cells = <0>; }; - i2c155: i2c_sfp4 { + i2c_sfp4: i2c_sfp4 { reg = <0x3>; #address-cells = <1>; #size-cells = <0>; }; }; + +&axi { + sfp_eth60: sfp-eth60 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>; + }; + sfp_eth61: sfp-eth61 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>; + }; + sfp_eth62: sfp-eth62 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp3>; + tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>; + }; + sfp_eth63: sfp-eth63 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp4>; + tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&mdio0 { + status = "ok"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + }; + phy6: ethernet-phy@6 { + reg = <6>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + }; + phy10: ethernet-phy@10 { + reg = <10>; + }; + phy11: ethernet-phy@11 { + reg = <11>; + }; + phy12: ethernet-phy@12 { + reg = <12>; + }; + phy13: ethernet-phy@13 { + reg = <13>; + }; + phy14: ethernet-phy@14 { + reg = <14>; + }; + phy15: ethernet-phy@15 { + reg = <15>; + }; + phy16: ethernet-phy@16 { + reg = <16>; + }; + phy17: ethernet-phy@17 { + reg = <17>; + }; + phy18: ethernet-phy@18 { + reg = <18>; + }; + phy19: ethernet-phy@19 { + reg = <19>; + }; + phy20: ethernet-phy@20 { + reg = <20>; + }; + phy21: ethernet-phy@21 { + reg = <21>; + }; + phy22: ethernet-phy@22 { + reg = <22>; + }; + phy23: ethernet-phy@23 { + reg = <23>; + }; +}; + +&mdio1 { + status = "ok"; + phy24: ethernet-phy@24 { + reg = <0>; + }; + phy25: ethernet-phy@25 { + reg = <1>; + }; + phy26: ethernet-phy@26 { + reg = <2>; + }; + phy27: ethernet-phy@27 { + reg = <3>; + }; + phy28: ethernet-phy@28 { + reg = <4>; + }; + phy29: ethernet-phy@29 { + reg = <5>; + }; + phy30: ethernet-phy@30 { + reg = <6>; + }; + phy31: ethernet-phy@31 { + reg = <7>; + }; + phy32: ethernet-phy@32 { + reg = <8>; + }; + phy33: ethernet-phy@33 { + reg = <9>; + }; + phy34: ethernet-phy@34 { + reg = <10>; + }; + phy35: ethernet-phy@35 { + reg = <11>; + }; + phy36: ethernet-phy@36 { + reg = <12>; + }; + phy37: ethernet-phy@37 { + reg = <13>; + }; + phy38: ethernet-phy@38 { + reg = <14>; + }; + phy39: ethernet-phy@39 { + reg = <15>; + }; + phy40: ethernet-phy@40 { + reg = <16>; + }; + phy41: ethernet-phy@41 { + reg = <17>; + }; + phy42: ethernet-phy@42 { + reg = <18>; + }; + phy43: ethernet-phy@43 { + reg = <19>; + }; + phy44: ethernet-phy@44 { + reg = <20>; + }; + phy45: ethernet-phy@45 { + reg = <21>; + }; + phy46: ethernet-phy@46 { + reg = <22>; + }; + phy47: ethernet-phy@47 { + reg = <23>; + }; +}; + +&mdio3 { + status = "ok"; + phy64: ethernet-phy@64 { + reg = <28>; + }; +}; + +&switch { + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port0: port@0 { + reg = <0>; + microchip,bandwidth = <1000>; + phys = <&serdes 13>; + phy-handle = <&phy0>; + phy-mode = "qsgmii"; + }; + port1: port@1 { + reg = <1>; + microchip,bandwidth = <1000>; + phys = <&serdes 13>; + phy-handle = <&phy1>; + phy-mode = "qsgmii"; + }; + port2: port@2 { + reg = <2>; + microchip,bandwidth = <1000>; + phys = <&serdes 13>; + phy-handle = <&phy2>; + phy-mode = "qsgmii"; + }; + port3: port@3 { + reg = <3>; + microchip,bandwidth = <1000>; + phys = <&serdes 13>; + phy-handle = <&phy3>; + phy-mode = "qsgmii"; + }; + port4: port@4 { + reg = <4>; + microchip,bandwidth = <1000>; + phys = <&serdes 14>; + phy-handle = <&phy4>; + phy-mode = "qsgmii"; + }; + port5: port@5 { + reg = <5>; + microchip,bandwidth = <1000>; + phys = <&serdes 14>; + phy-handle = <&phy5>; + phy-mode = "qsgmii"; + }; + port6: port@6 { + reg = <6>; + microchip,bandwidth = <1000>; + phys = <&serdes 14>; + phy-handle = <&phy6>; + phy-mode = "qsgmii"; + }; + port7: port@7 { + reg = <7>; + microchip,bandwidth = <1000>; + phys = <&serdes 14>; + phy-handle = <&phy7>; + phy-mode = "qsgmii"; + }; + port8: port@8 { + reg = <8>; + microchip,bandwidth = <1000>; + phys = <&serdes 15>; + phy-handle = <&phy8>; + phy-mode = "qsgmii"; + }; + port9: port@9 { + reg = <9>; + microchip,bandwidth = <1000>; + phys = <&serdes 15>; + phy-handle = <&phy9>; + phy-mode = "qsgmii"; + }; + port10: port@10 { + reg = <10>; + microchip,bandwidth = <1000>; + phys = <&serdes 15>; + phy-handle = <&phy10>; + phy-mode = "qsgmii"; + }; + port11: port@11 { + reg = <11>; + microchip,bandwidth = <1000>; + phys = <&serdes 15>; + phy-handle = <&phy11>; + phy-mode = "qsgmii"; + }; + port12: port@12 { + reg = <12>; + microchip,bandwidth = <1000>; + phys = <&serdes 16>; + phy-handle = <&phy12>; + phy-mode = "qsgmii"; + }; + port13: port@13 { + reg = <13>; + microchip,bandwidth = <1000>; + phys = <&serdes 16>; + phy-handle = <&phy13>; + phy-mode = "qsgmii"; + }; + port14: port@14 { + reg = <14>; + microchip,bandwidth = <1000>; + phys = <&serdes 16>; + phy-handle = <&phy14>; + phy-mode = "qsgmii"; + }; + port15: port@15 { + reg = <15>; + microchip,bandwidth = <1000>; + phys = <&serdes 16>; + phy-handle = <&phy15>; + phy-mode = "qsgmii"; + }; + port16: port@16 { + reg = <16>; + microchip,bandwidth = <1000>; + phys = <&serdes 17>; + phy-handle = <&phy16>; + phy-mode = "qsgmii"; + }; + port17: port@17 { + reg = <17>; + microchip,bandwidth = <1000>; + phys = <&serdes 17>; + phy-handle = <&phy17>; + phy-mode = "qsgmii"; + }; + port18: port@18 { + reg = <18>; + microchip,bandwidth = <1000>; + phys = <&serdes 17>; + phy-handle = <&phy18>; + phy-mode = "qsgmii"; + }; + port19: port@19 { + reg = <19>; + microchip,bandwidth = <1000>; + phys = <&serdes 17>; + phy-handle = <&phy19>; + phy-mode = "qsgmii"; + }; + port20: port@20 { + reg = <20>; + microchip,bandwidth = <1000>; + phys = <&serdes 18>; + phy-handle = <&phy20>; + phy-mode = "qsgmii"; + }; + port21: port@21 { + reg = <21>; + microchip,bandwidth = <1000>; + phys = <&serdes 18>; + phy-handle = <&phy21>; + phy-mode = "qsgmii"; + }; + port22: port@22 { + reg = <22>; + microchip,bandwidth = <1000>; + phys = <&serdes 18>; + phy-handle = <&phy22>; + phy-mode = "qsgmii"; + }; + port23: port@23 { + reg = <23>; + microchip,bandwidth = <1000>; + phys = <&serdes 18>; + phy-handle = <&phy23>; + phy-mode = "qsgmii"; + }; + port24: port@24 { + reg = <24>; + microchip,bandwidth = <1000>; + phys = <&serdes 19>; + phy-handle = <&phy24>; + phy-mode = "qsgmii"; + }; + port25: port@25 { + reg = <25>; + microchip,bandwidth = <1000>; + phys = <&serdes 19>; + phy-handle = <&phy25>; + phy-mode = "qsgmii"; + }; + port26: port@26 { + reg = <26>; + microchip,bandwidth = <1000>; + phys = <&serdes 19>; + phy-handle = <&phy26>; + phy-mode = "qsgmii"; + }; + port27: port@27 { + reg = <27>; + microchip,bandwidth = <1000>; + phys = <&serdes 19>; + phy-handle = <&phy27>; + phy-mode = "qsgmii"; + }; + port28: port@28 { + reg = <28>; + microchip,bandwidth = <1000>; + phys = <&serdes 20>; + phy-handle = <&phy28>; + phy-mode = "qsgmii"; + }; + port29: port@29 { + reg = <29>; + microchip,bandwidth = <1000>; + phys = <&serdes 20>; + phy-handle = <&phy29>; + phy-mode = "qsgmii"; + }; + port30: port@30 { + reg = <30>; + microchip,bandwidth = <1000>; + phys = <&serdes 20>; + phy-handle = <&phy30>; + phy-mode = "qsgmii"; + }; + port31: port@31 { + reg = <31>; + microchip,bandwidth = <1000>; + phys = <&serdes 20>; + phy-handle = <&phy31>; + phy-mode = "qsgmii"; + }; + port32: port@32 { + reg = <32>; + microchip,bandwidth = <1000>; + phys = <&serdes 21>; + phy-handle = <&phy32>; + phy-mode = "qsgmii"; + }; + port33: port@33 { + reg = <33>; + microchip,bandwidth = <1000>; + phys = <&serdes 21>; + phy-handle = <&phy33>; + phy-mode = "qsgmii"; + }; + port34: port@34 { + reg = <34>; + microchip,bandwidth = <1000>; + phys = <&serdes 21>; + phy-handle = <&phy34>; + phy-mode = "qsgmii"; + }; + port35: port@35 { + reg = <35>; + microchip,bandwidth = <1000>; + phys = <&serdes 21>; + phy-handle = <&phy35>; + phy-mode = "qsgmii"; + }; + port36: port@36 { + reg = <36>; + microchip,bandwidth = <1000>; + phys = <&serdes 22>; + phy-handle = <&phy36>; + phy-mode = "qsgmii"; + }; + port37: port@37 { + reg = <37>; + microchip,bandwidth = <1000>; + phys = <&serdes 22>; + phy-handle = <&phy37>; + phy-mode = "qsgmii"; + }; + port38: port@38 { + reg = <38>; + microchip,bandwidth = <1000>; + phys = <&serdes 22>; + phy-handle = <&phy38>; + phy-mode = "qsgmii"; + }; + port39: port@39 { + reg = <39>; + microchip,bandwidth = <1000>; + phys = <&serdes 22>; + phy-handle = <&phy39>; + phy-mode = "qsgmii"; + }; + port40: port@40 { + reg = <40>; + microchip,bandwidth = <1000>; + phys = <&serdes 23>; + phy-handle = <&phy40>; + phy-mode = "qsgmii"; + }; + port41: port@41 { + reg = <41>; + microchip,bandwidth = <1000>; + phys = <&serdes 23>; + phy-handle = <&phy41>; + phy-mode = "qsgmii"; + }; + port42: port@42 { + reg = <42>; + microchip,bandwidth = <1000>; + phys = <&serdes 23>; + phy-handle = <&phy42>; + phy-mode = "qsgmii"; + }; + port43: port@43 { + reg = <43>; + microchip,bandwidth = <1000>; + phys = <&serdes 23>; + phy-handle = <&phy43>; + phy-mode = "qsgmii"; + }; + port44: port@44 { + reg = <44>; + microchip,bandwidth = <1000>; + phys = <&serdes 24>; + phy-handle = <&phy44>; + phy-mode = "qsgmii"; + }; + port45: port@45 { + reg = <45>; + microchip,bandwidth = <1000>; + phys = <&serdes 24>; + phy-handle = <&phy45>; + phy-mode = "qsgmii"; + }; + port46: port@46 { + reg = <46>; + microchip,bandwidth = <1000>; + phys = <&serdes 24>; + phy-handle = <&phy46>; + phy-mode = "qsgmii"; + }; + port47: port@47 { + reg = <47>; + microchip,bandwidth = <1000>; + phys = <&serdes 24>; + phy-handle = <&phy47>; + phy-mode = "qsgmii"; + }; + /* Then the 25G interfaces */ + port60: port@60 { + reg = <60>; + microchip,bandwidth = <25000>; + phys = <&serdes 29>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth60>; + managed = "in-band-status"; + }; + port61: port@61 { + reg = <61>; + microchip,bandwidth = <25000>; + phys = <&serdes 30>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth61>; + managed = "in-band-status"; + }; + port62: port@62 { + reg = <62>; + microchip,bandwidth = <25000>; + phys = <&serdes 31>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth62>; + managed = "in-band-status"; + }; + port63: port@63 { + reg = <63>; + microchip,bandwidth = <25000>; + phys = <&serdes 32>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth63>; + managed = "in-band-status"; + }; + /* Finally the Management interface */ + port64: port@64 { + reg = <64>; + microchip,bandwidth = <1000>; + phys = <&serdes 0>; + phy-handle = <&phy64>; + phy-mode = "sgmii"; + }; + }; +}; -- cgit From 328aac5ecd119ede3633f7d17969b1ff34ccc784 Mon Sep 17 00:00:00 2001 From: Ravi Bangoria Date: Tue, 22 Jun 2021 16:30:26 +0530 Subject: bpf, x86: Fix extable offset calculation Commit 4c5de127598e1 ("bpf: Emit explicit NULL pointer checks for PROBE_LDX instructions.") is emitting a couple of instructions before the actual load. Consider those additional instructions while calculating extable offset. Fixes: 4c5de127598e1 ("bpf: Emit explicit NULL pointer checks for PROBE_LDX instructions.") Signed-off-by: Ravi Bangoria Signed-off-by: Alexei Starovoitov Signed-off-by: Daniel Borkmann Link: https://lore.kernel.org/bpf/20210622110026.1157847-1-ravi.bangoria@linux.ibm.com --- arch/x86/net/bpf_jit_comp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index db1e83813db5..e835164189f1 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -1281,7 +1281,7 @@ st: if (is_imm8(insn->off)) emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); if (BPF_MODE(insn->code) == BPF_PROBE_MEM) { struct exception_table_entry *ex; - u8 *_insn = image + proglen; + u8 *_insn = image + proglen + (start_of_ldx - temp); s64 delta; /* populate jmp_offset for JMP above */ -- cgit