From 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sat, 16 Apr 2005 15:20:36 -0700 Subject: Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip! --- drivers/char/ChangeLog | 775 ++ drivers/char/Kconfig | 988 ++ drivers/char/Makefile | 118 + drivers/char/agp/Kconfig | 171 + drivers/char/agp/Makefile | 18 + drivers/char/agp/agp.h | 331 + drivers/char/agp/ali-agp.c | 414 + drivers/char/agp/alpha-agp.c | 216 + drivers/char/agp/amd-k7-agp.c | 542 + drivers/char/agp/amd64-agp.c | 761 ++ drivers/char/agp/ati-agp.c | 548 + drivers/char/agp/backend.c | 348 + drivers/char/agp/efficeon-agp.c | 463 + drivers/char/agp/frontend.c | 1103 ++ drivers/char/agp/generic.c | 1222 +++ drivers/char/agp/hp-agp.c | 552 + drivers/char/agp/i460-agp.c | 642 ++ drivers/char/agp/intel-agp.c | 1833 ++++ drivers/char/agp/isoch.c | 470 + drivers/char/agp/nvidia-agp.c | 424 + drivers/char/agp/sgi-agp.c | 331 + drivers/char/agp/sis-agp.c | 360 + drivers/char/agp/sworks-agp.c | 556 ++ drivers/char/agp/uninorth-agp.c | 647 ++ drivers/char/agp/via-agp.c | 548 + drivers/char/amiserial.c | 2179 ++++ drivers/char/applicom.c | 862 ++ drivers/char/applicom.h | 85 + drivers/char/cd1865.h | 263 + drivers/char/consolemap.c | 672 ++ drivers/char/cp437.uni | 291 + drivers/char/cyclades.c | 5540 ++++++++++ drivers/char/decserial.c | 100 + drivers/char/defkeymap.c_shipped | 262 + drivers/char/defkeymap.map | 357 + drivers/char/digi.h | 71 + drivers/char/digi1.h | 100 + drivers/char/digiFep1.h | 136 + drivers/char/digiPCI.h | 42 + drivers/char/drm/Kconfig | 98 + drivers/char/drm/Makefile | 33 + drivers/char/drm/README.drm | 46 + drivers/char/drm/ati_pcigart.c | 208 + drivers/char/drm/drm.h | 675 ++ drivers/char/drm/drmP.h | 1073 ++ drivers/char/drm/drm_agpsupport.c | 448 + drivers/char/drm/drm_auth.c | 230 + drivers/char/drm/drm_bufs.c | 1270 +++ drivers/char/drm/drm_context.c | 578 ++ drivers/char/drm/drm_core.h | 34 + drivers/char/drm/drm_dma.c | 180 + drivers/char/drm/drm_drawable.c | 56 + drivers/char/drm/drm_drv.c | 531 + drivers/char/drm/drm_fops.c | 451 + drivers/char/drm/drm_init.c | 52 + drivers/char/drm/drm_ioctl.c | 370 + drivers/char/drm/drm_irq.c | 370 + drivers/char/drm/drm_lock.c | 303 + drivers/char/drm/drm_memory.c | 181 + drivers/char/drm/drm_memory.h | 197 + drivers/char/drm/drm_memory_debug.h | 459 + drivers/char/drm/drm_os_linux.h | 149 + drivers/char/drm/drm_pci.c | 140 + drivers/char/drm/drm_pciids.h | 224 + drivers/char/drm/drm_proc.c | 539 + drivers/char/drm/drm_sarea.h | 78 + drivers/char/drm/drm_scatter.c | 231 + drivers/char/drm/drm_stub.c | 319 + drivers/char/drm/drm_sysfs.c | 208 + drivers/char/drm/drm_vm.c | 678 ++ drivers/char/drm/ffb_context.c | 551 + drivers/char/drm/ffb_drv.c | 365 + drivers/char/drm/ffb_drv.h | 286 + drivers/char/drm/gamma_context.h | 492 + drivers/char/drm/gamma_dma.c | 946 ++ drivers/char/drm/gamma_drm.h | 90 + drivers/char/drm/gamma_drv.c | 59 + drivers/char/drm/gamma_drv.h | 147 + drivers/char/drm/gamma_lists.h | 215 + drivers/char/drm/gamma_lock.h | 140 + drivers/char/drm/gamma_old_dma.h | 313 + drivers/char/drm/i810_dma.c | 1385 +++ drivers/char/drm/i810_drm.h | 289 + drivers/char/drm/i810_drv.c | 126 + drivers/char/drm/i810_drv.h | 236 + drivers/char/drm/i830_dma.c | 1588 +++ drivers/char/drm/i830_drm.h | 350 + drivers/char/drm/i830_drv.c | 137 + drivers/char/drm/i830_drv.h | 301 + drivers/char/drm/i830_irq.c | 204 + drivers/char/drm/i915_dma.c | 725 ++ drivers/char/drm/i915_drm.h | 167 + drivers/char/drm/i915_drv.c | 104 + drivers/char/drm/i915_drv.h | 243 + drivers/char/drm/i915_irq.c | 161 + drivers/char/drm/i915_mem.c | 346 + drivers/char/drm/mga_dma.c | 754 ++ drivers/char/drm/mga_drm.h | 349 + drivers/char/drm/mga_drv.c | 127 + drivers/char/drm/mga_drv.h | 638 ++ drivers/char/drm/mga_irq.c | 102 + drivers/char/drm/mga_state.c | 1123 +++ drivers/char/drm/mga_ucode.h | 11645 ++++++++++++++++++++++ drivers/char/drm/mga_warp.c | 210 + drivers/char/drm/r128_cce.c | 943 ++ drivers/char/drm/r128_drm.h | 345 + drivers/char/drm/r128_drv.c | 122 + drivers/char/drm/r128_drv.h | 521 + drivers/char/drm/r128_irq.c | 102 + drivers/char/drm/r128_state.c | 1732 ++++ drivers/char/drm/radeon_cp.c | 2061 ++++ drivers/char/drm/radeon_drm.h | 659 ++ drivers/char/drm/radeon_drv.c | 127 + drivers/char/drm/radeon_drv.h | 1044 ++ drivers/char/drm/radeon_irq.c | 251 + drivers/char/drm/radeon_mem.c | 322 + drivers/char/drm/radeon_state.c | 3102 ++++++ drivers/char/drm/sis_drm.h | 42 + drivers/char/drm/sis_drv.c | 110 + drivers/char/drm/sis_drv.h | 52 + drivers/char/drm/sis_ds.c | 301 + drivers/char/drm/sis_ds.h | 145 + drivers/char/drm/sis_mm.c | 417 + drivers/char/drm/tdfx_drv.c | 107 + drivers/char/drm/tdfx_drv.h | 50 + drivers/char/ds1286.c | 578 ++ drivers/char/ds1302.c | 354 + drivers/char/ds1620.c | 416 + drivers/char/dsp56k.c | 547 + drivers/char/dtlk.c | 659 ++ drivers/char/ec3104_keyb.c | 459 + drivers/char/efirtc.c | 417 + drivers/char/epca.c | 3789 +++++++ drivers/char/epca.h | 165 + drivers/char/epcaconfig.h | 7 + drivers/char/esp.c | 2630 +++++ drivers/char/ftape/Kconfig | 340 + drivers/char/ftape/Makefile | 28 + drivers/char/ftape/README.PCI | 81 + drivers/char/ftape/RELEASE-NOTES | 966 ++ drivers/char/ftape/compressor/Makefile | 31 + drivers/char/ftape/compressor/lzrw3.c | 743 ++ drivers/char/ftape/compressor/lzrw3.h | 253 + drivers/char/ftape/compressor/zftape-compress.c | 1203 +++ drivers/char/ftape/compressor/zftape-compress.h | 83 + drivers/char/ftape/lowlevel/Makefile | 43 + drivers/char/ftape/lowlevel/fc-10.c | 175 + drivers/char/ftape/lowlevel/fc-10.h | 39 + drivers/char/ftape/lowlevel/fdc-io.c | 1352 +++ drivers/char/ftape/lowlevel/fdc-io.h | 252 + drivers/char/ftape/lowlevel/fdc-isr.c | 1170 +++ drivers/char/ftape/lowlevel/fdc-isr.h | 55 + drivers/char/ftape/lowlevel/ftape-bsm.c | 491 + drivers/char/ftape/lowlevel/ftape-bsm.h | 66 + drivers/char/ftape/lowlevel/ftape-buffer.c | 129 + drivers/char/ftape/lowlevel/ftape-buffer.h | 32 + drivers/char/ftape/lowlevel/ftape-calibr.c | 276 + drivers/char/ftape/lowlevel/ftape-calibr.h | 37 + drivers/char/ftape/lowlevel/ftape-ctl.c | 897 ++ drivers/char/ftape/lowlevel/ftape-ctl.h | 162 + drivers/char/ftape/lowlevel/ftape-ecc.c | 853 ++ drivers/char/ftape/lowlevel/ftape-ecc.h | 84 + drivers/char/ftape/lowlevel/ftape-format.c | 344 + drivers/char/ftape/lowlevel/ftape-format.h | 37 + drivers/char/ftape/lowlevel/ftape-init.c | 161 + drivers/char/ftape/lowlevel/ftape-init.h | 43 + drivers/char/ftape/lowlevel/ftape-io.c | 992 ++ drivers/char/ftape/lowlevel/ftape-io.h | 90 + drivers/char/ftape/lowlevel/ftape-proc.c | 215 + drivers/char/ftape/lowlevel/ftape-proc.h | 35 + drivers/char/ftape/lowlevel/ftape-read.c | 621 ++ drivers/char/ftape/lowlevel/ftape-read.h | 51 + drivers/char/ftape/lowlevel/ftape-rw.c | 1092 ++ drivers/char/ftape/lowlevel/ftape-rw.h | 111 + drivers/char/ftape/lowlevel/ftape-setup.c | 105 + drivers/char/ftape/lowlevel/ftape-tracing.c | 118 + drivers/char/ftape/lowlevel/ftape-tracing.h | 180 + drivers/char/ftape/lowlevel/ftape-write.c | 336 + drivers/char/ftape/lowlevel/ftape-write.h | 53 + drivers/char/ftape/lowlevel/ftape_syms.c | 88 + drivers/char/ftape/zftape/Makefile | 36 + drivers/char/ftape/zftape/zftape-buffers.c | 149 + drivers/char/ftape/zftape/zftape-buffers.h | 55 + drivers/char/ftape/zftape/zftape-ctl.c | 1418 +++ drivers/char/ftape/zftape/zftape-ctl.h | 59 + drivers/char/ftape/zftape/zftape-eof.c | 199 + drivers/char/ftape/zftape/zftape-eof.h | 52 + drivers/char/ftape/zftape/zftape-init.c | 403 + drivers/char/ftape/zftape/zftape-init.h | 77 + drivers/char/ftape/zftape/zftape-read.c | 377 + drivers/char/ftape/zftape/zftape-read.h | 53 + drivers/char/ftape/zftape/zftape-rw.c | 376 + drivers/char/ftape/zftape/zftape-rw.h | 102 + drivers/char/ftape/zftape/zftape-vtbl.c | 757 ++ drivers/char/ftape/zftape/zftape-vtbl.h | 227 + drivers/char/ftape/zftape/zftape-write.c | 483 + drivers/char/ftape/zftape/zftape-write.h | 38 + drivers/char/ftape/zftape/zftape_syms.c | 43 + drivers/char/generic_nvram.c | 145 + drivers/char/generic_serial.c | 1001 ++ drivers/char/genrtc.c | 535 + drivers/char/hangcheck-timer.c | 129 + drivers/char/hpet.c | 994 ++ drivers/char/hvc_console.c | 831 ++ drivers/char/hvcs.c | 1649 +++ drivers/char/hvsi.c | 1320 +++ drivers/char/hw_random.c | 630 ++ drivers/char/i8k.c | 788 ++ drivers/char/ip2.c | 110 + drivers/char/ip2/fip_firm.h | 2149 ++++ drivers/char/ip2/i2cmd.c | 209 + drivers/char/ip2/i2cmd.h | 643 ++ drivers/char/ip2/i2ellis.c | 1487 +++ drivers/char/ip2/i2ellis.h | 615 ++ drivers/char/ip2/i2hw.h | 648 ++ drivers/char/ip2/i2lib.c | 2219 +++++ drivers/char/ip2/i2lib.h | 351 + drivers/char/ip2/i2os.h | 127 + drivers/char/ip2/i2pack.h | 364 + drivers/char/ip2/ip2.h | 107 + drivers/char/ip2/ip2ioctl.h | 35 + drivers/char/ip2/ip2trace.h | 42 + drivers/char/ip2/ip2types.h | 57 + drivers/char/ip27-rtc.c | 327 + drivers/char/ip2main.c | 3265 ++++++ drivers/char/ipmi/Kconfig | 67 + drivers/char/ipmi/Makefile | 15 + drivers/char/ipmi/ipmi_bt_sm.c | 513 + drivers/char/ipmi/ipmi_devintf.c | 582 ++ drivers/char/ipmi/ipmi_kcs_sm.c | 500 + drivers/char/ipmi/ipmi_msghandler.c | 3174 ++++++ drivers/char/ipmi/ipmi_poweroff.c | 549 + drivers/char/ipmi/ipmi_si_intf.c | 2359 +++++ drivers/char/ipmi/ipmi_si_sm.h | 120 + drivers/char/ipmi/ipmi_smic_sm.c | 599 ++ drivers/char/ipmi/ipmi_watchdog.c | 1068 ++ drivers/char/isicom.c | 2079 ++++ drivers/char/istallion.c | 5276 ++++++++++ drivers/char/ite_gpio.c | 419 + drivers/char/keyboard.c | 1254 +++ drivers/char/lcd.c | 683 ++ drivers/char/lcd.h | 186 + drivers/char/lp.c | 995 ++ drivers/char/mem.c | 880 ++ drivers/char/misc.c | 331 + drivers/char/mmtimer.c | 725 ++ drivers/char/moxa.c | 3243 ++++++ drivers/char/mwave/3780i.c | 727 ++ drivers/char/mwave/3780i.h | 362 + drivers/char/mwave/Makefile | 15 + drivers/char/mwave/README | 50 + drivers/char/mwave/mwavedd.c | 674 ++ drivers/char/mwave/mwavedd.h | 150 + drivers/char/mwave/mwavepub.h | 89 + drivers/char/mwave/smapi.c | 570 ++ drivers/char/mwave/smapi.h | 80 + drivers/char/mwave/tp3780i.c | 592 ++ drivers/char/mwave/tp3780i.h | 103 + drivers/char/mxser.c | 3170 ++++++ drivers/char/mxser.h | 450 + drivers/char/n_hdlc.c | 978 ++ drivers/char/n_r3964.c | 1416 +++ drivers/char/n_tty.c | 1562 +++ drivers/char/nvram.c | 926 ++ drivers/char/nwbutton.c | 248 + drivers/char/nwbutton.h | 40 + drivers/char/nwflash.c | 702 ++ drivers/char/pcmcia/Kconfig | 22 + drivers/char/pcmcia/Makefile | 7 + drivers/char/pcmcia/synclink_cs.c | 4611 +++++++++ drivers/char/ppdev.c | 824 ++ drivers/char/pty.c | 412 + drivers/char/qtronix.c | 601 ++ drivers/char/qtronixmap.c_shipped | 265 + drivers/char/qtronixmap.map | 287 + drivers/char/random.c | 1629 +++ drivers/char/raw.c | 342 + drivers/char/rio/Makefile | 12 + drivers/char/rio/board.h | 143 + drivers/char/rio/bootpkt.h | 62 + drivers/char/rio/brates.h | 107 + drivers/char/rio/chan.h | 33 + drivers/char/rio/cirrus.h | 463 + drivers/char/rio/cmd.h | 84 + drivers/char/rio/cmdblk.h | 60 + drivers/char/rio/cmdpkt.h | 206 + drivers/char/rio/control.h | 62 + drivers/char/rio/daemon.h | 334 + drivers/char/rio/data.h | 40 + drivers/char/rio/debug.h | 39 + drivers/char/rio/defaults.h | 59 + drivers/char/rio/eisa.h | 104 + drivers/char/rio/enable.h | 50 + drivers/char/rio/error.h | 85 + drivers/char/rio/errors.h | 104 + drivers/char/rio/formpkt.h | 154 + drivers/char/rio/func.h | 154 + drivers/char/rio/host.h | 134 + drivers/char/rio/hosthw.h | 57 + drivers/char/rio/link.h | 188 + drivers/char/rio/linux_compat.h | 122 + drivers/char/rio/list.h | 196 + drivers/char/rio/lrt.h | 55 + drivers/char/rio/ltt.h | 55 + drivers/char/rio/lttwake.h | 53 + drivers/char/rio/map.h | 103 + drivers/char/rio/mca.h | 73 + drivers/char/rio/mesg.h | 41 + drivers/char/rio/param.h | 61 + drivers/char/rio/parmmap.h | 96 + drivers/char/rio/pci.h | 76 + drivers/char/rio/phb.h | 293 + drivers/char/rio/pkt.h | 120 + drivers/char/rio/poll.h | 76 + drivers/char/rio/port.h | 245 + drivers/char/rio/proto.h | 244 + drivers/char/rio/protsts.h | 119 + drivers/char/rio/qbuf.h | 67 + drivers/char/rio/rio.h | 294 + drivers/char/rio/rio_linux.c | 1380 +++ drivers/char/rio/rio_linux.h | 187 + drivers/char/rio/rioboard.h | 281 + drivers/char/rio/rioboot.c | 1360 +++ drivers/char/rio/riocmd.c | 1041 ++ drivers/char/rio/rioctrl.c | 1869 ++++ drivers/char/rio/riodrvr.h | 144 + drivers/char/rio/rioinfo.h | 96 + drivers/char/rio/rioinit.c | 1617 +++ drivers/char/rio/riointr.c | 951 ++ drivers/char/rio/rioioctl.h | 103 + drivers/char/rio/riolocks.h | 43 + drivers/char/rio/rioparam.c | 744 ++ drivers/char/rio/riopcicopy.c | 8 + drivers/char/rio/rioroute.c | 1238 +++ drivers/char/rio/riospace.h | 161 + drivers/char/rio/riotable.c | 1044 ++ drivers/char/rio/riotime.h | 63 + drivers/char/rio/riotty.c | 1376 +++ drivers/char/rio/riotypes.h | 135 + drivers/char/rio/riowinif.h | 1335 +++ drivers/char/rio/riscos.h | 63 + drivers/char/rio/rom.h | 64 + drivers/char/rio/route.h | 108 + drivers/char/rio/rtahw.h | 75 + drivers/char/rio/rup.h | 82 + drivers/char/rio/rupstat.h | 51 + drivers/char/rio/sam.h | 74 + drivers/char/rio/selftest.h | 73 + drivers/char/rio/space.h | 45 + drivers/char/rio/sysmap.h | 63 + drivers/char/rio/timeouts.h | 51 + drivers/char/rio/top.h | 49 + drivers/char/rio/typdef.h | 82 + drivers/char/rio/unixrup.h | 56 + drivers/char/riscom8.c | 1809 ++++ drivers/char/riscom8.h | 102 + drivers/char/riscom8_reg.h | 254 + drivers/char/rocket.c | 3299 ++++++ drivers/char/rocket.h | 111 + drivers/char/rocket_int.h | 1296 +++ drivers/char/rtc.c | 1354 +++ drivers/char/s3c2410-rtc.c | 588 ++ drivers/char/scan_keyb.c | 149 + drivers/char/scan_keyb.h | 15 + drivers/char/scc.h | 613 ++ drivers/char/scx200_gpio.c | 149 + drivers/char/selection.c | 306 + drivers/char/ser_a2232.c | 825 ++ drivers/char/ser_a2232.h | 202 + drivers/char/ser_a2232fw.ax | 529 + drivers/char/ser_a2232fw.h | 306 + drivers/char/serial167.c | 2858 ++++++ drivers/char/snsc.c | 448 + drivers/char/snsc.h | 50 + drivers/char/sonypi.c | 1403 +++ drivers/char/specialix.c | 2610 +++++ drivers/char/specialix_io8.h | 149 + drivers/char/stallion.c | 5197 ++++++++++ drivers/char/sx.c | 2621 +++++ drivers/char/sx.h | 202 + drivers/char/sxboards.h | 206 + drivers/char/sxwindow.h | 393 + drivers/char/synclink.c | 8214 +++++++++++++++ drivers/char/synclinkmp.c | 5671 +++++++++++ drivers/char/sysrq.c | 432 + drivers/char/tb0219.c | 347 + drivers/char/tipar.c | 564 ++ drivers/char/toshiba.c | 532 + drivers/char/tpm/Kconfig | 39 + drivers/char/tpm/Makefile | 7 + drivers/char/tpm/tpm.c | 697 ++ drivers/char/tpm/tpm.h | 93 + drivers/char/tpm/tpm_atmel.c | 216 + drivers/char/tpm/tpm_nsc.c | 373 + drivers/char/tty_io.c | 2980 ++++++ drivers/char/tty_ioctl.c | 551 + drivers/char/vc_screen.c | 509 + drivers/char/viocons.c | 1195 +++ drivers/char/viotape.c | 1129 +++ drivers/char/vme_scc.c | 1056 ++ drivers/char/vr41xx_rtc.c | 709 ++ drivers/char/vt.c | 3242 ++++++ drivers/char/vt_ioctl.c | 1201 +++ drivers/char/watchdog/Kconfig | 549 + drivers/char/watchdog/Makefile | 42 + drivers/char/watchdog/acquirewdt.c | 332 + drivers/char/watchdog/advantechwdt.c | 333 + drivers/char/watchdog/alim1535_wdt.c | 463 + drivers/char/watchdog/alim7101_wdt.c | 421 + drivers/char/watchdog/cpu5wdt.c | 303 + drivers/char/watchdog/eurotechwdt.c | 474 + drivers/char/watchdog/i8xx_tco.c | 535 + drivers/char/watchdog/i8xx_tco.h | 42 + drivers/char/watchdog/ib700wdt.c | 352 + drivers/char/watchdog/indydog.c | 221 + drivers/char/watchdog/ixp2000_wdt.c | 219 + drivers/char/watchdog/ixp4xx_wdt.c | 230 + drivers/char/watchdog/machzwd.c | 501 + drivers/char/watchdog/mixcomwd.c | 306 + drivers/char/watchdog/mpc8xx_wdt.c | 164 + drivers/char/watchdog/pcwd.c | 926 ++ drivers/char/watchdog/pcwd_pci.c | 677 ++ drivers/char/watchdog/pcwd_usb.c | 796 ++ drivers/char/watchdog/s3c2410_wdt.c | 516 + drivers/char/watchdog/sa1100_wdt.c | 223 + drivers/char/watchdog/sbc60xxwdt.c | 413 + drivers/char/watchdog/sc1200wdt.c | 467 + drivers/char/watchdog/sc520_wdt.c | 447 + drivers/char/watchdog/scx200_wdt.c | 274 + drivers/char/watchdog/shwdt.c | 452 + drivers/char/watchdog/softdog.c | 309 + drivers/char/watchdog/w83627hf_wdt.c | 362 + drivers/char/watchdog/w83877f_wdt.c | 426 + drivers/char/watchdog/wafer5823wdt.c | 330 + drivers/char/watchdog/wd501p.h | 52 + drivers/char/watchdog/wdt.c | 647 ++ drivers/char/watchdog/wdt285.c | 229 + drivers/char/watchdog/wdt977.c | 459 + drivers/char/watchdog/wdt_pci.c | 763 ++ 439 files changed, 264246 insertions(+) create mode 100644 drivers/char/ChangeLog create mode 100644 drivers/char/Kconfig create mode 100644 drivers/char/Makefile create mode 100644 drivers/char/agp/Kconfig create mode 100644 drivers/char/agp/Makefile create mode 100644 drivers/char/agp/agp.h create mode 100644 drivers/char/agp/ali-agp.c create mode 100644 drivers/char/agp/alpha-agp.c create mode 100644 drivers/char/agp/amd-k7-agp.c create mode 100644 drivers/char/agp/amd64-agp.c create mode 100644 drivers/char/agp/ati-agp.c create mode 100644 drivers/char/agp/backend.c create mode 100644 drivers/char/agp/efficeon-agp.c create mode 100644 drivers/char/agp/frontend.c create mode 100644 drivers/char/agp/generic.c create mode 100644 drivers/char/agp/hp-agp.c create mode 100644 drivers/char/agp/i460-agp.c create mode 100644 drivers/char/agp/intel-agp.c create mode 100644 drivers/char/agp/isoch.c create mode 100644 drivers/char/agp/nvidia-agp.c create mode 100644 drivers/char/agp/sgi-agp.c create mode 100644 drivers/char/agp/sis-agp.c create mode 100644 drivers/char/agp/sworks-agp.c create mode 100644 drivers/char/agp/uninorth-agp.c create mode 100644 drivers/char/agp/via-agp.c create mode 100644 drivers/char/amiserial.c create mode 100644 drivers/char/applicom.c create mode 100644 drivers/char/applicom.h create mode 100644 drivers/char/cd1865.h create mode 100644 drivers/char/consolemap.c create mode 100644 drivers/char/cp437.uni create mode 100644 drivers/char/cyclades.c create mode 100644 drivers/char/decserial.c create mode 100644 drivers/char/defkeymap.c_shipped create mode 100644 drivers/char/defkeymap.map create mode 100644 drivers/char/digi.h create mode 100644 drivers/char/digi1.h create mode 100644 drivers/char/digiFep1.h create mode 100644 drivers/char/digiPCI.h create mode 100644 drivers/char/drm/Kconfig create mode 100644 drivers/char/drm/Makefile create mode 100644 drivers/char/drm/README.drm create mode 100644 drivers/char/drm/ati_pcigart.c create mode 100644 drivers/char/drm/drm.h create mode 100644 drivers/char/drm/drmP.h create mode 100644 drivers/char/drm/drm_agpsupport.c create mode 100644 drivers/char/drm/drm_auth.c create mode 100644 drivers/char/drm/drm_bufs.c create mode 100644 drivers/char/drm/drm_context.c create mode 100644 drivers/char/drm/drm_core.h create mode 100644 drivers/char/drm/drm_dma.c create mode 100644 drivers/char/drm/drm_drawable.c create mode 100644 drivers/char/drm/drm_drv.c create mode 100644 drivers/char/drm/drm_fops.c create mode 100644 drivers/char/drm/drm_init.c create mode 100644 drivers/char/drm/drm_ioctl.c create mode 100644 drivers/char/drm/drm_irq.c create mode 100644 drivers/char/drm/drm_lock.c create mode 100644 drivers/char/drm/drm_memory.c create mode 100644 drivers/char/drm/drm_memory.h create mode 100644 drivers/char/drm/drm_memory_debug.h create mode 100644 drivers/char/drm/drm_os_linux.h create mode 100644 drivers/char/drm/drm_pci.c create mode 100644 drivers/char/drm/drm_pciids.h create mode 100644 drivers/char/drm/drm_proc.c create mode 100644 drivers/char/drm/drm_sarea.h create mode 100644 drivers/char/drm/drm_scatter.c create mode 100644 drivers/char/drm/drm_stub.c create mode 100644 drivers/char/drm/drm_sysfs.c create mode 100644 drivers/char/drm/drm_vm.c create mode 100644 drivers/char/drm/ffb_context.c create mode 100644 drivers/char/drm/ffb_drv.c create mode 100644 drivers/char/drm/ffb_drv.h create mode 100644 drivers/char/drm/gamma_context.h create mode 100644 drivers/char/drm/gamma_dma.c create mode 100644 drivers/char/drm/gamma_drm.h create mode 100644 drivers/char/drm/gamma_drv.c create mode 100644 drivers/char/drm/gamma_drv.h create mode 100644 drivers/char/drm/gamma_lists.h create mode 100644 drivers/char/drm/gamma_lock.h create mode 100644 drivers/char/drm/gamma_old_dma.h create mode 100644 drivers/char/drm/i810_dma.c create mode 100644 drivers/char/drm/i810_drm.h create mode 100644 drivers/char/drm/i810_drv.c create mode 100644 drivers/char/drm/i810_drv.h create mode 100644 drivers/char/drm/i830_dma.c create mode 100644 drivers/char/drm/i830_drm.h create mode 100644 drivers/char/drm/i830_drv.c create mode 100644 drivers/char/drm/i830_drv.h create mode 100644 drivers/char/drm/i830_irq.c create mode 100644 drivers/char/drm/i915_dma.c create mode 100644 drivers/char/drm/i915_drm.h create mode 100644 drivers/char/drm/i915_drv.c create mode 100644 drivers/char/drm/i915_drv.h create mode 100644 drivers/char/drm/i915_irq.c create mode 100644 drivers/char/drm/i915_mem.c create mode 100644 drivers/char/drm/mga_dma.c create mode 100644 drivers/char/drm/mga_drm.h create mode 100644 drivers/char/drm/mga_drv.c create mode 100644 drivers/char/drm/mga_drv.h create mode 100644 drivers/char/drm/mga_irq.c create mode 100644 drivers/char/drm/mga_state.c create mode 100644 drivers/char/drm/mga_ucode.h create mode 100644 drivers/char/drm/mga_warp.c create mode 100644 drivers/char/drm/r128_cce.c create mode 100644 drivers/char/drm/r128_drm.h create mode 100644 drivers/char/drm/r128_drv.c create mode 100644 drivers/char/drm/r128_drv.h create mode 100644 drivers/char/drm/r128_irq.c create mode 100644 drivers/char/drm/r128_state.c create mode 100644 drivers/char/drm/radeon_cp.c create mode 100644 drivers/char/drm/radeon_drm.h create mode 100644 drivers/char/drm/radeon_drv.c create mode 100644 drivers/char/drm/radeon_drv.h create mode 100644 drivers/char/drm/radeon_irq.c create mode 100644 drivers/char/drm/radeon_mem.c create mode 100644 drivers/char/drm/radeon_state.c create mode 100644 drivers/char/drm/sis_drm.h create mode 100644 drivers/char/drm/sis_drv.c create mode 100644 drivers/char/drm/sis_drv.h create mode 100644 drivers/char/drm/sis_ds.c create mode 100644 drivers/char/drm/sis_ds.h create mode 100644 drivers/char/drm/sis_mm.c create mode 100644 drivers/char/drm/tdfx_drv.c create mode 100644 drivers/char/drm/tdfx_drv.h create mode 100644 drivers/char/ds1286.c create mode 100644 drivers/char/ds1302.c create mode 100644 drivers/char/ds1620.c create mode 100644 drivers/char/dsp56k.c create mode 100644 drivers/char/dtlk.c create mode 100644 drivers/char/ec3104_keyb.c create mode 100644 drivers/char/efirtc.c create mode 100644 drivers/char/epca.c create mode 100644 drivers/char/epca.h create mode 100644 drivers/char/epcaconfig.h create mode 100644 drivers/char/esp.c create mode 100644 drivers/char/ftape/Kconfig create mode 100644 drivers/char/ftape/Makefile create mode 100644 drivers/char/ftape/README.PCI create mode 100644 drivers/char/ftape/RELEASE-NOTES create mode 100644 drivers/char/ftape/compressor/Makefile create mode 100644 drivers/char/ftape/compressor/lzrw3.c create mode 100644 drivers/char/ftape/compressor/lzrw3.h create mode 100644 drivers/char/ftape/compressor/zftape-compress.c create mode 100644 drivers/char/ftape/compressor/zftape-compress.h create mode 100644 drivers/char/ftape/lowlevel/Makefile create mode 100644 drivers/char/ftape/lowlevel/fc-10.c create mode 100644 drivers/char/ftape/lowlevel/fc-10.h create mode 100644 drivers/char/ftape/lowlevel/fdc-io.c create mode 100644 drivers/char/ftape/lowlevel/fdc-io.h create mode 100644 drivers/char/ftape/lowlevel/fdc-isr.c create mode 100644 drivers/char/ftape/lowlevel/fdc-isr.h create mode 100644 drivers/char/ftape/lowlevel/ftape-bsm.c create mode 100644 drivers/char/ftape/lowlevel/ftape-bsm.h create mode 100644 drivers/char/ftape/lowlevel/ftape-buffer.c create mode 100644 drivers/char/ftape/lowlevel/ftape-buffer.h create mode 100644 drivers/char/ftape/lowlevel/ftape-calibr.c create mode 100644 drivers/char/ftape/lowlevel/ftape-calibr.h create mode 100644 drivers/char/ftape/lowlevel/ftape-ctl.c create mode 100644 drivers/char/ftape/lowlevel/ftape-ctl.h create mode 100644 drivers/char/ftape/lowlevel/ftape-ecc.c create mode 100644 drivers/char/ftape/lowlevel/ftape-ecc.h create mode 100644 drivers/char/ftape/lowlevel/ftape-format.c create mode 100644 drivers/char/ftape/lowlevel/ftape-format.h create mode 100644 drivers/char/ftape/lowlevel/ftape-init.c create mode 100644 drivers/char/ftape/lowlevel/ftape-init.h create mode 100644 drivers/char/ftape/lowlevel/ftape-io.c create mode 100644 drivers/char/ftape/lowlevel/ftape-io.h create mode 100644 drivers/char/ftape/lowlevel/ftape-proc.c create mode 100644 drivers/char/ftape/lowlevel/ftape-proc.h create mode 100644 drivers/char/ftape/lowlevel/ftape-read.c create mode 100644 drivers/char/ftape/lowlevel/ftape-read.h create mode 100644 drivers/char/ftape/lowlevel/ftape-rw.c create mode 100644 drivers/char/ftape/lowlevel/ftape-rw.h create mode 100644 drivers/char/ftape/lowlevel/ftape-setup.c create mode 100644 drivers/char/ftape/lowlevel/ftape-tracing.c create mode 100644 drivers/char/ftape/lowlevel/ftape-tracing.h create mode 100644 drivers/char/ftape/lowlevel/ftape-write.c create mode 100644 drivers/char/ftape/lowlevel/ftape-write.h create mode 100644 drivers/char/ftape/lowlevel/ftape_syms.c create mode 100644 drivers/char/ftape/zftape/Makefile create mode 100644 drivers/char/ftape/zftape/zftape-buffers.c create mode 100644 drivers/char/ftape/zftape/zftape-buffers.h create mode 100644 drivers/char/ftape/zftape/zftape-ctl.c create mode 100644 drivers/char/ftape/zftape/zftape-ctl.h create mode 100644 drivers/char/ftape/zftape/zftape-eof.c create mode 100644 drivers/char/ftape/zftape/zftape-eof.h create mode 100644 drivers/char/ftape/zftape/zftape-init.c create mode 100644 drivers/char/ftape/zftape/zftape-init.h create mode 100644 drivers/char/ftape/zftape/zftape-read.c create mode 100644 drivers/char/ftape/zftape/zftape-read.h create mode 100644 drivers/char/ftape/zftape/zftape-rw.c create mode 100644 drivers/char/ftape/zftape/zftape-rw.h create mode 100644 drivers/char/ftape/zftape/zftape-vtbl.c create mode 100644 drivers/char/ftape/zftape/zftape-vtbl.h create mode 100644 drivers/char/ftape/zftape/zftape-write.c create mode 100644 drivers/char/ftape/zftape/zftape-write.h create mode 100644 drivers/char/ftape/zftape/zftape_syms.c create mode 100644 drivers/char/generic_nvram.c create mode 100644 drivers/char/generic_serial.c create mode 100644 drivers/char/genrtc.c create mode 100644 drivers/char/hangcheck-timer.c create mode 100644 drivers/char/hpet.c create mode 100644 drivers/char/hvc_console.c create mode 100644 drivers/char/hvcs.c create mode 100644 drivers/char/hvsi.c create mode 100644 drivers/char/hw_random.c create mode 100644 drivers/char/i8k.c create mode 100644 drivers/char/ip2.c create mode 100644 drivers/char/ip2/fip_firm.h create mode 100644 drivers/char/ip2/i2cmd.c create mode 100644 drivers/char/ip2/i2cmd.h create mode 100644 drivers/char/ip2/i2ellis.c create mode 100644 drivers/char/ip2/i2ellis.h create mode 100644 drivers/char/ip2/i2hw.h create mode 100644 drivers/char/ip2/i2lib.c create mode 100644 drivers/char/ip2/i2lib.h create mode 100644 drivers/char/ip2/i2os.h create mode 100644 drivers/char/ip2/i2pack.h create mode 100644 drivers/char/ip2/ip2.h create mode 100644 drivers/char/ip2/ip2ioctl.h create mode 100644 drivers/char/ip2/ip2trace.h create mode 100644 drivers/char/ip2/ip2types.h create mode 100644 drivers/char/ip27-rtc.c create mode 100644 drivers/char/ip2main.c create mode 100644 drivers/char/ipmi/Kconfig create mode 100644 drivers/char/ipmi/Makefile create mode 100644 drivers/char/ipmi/ipmi_bt_sm.c create mode 100644 drivers/char/ipmi/ipmi_devintf.c create mode 100644 drivers/char/ipmi/ipmi_kcs_sm.c create mode 100644 drivers/char/ipmi/ipmi_msghandler.c create mode 100644 drivers/char/ipmi/ipmi_poweroff.c create mode 100644 drivers/char/ipmi/ipmi_si_intf.c create mode 100644 drivers/char/ipmi/ipmi_si_sm.h create mode 100644 drivers/char/ipmi/ipmi_smic_sm.c create mode 100644 drivers/char/ipmi/ipmi_watchdog.c create mode 100644 drivers/char/isicom.c create mode 100644 drivers/char/istallion.c create mode 100644 drivers/char/ite_gpio.c create mode 100644 drivers/char/keyboard.c create mode 100644 drivers/char/lcd.c create mode 100644 drivers/char/lcd.h create mode 100644 drivers/char/lp.c create mode 100644 drivers/char/mem.c create mode 100644 drivers/char/misc.c create mode 100644 drivers/char/mmtimer.c create mode 100644 drivers/char/moxa.c create mode 100644 drivers/char/mwave/3780i.c create mode 100644 drivers/char/mwave/3780i.h create mode 100644 drivers/char/mwave/Makefile create mode 100644 drivers/char/mwave/README create mode 100644 drivers/char/mwave/mwavedd.c create mode 100644 drivers/char/mwave/mwavedd.h create mode 100644 drivers/char/mwave/mwavepub.h create mode 100644 drivers/char/mwave/smapi.c create mode 100644 drivers/char/mwave/smapi.h create mode 100644 drivers/char/mwave/tp3780i.c create mode 100644 drivers/char/mwave/tp3780i.h create mode 100644 drivers/char/mxser.c create mode 100644 drivers/char/mxser.h create mode 100644 drivers/char/n_hdlc.c create mode 100644 drivers/char/n_r3964.c create mode 100644 drivers/char/n_tty.c create mode 100644 drivers/char/nvram.c create mode 100644 drivers/char/nwbutton.c create mode 100644 drivers/char/nwbutton.h create mode 100644 drivers/char/nwflash.c create mode 100644 drivers/char/pcmcia/Kconfig create mode 100644 drivers/char/pcmcia/Makefile create mode 100644 drivers/char/pcmcia/synclink_cs.c create mode 100644 drivers/char/ppdev.c create mode 100644 drivers/char/pty.c create mode 100644 drivers/char/qtronix.c create mode 100644 drivers/char/qtronixmap.c_shipped create mode 100644 drivers/char/qtronixmap.map create mode 100644 drivers/char/random.c create mode 100644 drivers/char/raw.c create mode 100644 drivers/char/rio/Makefile create mode 100644 drivers/char/rio/board.h create mode 100644 drivers/char/rio/bootpkt.h create mode 100644 drivers/char/rio/brates.h create mode 100644 drivers/char/rio/chan.h create mode 100644 drivers/char/rio/cirrus.h create mode 100644 drivers/char/rio/cmd.h create mode 100644 drivers/char/rio/cmdblk.h create mode 100644 drivers/char/rio/cmdpkt.h create mode 100644 drivers/char/rio/control.h create mode 100644 drivers/char/rio/daemon.h create mode 100644 drivers/char/rio/data.h create mode 100644 drivers/char/rio/debug.h create mode 100644 drivers/char/rio/defaults.h create mode 100644 drivers/char/rio/eisa.h create mode 100644 drivers/char/rio/enable.h create mode 100644 drivers/char/rio/error.h create mode 100644 drivers/char/rio/errors.h create mode 100644 drivers/char/rio/formpkt.h create mode 100644 drivers/char/rio/func.h create mode 100644 drivers/char/rio/host.h create mode 100644 drivers/char/rio/hosthw.h create mode 100644 drivers/char/rio/link.h create mode 100644 drivers/char/rio/linux_compat.h create mode 100644 drivers/char/rio/list.h create mode 100644 drivers/char/rio/lrt.h create mode 100644 drivers/char/rio/ltt.h create mode 100644 drivers/char/rio/lttwake.h create mode 100644 drivers/char/rio/map.h create mode 100644 drivers/char/rio/mca.h create mode 100644 drivers/char/rio/mesg.h create mode 100644 drivers/char/rio/param.h create mode 100644 drivers/char/rio/parmmap.h create mode 100644 drivers/char/rio/pci.h create mode 100644 drivers/char/rio/phb.h create mode 100644 drivers/char/rio/pkt.h create mode 100644 drivers/char/rio/poll.h create mode 100644 drivers/char/rio/port.h create mode 100644 drivers/char/rio/proto.h create mode 100644 drivers/char/rio/protsts.h create mode 100644 drivers/char/rio/qbuf.h create mode 100644 drivers/char/rio/rio.h create mode 100644 drivers/char/rio/rio_linux.c create mode 100644 drivers/char/rio/rio_linux.h create mode 100644 drivers/char/rio/rioboard.h create mode 100644 drivers/char/rio/rioboot.c create mode 100644 drivers/char/rio/riocmd.c create mode 100644 drivers/char/rio/rioctrl.c create mode 100644 drivers/char/rio/riodrvr.h create mode 100644 drivers/char/rio/rioinfo.h create mode 100644 drivers/char/rio/rioinit.c create mode 100644 drivers/char/rio/riointr.c create mode 100644 drivers/char/rio/rioioctl.h create mode 100644 drivers/char/rio/riolocks.h create mode 100644 drivers/char/rio/rioparam.c create mode 100644 drivers/char/rio/riopcicopy.c create mode 100644 drivers/char/rio/rioroute.c create mode 100644 drivers/char/rio/riospace.h create mode 100644 drivers/char/rio/riotable.c create mode 100644 drivers/char/rio/riotime.h create mode 100644 drivers/char/rio/riotty.c create mode 100644 drivers/char/rio/riotypes.h create mode 100644 drivers/char/rio/riowinif.h create mode 100644 drivers/char/rio/riscos.h create mode 100644 drivers/char/rio/rom.h create mode 100644 drivers/char/rio/route.h create mode 100644 drivers/char/rio/rtahw.h create mode 100644 drivers/char/rio/rup.h create mode 100644 drivers/char/rio/rupstat.h create mode 100644 drivers/char/rio/sam.h create mode 100644 drivers/char/rio/selftest.h create mode 100644 drivers/char/rio/space.h create mode 100644 drivers/char/rio/sysmap.h create mode 100644 drivers/char/rio/timeouts.h create mode 100644 drivers/char/rio/top.h create mode 100644 drivers/char/rio/typdef.h create mode 100644 drivers/char/rio/unixrup.h create mode 100644 drivers/char/riscom8.c create mode 100644 drivers/char/riscom8.h create mode 100644 drivers/char/riscom8_reg.h create mode 100644 drivers/char/rocket.c create mode 100644 drivers/char/rocket.h create mode 100644 drivers/char/rocket_int.h create mode 100644 drivers/char/rtc.c create mode 100644 drivers/char/s3c2410-rtc.c create mode 100644 drivers/char/scan_keyb.c create mode 100644 drivers/char/scan_keyb.h create mode 100644 drivers/char/scc.h create mode 100644 drivers/char/scx200_gpio.c create mode 100644 drivers/char/selection.c create mode 100644 drivers/char/ser_a2232.c create mode 100644 drivers/char/ser_a2232.h create mode 100644 drivers/char/ser_a2232fw.ax create mode 100644 drivers/char/ser_a2232fw.h create mode 100644 drivers/char/serial167.c create mode 100644 drivers/char/snsc.c create mode 100644 drivers/char/snsc.h create mode 100644 drivers/char/sonypi.c create mode 100644 drivers/char/specialix.c create mode 100644 drivers/char/specialix_io8.h create mode 100644 drivers/char/stallion.c create mode 100644 drivers/char/sx.c create mode 100644 drivers/char/sx.h create mode 100644 drivers/char/sxboards.h create mode 100644 drivers/char/sxwindow.h create mode 100644 drivers/char/synclink.c create mode 100644 drivers/char/synclinkmp.c create mode 100644 drivers/char/sysrq.c create mode 100644 drivers/char/tb0219.c create mode 100644 drivers/char/tipar.c create mode 100644 drivers/char/toshiba.c create mode 100644 drivers/char/tpm/Kconfig create mode 100644 drivers/char/tpm/Makefile create mode 100644 drivers/char/tpm/tpm.c create mode 100644 drivers/char/tpm/tpm.h create mode 100644 drivers/char/tpm/tpm_atmel.c create mode 100644 drivers/char/tpm/tpm_nsc.c create mode 100644 drivers/char/tty_io.c create mode 100644 drivers/char/tty_ioctl.c create mode 100644 drivers/char/vc_screen.c create mode 100644 drivers/char/viocons.c create mode 100644 drivers/char/viotape.c create mode 100644 drivers/char/vme_scc.c create mode 100644 drivers/char/vr41xx_rtc.c create mode 100644 drivers/char/vt.c create mode 100644 drivers/char/vt_ioctl.c create mode 100644 drivers/char/watchdog/Kconfig create mode 100644 drivers/char/watchdog/Makefile create mode 100644 drivers/char/watchdog/acquirewdt.c create mode 100644 drivers/char/watchdog/advantechwdt.c create mode 100644 drivers/char/watchdog/alim1535_wdt.c create mode 100644 drivers/char/watchdog/alim7101_wdt.c create mode 100644 drivers/char/watchdog/cpu5wdt.c create mode 100644 drivers/char/watchdog/eurotechwdt.c create mode 100644 drivers/char/watchdog/i8xx_tco.c create mode 100644 drivers/char/watchdog/i8xx_tco.h create mode 100644 drivers/char/watchdog/ib700wdt.c create mode 100644 drivers/char/watchdog/indydog.c create mode 100644 drivers/char/watchdog/ixp2000_wdt.c create mode 100644 drivers/char/watchdog/ixp4xx_wdt.c create mode 100644 drivers/char/watchdog/machzwd.c create mode 100644 drivers/char/watchdog/mixcomwd.c create mode 100644 drivers/char/watchdog/mpc8xx_wdt.c create mode 100644 drivers/char/watchdog/pcwd.c create mode 100644 drivers/char/watchdog/pcwd_pci.c create mode 100644 drivers/char/watchdog/pcwd_usb.c create mode 100644 drivers/char/watchdog/s3c2410_wdt.c create mode 100644 drivers/char/watchdog/sa1100_wdt.c create mode 100644 drivers/char/watchdog/sbc60xxwdt.c create mode 100644 drivers/char/watchdog/sc1200wdt.c create mode 100644 drivers/char/watchdog/sc520_wdt.c create mode 100644 drivers/char/watchdog/scx200_wdt.c create mode 100644 drivers/char/watchdog/shwdt.c create mode 100644 drivers/char/watchdog/softdog.c create mode 100644 drivers/char/watchdog/w83627hf_wdt.c create mode 100644 drivers/char/watchdog/w83877f_wdt.c create mode 100644 drivers/char/watchdog/wafer5823wdt.c create mode 100644 drivers/char/watchdog/wd501p.h create mode 100644 drivers/char/watchdog/wdt.c create mode 100644 drivers/char/watchdog/wdt285.c create mode 100644 drivers/char/watchdog/wdt977.c create mode 100644 drivers/char/watchdog/wdt_pci.c (limited to 'drivers/char') diff --git a/drivers/char/ChangeLog b/drivers/char/ChangeLog new file mode 100644 index 000000000000..56b8a2e76ab1 --- /dev/null +++ b/drivers/char/ChangeLog @@ -0,0 +1,775 @@ +2001-08-11 Tim Waugh + + * serial.c (get_pci_port): Deal with awkward Titan cards. + +1998-08-26 Theodore Ts'o + + * serial.c (rs_open): Correctly decrement the module in-use count + on errors. + +Thu Feb 19 14:24:08 1998 Theodore Ts'o + + * tty_io.c (tty_name): Remove the non-reentrant (and non-SMP safe) + version of tty_name, and rename the reentrant _tty_name + function to be tty_name. + (tty_open): Add a warning message stating callout devices + are deprecated. + +Mon Dec 1 08:24:15 1997 Theodore Ts'o + + * tty_io.c (tty_get_baud_rate): Print a warning syslog if the + tty->alt_speed kludge is used; this means the system is + using the deprecated SPD_HI ioctls. + +Mon Nov 24 10:37:49 1997 Theodore Ts'o + + * serial.c, esp.c, rocket.c: Change drivers to take advantage of + tty_get_baud_rate(). + + * tty_io.c (tty_get_baud_rate): New function which computes the + correct baud rate for the tty. More factoring out of + common code out of the serial driver to the high-level tty + functions.... + +Sat Nov 22 07:53:36 1997 Theodore Ts'o + + * serial.c, esp.c, rocket.c: Add tty->driver.break() routine, and + allow high-level tty code to handle the break and soft + carrier ioctls. + + * tty_ioctl.c (n_tty_ioctl): Support TIOCGSOFTCAR and + TIOCSSOFTCAR, so that device drivers don't have to support + it. + + * serial.c (autoconfig): Change 16750 test to hopefully eliminate + false results by people with strange 16550As being + detected as 16750s. Hopefully 16750s will still be + detected as 16750, and other weird UARTs won't get poorly + autodetected. If this doesn't work, I'll have to disable + the auto identification for the 16750. + + * tty_io.c (tty_hangup): Now actually do the tty hangup + processing during the timer processing, and disable + interrupts while doing the hangup processing. This avoids + several nasty race conditions which happened when the + hangup processing was done asynchronously. + (tty_ioctl): Do break handling in the tty driver if + driver's break function is supported. + (tty_flip_buffer_push): New exported function which should + be used by drivers to push characters in the flip buffer + to the tty handler. This may either be done using a task + queue function for better CPU efficiency, or directly for + low latency operation. + + * serial.c (rs_set_termios): Fix bug rs_set_termios when + transitioning away from B0, submitted by Stanislav + Voronyi. + +Thu Jun 19 20:05:58 1997 Theodore Ts'o + + * serial.c (begin_break, end_break, rs_ioctl): Applied patch + to support BSD ioctls to set and clear the break + condition explicitly. + + * console.c (scrup, scrdown, insert_line, delete_line): Applied + fix suggested by Aaron Tiensivu to speed up block scrolls + up and down. + + * n_tty.c (opost_block, write_chan): Added a modified "fast + console" patch which processes a block of text via + "cooking" efficiently. + +Wed Jun 18 15:25:50 1997 Theodore Ts'o + + * tty_io.c (init_dev, release_dev): Applied fix suggested by Bill + Hawes to prevent race conditions in the tty code. + + * n_tty.c (n_tty_chars_in_buffer): Applied fix suggested by Bill + Hawes so that n_tty_chars_in_buffer returns the correct + value in the case when the tty is in cannonical mode. (To + avoid a pty deadlock with telnetd.) + +Thu Feb 27 01:53:08 1997 Theodore Ts'o + + * serial.c (change_speed): Add support for the termios flag + CMSPAR, which allows the user to select stick parity. + (i.e, if PARODD is set, the parity bit is always 1; if + PARRODD is not set, then the parity bit is always 0). + +Wed Feb 26 19:03:10 1997 Theodore Ts'o + + * serial.c (cleanup_module): Fix memory leak when using the serial + driver as a module; make sure tmp_buf gets freed! + +Tue Feb 25 11:01:59 1997 Theodore Ts'o + + * serial.c (set_modem_info): Add support for setting and clearing + the OUT1 and OUT2 bits. (For special case UART's, usually + for half-duplex.) + (autoconfig, change_speed): Fix TI 16750 support. + +Sun Feb 16 00:14:43 1997 Theodore Ts'o + + * tty_io.c (release_dev): Add sanity check to make sure there are + no waiters on tty->read_wait or tty->write_wait. + + * serial.c (rs_init): Don't autoconfig a device if the I/O region + is already reserved. + + * serial.c (serial_proc_info): Add support for /proc/serial. + +Thu Feb 13 00:49:10 1997 Theodore Ts'o + + * serial.c (receive_chars): When the UART repotrs an overrun + condition, it does so with a valid character. Changed to + not throw away the valid character, but instead report the + overrun after the valid character. + + * serial.c: Added new #ifdef's for some of the advanced serial + driver features. A minimal driver that only supports COM + 1/2/3/4 without sharing serial interrupts only takes 17k; + the full driver takes 32k. + +Wed Feb 12 14:50:44 1997 Theodore Ts'o + + * vt.c: + * pty.c: + * tty_ioctl.c: + * serial.c: Update routines to use the new 2.1 memory access + routines. + +Wed Dec 4 07:51:52 1996 Theodore Ts'o + + * serial.c (change_speed): Use save_flags(); cli() and + restore_flags() in order to ensure we don't accidentally + turn on interrupts when starting up the port. + (startup): Move the insertion of serial structure into the + IRQ chain earlier into the startup processing. Interrupts + should be off this whole time, but we eventually will want + to reduce this window. + +Thu Nov 21 10:05:22 1996 Theodore Ts'o + + * tty_ioctl.c (tty_wait_until_sent): Always check the driver + wait_until_ready routine, even if there are no characters + in the xmit buffer. (There may be charactes in the device + FIFO.) + (n_tty_ioctl): Add new flag tty->flow_stopped which + indicates whether the tty is stopped due to a request by + the TCXONC ioctl (used by tcflow). If so, don't let an + incoming XOFF character restart the tty. The tty can only + be restarted by another TCXONC request. + + * tty_io.c (start_tty): Don't allow the tty to be restarted if + tty->flow_stopped is true. + + * n_tty.c (n_tty_receive_char): If tty->flow_stopped is true, and + IXANY is set, don't eat a character trying to restart the + tty. + + * serial.c (startup): Remove need for MCR_noint from the + async_struct structure. Only turn on DTR and RTS if the + baud rate is not zero. + (change_speed): More accurately calculate the timeout + value based on the word size. Move responsibility of + hangup when speed becomes B0 to rs_set_termios() + (set_serial_info): When changing the UART type set the + current xmit_fifo_size as well as the permanent + xmit_fifo_size. + (rs_ioctl): Fix TCSBRK (used by tcdrain) and TCSBRKP + ioctls to return EINTR if interrupted by a signal. + (rs_set_termios): If the baud rate changes to or from B0, + this function is now responsible for setting or clearing + DTR and RTS. DTR and RTS are only be changed on the + transition to or from the B0 state. + (rs_close): Wait for the characters to drain based on + info->timeout. At low baud rates (50 bps), it may take a + long time for the FIFO to completely drain out! + (rs_wait_until_sent): Fixed timeout handling. Now + releases control to the scheduler, but checks frequently + enough so that the function is sensitive enough to pass + the timing requirements of the NIST-PCTS. + (block_til_ready): When opening the device, don't turn on + DTR and RTS if the baud rate is B0. + +Thu Nov 14 00:06:09 1996 Theodore Ts'o + + * serial.c (autoconfig): Fix autoconfiguration problems; + info->flags wasn't getting initialized from the state + structure. Put in more paranoid test for the 16750. + +Fri Nov 8 20:19:50 1996 Theodore Ts'o + + * n_tty.c (n_tty_flush_buffer): Only call driver->unthrottle() if + the tty was previous throttled. + (n_tty_set_termios, write_chan): Add changes suggested by + Simon P. Allen to allow hardware cooking. + + * tty_ioctl.c (set_termios): If we get a signal while waiting for + the tty to drain, return -EINTR. + + * serial.c (change_speed): Add support for CREAD, as required by + POSIX. + +Sat Nov 2 20:43:10 1996 Theodore Ts'o + + * serial.c: Wholesale changes. Added support for the Startech + 16650 and 16650V2 chips. (WARNING: the new startech + 16650A may or may not work!) Added support for the + TI16750 (not yet tested). Split async_struct into a + transient part (async_struct) and a permanent part + (serial_state) which contains the configuration + information for the ports. Added new driver routines + wait_until_sent() and send_xchar() to help with POSIX + compliance. Added support for radio clocks which waggle + the carrier detect line (CONFIG_HARD_PPS). + + * tty_ioctl.c (tty_wait_until_sent): Added call to new driver + function tty->driver.wait_until_sent(), which returns when + the tty's device xmit buffers are drained. Needed for + full POSIX compliance. + + (send_prio_char): New function, called by the ioctl's + TCIOFF and TCION; uses the new driver call send_xchar(), + which will send the XON or XOFF character at high priority + (and even if tty output is stopped). + +Wed Jun 5 18:52:04 1996 Theodore Ts'o + + * pty.c (pty_close): When closing a pty, make sure packet mode is + cleared. + +Sun May 26 09:33:52 1996 Theodore Ts'o + + * vesa_blank.c (set_vesa_blanking): Add missing verify_area() call. + + * selection.c (set_selection): Add missing verify_area() call. + + * tty_io.c (tty_ioctl): Add missing verify_area() calls. + + * serial.c (rs_ioctl): Add missing verify_area() calls. + (rs_init): Allow initialization of serial driver + configuration from a module. + + * random.c (extract_entropy): Add missing verify_area call. + Don't limit number of characters returned to + 32,768. Extract entropy is now no longer a inlined + function. + + (random_read): Check return value in case extract_entropy + returns an error. + + (secure_tcp_sequence_number): New function which returns a + secure TCP sequence number. This is needed to prevent some + nasty TCP hijacking attacks. + + (init_std_data): Initialize using gettimeofday() instead of + struct timeval xtime. + + (fast_add_entropy_word, add_entropy_word): Rename the + inline function add_entropy_word() to + fast_add_entropy_word(). Make add_entropy_word() be the + non-inlined function which is used in non-timing critical + places, in order to save space. + + (initialize_benchmark, begin_benchmark, end_benchmark): New + functions defined when RANDOM_BENCHMARK is defined. They + allow us to benchmark the speed of the + add_timer_randomness() call. + + (int_ln, rotate_left): Add two new inline functions with + i386 optimized asm instructions. This speeds up the + critical add_entropy_word() and add_timer_randomness() + functions, which are called from interrupt handlers. + +Tue May 7 22:51:11 1996 + + * random.c (add_timer_randomness): Limit the amount randomness + that we estimate to 12 bits. (An arbitrary amount). + + (extract_entropy): To make it harder to analyze the hash + function, fold the hash function in half using XOR, and + use the folded result as the value to emit to the user. + Also, add timer randomness each pass through the + exact_entropy call, to increase the amount of unknown + values during the extraction process. + + (random_ioctl): Use IOR/IOW definitions to define the + ioctl values used by the /dev/random driver. Allow the + old ioctl values to be used for backwards compatibility + (for a limited amount of time). + +Wed Apr 24 14:02:04 1996 Theodore Ts'o + + * random.c (add_timer_randomness): Use 2nd derivative as well to + better estimate entropy. + + (rand_initialize): Explicitly initialize all the pointers + to NULL. (Clearing pointers using memset isn't portable.) + Initialize the random pool with OS-dependent data. + + (random_write): Add sanity checking to the arguments to + random_write(), so that bad arguments won't cause a kernel + SEGV. + + (random_read): Update the access time of the device inode + when you return data to the user. + + (random_ioctl): Wake up the random_wait channel when there + are only WAIT_INPUT_BITS available. Add more paranoia + checks to make sure entropy_count doesn't go beyond the + bounds of (0, POOLSIZE). Add a few missing verify_area + checks. Add support for the RNDCLEARPOOL ioctl, which + zaps the random pool. + + (add_timer_randomness): Wake up the random_wait + channel only when there are WAIT_INPUT_BITS available. + + (random_select): Allow a random refresh daemon process to + select on /dev/random for writing; wake up the daemon when + there are less than WAIT_OUTPUT_BITS bits of randomness + available. + +Tue Apr 23 22:56:07 1996 + + * tty_io.c (init_dev): Change return code when user attempts to + open master pty which is already open from EAGAIN to EIO, + to match with BSD expectations. EIO is more correct + anyway, since EAGAIN implies that retrying will be + successful --- which it might be.... Eventually!! + + * pty.c (pty_open, pty_close): Fix wait loop so that we don't + busy loop while waiting for the master side to open. + Fix tty opening/closing logic. TTY_SLAVE_CLOSED was + renamed to TTY_OTHER_CLOSED, so that the name is more + descriptive. Also fixed code so that the tty flag + actually works correctly now.... + +Mon Apr 1 10:22:01 1996 + + * serial.c (rs_close): Cleaned up modularization changes. + Remove code which forced line discipline back to N_TTY + this is done in the tty upper layers, and there's no + reason to do it here. (Making this change also + removed the requirement that the serial module access + the internal kernel symbol "ldiscs".) + + * tty_io.c (tty_init): Formally register a tty_driver entry for + /dev/tty (device 4, 0) and /dev/console (device 5, 0). + This guarantees that major device numbers 4 and 5 will be + reserved for the tty subsystem (as they have to be because + of /dev/tty and /dev/console). Removed tty_regdev, as + this interface is no longer necessary. + +Sun Mar 17 20:42:47 GMT 1996 + + * serial.c : modularisation (changes in linux/fs/device.c allow + kerneld to automatically load the serial module). + + * Makefile, Config.in : serial modularisation adds. + + * tty_io.c : tty_init_ctty used by to register "cua" driver just + for the /dev/tty device (5,0). Added tty_regdev. + + * serial.c (shutdown, rs_ioctl) : when port shuts down wakeup processes + waiting on delta_msr_wait. The TIOCMIWAIT ioctl returns EIO + if no change was done since the time of call. + +Sat Mar 16 14:33:13 1996 + + * tty_io.c (disassociate_ctty): If disassociate_ctty is called by + exit, do not perform an implicit vhangup on a pty. + +Fri Feb 9 14:15:47 1996 + + * serial.c (block_til_ready): Fixed another race condition which + happens if a hangup happens during the open. + +Wed Jan 10 10:08:00 1996 + + * serial.c (block_til_ready): Remove race condition which happened + if a hangup condition happened during the setup of the + UART, before rs_open() called block_til_ready(). This + caused the info->count counter to be erroneously + decremented. + + * serial.c (startup, rs_open): Remove race condition that could + cause a memory leak of one page. (Fortunately, both race + conditions were relatively rare in practice.) + +Tue Dec 5 13:21:27 1995 + + * serial.c (check_modem_status, rs_ioctl): Support the new + ioctl()'s TIOCGICOUNT, TIOCMIWAIT. These allow an + application program to wait on a modem serial register + status bit change, and to find out how many changes have + taken place for the MSR bits. + + (rs_write): Eliminate a race condition which is introduced + if it is necessary to wait for the semaphore. + +Sat Nov 4 17:14:45 1995 + + * tty_io.c (tty_init): Move registration of TTY_MAJOR and + TTY_AUX_MAJOR to the end, so that /proc/devices looks + prettier. + + * pty.c (pty_init): Use new major numbers for PTY master and slave + devices. This allow us to have more than 64 pty's. We + register the old pty devices for backwards compatibility. + Note that a system should either be using the old pty + devices or the new pty devices --- in general, it should + try to use both, since they map into the same pty table. + The old pty devices are strictly for backwards compatibility. + +Wed Oct 11 12:45:24 1995 + + * tty_io.c (disassociate_ctty): If disassociate_ctty is called by + exit, perform an implicit vhangup on the tty. + + * pty.c (pty_close): When the master pty is closed, send a hangup + to the slave pty. + (pty_open): Use the flag TTY_SLAVE_CLOSED to test to see + if there are any open slave ptys, instead of using + tty->link->count. The old method got confused if there + were processes that had hung-up file descriptors on the + slave tty. + +Tue May 2 00:53:25 1995 + + * tty_io.c (tty_set_ldisc): Wait until the output buffer is + drained before closing the old line discipline --- needed + in only one case: XON/XOFF processing. + + * n_tty.c (n_tty_close): Don't bother waiting until the output + driver is closed; in general, the line discipline + shouldn't care if the hardware is finished + transmitting before the line discipline terminates. + + * tty_io.c (release_dev): Shutdown the line discipline after + decrementing the tty count variable; but set the + TTY_CLOSING flag so that we know that this tty structure + isn't long for this world. + + * tty_io.c (init_dev): Add sanity code to check to see if + TTY_CLOSING is set on a tty structure; if so, something + bad has happened (probably a line discipline close blocked + when it shouldn't have; so do a kernel printk and then + return an error). + +Wed Apr 26 10:23:44 1995 Theodore Y. Ts'o + + * tty_io.c (release_dev): Try to shutdown the line discipline + *before* decrementing the tty count variable; this removes + a potential race condition which occurs when the line + discipline close blocks, and another process then tries + open the same serial port. + + * serial.c (rs_hangup): When hanging up, flush the output buffer + before shutting down the UART. Otherwise the line + discipline close blocks waiting for the characters to get + flushed, which never happens until the serial port gets reused. + +Wed Apr 12 08:06:16 1995 Theodore Y. Ts'o + + * serial.c (do_serial_hangup, do_softint, check_modem_status, + rs_init): Hangups are now scheduled via a separate tqueue + structure in the async_struct structure, tqueue_hangup. + This task is pushed on to the tq_schedule queue, so that + it is processed synchronously by the scheduler. + +Sat Feb 18 12:13:51 1995 Theodore Y. Ts'o (tytso@rt-11) + + * tty_io.c (disassociate_ctty, tty_open, tty_ioctl): Clear + current->tty_old_pgrp field when a session leader + acquires a controlling tty, and after a session leader + has disassociated from a controlling tty. + +Fri Feb 17 09:34:09 1995 Theodore Y. Ts'o (tytso@rt-11) + + * serial.c (rs_interrupt_single, rs_interrupt, rs_interrupt_multi): + Change the number of passes made from 64 to be 256, + configurable with the #define RS_ISR_PASS_LIMIT. + + * serial.c (rs_init, set_serial_info, get_serial_info, rs_close): + Remove support for closing_wait2. Instead, set + tty->closing and rely on the line discipline to prevent + echo wars. + + * n_tty.c (n_tty_receive_char): IEXTEN does not need to be + enabled in order for IXANY to be active. + + If tty->closing is set, then only process XON and XOFF + characters. + +Sun Feb 12 23:57:48 1995 Theodore Y. Ts'o (tytso@rt-11) + + * serial.c (rs_timer): Change the interrupt poll time from 60 + seconds to 10 seconds, configurable with the #define + RS_STROBE_TIME. + + * serial.c (rs_interrupt_multi, startup, shutdown, rs_ioctl, + set_multiport_struct, get_multiport_struct): Add + provisions for a new type of interrupt service routine, + which better supports multiple serial ports on a single + IRQ. + +Sun Feb 5 19:35:11 1995 Theodore Y. Ts'o (tytso@rt-11) + + * tty_ioctl.c (n_tty_ioctl, set_termios, tty_wait_until_sent): + * serial.c (rs_ioctl, rs_close): + * cyclades.c (cy_ioctl, cy_close): + * n_tty.c (n_tty_close): Rename wait_until_sent to + tty_wait_until_sent, so that it's a better name to export + in ksyms.c. + +Sat Feb 4 23:36:20 1995 Theodore Y. Ts'o (tytso@rt-11) + + * serial.c (rs_close): Added missing check for closing_wait2 being + ASYNC_CLOSING_WAIT_NONE. + +Thu Jan 26 09:02:49 1995 Theodore Y. Ts'o (tytso@rt-11) + + * serial.c (rs_init, set_serial_info, get_serial_info, + rs_close): Support close_wait in the serial driver. + This is helpful for slow devices (like serial + plotters) so that their outputs don't get flushed upon + device close. This has to be configurable because + normally we don't want ports to be hung up for long + periods of time during a close when they are not + connected to a device, or the device is powered off. + + The default is to wait 30 seconds; in the case of a + very slow device, the close_wait timeout should be + lengthened. If it is set to 0, the kernel will wait + forever for all of the data to be transmitted. + +Thu Jan 17 01:17:20 1995 Theodore Y. Ts'o (tytso@rt-11) + + * serial.c (startup, change_speed, rs_init): Add support to detect + the StarTech 16650 chip. Treat it as a 16450 for now, + because of its FIFO bugs. + +Thu Jan 5 21:21:57 1995 + + * serial.c: (receive_char): Added counter to prevent infinite loop + when a PCMCIA serial device is ejected. + +Thu Dec 29 17:53:48 1994 + + * tty_io.c (check_tty_count): New procedure which checks + tty->count to make sure that it matches with the number of + open file descriptors which point at the structure. If + the number doesn't match, it prints a warning message. + +Wed Dec 28 15:41:51 1994 + + * tty_io.c (do_tty_hangup, disassociate_ctty): At hangup time, + save the tty's current foreground process group in the + session leader's task structure. When the session leader + terminates, send a SIGHUP, SIGCONT to that process group. + This is not required by POSIX, but it's not prohibited + either, and it appears to be the least intrusive way + to fix a problem that dialup servers have with + orphaned process groups caused by modem hangups. + +Thu Dec 8 14:52:11 1994 + + * serial.c (rs_ioctl): Don't allow most ioctl's if the serial port + isn't initialized. + + * serial.c (rs_close): Don't clear the IER if the serial port + isn't initialized. + + * serial.c (block_til_ready): Don't try to block on the dialin + port if the serial port isn't initialized. + +Wed Dec 7 10:48:30 1994 Si Park (si@wimpol.demon.co.uk) + * tty_io.c (tty_register_driver): Fix bug when linking onto + the tty_drivers list. We now test that there are elements + already on the list before setting the back link from the + first element to the new driver. + + * tty_io.c (tty_unregister_driver): Fix bug in unlinking the + specified driver from the tty_drivers list. We were not + setting the back link correctly. This used to result in + a dangling back link pointer and cause panics on the next + call to get_tty_driver(). + +Tue Nov 29 10:21:09 1994 Theodore Y. Ts'o (tytso@rt-11) + + * tty_io.c (tty_unregister_driver): Fix bug in + tty_unregister_driver where the pointer to the refcount is + tested, instead of the refcount itself. This caused + tty_unregister_driver to always return EBUSY. + +Sat Nov 26 11:59:24 1994 Theodore Y. Ts'o (tytso@rt-11) + + * tty_io.c (tty_ioctl): Add support for the new ioctl + TIOCTTYGSTRUCT, which allow a kernel debugging program + direct read access to the tty and tty_driver structures. + +Fri Nov 25 17:26:22 1994 Theodore Y. Ts'o (tytso@rt-11) + + * serial.c (rs_set_termios): Don't wake up processes blocked in + open when the CLOCAL flag changes, since a blocking + open only samples the CLOCAL flag once when it blocks, + and doesn't check it again. (n.b. FreeBSD has a + different behavior for blocking opens; it's not clear + whether Linux or FreeBSD's interpretation is correct. + POSIX doesn't give clear guidance on this issue, so + this may change in the future....) + + * serial.c (block_til_ready): Use the correct termios structure to + check the CLOCAL flag. If the cuaXX device is active, + then check the saved termios for the ttySXX device. + Otherwise, use the currently active termios structure. + +Sun Nov 6 21:05:44 1994 Theodore Y. Ts'o (tytso@rt-11) + + * serial.c (change_speed): Add support for direct access of + 57,600 and 115,200 bps. + +Wed Nov 2 10:32:36 1994 Theodore Y. Ts'o (tytso@rt-11) + + * n_tty.c (n_tty_receive_room): Only allow excess characters + through if we are in ICANON mode *and* there are other no + pending lines in the buffer. Otherwise cut and paste over + 4k breaks. + +Sat Oct 29 18:17:34 1994 Theodore Y. Ts'o (tytso@rt-11) + + * serial.c (rs_ioctl, get_lsr_info): Added patch suggested by Arne + Riiber so that user mode programs can tell when the + transmitter shift register is empty. + +Thu Oct 27 23:14:29 1994 Theodore Y. Ts'o (tytso@rt-11) + + * tty_ioctl.c (wait_until_sent): Added debugging printk statements + (under the #ifdef TTY_DEBUG_WAIT_UNTIL_SENT) + + * serial.c (rs_interrupt, rs_interrupt_single, receive_chars, + change_speed, rs_close): rs_close now disables receiver + interrupts when closing the serial port. This allows the + serial port to close quickly when Linux and a modem (or a + mouse) are engaged in an echo war; when closing the serial + port, we now first stop listening to incoming characters, + and *then* wait for the transmit buffer to drain. + + In order to make this change, the info->read_status_mask + is now used to control what bits of the line status + register are looked at in the interrupt routine in all + cases; previously it was only used in receive_chars to + select a few of the status bits. + +Mon Oct 24 23:36:21 1994 Theodore Y. Ts'o (tytso@rt-11) + + * serial.c (rs_close): Add a timeout to the transmitter flush + loop; this is just a sanity check in case we have flaky + (or non-existent-but-configured-by-the-user) hardware. + +Fri Oct 21 09:37:23 1994 Theodore Y. Ts'o (tytso@rt-11) + + * tty_io.c (tty_fasync): When asynchronous I/O is enabled, if the + process or process group has not be specified yet, set it + to be the tty's process group, or if that is not yet set, + to the current process's pid. + +Thu Oct 20 23:17:28 1994 Theodore Y. Ts'o (tytso@rt-11) + + * n_tty.c (n_tty_receive_room): If we are doing input + canonicalization, let as many characters through as + possible, so that the excess characters can be "beeped". + +Tue Oct 18 10:02:43 1994 Theodore Y. Ts'o (tytso@rt-11) + + * serial.c (rs_start): Removed an incorrect '!' that was + preventing transmit interrupts from being re-enabled in + rs_start(). Fortunately in most cases it would be + re-enabled elsewhere, but this still should be fixed + correctly. + +Sun Oct 9 23:46:03 1994 Theodore Y. Ts'o (tytso@rt-11) + + * tty_io.c (do_tty_hangup): If the tty driver flags + TTY_DRIVER_RESET_TERMIOS is set, then reset the termios + settings back to the driver's initial configuration. This + allows the termios settings to be reset even if a process + has hung up file descriptors keeping a pty's termios from + being freed and reset. + + * tty_io.c (release_dev): Fix memory leak. The pty's other + termios structure should also be freed. + + * serial.c (rs_close, shutdown): Change how we wait for the + transmitter to completely drain before shutting down the + serial port. We now do it by scheduling in another + process instead of busy looping with the interrupts turned + on. This may eliminate some race condition problems that + some people seem to be reporting. + +Sun Sep 25 14:18:14 1994 Theodore Y. Ts'o (tytso@rt-11) + + * tty_io.c (release_dev): When freeing a tty make sure that both + the tty and the o_tty (if present) aren't a process's + controlling tty. (Previously, we only checked the tty.) + + * serial.c (change_speed): Only enable the Modem Status + Interrupt for a port if CLOCAL is not set or CRTSCTS + is set. If we're not checking the carrier detect and + CTS line, there's no point in enabling the modem + status interrupt. This will save spurious interrupts + from slowing down systems who have terminals that + don't support either line. (Of course, if you want + only one of CD and CTS support, you will need a + properly wired serial cable.) + +Thu Sep 22 08:32:48 1994 Theodore Y. Ts'o (tytso@rt-11) + + * tty_io.c (do_SAK): Return if tty is null. + + * tty_io.c (_tty_name): Return "NULL tty" if the passed in tty is + NULL. + +Sat Sep 17 13:19:25 1994 Theodore Y. Ts'o (tytso@rt-11) + + * tty_ioctl.c (n_tty_ioctl): Fix TIOCGLCKTRMIOS and + TIOCSLCKTRMIOS, which were totally broken. Remove + extra indirection from argument; it should be a struct + termios *, not a struct termios **. + &real_tty->termios_locked should have been + real_tty->termios_locked. This caused us to be + reading and writing the termios_locked structure to + random places in kernel memory. + + * tty_io.c (release_dev): Oops! Forgot to delete a critical kfree + of the locked_termios. This leaves the locked_termios + structure pointed at a freed object. + +Fri Sep 16 08:13:25 1994 Theodore Y. Ts'o (tytso@rt-11) + + * tty_io.c (tty_open): Don't check for an exclusive open until + after the device specific open routine has been called. + Otherwise, the serial device ref counting will be screwed + up. + + * serial.c (rs_open, block_til_ready): Don't set termios structure + until after block_til_ready has returned successfully. + Modify block_til_ready to check the normal_termios + structure directly, so it doesn't rely on termios being + set before it's called. + +Thu Sep 15 23:34:01 1994 Theodore Y. Ts'o (tytso@rt-11) + + * serial.c (rs_close): Turn off interrupts during rs_close() to + prevent a race condition with the hangup code (which + runs during a software interrupt). + + * tty_io.c (release_dev): Don't free the locked_termios structure; + its state must be retained across device opens. + + + * tty_io.c (tty_unregister_driver): Added function to unregister a + tty driver. (For loadable device drivers.) + + diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig new file mode 100644 index 000000000000..096a1202ea07 --- /dev/null +++ b/drivers/char/Kconfig @@ -0,0 +1,988 @@ +# +# Character device configuration +# + +menu "Character devices" + +config VT + bool "Virtual terminal" if EMBEDDED + select INPUT + default y if !VIOCONS + ---help--- + If you say Y here, you will get support for terminal devices with + display and keyboard devices. These are called "virtual" because you + can run several virtual terminals (also called virtual consoles) on + one physical terminal. This is rather useful, for example one + virtual terminal can collect system messages and warnings, another + one can be used for a text-mode user session, and a third could run + an X session, all in parallel. Switching between virtual terminals + is done with certain key combinations, usually Alt-. + + The setterm command ("man setterm") can be used to change the + properties (such as colors or beeping) of a virtual terminal. The + man page console_codes(4) ("man console_codes") contains the special + character sequences that can be used to change those properties + directly. The fonts used on virtual terminals can be changed with + the setfont ("man setfont") command and the key bindings are defined + with the loadkeys ("man loadkeys") command. + + You need at least one virtual terminal device in order to make use + of your keyboard and monitor. Therefore, only people configuring an + embedded system would want to say N here in order to save some + memory; the only way to log into such a system is then via a serial + or network connection. + + If unsure, say Y, or else you won't be able to do much with your new + shiny Linux system :-) + +config VT_CONSOLE + bool "Support for console on virtual terminal" if EMBEDDED + depends on VT + default y + ---help--- + The system console is the device which receives all kernel messages + and warnings and which allows logins in single user mode. If you + answer Y here, a virtual terminal (the device used to interact with + a physical terminal) can be used as system console. This is the most + common mode of operations, so you should say Y here unless you want + the kernel messages be output only to a serial port (in which case + you should say Y to "Console on serial port", below). + + If you do say Y here, by default the currently visible virtual + terminal (/dev/tty0) will be used as system console. You can change + that with a kernel command line option such as "console=tty3" which + would use the third virtual terminal as system console. (Try "man + bootparam" or see the documentation of your boot loader (lilo or + loadlin) about how to pass options to the kernel at boot time.) + + If unsure, say Y. + +config HW_CONSOLE + bool + depends on VT && !S390 && !UML + default y + +config SERIAL_NONSTANDARD + bool "Non-standard serial port support" + ---help--- + Say Y here if you have any non-standard serial boards -- boards + which aren't supported using the standard "dumb" serial driver. + This includes intelligent serial boards such as Cyclades, + Digiboards, etc. These are usually used for systems that need many + serial ports because they serve many terminals or dial-in + connections. + + Note that the answer to this question won't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about non-standard serial boards. + + Most people can say N here. + +config COMPUTONE + tristate "Computone IntelliPort Plus serial support" + depends on SERIAL_NONSTANDARD && BROKEN_ON_SMP + ---help--- + This driver supports the entire family of Intelliport II/Plus + controllers with the exception of the MicroChannel controllers and + products previous to the Intelliport II. These are multiport cards, + which give you many serial ports. You would need something like this + to connect more than two modems to your Linux box, for instance in + order to become a dial-in server. If you have a card like that, say + Y here and read . + + To compile this driver as modules, choose M here: the + modules will be called ip2 and ip2main. + +config ROCKETPORT + tristate "Comtrol RocketPort support" + depends on SERIAL_NONSTANDARD + help + This driver supports Comtrol RocketPort and RocketModem PCI boards. + These boards provide 2, 4, 8, 16, or 32 high-speed serial ports or + modems. For information about the RocketPort/RocketModem boards + and this driver read . + + To compile this driver as a module, choose M here: the + module will be called rocket. + + If you want to compile this driver into the kernel, say Y here. If + you don't have a Comtrol RocketPort/RocketModem card installed, say N. + +config CYCLADES + tristate "Cyclades async mux support" + depends on SERIAL_NONSTANDARD + ---help--- + This driver supports Cyclades Z and Y multiserial boards. + You would need something like this to connect more than two modems to + your Linux box, for instance in order to become a dial-in server. + + For information about the Cyclades-Z card, read + . + + To compile this driver as a module, choose M here: the + module will be called cyclades. + + If you haven't heard about it, it's safe to say N. + +config CYZ_INTR + bool "Cyclades-Z interrupt mode operation (EXPERIMENTAL)" + depends on EXPERIMENTAL && CYCLADES + help + The Cyclades-Z family of multiport cards allows 2 (two) driver op + modes: polling and interrupt. In polling mode, the driver will check + the status of the Cyclades-Z ports every certain amount of time + (which is called polling cycle and is configurable). In interrupt + mode, it will use an interrupt line (IRQ) in order to check the + status of the Cyclades-Z ports. The default op mode is polling. If + unsure, say N. + +config DIGIEPCA + tristate "Digiboard Intelligent Async Support" + depends on SERIAL_NONSTANDARD && BROKEN_ON_SMP + ---help--- + This is a driver for Digi International's Xx, Xeve, and Xem series + of cards which provide multiple serial ports. You would need + something like this to connect more than two modems to your Linux + box, for instance in order to become a dial-in server. This driver + supports the original PC (ISA) boards as well as PCI, and EISA. If + you have a card like this, say Y here and read the file + . + + To compile this driver as a module, choose M here: the + module will be called epca. + +config ESPSERIAL + tristate "Hayes ESP serial port support" + depends on SERIAL_NONSTANDARD && ISA && BROKEN_ON_SMP + help + This is a driver which supports Hayes ESP serial ports. Both single + port cards and multiport cards are supported. Make sure to read + . + + To compile this driver as a module, choose M here: the + module will be called esp. + + If unsure, say N. + +config MOXA_INTELLIO + tristate "Moxa Intellio support" + depends on SERIAL_NONSTANDARD && BROKEN_ON_SMP + help + Say Y here if you have a Moxa Intellio multiport serial card. + + To compile this driver as a module, choose M here: the + module will be called moxa. + +config MOXA_SMARTIO + tristate "Moxa SmartIO support" + depends on SERIAL_NONSTANDARD + help + Say Y here if you have a Moxa SmartIO multiport serial card. + + This driver can also be built as a module ( = code which can be + inserted in and removed from the running kernel whenever you want). + The module will be called mxser. If you want to do that, say M + here. + +config ISI + tristate "Multi-Tech multiport card support (EXPERIMENTAL)" + depends on SERIAL_NONSTANDARD + help + This is a driver for the Multi-Tech cards which provide several + serial ports. The driver is experimental and can currently only be + built as a module. The module will be called isicom. + If you want to do that, choose M here. + +config SYNCLINK + tristate "Microgate SyncLink card support" + depends on SERIAL_NONSTANDARD && PCI + help + Provides support for the SyncLink ISA and PCI multiprotocol serial + adapters. These adapters support asynchronous and HDLC bit + synchronous communication up to 10Mbps (PCI adapter). + + This driver can only be built as a module ( = code which can be + inserted in and removed from the running kernel whenever you want). + The module will be called synclink. If you want to do that, say M + here. + +config SYNCLINKMP + tristate "SyncLink Multiport support" + depends on SERIAL_NONSTANDARD + help + Enable support for the SyncLink Multiport (2 or 4 ports) + serial adapter, running asynchronous and HDLC communications up + to 2.048Mbps. Each ports is independently selectable for + RS-232, V.35, RS-449, RS-530, and X.21 + + This driver may be built as a module ( = code which can be + inserted in and removed from the running kernel whenever you want). + The module will be called synclinkmp. If you want to do that, say M + here. + +config N_HDLC + tristate "HDLC line discipline support" + depends on SERIAL_NONSTANDARD + help + Allows synchronous HDLC communications with tty device drivers that + support synchronous HDLC such as the Microgate SyncLink adapter. + + This driver can only be built as a module ( = code which can be + inserted in and removed from the running kernel whenever you want). + The module will be called n_hdlc. If you want to do that, say M + here. + +config RISCOM8 + tristate "SDL RISCom/8 card support" + depends on SERIAL_NONSTANDARD && BROKEN_ON_SMP + help + This is a driver for the SDL Communications RISCom/8 multiport card, + which gives you many serial ports. You would need something like + this to connect more than two modems to your Linux box, for instance + in order to become a dial-in server. If you have a card like that, + say Y here and read the file . + + Also it's possible to say M here and compile this driver as kernel + loadable module; the module will be called riscom8. + +config SPECIALIX + tristate "Specialix IO8+ card support" + depends on SERIAL_NONSTANDARD + help + This is a driver for the Specialix IO8+ multiport card (both the + ISA and the PCI version) which gives you many serial ports. You + would need something like this to connect more than two modems to + your Linux box, for instance in order to become a dial-in server. + + If you have a card like that, say Y here and read the file + . Also it's possible to say M here + and compile this driver as kernel loadable module which will be + called specialix. + +config SPECIALIX_RTSCTS + bool "Specialix DTR/RTS pin is RTS" + depends on SPECIALIX + help + The Specialix IO8+ card can only support either RTS or DTR. If you + say N here, the driver will use the pin as "DTR" when the tty is in + software handshake mode. If you say Y here or hardware handshake is + on, it will always be RTS. Read the file + for more information. + +config SX + tristate "Specialix SX (and SI) card support" + depends on SERIAL_NONSTANDARD + help + This is a driver for the SX and SI multiport serial cards. + Please read the file for details. + + This driver can only be built as a module ( = code which can be + inserted in and removed from the running kernel whenever you want). + The module will be called sx. If you want to do that, say M here. + +config RIO + tristate "Specialix RIO system support" + depends on SERIAL_NONSTANDARD && BROKEN_ON_SMP + help + This is a driver for the Specialix RIO, a smart serial card which + drives an outboard box that can support up to 128 ports. Product + information is at . + There are both ISA and PCI versions. + +config RIO_OLDPCI + bool "Support really old RIO/PCI cards" + depends on RIO + help + Older RIO PCI cards need some initialization-time configuration to + determine the IRQ and some control addresses. If you have a RIO and + this doesn't seem to work, try setting this to Y. + +config STALDRV + bool "Stallion multiport serial support" + depends on SERIAL_NONSTANDARD + help + Stallion cards give you many serial ports. You would need something + like this to connect more than two modems to your Linux box, for + instance in order to become a dial-in server. If you say Y here, + you will be asked for your specific card model in the next + questions. Make sure to read in + this case. If you have never heard about all this, it's safe to + say N. + +config STALLION + tristate "Stallion EasyIO or EC8/32 support" + depends on STALDRV && BROKEN_ON_SMP + help + If you have an EasyIO or EasyConnection 8/32 multiport Stallion + card, then this is for you; say Y. Make sure to read + . + + To compile this driver as a module, choose M here: the + module will be called stallion. + +config ISTALLION + tristate "Stallion EC8/64, ONboard, Brumby support" + depends on STALDRV && BROKEN_ON_SMP + help + If you have an EasyConnection 8/64, ONboard, Brumby or Stallion + serial multiport card, say Y here. Make sure to read + . + + To compile this driver as a module, choose M here: the + module will be called istallion. + +config AU1000_UART + bool "Enable Au1000 UART Support" + depends on SERIAL_NONSTANDARD && MIPS + help + If you have an Alchemy AU1000 processor (MIPS based) and you want + to use serial ports, say Y. Otherwise, say N. + +config AU1000_SERIAL_CONSOLE + bool "Enable Au1000 serial console" + depends on AU1000_UART + help + If you have an Alchemy AU1000 processor (MIPS based) and you want + to use a console on a serial port, say Y. Otherwise, say N. + +config QTRONIX_KEYBOARD + bool "Enable Qtronix 990P Keyboard Support" + depends on IT8712 + help + Images of Qtronix keyboards are at + . + +config IT8172_CIR + bool + depends on QTRONIX_KEYBOARD + default y + +config IT8172_SCR0 + bool "Enable Smart Card Reader 0 Support " + depends on IT8712 + help + Say Y here to support smart-card reader 0 (SCR0) on the Integrated + Technology Express, Inc. ITE8172 SBC. Vendor page at + ; picture of the + board at . + +config IT8172_SCR1 + bool "Enable Smart Card Reader 1 Support " + depends on IT8712 + help + Say Y here to support smart-card reader 1 (SCR1) on the Integrated + Technology Express, Inc. ITE8172 SBC. Vendor page at + ; picture of the + board at . + +config A2232 + tristate "Commodore A2232 serial support (EXPERIMENTAL)" + depends on EXPERIMENTAL && ZORRO && BROKEN_ON_SMP + ---help--- + This option supports the 2232 7-port serial card shipped with the + Amiga 2000 and other Zorro-bus machines, dating from 1989. At + a max of 19,200 bps, the ports are served by a 6551 ACIA UART chip + each, plus a 8520 CIA, and a master 6502 CPU and buffer as well. The + ports were connected with 8 pin DIN connectors on the card bracket, + for which 8 pin to DB25 adapters were supplied. The card also had + jumpers internally to toggle various pinning configurations. + + This driver can be built as a module; but then "generic_serial" + will also be built as a module. This has to be loaded before + "ser_a2232". If you want to do this, answer M here. + +config SGI_SNSC + bool "SGI Altix system controller communication support" + depends on (IA64_SGI_SN2 || IA64_GENERIC) + help + If you have an SGI Altix and you want to enable system + controller communication from user space (you want this!), + say Y. Otherwise, say N. + +source "drivers/serial/Kconfig" + +config UNIX98_PTYS + bool "Unix98 PTY support" if EMBEDDED + default y + ---help--- + A pseudo terminal (PTY) is a software device consisting of two + halves: a master and a slave. The slave device behaves identical to + a physical terminal; the master device is used by a process to + read data from and write data to the slave, thereby emulating a + terminal. Typical programs for the master side are telnet servers + and xterms. + + Linux has traditionally used the BSD-like names /dev/ptyxx for + masters and /dev/ttyxx for slaves of pseudo terminals. This scheme + has a number of problems. The GNU C library glibc 2.1 and later, + however, supports the Unix98 naming standard: in order to acquire a + pseudo terminal, a process opens /dev/ptmx; the number of the pseudo + terminal is then made available to the process and the pseudo + terminal slave can be accessed as /dev/pts/. What was + traditionally /dev/ttyp2 will then be /dev/pts/2, for example. + + All modern Linux systems use the Unix98 ptys. Say Y unless + you're on an embedded system and want to conserve memory. + +config LEGACY_PTYS + bool "Legacy (BSD) PTY support" + default y + ---help--- + A pseudo terminal (PTY) is a software device consisting of two + halves: a master and a slave. The slave device behaves identical to + a physical terminal; the master device is used by a process to + read data from and write data to the slave, thereby emulating a + terminal. Typical programs for the master side are telnet servers + and xterms. + + Linux has traditionally used the BSD-like names /dev/ptyxx + for masters and /dev/ttyxx for slaves of pseudo + terminals. This scheme has a number of problems, including + security. This option enables these legacy devices; on most + systems, it is safe to say N. + + +config LEGACY_PTY_COUNT + int "Maximum number of legacy PTY in use" + depends on LEGACY_PTYS + range 1 256 + default "256" + ---help--- + The maximum number of legacy PTYs that can be used at any one time. + The default is 256, and should be more than enough. Embedded + systems may want to reduce this to save memory. + + When not in use, each legacy PTY occupies 12 bytes on 32-bit + architectures and 24 bytes on 64-bit architectures. + +config PRINTER + tristate "Parallel printer support" + depends on PARPORT + ---help--- + If you intend to attach a printer to the parallel port of your Linux + box (as opposed to using a serial printer; if the connector at the + printer has 9 or 25 holes ["female"], then it's serial), say Y. + Also read the Printing-HOWTO, available from + . + + It is possible to share one parallel port among several devices + (e.g. printer and ZIP drive) and it is safe to compile the + corresponding drivers into the kernel. + + To compile this driver as a module, choose M here and read + . The module will be called lp. + + If you have several parallel ports, you can specify which ports to + use with the "lp" kernel command line option. (Try "man bootparam" + or see the documentation of your boot loader (lilo or loadlin) about + how to pass options to the kernel at boot time.) The syntax of the + "lp" command line option can be found in . + + If you have more than 8 printers, you need to increase the LP_NO + macro in lp.c and the PARPORT_MAX macro in parport.h. + +config LP_CONSOLE + bool "Support for console on line printer" + depends on PRINTER + ---help--- + If you want kernel messages to be printed out as they occur, you + can have a console on the printer. This option adds support for + doing that; to actually get it to happen you need to pass the + option "console=lp0" to the kernel at boot time. + + If the printer is out of paper (or off, or unplugged, or too + busy..) the kernel will stall until the printer is ready again. + By defining CONSOLE_LP_STRICT to 0 (at your own risk) you + can make the kernel continue when this happens, + but it'll lose the kernel messages. + + If unsure, say N. + +config PPDEV + tristate "Support for user-space parallel port device drivers" + depends on PARPORT + ---help--- + Saying Y to this adds support for /dev/parport device nodes. This + is needed for programs that want portable access to the parallel + port, for instance deviceid (which displays Plug-and-Play device + IDs). + + This is the parallel port equivalent of SCSI generic support (sg). + It is safe to say N to this -- it is not needed for normal printing + or parallel port CD-ROM/disk support. + + To compile this driver as a module, choose M here: the + module will be called ppdev. + + If unsure, say N. + +config TIPAR + tristate "Texas Instruments parallel link cable support" + depends on PARPORT + ---help--- + If you own a Texas Instruments graphing calculator and use a + parallel link cable, then you might be interested in this driver. + + If you enable this driver, you will be able to communicate with + your calculator through a set of device nodes under /dev. The + main advantage of this driver is that you don't have to be root + to use this precise link cable (depending on the permissions on + the device nodes, though). + + To compile this driver as a module, choose M here: the + module will be called tipar. + + If you don't know what a parallel link cable is or what a Texas + Instruments graphing calculator is, then you probably don't need this + driver. + + If unsure, say N. + +config HVC_CONSOLE + bool "pSeries Hypervisor Virtual Console support" + depends on PPC_PSERIES + help + pSeries machines when partitioned support a hypervisor virtual + console. This driver allows each pSeries partition to have a console + which is accessed via the HMC. + +config HVCS + tristate "IBM Hypervisor Virtual Console Server support" + depends on PPC_PSERIES + help + Partitionable IBM Power5 ppc64 machines allow hosting of + firmware virtual consoles from one Linux partition by + another Linux partition. This driver allows console data + from Linux partitions to be accessed through TTY device + interfaces in the device tree of a Linux partition running + this driver. + + To compile this driver as a module, choose M here: the + module will be called hvcs.ko. Additionally, this module + will depend on arch specific APIs exported from hvcserver.ko + which will also be compiled when this driver is built as a + module. + +source "drivers/char/ipmi/Kconfig" + +source "drivers/char/watchdog/Kconfig" + +config DS1620 + tristate "NetWinder thermometer support" + depends on ARCH_NETWINDER + help + Say Y here to include support for the thermal management hardware + found in the NetWinder. This driver allows the user to control the + temperature set points and to read the current temperature. + + It is also possible to say M here to build it as a module (ds1620) + It is recommended to be used on a NetWinder, but it is not a + necessity. + +config NWBUTTON + tristate "NetWinder Button" + depends on ARCH_NETWINDER + ---help--- + If you say Y here and create a character device node /dev/nwbutton + with major and minor numbers 10 and 158 ("man mknod"), then every + time the orange button is pressed a number of times, the number of + times the button was pressed will be written to that device. + + This is most useful for applications, as yet unwritten, which + perform actions based on how many times the button is pressed in a + row. + + Do not hold the button down for too long, as the driver does not + alter the behaviour of the hardware reset circuitry attached to the + button; it will still execute a hard reset if the button is held + down for longer than approximately five seconds. + + To compile this driver as a module, choose M here: the + module will be called nwbutton. + + Most people will answer Y to this question and "Reboot Using Button" + below to be able to initiate a system shutdown from the button. + +config NWBUTTON_REBOOT + bool "Reboot Using Button" + depends on NWBUTTON + help + If you say Y here, then you will be able to initiate a system + shutdown and reboot by pressing the orange button a number of times. + The number of presses to initiate the shutdown is two by default, + but this can be altered by modifying the value of NUM_PRESSES_REBOOT + in nwbutton.h and recompiling the driver or, if you compile the + driver as a module, you can specify the number of presses at load + time with "insmod button reboot_count=". + +config NWFLASH + tristate "NetWinder flash support" + depends on ARCH_NETWINDER + ---help--- + If you say Y here and create a character device /dev/flash with + major 10 and minor 160 you can manipulate the flash ROM containing + the NetWinder firmware. Be careful as accidentally overwriting the + flash contents can render your computer unbootable. On no account + allow random users access to this device. :-) + + To compile this driver as a module, choose M here: the + module will be called nwflash. + + If you're not sure, say N. + +config HW_RANDOM + tristate "Intel/AMD/VIA HW Random Number Generator support" + depends on (X86 || IA64) && PCI + ---help--- + This driver provides kernel-side support for the Random Number + Generator hardware found on Intel i8xx-based motherboards, + AMD 76x-based motherboards, and Via Nehemiah CPUs. + + Provides a character driver, used to read() entropy data. + + To compile this driver as a module, choose M here: the + module will be called hw_random. + + If unsure, say N. + +config NVRAM + tristate "/dev/nvram support" + depends on ATARI || X86 || X86_64 || ARM || GENERIC_NVRAM + ---help--- + If you say Y here and create a character special file /dev/nvram + with major number 10 and minor number 144 using mknod ("man mknod"), + you get read and write access to the extra bytes of non-volatile + memory in the real time clock (RTC), which is contained in every PC + and most Ataris. The actual number of bytes varies, depending on the + nvram in the system, but is usually 114 (128-14 for the RTC). + + This memory is conventionally called "CMOS RAM" on PCs and "NVRAM" + on Ataris. /dev/nvram may be used to view settings there, or to + change them (with some utility). It could also be used to frequently + save a few bits of very important data that may not be lost over + power-off and for which writing to disk is too insecure. Note + however that most NVRAM space in a PC belongs to the BIOS and you + should NEVER idly tamper with it. See Ralf Brown's interrupt list + for a guide to the use of CMOS bytes by your BIOS. + + On Atari machines, /dev/nvram is always configured and does not need + to be selected. + + To compile this driver as a module, choose M here: the + module will be called nvram. + +config RTC + tristate "Enhanced Real Time Clock Support" + depends on !PPC32 && !PARISC && !IA64 && !M68K + ---help--- + If you say Y here and create a character special file /dev/rtc with + major number 10 and minor number 135 using mknod ("man mknod"), you + will get access to the real time clock (or hardware clock) built + into your computer. + + Every PC has such a clock built in. It can be used to generate + signals from as low as 1Hz up to 8192Hz, and can also be used + as a 24 hour alarm. It reports status information via the file + /proc/driver/rtc and its behaviour is set by various ioctls on + /dev/rtc. + + If you run Linux on a multiprocessor machine and said Y to + "Symmetric Multi Processing" above, you should say Y here to read + and set the RTC in an SMP compatible fashion. + + If you think you have a use for such a device (such as periodic data + sampling), then say Y here, and read + for details. + + To compile this driver as a module, choose M here: the + module will be called rtc. + +config SGI_DS1286 + tristate "SGI DS1286 RTC support" + depends on SGI_IP22 + help + If you say Y here and create a character special file /dev/rtc with + major number 10 and minor number 135 using mknod ("man mknod"), you + will get access to the real time clock built into your computer. + Every SGI has such a clock built in. It reports status information + via the file /proc/rtc and its behaviour is set by various ioctls on + /dev/rtc. + +config SGI_IP27_RTC + bool "SGI M48T35 RTC support" + depends on SGI_IP27 + help + If you say Y here and create a character special file /dev/rtc with + major number 10 and minor number 135 using mknod ("man mknod"), you + will get access to the real time clock built into your computer. + Every SGI has such a clock built in. It reports status information + via the file /proc/rtc and its behaviour is set by various ioctls on + /dev/rtc. + +config GEN_RTC + tristate "Generic /dev/rtc emulation" + depends on RTC!=y && !IA64 && !ARM + ---help--- + If you say Y here and create a character special file /dev/rtc with + major number 10 and minor number 135 using mknod ("man mknod"), you + will get access to the real time clock (or hardware clock) built + into your computer. + + It reports status information via the file /proc/driver/rtc and its + behaviour is set by various ioctls on /dev/rtc. If you enable the + "extended RTC operation" below it will also provide an emulation + for RTC_UIE which is required by some programs and may improve + precision in some cases. + + To compile this driver as a module, choose M here: the + module will be called genrtc. + +config GEN_RTC_X + bool "Extended RTC operation" + depends on GEN_RTC + help + Provides an emulation for RTC_UIE which is required by some programs + and may improve precision of the generic RTC support in some cases. + +config EFI_RTC + bool "EFI Real Time Clock Services" + depends on IA64 + +config DS1302 + tristate "DS1302 RTC support" + depends on M32R && (PLAT_M32700UT || PLAT_OPSPUT) + help + If you say Y here and create a character special file /dev/rtc with + major number 121 and minor number 0 using mknod ("man mknod"), you + will get access to the real time clock (or hardware clock) built + into your computer. + +config S3C2410_RTC + bool "S3C2410 RTC Driver" + depends on ARCH_S3C2410 + help + RTC (Realtime Clock) driver for the clock inbuilt into the + Samsung S3C2410. This can provide periodic interrupt rates + from 1Hz to 64Hz for user programs, and wakeup from Alarm. + +config RTC_VR41XX + tristate "NEC VR4100 series Real Time Clock Support" + depends on CPU_VR41XX + +config COBALT_LCD + bool "Support for Cobalt LCD" + depends on MIPS_COBALT + help + This option enables support for the LCD display and buttons found + on Cobalt systems through a misc device. + +config DTLK + tristate "Double Talk PC internal speech card support" + help + This driver is for the DoubleTalk PC, a speech synthesizer + manufactured by RC Systems (). It is also + called the `internal DoubleTalk'. + + To compile this driver as a module, choose M here: the + module will be called dtlk. + +config R3964 + tristate "Siemens R3964 line discipline" + ---help--- + This driver allows synchronous communication with devices using the + Siemens R3964 packet protocol. Unless you are dealing with special + hardware like PLCs, you are unlikely to need this. + + To compile this driver as a module, choose M here: the + module will be called n_r3964. + + If unsure, say N. + +config APPLICOM + tristate "Applicom intelligent fieldbus card support" + depends on PCI + ---help--- + This driver provides the kernel-side support for the intelligent + fieldbus cards made by Applicom International. More information + about these cards can be found on the WWW at the address + , or by email from David Woodhouse + . + + To compile this driver as a module, choose M here: the + module will be called applicom. + + If unsure, say N. + +config SONYPI + tristate "Sony Vaio Programmable I/O Control Device support (EXPERIMENTAL)" + depends on EXPERIMENTAL && X86 && PCI && INPUT && !64BIT + ---help--- + This driver enables access to the Sony Programmable I/O Control + Device which can be found in many (all ?) Sony Vaio laptops. + + If you have one of those laptops, read + , and say Y or M here. + + To compile this driver as a module, choose M here: the + module will be called sonypi. + +config TANBAC_TB0219 + tristate "TANBAC TB0219 base board support" + depends TANBAC_TB0229 + + +menu "Ftape, the floppy tape device driver" + +config FTAPE + tristate "Ftape (QIC-80/Travan) support" + depends on BROKEN_ON_SMP && (ALPHA || X86) + ---help--- + If you have a tape drive that is connected to your floppy + controller, say Y here. + + Some tape drives (like the Seagate "Tape Store 3200" or the Iomega + "Ditto 3200" or the Exabyte "Eagle TR-3") come with a "high speed" + controller of their own. These drives (and their companion + controllers) are also supported if you say Y here. + + If you have a special controller (such as the CMS FC-10, FC-20, + Mountain Mach-II, or any controller that is based on the Intel 82078 + FDC like the high speed controllers by Seagate and Exabyte and + Iomega's "Ditto Dash") you must configure it by selecting the + appropriate entries from the "Floppy tape controllers" sub-menu + below and possibly modify the default values for the IRQ and DMA + channel and the IO base in ftape's configuration menu. + + If you want to use your floppy tape drive on a PCI-bus based system, + please read the file . + + The ftape kernel driver is also available as a runtime loadable + module. To compile this driver as a module, choose M here: the + module will be called ftape. + + Note that the Ftape-HOWTO is out of date (sorry) and documents the + older version 2.08 of this software but still contains useful + information. There is a web page with more recent documentation at + . This page + always contains the latest release of the ftape driver and useful + information (backup software, ftape related patches and + documentation, FAQ). Note that the file system interface has + changed quite a bit compared to previous versions of ftape. Please + read . + +source "drivers/char/ftape/Kconfig" + +endmenu + +source "drivers/char/agp/Kconfig" + +source "drivers/char/drm/Kconfig" + +source "drivers/char/pcmcia/Kconfig" + +config MWAVE + tristate "ACP Modem (Mwave) support" + depends on X86 + select SERIAL_8250 + ---help--- + The ACP modem (Mwave) for Linux is a WinModem. It is composed of a + kernel driver and a user level application. Together these components + support direct attachment to public switched telephone networks (PSTNs) + and support selected world wide countries. + + This version of the ACP Modem driver supports the IBM Thinkpad 600E, + 600, and 770 that include on board ACP modem hardware. + + The modem also supports the standard communications port interface + (ttySx) and is compatible with the Hayes AT Command Set. + + The user level application needed to use this driver can be found at + the IBM Linux Technology Center (LTC) web site: + . + + If you own one of the above IBM Thinkpads which has the Mwave chipset + in it, say Y. + + To compile this driver as a module, choose M here: the + module will be called mwave. + +config SCx200_GPIO + tristate "NatSemi SCx200 GPIO Support" + depends on SCx200 + help + Give userspace access to the GPIO pins on the National + Semiconductor SCx200 processors. + + If compiled as a module, it will be called scx200_gpio. + +config RAW_DRIVER + tristate "RAW driver (/dev/raw/rawN) (OBSOLETE)" + help + The raw driver permits block devices to be bound to /dev/raw/rawN. + Once bound, I/O against /dev/raw/rawN uses efficient zero-copy I/O. + See the raw(8) manpage for more details. + + The raw driver is deprecated and may be removed from 2.7 + kernels. Applications should simply open the device (eg /dev/hda1) + with the O_DIRECT flag. + +config HPET + bool "HPET - High Precision Event Timer" if (X86 || IA64) + default n + depends on ACPI + help + If you say Y here, you will have a miscdevice named "/dev/hpet/". Each + open selects one of the timers supported by the HPET. The timers are + non-periodioc and/or periodic. + +config HPET_RTC_IRQ + bool "HPET Control RTC IRQ" if !HPET_EMULATE_RTC + default n + depends on HPET + help + If you say Y here, you will disable RTC_IRQ in drivers/char/rtc.c. It + is assumed the platform called hpet_alloc with the RTC IRQ values for + the HPET timers. + +config HPET_MMAP + bool "Allow mmap of HPET" + default y + depends on HPET + help + If you say Y here, user applications will be able to mmap + the HPET registers. + + In some hardware implementations, the page containing HPET + registers may also contain other things that shouldn't be + exposed to the user. If this applies to your hardware, + say N here. + +config MAX_RAW_DEVS + int "Maximum number of RAW devices to support (1-8192)" + depends on RAW_DRIVER + default "256" + help + The maximum number of RAW devices that are supported. + Default is 256. Increase this number in case you need lots of + raw devices. + +config HANGCHECK_TIMER + tristate "Hangcheck timer" + depends on X86_64 || X86 + help + The hangcheck-timer module detects when the system has gone + out to lunch past a certain margin. It can reboot the system + or merely print a warning. + +config MMTIMER + tristate "MMTIMER Memory mapped RTC for SGI Altix" + depends on IA64_GENERIC || IA64_SGI_SN2 + default y + help + The mmtimer device allows direct userspace access to the + Altix system timer. + +source "drivers/char/tpm/Kconfig" + +endmenu + diff --git a/drivers/char/Makefile b/drivers/char/Makefile new file mode 100644 index 000000000000..54ed76af1a47 --- /dev/null +++ b/drivers/char/Makefile @@ -0,0 +1,118 @@ +# +# Makefile for the kernel character device drivers. +# + +# +# This file contains the font map for the default (hardware) font +# +FONTMAPFILE = cp437.uni + +obj-y += mem.o random.o tty_io.o n_tty.o tty_ioctl.o + +obj-$(CONFIG_LEGACY_PTYS) += pty.o +obj-$(CONFIG_UNIX98_PTYS) += pty.o +obj-y += misc.o +obj-$(CONFIG_VT) += vt_ioctl.o vc_screen.o consolemap.o \ + consolemap_deftbl.o selection.o keyboard.o +obj-$(CONFIG_HW_CONSOLE) += vt.o defkeymap.o +obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o +obj-$(CONFIG_ESPSERIAL) += esp.o +obj-$(CONFIG_MVME147_SCC) += generic_serial.o vme_scc.o +obj-$(CONFIG_MVME162_SCC) += generic_serial.o vme_scc.o +obj-$(CONFIG_BVME6000_SCC) += generic_serial.o vme_scc.o +obj-$(CONFIG_ROCKETPORT) += rocket.o +obj-$(CONFIG_SERIAL167) += serial167.o +obj-$(CONFIG_CYCLADES) += cyclades.o +obj-$(CONFIG_STALLION) += stallion.o +obj-$(CONFIG_ISTALLION) += istallion.o +obj-$(CONFIG_DIGIEPCA) += epca.o +obj-$(CONFIG_SPECIALIX) += specialix.o +obj-$(CONFIG_MOXA_INTELLIO) += moxa.o +obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o +obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o +obj-$(CONFIG_MOXA_SMARTIO) += mxser.o +obj-$(CONFIG_COMPUTONE) += ip2.o ip2main.o +obj-$(CONFIG_RISCOM8) += riscom8.o +obj-$(CONFIG_ISI) += isicom.o +obj-$(CONFIG_SYNCLINK) += synclink.o +obj-$(CONFIG_SYNCLINKMP) += synclinkmp.o +obj-$(CONFIG_N_HDLC) += n_hdlc.o +obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o +obj-$(CONFIG_SX) += sx.o generic_serial.o +obj-$(CONFIG_RIO) += rio/ generic_serial.o +obj-$(CONFIG_HVC_CONSOLE) += hvc_console.o hvsi.o +obj-$(CONFIG_RAW_DRIVER) += raw.o +obj-$(CONFIG_SGI_SNSC) += snsc.o +obj-$(CONFIG_MMTIMER) += mmtimer.o +obj-$(CONFIG_VIOCONS) += viocons.o +obj-$(CONFIG_VIOTAPE) += viotape.o +obj-$(CONFIG_HVCS) += hvcs.o + +obj-$(CONFIG_PRINTER) += lp.o +obj-$(CONFIG_TIPAR) += tipar.o + +obj-$(CONFIG_DTLK) += dtlk.o +obj-$(CONFIG_R3964) += n_r3964.o +obj-$(CONFIG_APPLICOM) += applicom.o +obj-$(CONFIG_SONYPI) += sonypi.o +obj-$(CONFIG_RTC) += rtc.o +obj-$(CONFIG_HPET) += hpet.o +obj-$(CONFIG_GEN_RTC) += genrtc.o +obj-$(CONFIG_EFI_RTC) += efirtc.o +obj-$(CONFIG_SGI_DS1286) += ds1286.o +obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o +obj-$(CONFIG_DS1302) += ds1302.o +obj-$(CONFIG_S3C2410_RTC) += s3c2410-rtc.o +obj-$(CONFIG_RTC_VR41XX) += vr41xx_rtc.o +ifeq ($(CONFIG_GENERIC_NVRAM),y) + obj-$(CONFIG_NVRAM) += generic_nvram.o +else + obj-$(CONFIG_NVRAM) += nvram.o +endif +obj-$(CONFIG_TOSHIBA) += toshiba.o +obj-$(CONFIG_I8K) += i8k.o +obj-$(CONFIG_DS1620) += ds1620.o +obj-$(CONFIG_HW_RANDOM) += hw_random.o +obj-$(CONFIG_FTAPE) += ftape/ +obj-$(CONFIG_COBALT_LCD) += lcd.o +obj-$(CONFIG_PPDEV) += ppdev.o +obj-$(CONFIG_NWBUTTON) += nwbutton.o +obj-$(CONFIG_NWFLASH) += nwflash.o +obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o +obj-$(CONFIG_TANBAC_TB0219) += tb0219.o + +obj-$(CONFIG_WATCHDOG) += watchdog/ +obj-$(CONFIG_MWAVE) += mwave/ +obj-$(CONFIG_AGP) += agp/ +obj-$(CONFIG_DRM) += drm/ +obj-$(CONFIG_PCMCIA) += pcmcia/ +obj-$(CONFIG_IPMI_HANDLER) += ipmi/ + +obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o +obj-$(CONFIG_TCG_TPM) += tpm/ +# Files generated that shall be removed upon make clean +clean-files := consolemap_deftbl.c defkeymap.c qtronixmap.c + +quiet_cmd_conmk = CONMK $@ + cmd_conmk = scripts/conmakehash $< > $@ + +$(obj)/consolemap_deftbl.c: $(src)/$(FONTMAPFILE) + $(call cmd,conmk) + +$(obj)/defkeymap.o: $(obj)/defkeymap.c + +$(obj)/qtronixmap.o: $(obj)/qtronixmap.c + +# Uncomment if you're changing the keymap and have an appropriate +# loadkeys version for the map. By default, we'll use the shipped +# versions. +# GENERATE_KEYMAP := 1 + +ifdef GENERATE_KEYMAP + +$(obj)/defkeymap.c $(obj)/qtronixmap.c: $(obj)/%.c: $(src)/%.map + loadkeys --mktable $< > $@.tmp + sed -e 's/^static *//' $@.tmp > $@ + rm $@.tmp + +endif diff --git a/drivers/char/agp/Kconfig b/drivers/char/agp/Kconfig new file mode 100644 index 000000000000..7f8c1b53b754 --- /dev/null +++ b/drivers/char/agp/Kconfig @@ -0,0 +1,171 @@ +config AGP + tristate "/dev/agpgart (AGP Support)" if !GART_IOMMU + depends on ALPHA || IA64 || PPC || X86 + default y if GART_IOMMU + ---help--- + AGP (Accelerated Graphics Port) is a bus system mainly used to + connect graphics cards to the rest of the system. + + If you have an AGP system and you say Y here, it will be possible to + use the AGP features of your 3D rendering video card. This code acts + as a sort of "AGP driver" for the motherboard's chipset. + + If you need more texture memory than you can get with the AGP GART + (theoretically up to 256 MB, but in practice usually 64 or 128 MB + due to kernel allocation issues), you could use PCI accesses + and have up to a couple gigs of texture space. + + Note that this is the only means to have XFree4/GLX use + write-combining with MTRR support on the AGP bus. Without it, OpenGL + direct rendering will be a lot slower but still faster than PIO. + + You should say Y here if you use XFree86 3.3.6 or 4.x and want to + use GLX or DRI. If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called agpgart. + +config AGP_ALI + tristate "ALI chipset support" + depends on AGP && X86 && !X86_64 + ---help--- + This option gives you AGP support for the GLX component of + XFree86 4.x on the following ALi chipsets. The supported chipsets + include M1541, M1621, M1631, M1632, M1641,M1647,and M1651. + For the ALi-chipset question, ALi suggests you refer to + . + + The M1541 chipset can do AGP 1x and 2x, but note that there is an + acknowledged incompatibility with Matrox G200 cards. Due to + timing issues, this chipset cannot do AGP 2x with the G200. + This is a hardware limitation. AGP 1x seems to be fine, though. + + You should say Y here if you use XFree86 3.3.6 or 4.x and want to + use GLX or DRI. If unsure, say N. + +config AGP_ATI + tristate "ATI chipset support" + depends on AGP && X86 && !X86_64 + ---help--- + This option gives you AGP support for the GLX component of + XFree86 4.x on the ATI RadeonIGP family of chipsets. + + You should say Y here if you use XFree86 3.3.6 or 4.x and want to + use GLX or DRI. If unsure, say N. + +config AGP_AMD + tristate "AMD Irongate, 761, and 762 chipset support" + depends on AGP && X86 && !X86_64 + help + This option gives you AGP support for the GLX component of + XFree86 4.x on AMD Irongate, 761, and 762 chipsets. + + You should say Y here if you use XFree86 3.3.6 or 4.x and want to + use GLX or DRI. If unsure, say N. + +config AGP_AMD64 + tristate "AMD Opteron/Athlon64 on-CPU GART support" if !GART_IOMMU + depends on AGP && X86 + default y if GART_IOMMU + help + This option gives you AGP support for the GLX component of + XFree86 4.x using the on-CPU northbridge of the AMD Athlon64/Opteron CPUs. + You still need an external AGP bridge like the AMD 8151, VIA + K8T400M, SiS755. It may also support other AGP bridges when loaded + with agp_try_unsupported=1. + You should say Y here if you use XFree86 3.3.6 or 4.x and want to + use GLX or DRI. If unsure, say Y + +config AGP_INTEL + tristate "Intel 440LX/BX/GX, I8xx and E7x05 chipset support" + depends on AGP && X86 + help + This option gives you AGP support for the GLX component of XFree86 4.x + on Intel 440LX/BX/GX, 815, 820, 830, 840, 845, 850, 860, 875, + E7205 and E7505 chipsets and full support for the 810, 815, 830M, 845G, + 852GM, 855GM, 865G and I915 integrated graphics chipsets. + + You should say Y here if you use XFree86 3.3.6 or 4.x and want to + use GLX or DRI, or if you have any Intel integrated graphics + chipsets. If unsure, say Y. + +config AGP_NVIDIA + tristate "NVIDIA nForce/nForce2 chipset support" + depends on AGP && X86 && !X86_64 + help + This option gives you AGP support for the GLX component of + XFree86 4.x on the following NVIDIA chipsets. The supported chipsets + include nForce and nForce2 + +config AGP_SIS + tristate "SiS chipset support" + depends on AGP && X86 && !X86_64 + help + This option gives you AGP support for the GLX component of + XFree86 4.x on Silicon Integrated Systems [SiS] chipsets. + + Note that 5591/5592 AGP chipsets are NOT supported. + + You should say Y here if you use XFree86 3.3.6 or 4.x and want to + use GLX or DRI. If unsure, say N. + +config AGP_SWORKS + tristate "Serverworks LE/HE chipset support" + depends on AGP && X86 && !X86_64 + help + Say Y here to support the Serverworks AGP card. See + for product descriptions and images. + +config AGP_VIA + tristate "VIA chipset support" + depends on AGP && X86 && !X86_64 + help + This option gives you AGP support for the GLX component of + XFree86 4.x on VIA MVP3/Apollo Pro chipsets. + + You should say Y here if you use XFree86 3.3.6 or 4.x and want to + use GLX or DRI. If unsure, say N. + +config AGP_I460 + tristate "Intel 460GX chipset support" + depends on AGP && (IA64_DIG || IA64_GENERIC) + help + This option gives you AGP GART support for the Intel 460GX chipset + for IA64 processors. + +config AGP_HP_ZX1 + tristate "HP ZX1 chipset AGP support" + depends on AGP && (IA64_HP_ZX1 || IA64_HP_ZX1_SWIOTLB || IA64_GENERIC) + help + This option gives you AGP GART support for the HP ZX1 chipset + for IA64 processors. + +config AGP_ALPHA_CORE + tristate "Alpha AGP support" + depends on AGP && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL) + default AGP + +config AGP_UNINORTH + tristate "Apple UniNorth & U3 AGP support" + depends on AGP && PPC_PMAC + help + This option gives you AGP support for Apple machines with a + UniNorth or U3 (Apple G5) bridge. + +config AGP_EFFICEON + tristate "Transmeta Efficeon support" + depends on AGP && X86 && !X86_64 + help + This option gives you AGP support for the Transmeta Efficeon + series processors with integrated northbridges. + + You should say Y here if you use XFree86 3.3.6 or 4.x and want to + use GLX or DRI. If unsure, say Y. + +config AGP_SGI_TIOCA + tristate "SGI TIO chipset AGP support" + depends on AGP && (IA64_SGI_SN2 || IA64_GENERIC) + help + This option gives you AGP GART support for the SGI TIO chipset + for IA64 processors. + diff --git a/drivers/char/agp/Makefile b/drivers/char/agp/Makefile new file mode 100644 index 000000000000..d33a22f2fa0b --- /dev/null +++ b/drivers/char/agp/Makefile @@ -0,0 +1,18 @@ +agpgart-y := backend.o frontend.o generic.o isoch.o + +obj-$(CONFIG_AGP) += agpgart.o +obj-$(CONFIG_AGP_ALI) += ali-agp.o +obj-$(CONFIG_AGP_ATI) += ati-agp.o +obj-$(CONFIG_AGP_AMD) += amd-k7-agp.o +obj-$(CONFIG_AGP_AMD64) += amd64-agp.o +obj-$(CONFIG_AGP_ALPHA_CORE) += alpha-agp.o +obj-$(CONFIG_AGP_EFFICEON) += efficeon-agp.o +obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o +obj-$(CONFIG_AGP_I460) += i460-agp.o +obj-$(CONFIG_AGP_INTEL) += intel-agp.o +obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o +obj-$(CONFIG_AGP_SGI_TIOCA) += sgi-agp.o +obj-$(CONFIG_AGP_SIS) += sis-agp.o +obj-$(CONFIG_AGP_SWORKS) += sworks-agp.o +obj-$(CONFIG_AGP_UNINORTH) += uninorth-agp.o +obj-$(CONFIG_AGP_VIA) += via-agp.o diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h new file mode 100644 index 000000000000..ad9c11391d81 --- /dev/null +++ b/drivers/char/agp/agp.h @@ -0,0 +1,331 @@ +/* + * AGPGART + * Copyright (C) 2004 Silicon Graphics, Inc. + * Copyright (C) 2002-2004 Dave Jones + * Copyright (C) 1999 Jeff Hartmann + * Copyright (C) 1999 Precision Insight, Inc. + * Copyright (C) 1999 Xi Graphics, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _AGP_BACKEND_PRIV_H +#define _AGP_BACKEND_PRIV_H 1 + +#include /* for flush_agp_cache() */ + +#define PFX "agpgart: " + +//#define AGP_DEBUG 1 +#ifdef AGP_DEBUG +#define DBG(x,y...) printk (KERN_DEBUG PFX "%s: " x "\n", __FUNCTION__ , ## y) +#else +#define DBG(x,y...) do { } while (0) +#endif + +extern struct agp_bridge_data *agp_bridge; + +enum aper_size_type { + U8_APER_SIZE, + U16_APER_SIZE, + U32_APER_SIZE, + LVL2_APER_SIZE, + FIXED_APER_SIZE +}; + +struct gatt_mask { + unsigned long mask; + u32 type; + /* totally device specific, for integrated chipsets that + * might have different types of memory masks. For other + * devices this will probably be ignored */ +}; + +struct aper_size_info_8 { + int size; + int num_entries; + int page_order; + u8 size_value; +}; + +struct aper_size_info_16 { + int size; + int num_entries; + int page_order; + u16 size_value; +}; + +struct aper_size_info_32 { + int size; + int num_entries; + int page_order; + u32 size_value; +}; + +struct aper_size_info_lvl2 { + int size; + int num_entries; + u32 size_value; +}; + +struct aper_size_info_fixed { + int size; + int num_entries; + int page_order; +}; + +struct agp_bridge_driver { + struct module *owner; + void *aperture_sizes; + int num_aperture_sizes; + enum aper_size_type size_type; + int cant_use_aperture; + int needs_scratch_page; + struct gatt_mask *masks; + int (*fetch_size)(void); + int (*configure)(void); + void (*agp_enable)(struct agp_bridge_data *, u32); + void (*cleanup)(void); + void (*tlb_flush)(struct agp_memory *); + unsigned long (*mask_memory)(struct agp_bridge_data *, + unsigned long, int); + void (*cache_flush)(void); + int (*create_gatt_table)(struct agp_bridge_data *); + int (*free_gatt_table)(struct agp_bridge_data *); + int (*insert_memory)(struct agp_memory *, off_t, int); + int (*remove_memory)(struct agp_memory *, off_t, int); + struct agp_memory *(*alloc_by_type) (size_t, int); + void (*free_by_type)(struct agp_memory *); + void *(*agp_alloc_page)(struct agp_bridge_data *); + void (*agp_destroy_page)(void *); +}; + +struct agp_bridge_data { + struct agp_version *version; + struct agp_bridge_driver *driver; + struct vm_operations_struct *vm_ops; + void *previous_size; + void *current_size; + void *dev_private_data; + struct pci_dev *dev; + u32 __iomem *gatt_table; + u32 *gatt_table_real; + unsigned long scratch_page; + unsigned long scratch_page_real; + unsigned long gart_bus_addr; + unsigned long gatt_bus_addr; + u32 mode; + enum chipset_type type; + unsigned long *key_list; + atomic_t current_memory_agp; + atomic_t agp_in_use; + int max_memory_agp; /* in number of pages */ + int aperture_size_idx; + int capndx; + int flags; + char major_version; + char minor_version; + struct list_head list; +}; + +#define KB(x) ((x) * 1024) +#define MB(x) (KB (KB (x))) +#define GB(x) (MB (KB (x))) + +#define A_SIZE_8(x) ((struct aper_size_info_8 *) x) +#define A_SIZE_16(x) ((struct aper_size_info_16 *) x) +#define A_SIZE_32(x) ((struct aper_size_info_32 *) x) +#define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x) +#define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x) +#define A_IDX8(bridge) (A_SIZE_8((bridge)->driver->aperture_sizes) + i) +#define A_IDX16(bridge) (A_SIZE_16((bridge)->driver->aperture_sizes) + i) +#define A_IDX32(bridge) (A_SIZE_32((bridge)->driver->aperture_sizes) + i) +#define MAXKEY (4096 * 32) + +#define PGE_EMPTY(b, p) (!(p) || (p) == (unsigned long) (b)->scratch_page) + + +/* Intel registers */ +#define INTEL_APSIZE 0xb4 +#define INTEL_ATTBASE 0xb8 +#define INTEL_AGPCTRL 0xb0 +#define INTEL_NBXCFG 0x50 +#define INTEL_ERRSTS 0x91 + +/* Intel i830 registers */ +#define I830_GMCH_CTRL 0x52 +#define I830_GMCH_ENABLED 0x4 +#define I830_GMCH_MEM_MASK 0x1 +#define I830_GMCH_MEM_64M 0x1 +#define I830_GMCH_MEM_128M 0 +#define I830_GMCH_GMS_MASK 0x70 +#define I830_GMCH_GMS_DISABLED 0x00 +#define I830_GMCH_GMS_LOCAL 0x10 +#define I830_GMCH_GMS_STOLEN_512 0x20 +#define I830_GMCH_GMS_STOLEN_1024 0x30 +#define I830_GMCH_GMS_STOLEN_8192 0x40 +#define I830_RDRAM_CHANNEL_TYPE 0x03010 +#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5) +#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3) + +/* This one is for I830MP w. an external graphic card */ +#define INTEL_I830_ERRSTS 0x92 + +/* Intel 855GM/852GM registers */ +#define I855_GMCH_GMS_STOLEN_0M 0x0 +#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) +#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) +#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) +#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) +#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) +#define I85X_CAPID 0x44 +#define I85X_VARIANT_MASK 0x7 +#define I85X_VARIANT_SHIFT 5 +#define I855_GME 0x0 +#define I855_GM 0x4 +#define I852_GME 0x2 +#define I852_GM 0x5 + +/* Intel i845 registers */ +#define INTEL_I845_AGPM 0x51 +#define INTEL_I845_ERRSTS 0xc8 + +/* Intel i860 registers */ +#define INTEL_I860_MCHCFG 0x50 +#define INTEL_I860_ERRSTS 0xc8 + +/* Intel i810 registers */ +#define I810_GMADDR 0x10 +#define I810_MMADDR 0x14 +#define I810_PTE_BASE 0x10000 +#define I810_PTE_MAIN_UNCACHED 0x00000000 +#define I810_PTE_LOCAL 0x00000002 +#define I810_PTE_VALID 0x00000001 +#define I810_SMRAM_MISCC 0x70 +#define I810_GFX_MEM_WIN_SIZE 0x00010000 +#define I810_GFX_MEM_WIN_32M 0x00010000 +#define I810_GMS 0x000000c0 +#define I810_GMS_DISABLE 0x00000000 +#define I810_PGETBL_CTL 0x2020 +#define I810_PGETBL_ENABLED 0x00000001 +#define I810_DRAM_CTL 0x3000 +#define I810_DRAM_ROW_0 0x00000001 +#define I810_DRAM_ROW_0_SDRAM 0x00000001 + +struct agp_device_ids { + unsigned short device_id; /* first, to make table easier to read */ + enum chipset_type chipset; + const char *chipset_name; + int (*chipset_setup) (struct pci_dev *pdev); /* used to override generic */ +}; + +/* Driver registration */ +struct agp_bridge_data *agp_alloc_bridge(void); +void agp_put_bridge(struct agp_bridge_data *bridge); +int agp_add_bridge(struct agp_bridge_data *bridge); +void agp_remove_bridge(struct agp_bridge_data *bridge); + +/* Frontend routines. */ +int agp_frontend_initialize(void); +void agp_frontend_cleanup(void); + +/* Generic routines. */ +void agp_generic_enable(struct agp_bridge_data *bridge, u32 mode); +int agp_generic_create_gatt_table(struct agp_bridge_data *bridge); +int agp_generic_free_gatt_table(struct agp_bridge_data *bridge); +struct agp_memory *agp_create_memory(int scratch_pages); +int agp_generic_insert_memory(struct agp_memory *mem, off_t pg_start, int type); +int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type); +struct agp_memory *agp_generic_alloc_by_type(size_t page_count, int type); +void agp_generic_free_by_type(struct agp_memory *curr); +void *agp_generic_alloc_page(struct agp_bridge_data *bridge); +void agp_generic_destroy_page(void *addr); +void agp_free_key(int key); +int agp_num_entries(void); +u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command); +void agp_device_command(u32 command, int agp_v3); +int agp_3_5_enable(struct agp_bridge_data *bridge); +void global_cache_flush(void); +void get_agp_version(struct agp_bridge_data *bridge); +unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge, + unsigned long addr, int type); +struct agp_bridge_data *agp_generic_find_bridge(struct pci_dev *pdev); + +/* generic routines for agp>=3 */ +int agp3_generic_fetch_size(void); +void agp3_generic_tlbflush(struct agp_memory *mem); +int agp3_generic_configure(void); +void agp3_generic_cleanup(void); + +/* aperture sizes have been standardised since v3 */ +#define AGP_GENERIC_SIZES_ENTRIES 11 +extern struct aper_size_info_16 agp3_generic_sizes[]; + + +extern int agp_off; +extern int agp_try_unsupported_boot; + +/* Chipset independant registers (from AGP Spec) */ +#define AGP_APBASE 0x10 + +#define AGPSTAT 0x4 +#define AGPCMD 0x8 +#define AGPNISTAT 0xc +#define AGPCTRL 0x10 +#define AGPAPSIZE 0x14 +#define AGPNEPG 0x16 +#define AGPGARTLO 0x18 +#define AGPGARTHI 0x1c +#define AGPNICMD 0x20 + +#define AGP_MAJOR_VERSION_SHIFT (20) +#define AGP_MINOR_VERSION_SHIFT (16) + +#define AGPSTAT_RQ_DEPTH (0xff000000) +#define AGPSTAT_RQ_DEPTH_SHIFT 24 + +#define AGPSTAT_CAL_MASK (1<<12|1<<11|1<<10) +#define AGPSTAT_ARQSZ (1<<15|1<<14|1<<13) +#define AGPSTAT_ARQSZ_SHIFT 13 + +#define AGPSTAT_SBA (1<<9) +#define AGPSTAT_AGP_ENABLE (1<<8) +#define AGPSTAT_FW (1<<4) +#define AGPSTAT_MODE_3_0 (1<<3) + +#define AGPSTAT2_1X (1<<0) +#define AGPSTAT2_2X (1<<1) +#define AGPSTAT2_4X (1<<2) + +#define AGPSTAT3_RSVD (1<<2) +#define AGPSTAT3_8X (1<<1) +#define AGPSTAT3_4X (1) + +#define AGPCTRL_APERENB (1<<8) +#define AGPCTRL_GTLBEN (1<<7) + +#define AGP2_RESERVED_MASK 0x00fffcc8 +#define AGP3_RESERVED_MASK 0x00ff00c4 + +#define AGP_ERRATA_FASTWRITES 1<<0 +#define AGP_ERRATA_SBA 1<<1 +#define AGP_ERRATA_1X 1<<2 + +#endif /* _AGP_BACKEND_PRIV_H */ diff --git a/drivers/char/agp/ali-agp.c b/drivers/char/agp/ali-agp.c new file mode 100644 index 000000000000..c86a22c5499b --- /dev/null +++ b/drivers/char/agp/ali-agp.c @@ -0,0 +1,414 @@ +/* + * ALi AGPGART routines. + */ + +#include +#include +#include +#include +#include +#include "agp.h" + +#define ALI_AGPCTRL 0xb8 +#define ALI_ATTBASE 0xbc +#define ALI_TLBCTRL 0xc0 +#define ALI_TAGCTRL 0xc4 +#define ALI_CACHE_FLUSH_CTRL 0xD0 +#define ALI_CACHE_FLUSH_ADDR_MASK 0xFFFFF000 +#define ALI_CACHE_FLUSH_EN 0x100 + +static int ali_fetch_size(void) +{ + int i; + u32 temp; + struct aper_size_info_32 *values; + + pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp); + temp &= ~(0xfffffff0); + values = A_SIZE_32(agp_bridge->driver->aperture_sizes); + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + + return 0; +} + +static void ali_tlbflush(struct agp_memory *mem) +{ + u32 temp; + + pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); + temp &= 0xfffffff0; + temp |= (1<<0 | 1<<1); + pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL, temp); +} + +static void ali_cleanup(void) +{ + struct aper_size_info_32 *previous_size; + u32 temp; + + previous_size = A_SIZE_32(agp_bridge->previous_size); + + pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); +// clear tag + pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL, + ((temp & 0xffffff00) | 0x00000001|0x00000002)); + + pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp); + pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, + ((temp & 0x00000ff0) | previous_size->size_value)); +} + +static int ali_configure(void) +{ + u32 temp; + struct aper_size_info_32 *current_size; + + current_size = A_SIZE_32(agp_bridge->current_size); + + /* aperture size and gatt addr */ + pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp); + temp = (((temp & 0x00000ff0) | (agp_bridge->gatt_bus_addr & 0xfffff000)) + | (current_size->size_value & 0xf)); + pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, temp); + + /* tlb control */ + pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010)); + + /* address to map to */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + +#if 0 + if (agp_bridge->type == ALI_M1541) { + u32 nlvm_addr = 0; + + switch (current_size->size_value) { + case 0: break; + case 1: nlvm_addr = 0x100000;break; + case 2: nlvm_addr = 0x200000;break; + case 3: nlvm_addr = 0x400000;break; + case 4: nlvm_addr = 0x800000;break; + case 6: nlvm_addr = 0x1000000;break; + case 7: nlvm_addr = 0x2000000;break; + case 8: nlvm_addr = 0x4000000;break; + case 9: nlvm_addr = 0x8000000;break; + case 10: nlvm_addr = 0x10000000;break; + default: break; + } + nlvm_addr--; + nlvm_addr&=0xfff00000; + + nlvm_addr+= agp_bridge->gart_bus_addr; + nlvm_addr|=(agp_bridge->gart_bus_addr>>12); + printk(KERN_INFO PFX "nlvm top &base = %8x\n",nlvm_addr); + } +#endif + + pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); + temp &= 0xffffff7f; //enable TLB + pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, temp); + + return 0; +} + + +static void m1541_cache_flush(void) +{ + int i, page_count; + u32 temp; + + global_cache_flush(); + + page_count = 1 << A_SIZE_32(agp_bridge->current_size)->page_order; + for (i = 0; i < PAGE_SIZE * page_count; i += PAGE_SIZE) { + pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, + &temp); + pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, + (((temp & ALI_CACHE_FLUSH_ADDR_MASK) | + (agp_bridge->gatt_bus_addr + i)) | + ALI_CACHE_FLUSH_EN)); + } +} + +static void *m1541_alloc_page(struct agp_bridge_data *bridge) +{ + void *addr = agp_generic_alloc_page(agp_bridge); + u32 temp; + + if (!addr) + return NULL; + + pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp); + pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, + (((temp & ALI_CACHE_FLUSH_ADDR_MASK) | + virt_to_phys(addr)) | ALI_CACHE_FLUSH_EN )); + return addr; +} + +static void ali_destroy_page(void * addr) +{ + if (addr) { + global_cache_flush(); /* is this really needed? --hch */ + agp_generic_destroy_page(addr); + } +} + +static void m1541_destroy_page(void * addr) +{ + u32 temp; + + if (addr == NULL) + return; + + global_cache_flush(); + + pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp); + pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, + (((temp & ALI_CACHE_FLUSH_ADDR_MASK) | + virt_to_phys(addr)) | ALI_CACHE_FLUSH_EN)); + agp_generic_destroy_page(addr); +} + + +/* Setup function */ + +static struct aper_size_info_32 ali_generic_sizes[7] = +{ + {256, 65536, 6, 10}, + {128, 32768, 5, 9}, + {64, 16384, 4, 8}, + {32, 8192, 3, 7}, + {16, 4096, 2, 6}, + {8, 2048, 1, 4}, + {4, 1024, 0, 3} +}; + +struct agp_bridge_driver ali_generic_bridge = { + .owner = THIS_MODULE, + .aperture_sizes = ali_generic_sizes, + .size_type = U32_APER_SIZE, + .num_aperture_sizes = 7, + .configure = ali_configure, + .fetch_size = ali_fetch_size, + .cleanup = ali_cleanup, + .tlb_flush = ali_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = NULL, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = ali_destroy_page, +}; + +struct agp_bridge_driver ali_m1541_bridge = { + .owner = THIS_MODULE, + .aperture_sizes = ali_generic_sizes, + .size_type = U32_APER_SIZE, + .num_aperture_sizes = 7, + .configure = ali_configure, + .fetch_size = ali_fetch_size, + .cleanup = ali_cleanup, + .tlb_flush = ali_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = NULL, + .agp_enable = agp_generic_enable, + .cache_flush = m1541_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = m1541_alloc_page, + .agp_destroy_page = m1541_destroy_page, +}; + + +static struct agp_device_ids ali_agp_device_ids[] __devinitdata = +{ + { + .device_id = PCI_DEVICE_ID_AL_M1541, + .chipset_name = "M1541", + }, + { + .device_id = PCI_DEVICE_ID_AL_M1621, + .chipset_name = "M1621", + }, + { + .device_id = PCI_DEVICE_ID_AL_M1631, + .chipset_name = "M1631", + }, + { + .device_id = PCI_DEVICE_ID_AL_M1632, + .chipset_name = "M1632", + }, + { + .device_id = PCI_DEVICE_ID_AL_M1641, + .chipset_name = "M1641", + }, + { + .device_id = PCI_DEVICE_ID_AL_M1644, + .chipset_name = "M1644", + }, + { + .device_id = PCI_DEVICE_ID_AL_M1647, + .chipset_name = "M1647", + }, + { + .device_id = PCI_DEVICE_ID_AL_M1651, + .chipset_name = "M1651", + }, + { + .device_id = PCI_DEVICE_ID_AL_M1671, + .chipset_name = "M1671", + }, + { + .device_id = PCI_DEVICE_ID_AL_M1681, + .chipset_name = "M1681", + }, + { + .device_id = PCI_DEVICE_ID_AL_M1683, + .chipset_name = "M1683", + }, + + { }, /* dummy final entry, always present */ +}; + +static int __devinit agp_ali_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_device_ids *devs = ali_agp_device_ids; + struct agp_bridge_data *bridge; + u8 hidden_1621_id, cap_ptr; + int j; + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (!cap_ptr) + return -ENODEV; + + /* probe for known chipsets */ + for (j = 0; devs[j].chipset_name; j++) { + if (pdev->device == devs[j].device_id) + goto found; + } + + printk(KERN_ERR PFX "Unsupported ALi chipset (device id: %04x)\n", + pdev->device); + return -ENODEV; + + +found: + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + bridge->dev = pdev; + bridge->capndx = cap_ptr; + + switch (pdev->device) { + case PCI_DEVICE_ID_AL_M1541: + bridge->driver = &ali_m1541_bridge; + break; + case PCI_DEVICE_ID_AL_M1621: + pci_read_config_byte(pdev, 0xFB, &hidden_1621_id); + switch (hidden_1621_id) { + case 0x31: + devs[j].chipset_name = "M1631"; + break; + case 0x32: + devs[j].chipset_name = "M1632"; + break; + case 0x41: + devs[j].chipset_name = "M1641"; + break; + case 0x43: + devs[j].chipset_name = "M????"; + break; + case 0x47: + devs[j].chipset_name = "M1647"; + break; + case 0x51: + devs[j].chipset_name = "M1651"; + break; + default: + break; + } + /*FALLTHROUGH*/ + default: + bridge->driver = &ali_generic_bridge; + } + + printk(KERN_INFO PFX "Detected ALi %s chipset\n", + devs[j].chipset_name); + + /* Fill in the mode register */ + pci_read_config_dword(pdev, + bridge->capndx+PCI_AGP_STATUS, + &bridge->mode); + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void __devexit agp_ali_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +static struct pci_device_id agp_ali_pci_table[] = { + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_AL, + .device = PCI_ANY_ID, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_ali_pci_table); + +static struct pci_driver agp_ali_pci_driver = { + .name = "agpgart-ali", + .id_table = agp_ali_pci_table, + .probe = agp_ali_probe, + .remove = agp_ali_remove, +}; + +static int __init agp_ali_init(void) +{ + if (agp_off) + return -EINVAL; + return pci_register_driver(&agp_ali_pci_driver); +} + +static void __exit agp_ali_cleanup(void) +{ + pci_unregister_driver(&agp_ali_pci_driver); +} + +module_init(agp_ali_init); +module_exit(agp_ali_cleanup); + +MODULE_AUTHOR("Dave Jones "); +MODULE_LICENSE("GPL and additional rights"); + diff --git a/drivers/char/agp/alpha-agp.c b/drivers/char/agp/alpha-agp.c new file mode 100644 index 000000000000..a072d32005a4 --- /dev/null +++ b/drivers/char/agp/alpha-agp.c @@ -0,0 +1,216 @@ +#include +#include +#include +#include +#include +#include + +#include +#include +#include "../../../arch/alpha/kernel/pci_impl.h" + +#include "agp.h" + +static struct page *alpha_core_agp_vm_nopage(struct vm_area_struct *vma, + unsigned long address, + int *type) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + dma_addr_t dma_addr; + unsigned long pa; + struct page *page; + + dma_addr = address - vma->vm_start + agp->aperture.bus_base; + pa = agp->ops->translate(agp, dma_addr); + + if (pa == (unsigned long)-EINVAL) return NULL; /* no translation */ + + /* + * Get the page, inc the use count, and return it + */ + page = virt_to_page(__va(pa)); + get_page(page); + if (type) + *type = VM_FAULT_MINOR; + return page; +} + +static struct aper_size_info_fixed alpha_core_agp_sizes[] = +{ + { 0, 0, 0 }, /* filled in by alpha_core_agp_setup */ +}; + +struct vm_operations_struct alpha_core_agp_vm_ops = { + .nopage = alpha_core_agp_vm_nopage, +}; + + +static int alpha_core_agp_nop(void) +{ + /* just return success */ + return 0; +} + +static int alpha_core_agp_fetch_size(void) +{ + return alpha_core_agp_sizes[0].size; +} + +static int alpha_core_agp_configure(void) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + agp_bridge->gart_bus_addr = agp->aperture.bus_base; + return 0; +} + +static void alpha_core_agp_cleanup(void) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + + agp->ops->cleanup(agp); +} + +static void alpha_core_agp_tlbflush(struct agp_memory *mem) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + alpha_mv.mv_pci_tbi(agp->hose, 0, -1); +} + +static void alpha_core_agp_enable(struct agp_bridge_data *bridge, u32 mode) +{ + alpha_agp_info *agp = bridge->dev_private_data; + + agp->mode.lw = agp_collect_device_status(bridge, mode, + agp->capability.lw); + + agp->mode.bits.enable = 1; + agp->ops->configure(agp); + + agp_device_command(agp->mode.lw, 0); +} + +static int alpha_core_agp_insert_memory(struct agp_memory *mem, off_t pg_start, + int type) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + int num_entries, status; + void *temp; + + temp = agp_bridge->current_size; + num_entries = A_SIZE_FIX(temp)->num_entries; + if ((pg_start + mem->page_count) > num_entries) return -EINVAL; + + status = agp->ops->bind(agp, pg_start, mem); + mb(); + alpha_core_agp_tlbflush(mem); + + return status; +} + +static int alpha_core_agp_remove_memory(struct agp_memory *mem, off_t pg_start, + int type) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + int status; + + status = agp->ops->unbind(agp, pg_start, mem); + alpha_core_agp_tlbflush(mem); + return status; +} + +struct agp_bridge_driver alpha_core_agp_driver = { + .owner = THIS_MODULE, + .aperture_sizes = alpha_core_agp_sizes, + .num_aperture_sizes = 1, + .size_type = FIXED_APER_SIZE, + .cant_use_aperture = 1, + .masks = NULL, + + .fetch_size = alpha_core_agp_fetch_size, + .configure = alpha_core_agp_configure, + .agp_enable = alpha_core_agp_enable, + .cleanup = alpha_core_agp_cleanup, + .tlb_flush = alpha_core_agp_tlbflush, + .mask_memory = agp_generic_mask_memory, + .cache_flush = global_cache_flush, + .create_gatt_table = alpha_core_agp_nop, + .free_gatt_table = alpha_core_agp_nop, + .insert_memory = alpha_core_agp_insert_memory, + .remove_memory = alpha_core_agp_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +struct agp_bridge_data *alpha_bridge; + +int __init +alpha_core_agp_setup(void) +{ + alpha_agp_info *agp = alpha_mv.agp_info(); + struct pci_dev *pdev; /* faked */ + struct aper_size_info_fixed *aper_size; + + if (!agp) + return -ENODEV; + if (agp->ops->setup(agp)) + return -ENODEV; + + /* + * Build the aperture size descriptor + */ + aper_size = alpha_core_agp_sizes; + aper_size->size = agp->aperture.size / (1024 * 1024); + aper_size->num_entries = agp->aperture.size / PAGE_SIZE; + aper_size->page_order = __ffs(aper_size->num_entries / 1024); + + /* + * Build a fake pci_dev struct + */ + pdev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL); + if (!pdev) + return -ENOMEM; + pdev->vendor = 0xffff; + pdev->device = 0xffff; + pdev->sysdata = agp->hose; + + alpha_bridge = agp_alloc_bridge(); + if (!alpha_bridge) + goto fail; + + alpha_bridge->driver = &alpha_core_agp_driver; + alpha_bridge->vm_ops = &alpha_core_agp_vm_ops; + alpha_bridge->current_size = aper_size; /* only 1 size */ + alpha_bridge->dev_private_data = agp; + alpha_bridge->dev = pdev; + alpha_bridge->mode = agp->capability.lw; + + printk(KERN_INFO PFX "Detected AGP on hose %d\n", agp->hose->index); + return agp_add_bridge(alpha_bridge); + + fail: + kfree(pdev); + return -ENOMEM; +} + +static int __init agp_alpha_core_init(void) +{ + if (agp_off) + return -EINVAL; + if (alpha_mv.agp_info) + return alpha_core_agp_setup(); + return -ENODEV; +} + +static void __exit agp_alpha_core_cleanup(void) +{ + agp_remove_bridge(alpha_bridge); + agp_put_bridge(alpha_bridge); +} + +module_init(agp_alpha_core_init); +module_exit(agp_alpha_core_cleanup); + +MODULE_AUTHOR("Jeff Wiedemeier "); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/agp/amd-k7-agp.c b/drivers/char/agp/amd-k7-agp.c new file mode 100644 index 000000000000..f1ea87ea6b65 --- /dev/null +++ b/drivers/char/agp/amd-k7-agp.c @@ -0,0 +1,542 @@ +/* + * AMD K7 AGPGART routines. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agp.h" + +#define AMD_MMBASE 0x14 +#define AMD_APSIZE 0xac +#define AMD_MODECNTL 0xb0 +#define AMD_MODECNTL2 0xb2 +#define AMD_GARTENABLE 0x02 /* In mmio region (16-bit register) */ +#define AMD_ATTBASE 0x04 /* In mmio region (32-bit register) */ +#define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */ +#define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */ + +static struct pci_device_id agp_amdk7_pci_table[]; + +struct amd_page_map { + unsigned long *real; + unsigned long __iomem *remapped; +}; + +static struct _amd_irongate_private { + volatile u8 __iomem *registers; + struct amd_page_map **gatt_pages; + int num_tables; +} amd_irongate_private; + +static int amd_create_page_map(struct amd_page_map *page_map) +{ + int i; + + page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL); + if (page_map->real == NULL) + return -ENOMEM; + + SetPageReserved(virt_to_page(page_map->real)); + global_cache_flush(); + page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real), + PAGE_SIZE); + if (page_map->remapped == NULL) { + ClearPageReserved(virt_to_page(page_map->real)); + free_page((unsigned long) page_map->real); + page_map->real = NULL; + return -ENOMEM; + } + global_cache_flush(); + + for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) { + writel(agp_bridge->scratch_page, page_map->remapped+i); + readl(page_map->remapped+i); /* PCI Posting. */ + } + + return 0; +} + +static void amd_free_page_map(struct amd_page_map *page_map) +{ + iounmap(page_map->remapped); + ClearPageReserved(virt_to_page(page_map->real)); + free_page((unsigned long) page_map->real); +} + +static void amd_free_gatt_pages(void) +{ + int i; + struct amd_page_map **tables; + struct amd_page_map *entry; + + tables = amd_irongate_private.gatt_pages; + for (i = 0; i < amd_irongate_private.num_tables; i++) { + entry = tables[i]; + if (entry != NULL) { + if (entry->real != NULL) + amd_free_page_map(entry); + kfree(entry); + } + } + kfree(tables); + amd_irongate_private.gatt_pages = NULL; +} + +static int amd_create_gatt_pages(int nr_tables) +{ + struct amd_page_map **tables; + struct amd_page_map *entry; + int retval = 0; + int i; + + tables = kmalloc((nr_tables + 1) * sizeof(struct amd_page_map *), + GFP_KERNEL); + if (tables == NULL) + return -ENOMEM; + + memset (tables, 0, sizeof(struct amd_page_map *) * (nr_tables + 1)); + for (i = 0; i < nr_tables; i++) { + entry = kmalloc(sizeof(struct amd_page_map), GFP_KERNEL); + if (entry == NULL) { + retval = -ENOMEM; + break; + } + memset (entry, 0, sizeof(struct amd_page_map)); + tables[i] = entry; + retval = amd_create_page_map(entry); + if (retval != 0) + break; + } + amd_irongate_private.num_tables = nr_tables; + amd_irongate_private.gatt_pages = tables; + + if (retval != 0) + amd_free_gatt_pages(); + + return retval; +} + +/* Since we don't need contigious memory we just try + * to get the gatt table once + */ + +#define GET_PAGE_DIR_OFF(addr) (addr >> 22) +#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \ + GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr)) +#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12) +#define GET_GATT(addr) (amd_irongate_private.gatt_pages[\ + GET_PAGE_DIR_IDX(addr)]->remapped) + +static int amd_create_gatt_table(struct agp_bridge_data *bridge) +{ + struct aper_size_info_lvl2 *value; + struct amd_page_map page_dir; + unsigned long addr; + int retval; + u32 temp; + int i; + + value = A_SIZE_LVL2(agp_bridge->current_size); + retval = amd_create_page_map(&page_dir); + if (retval != 0) + return retval; + + retval = amd_create_gatt_pages(value->num_entries / 1024); + if (retval != 0) { + amd_free_page_map(&page_dir); + return retval; + } + + agp_bridge->gatt_table_real = (u32 *)page_dir.real; + agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped; + agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real); + + /* Get the address for the gart region. + * This is a bus address even on the alpha, b/c its + * used to program the agp master not the cpu + */ + + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + agp_bridge->gart_bus_addr = addr; + + /* Calculate the agp offset */ + for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) { + writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1, + page_dir.remapped+GET_PAGE_DIR_OFF(addr)); + readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */ + } + + return 0; +} + +static int amd_free_gatt_table(struct agp_bridge_data *bridge) +{ + struct amd_page_map page_dir; + + page_dir.real = (unsigned long *)agp_bridge->gatt_table_real; + page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table; + + amd_free_gatt_pages(); + amd_free_page_map(&page_dir); + return 0; +} + +static int amd_irongate_fetch_size(void) +{ + int i; + u32 temp; + struct aper_size_info_lvl2 *values; + + pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp); + temp = (temp & 0x0000000e); + values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes); + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + + return 0; +} + +static int amd_irongate_configure(void) +{ + struct aper_size_info_lvl2 *current_size; + u32 temp; + u16 enable_reg; + + current_size = A_SIZE_LVL2(agp_bridge->current_size); + + /* Get the memory mapped registers */ + pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp); + temp = (temp & PCI_BASE_ADDRESS_MEM_MASK); + amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); + + /* Write out the address of the gatt table */ + writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE); + readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */ + + /* Write the Sync register */ + pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80); + + /* Set indexing mode */ + pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00); + + /* Write the enable register */ + enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); + enable_reg = (enable_reg | 0x0004); + writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); + readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */ + + /* Write out the size register */ + pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp); + temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1); + pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp); + + /* Flush the tlb */ + writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); + readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting.*/ + return 0; +} + +static void amd_irongate_cleanup(void) +{ + struct aper_size_info_lvl2 *previous_size; + u32 temp; + u16 enable_reg; + + previous_size = A_SIZE_LVL2(agp_bridge->previous_size); + + enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); + enable_reg = (enable_reg & ~(0x0004)); + writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); + readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */ + + /* Write back the previous size and disable gart translation */ + pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp); + temp = ((temp & ~(0x0000000f)) | previous_size->size_value); + pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp); + iounmap((void __iomem *) amd_irongate_private.registers); +} + +/* + * This routine could be implemented by taking the addresses + * written to the GATT, and flushing them individually. However + * currently it just flushes the whole table. Which is probably + * more efficent, since agp_memory blocks can be a large number of + * entries. + */ + +static void amd_irongate_tlbflush(struct agp_memory *temp) +{ + writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); + readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting. */ +} + +static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type) +{ + int i, j, num_entries; + unsigned long __iomem *cur_gatt; + unsigned long addr; + + num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; + + if (type != 0 || mem->type != 0) + return -EINVAL; + + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + + j = pg_start; + while (j < (pg_start + mem->page_count)) { + addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; + cur_gatt = GET_GATT(addr); + if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr)))) + return -EBUSY; + j++; + } + + if (mem->is_flushed == FALSE) { + global_cache_flush(); + mem->is_flushed = TRUE; + } + + for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { + addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; + cur_gatt = GET_GATT(addr); + writel(agp_generic_mask_memory(agp_bridge, + mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr)); + readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */ + } + amd_irongate_tlbflush(mem); + return 0; +} + +static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type) +{ + int i; + unsigned long __iomem *cur_gatt; + unsigned long addr; + + if (type != 0 || mem->type != 0) + return -EINVAL; + + for (i = pg_start; i < (mem->page_count + pg_start); i++) { + addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr; + cur_gatt = GET_GATT(addr); + writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr)); + readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */ + } + + amd_irongate_tlbflush(mem); + return 0; +} + +static struct aper_size_info_lvl2 amd_irongate_sizes[7] = +{ + {2048, 524288, 0x0000000c}, + {1024, 262144, 0x0000000a}, + {512, 131072, 0x00000008}, + {256, 65536, 0x00000006}, + {128, 32768, 0x00000004}, + {64, 16384, 0x00000002}, + {32, 8192, 0x00000000} +}; + +static struct gatt_mask amd_irongate_masks[] = +{ + {.mask = 1, .type = 0} +}; + +struct agp_bridge_driver amd_irongate_driver = { + .owner = THIS_MODULE, + .aperture_sizes = amd_irongate_sizes, + .size_type = LVL2_APER_SIZE, + .num_aperture_sizes = 7, + .configure = amd_irongate_configure, + .fetch_size = amd_irongate_fetch_size, + .cleanup = amd_irongate_cleanup, + .tlb_flush = amd_irongate_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = amd_irongate_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = amd_create_gatt_table, + .free_gatt_table = amd_free_gatt_table, + .insert_memory = amd_insert_memory, + .remove_memory = amd_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_device_ids amd_agp_device_ids[] __devinitdata = +{ + { + .device_id = PCI_DEVICE_ID_AMD_FE_GATE_7006, + .chipset_name = "Irongate", + }, + { + .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700E, + .chipset_name = "761", + }, + { + .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700C, + .chipset_name = "760MP", + }, + { }, /* dummy final entry, always present */ +}; + +static int __devinit agp_amdk7_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_bridge_data *bridge; + u8 cap_ptr; + int j; + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (!cap_ptr) + return -ENODEV; + + j = ent - agp_amdk7_pci_table; + printk(KERN_INFO PFX "Detected AMD %s chipset\n", + amd_agp_device_ids[j].chipset_name); + + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + bridge->driver = &amd_irongate_driver; + bridge->dev_private_data = &amd_irongate_private, + bridge->dev = pdev; + bridge->capndx = cap_ptr; + + /* 751 Errata (22564_B-1.PDF) + erratum 20: strobe glitch with Nvidia NV10 GeForce cards. + system controller may experience noise due to strong drive strengths + */ + if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_7006) { + u8 cap_ptr=0; + struct pci_dev *gfxcard=NULL; + while (!cap_ptr) { + gfxcard = pci_get_class(PCI_CLASS_DISPLAY_VGA<<8, gfxcard); + if (!gfxcard) { + printk (KERN_INFO PFX "Couldn't find an AGP VGA controller.\n"); + return -ENODEV; + } + cap_ptr = pci_find_capability(gfxcard, PCI_CAP_ID_AGP); + if (!cap_ptr) { + pci_dev_put(gfxcard); + continue; + } + } + + /* With so many variants of NVidia cards, it's simpler just + to blacklist them all, and then whitelist them as needed + (if necessary at all). */ + if (gfxcard->vendor == PCI_VENDOR_ID_NVIDIA) { + agp_bridge->flags |= AGP_ERRATA_1X; + printk (KERN_INFO PFX "AMD 751 chipset with NVidia GeForce detected. Forcing to 1X due to errata.\n"); + } + pci_dev_put(gfxcard); + } + + /* 761 Errata (23613_F.pdf) + * Revisions B0/B1 were a disaster. + * erratum 44: SYSCLK/AGPCLK skew causes 2X failures -- Force mode to 1X + * erratum 45: Timing problem prevents fast writes -- Disable fast write. + * erratum 46: Setup violation on AGP SBA pins - Disable side band addressing. + * With this lot disabled, we should prevent lockups. */ + if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) { + u8 revision=0; + pci_read_config_byte(pdev, PCI_REVISION_ID, &revision); + if (revision == 0x10 || revision == 0x11) { + agp_bridge->flags = AGP_ERRATA_FASTWRITES; + agp_bridge->flags |= AGP_ERRATA_SBA; + agp_bridge->flags |= AGP_ERRATA_1X; + printk (KERN_INFO PFX "AMD 761 chipset with errata detected - disabling AGP fast writes & SBA and forcing to 1X.\n"); + } + } + + /* Fill in the mode register */ + pci_read_config_dword(pdev, + bridge->capndx+PCI_AGP_STATUS, + &bridge->mode); + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void __devexit agp_amdk7_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +/* must be the same order as name table above */ +static struct pci_device_id agp_amdk7_pci_table[] = { + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_FE_GATE_7006, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_FE_GATE_700E, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_FE_GATE_700C, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table); + +static struct pci_driver agp_amdk7_pci_driver = { + .name = "agpgart-amdk7", + .id_table = agp_amdk7_pci_table, + .probe = agp_amdk7_probe, + .remove = agp_amdk7_remove, +}; + +static int __init agp_amdk7_init(void) +{ + if (agp_off) + return -EINVAL; + return pci_register_driver(&agp_amdk7_pci_driver); +} + +static void __exit agp_amdk7_cleanup(void) +{ + pci_unregister_driver(&agp_amdk7_pci_driver); +} + +module_init(agp_amdk7_init); +module_exit(agp_amdk7_cleanup); + +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c new file mode 100644 index 000000000000..905f0629c44f --- /dev/null +++ b/drivers/char/agp/amd64-agp.c @@ -0,0 +1,761 @@ +/* + * Copyright 2001-2003 SuSE Labs. + * Distributed under the GNU public license, v2. + * + * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge. + * It also includes support for the AMD 8151 AGP bridge, + * although it doesn't actually do much, as all the real + * work is done in the northbridge(s). + */ + +#include +#include +#include +#include +#include +#include "agp.h" + +/* Will need to be increased if AMD64 ever goes >8-way. */ +#define MAX_HAMMER_GARTS 8 + +/* PTE bits. */ +#define GPTE_VALID 1 +#define GPTE_COHERENT 2 + +/* Aperture control register bits. */ +#define GARTEN (1<<0) +#define DISGARTCPU (1<<4) +#define DISGARTIO (1<<5) + +/* GART cache control register bits. */ +#define INVGART (1<<0) +#define GARTPTEERR (1<<1) + +/* K8 On-cpu GART registers */ +#define AMD64_GARTAPERTURECTL 0x90 +#define AMD64_GARTAPERTUREBASE 0x94 +#define AMD64_GARTTABLEBASE 0x98 +#define AMD64_GARTCACHECTL 0x9c +#define AMD64_GARTEN (1<<0) + +/* NVIDIA K8 registers */ +#define NVIDIA_X86_64_0_APBASE 0x10 +#define NVIDIA_X86_64_1_APBASE1 0x50 +#define NVIDIA_X86_64_1_APLIMIT1 0x54 +#define NVIDIA_X86_64_1_APSIZE 0xa8 +#define NVIDIA_X86_64_1_APBASE2 0xd8 +#define NVIDIA_X86_64_1_APLIMIT2 0xdc + +/* ULi K8 registers */ +#define ULI_X86_64_BASE_ADDR 0x10 +#define ULI_X86_64_HTT_FEA_REG 0x50 +#define ULI_X86_64_ENU_SCR_REG 0x54 + +static int nr_garts; +static struct pci_dev * hammers[MAX_HAMMER_GARTS]; + +static struct resource *aperture_resource; +static int __initdata agp_try_unsupported; + +static int gart_iterator; +#define for_each_nb() for(gart_iterator=0;gart_iteratortype != 0) + return -EINVAL; + + /* Make sure we can fit the range in the gatt table. */ + /* FIXME: could wrap */ + if (((unsigned long)pg_start + mem->page_count) > num_entries) + return -EINVAL; + + j = pg_start; + + /* gatt table should be empty. */ + while (j < (pg_start + mem->page_count)) { + if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) + return -EBUSY; + j++; + } + + if (mem->is_flushed == FALSE) { + global_cache_flush(); + mem->is_flushed = TRUE; + } + + for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { + tmp = agp_bridge->driver->mask_memory(agp_bridge, + mem->memory[i], mem->type); + + BUG_ON(tmp & 0xffffff0000000ffcULL); + pte = (tmp & 0x000000ff00000000ULL) >> 28; + pte |=(tmp & 0x00000000fffff000ULL); + pte |= GPTE_VALID | GPTE_COHERENT; + + writel(pte, agp_bridge->gatt_table+j); + readl(agp_bridge->gatt_table+j); /* PCI Posting. */ + } + amd64_tlbflush(mem); + return 0; +} + +/* + * This hack alters the order element according + * to the size of a long. It sucks. I totally disown this, even + * though it does appear to work for the most part. + */ +static struct aper_size_info_32 amd64_aperture_sizes[7] = +{ + {32, 8192, 3+(sizeof(long)/8), 0 }, + {64, 16384, 4+(sizeof(long)/8), 1<<1 }, + {128, 32768, 5+(sizeof(long)/8), 1<<2 }, + {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 }, + {512, 131072, 7+(sizeof(long)/8), 1<<3 }, + {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3}, + {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3} +}; + + +/* + * Get the current Aperture size from the x86-64. + * Note, that there may be multiple x86-64's, but we just return + * the value from the first one we find. The set_size functions + * keep the rest coherent anyway. Or at least should do. + */ +static int amd64_fetch_size(void) +{ + struct pci_dev *dev; + int i; + u32 temp; + struct aper_size_info_32 *values; + + dev = hammers[0]; + if (dev==NULL) + return 0; + + pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp); + temp = (temp & 0xe); + values = A_SIZE_32(amd64_aperture_sizes); + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + return 0; +} + +/* + * In a multiprocessor x86-64 system, this function gets + * called once for each CPU. + */ +static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table) +{ + u64 aperturebase; + u32 tmp; + u64 addr, aper_base; + + /* Address to map to */ + pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp); + aperturebase = tmp << 25; + aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); + + /* address of the mappings table */ + addr = (u64) gatt_table; + addr >>= 12; + tmp = (u32) addr<<4; + tmp &= ~0xf; + pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp); + + /* Enable GART translation for this hammer. */ + pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp); + tmp |= GARTEN; + tmp &= ~(DISGARTCPU | DISGARTIO); + pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp); + + /* keep CPU's coherent. */ + flush_amd64_tlb (hammer); + + return aper_base; +} + + +static struct aper_size_info_32 amd_8151_sizes[7] = +{ + {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */ + {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */ + {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */ + {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */ + {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */ + {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */ + {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */ +}; + +static int amd_8151_configure(void) +{ + unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real); + + /* Configure AGP regs in each x86-64 host bridge. */ + for_each_nb() { + agp_bridge->gart_bus_addr = + amd64_configure(hammers[gart_iterator],gatt_bus); + } + return 0; +} + + +static void amd64_cleanup(void) +{ + u32 tmp; + + for_each_nb() { + /* disable gart translation */ + pci_read_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, &tmp); + tmp &= ~AMD64_GARTEN; + pci_write_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, tmp); + } +} + + +struct agp_bridge_driver amd_8151_driver = { + .owner = THIS_MODULE, + .aperture_sizes = amd_8151_sizes, + .size_type = U32_APER_SIZE, + .num_aperture_sizes = 7, + .configure = amd_8151_configure, + .fetch_size = amd64_fetch_size, + .cleanup = amd64_cleanup, + .tlb_flush = amd64_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = NULL, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = amd64_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +/* Some basic sanity checks for the aperture. */ +static int __devinit aperture_valid(u64 aper, u32 size) +{ + u32 pfn, c; + if (aper == 0) { + printk(KERN_ERR PFX "No aperture\n"); + return 0; + } + if (size < 32*1024*1024) { + printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20); + return 0; + } + if (aper + size > 0xffffffff) { + printk(KERN_ERR PFX "Aperture out of bounds\n"); + return 0; + } + pfn = aper >> PAGE_SHIFT; + for (c = 0; c < size/PAGE_SIZE; c++) { + if (!pfn_valid(pfn + c)) + break; + if (!PageReserved(pfn_to_page(pfn + c))) { + printk(KERN_ERR PFX "Aperture pointing to RAM\n"); + return 0; + } + } + + /* Request the Aperture. This catches cases when someone else + already put a mapping in there - happens with some very broken BIOS + + Maybe better to use pci_assign_resource/pci_enable_device instead + trusting the bridges? */ + if (!aperture_resource && + !(aperture_resource = request_mem_region(aper, size, "aperture"))) { + printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n"); + return 0; + } + return 1; +} + +/* + * W*s centric BIOS sometimes only set up the aperture in the AGP + * bridge, not the northbridge. On AMD64 this is handled early + * in aperture.c, but when GART_IOMMU is not enabled or we run + * on a 32bit kernel this needs to be redone. + * Unfortunately it is impossible to fix the aperture here because it's too late + * to allocate that much memory. But at least error out cleanly instead of + * crashing. + */ +static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, + u16 cap) +{ + u32 aper_low, aper_hi; + u64 aper, nb_aper; + int order = 0; + u32 nb_order, nb_base; + u16 apsize; + + pci_read_config_dword(nb, 0x90, &nb_order); + nb_order = (nb_order >> 1) & 7; + pci_read_config_dword(nb, 0x94, &nb_base); + nb_aper = nb_base << 25; + if (aperture_valid(nb_aper, (32*1024*1024)<> 25); + + return 0; +} + +static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr) +{ + struct pci_dev *loop_dev = NULL; + int i = 0; + + /* cache pci_devs of northbridges. */ + while ((loop_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1103, loop_dev)) + != NULL) { + if (i == MAX_HAMMER_GARTS) { + printk(KERN_ERR PFX "Too many northbridges for AGP\n"); + return -1; + } + if (fix_northbridge(loop_dev, pdev, cap_ptr) < 0) { + printk(KERN_ERR PFX "No usable aperture found.\n"); +#ifdef __x86_64__ + /* should port this to i386 */ + printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n"); +#endif + return -1; + } + hammers[i++] = loop_dev; + } + nr_garts = i; + return i == 0 ? -1 : 0; +} + +/* Handle AMD 8151 quirks */ +static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge) +{ + char *revstring; + u8 rev_id; + + pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); + switch (rev_id) { + case 0x01: revstring="A0"; break; + case 0x02: revstring="A1"; break; + case 0x11: revstring="B0"; break; + case 0x12: revstring="B1"; break; + case 0x13: revstring="B2"; break; + case 0x14: revstring="B3"; break; + default: revstring="??"; break; + } + + printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring); + + /* + * Work around errata. + * Chips before B2 stepping incorrectly reporting v3.5 + */ + if (rev_id < 0x13) { + printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n"); + bridge->major_version = 3; + bridge->minor_version = 0; + } +} + + +static struct aper_size_info_32 uli_sizes[7] = +{ + {256, 65536, 6, 10}, + {128, 32768, 5, 9}, + {64, 16384, 4, 8}, + {32, 8192, 3, 7}, + {16, 4096, 2, 6}, + {8, 2048, 1, 4}, + {4, 1024, 0, 3} +}; +static int __devinit uli_agp_init(struct pci_dev *pdev) +{ + u32 httfea,baseaddr,enuscr; + struct pci_dev *dev1; + int i; + unsigned size = amd64_fetch_size(); + printk(KERN_INFO "Setting up ULi AGP. \n"); + dev1 = pci_find_slot ((unsigned int)pdev->bus->number,PCI_DEVFN(0,0)); + if (dev1 == NULL) { + printk(KERN_INFO PFX "Detected a ULi chipset, " + "but could not fine the secondary device.\n"); + return -ENODEV; + } + + for (i = 0; i < ARRAY_SIZE(uli_sizes); i++) + if (uli_sizes[i].size == size) + break; + + if (i == ARRAY_SIZE(uli_sizes)) { + printk(KERN_INFO PFX "No ULi size found for %d\n", size); + return -ENODEV; + } + + /* shadow x86-64 registers into ULi registers */ + pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &httfea); + + /* if x86-64 aperture base is beyond 4G, exit here */ + if ((httfea & 0x7fff) >> (32 - 25)) + return -ENODEV; + + httfea = (httfea& 0x7fff) << 25; + + pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr); + baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK; + baseaddr|= httfea; + pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr); + + enuscr= httfea+ (size * 1024 * 1024) - 1; + pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea); + pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr); + return 0; +} + + +static struct aper_size_info_32 nforce3_sizes[5] = +{ + {512, 131072, 7, 0x00000000 }, + {256, 65536, 6, 0x00000008 }, + {128, 32768, 5, 0x0000000C }, + {64, 16384, 4, 0x0000000E }, + {32, 8192, 3, 0x0000000F } +}; + +/* Handle shadow device of the Nvidia NForce3 */ +/* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */ +static int __devinit nforce3_agp_init(struct pci_dev *pdev) +{ + u32 tmp, apbase, apbar, aplimit; + struct pci_dev *dev1; + int i; + unsigned size = amd64_fetch_size(); + + printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n"); + + dev1 = pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(11, 0)); + if (dev1 == NULL) { + printk(KERN_INFO PFX "agpgart: Detected an NVIDIA " + "nForce3 chipset, but could not find " + "the secondary device.\n"); + return -ENODEV; + } + + for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++) + if (nforce3_sizes[i].size == size) + break; + + if (i == ARRAY_SIZE(nforce3_sizes)) { + printk(KERN_INFO PFX "No NForce3 size found for %d\n", size); + return -ENODEV; + } + + pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp); + tmp &= ~(0xf); + tmp |= nforce3_sizes[i].size_value; + pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp); + + /* shadow x86-64 registers into NVIDIA registers */ + pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &apbase); + + /* if x86-64 aperture base is beyond 4G, exit here */ + if ( (apbase & 0x7fff) >> (32 - 25) ) + return -ENODEV; + + apbase = (apbase & 0x7fff) << 25; + + pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar); + apbar &= ~PCI_BASE_ADDRESS_MEM_MASK; + apbar |= apbase; + pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar); + + aplimit = apbase + (size * 1024 * 1024) - 1; + pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase); + pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit); + pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase); + pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit); + + return 0; +} + +static int __devinit agp_amd64_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_bridge_data *bridge; + u8 cap_ptr; + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (!cap_ptr) + return -ENODEV; + + /* Could check for AGPv3 here */ + + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + if (pdev->vendor == PCI_VENDOR_ID_AMD && + pdev->device == PCI_DEVICE_ID_AMD_8151_0) { + amd8151_init(pdev, bridge); + } else { + printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn); + } + + bridge->driver = &amd_8151_driver; + bridge->dev = pdev; + bridge->capndx = cap_ptr; + + /* Fill in the mode register */ + pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); + + if (cache_nbs(pdev, cap_ptr) == -1) { + agp_put_bridge(bridge); + return -ENODEV; + } + + if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) { + int ret = nforce3_agp_init(pdev); + if (ret) { + agp_put_bridge(bridge); + return ret; + } + } + + if (pdev->vendor == PCI_VENDOR_ID_AL) { + int ret = uli_agp_init(pdev); + if (ret) { + agp_put_bridge(bridge); + return ret; + } + } + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void __devexit agp_amd64_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + release_mem_region(virt_to_phys(bridge->gatt_table_real), + amd64_aperture_sizes[bridge->aperture_size_idx].size); + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +static struct pci_device_id agp_amd64_pci_table[] = { + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8151_0, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + /* ULi M1689 */ + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_AL, + .device = PCI_DEVICE_ID_AL_M1689, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + /* VIA K8T800Pro */ + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800PRO_0, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + /* VIA K8T800 */ + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_8385_0, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + /* VIA K8M800 / K8N800 */ + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_8380_0, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + /* VIA K8T890 */ + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_3238_0, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + /* VIA K8T800/K8M800/K8N800 */ + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_838X_1, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + /* NForce3 */ + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_NFORCE3, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + /* SIS 755 */ + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_SI, + .device = PCI_DEVICE_ID_SI_755, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table); + +static struct pci_driver agp_amd64_pci_driver = { + .name = "agpgart-amd64", + .id_table = agp_amd64_pci_table, + .probe = agp_amd64_probe, + .remove = agp_amd64_remove, +}; + + +/* Not static due to IOMMU code calling it early. */ +int __init agp_amd64_init(void) +{ + int err = 0; + static struct pci_device_id amd64nb[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) }, + { }, + }; + + if (agp_off) + return -EINVAL; + if (pci_register_driver(&agp_amd64_pci_driver) > 0) { + struct pci_dev *dev; + if (!agp_try_unsupported && !agp_try_unsupported_boot) { + printk(KERN_INFO PFX "No supported AGP bridge found.\n"); +#ifdef MODULE + printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n"); +#else + printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n"); +#endif + return -ENODEV; + } + + /* First check that we have at least one AMD64 NB */ + if (!pci_dev_present(amd64nb)) + return -ENODEV; + + /* Look for any AGP bridge */ + dev = NULL; + err = -ENODEV; + for_each_pci_dev(dev) { + if (!pci_find_capability(dev, PCI_CAP_ID_AGP)) + continue; + /* Only one bridge supported right now */ + if (agp_amd64_probe(dev, NULL) == 0) { + err = 0; + break; + } + } + } + return err; +} + +static void __exit agp_amd64_cleanup(void) +{ + if (aperture_resource) + release_resource(aperture_resource); + pci_unregister_driver(&agp_amd64_pci_driver); +} + +/* On AMD64 the PCI driver needs to initialize this driver early + for the IOMMU, so it has to be called via a backdoor. */ +#ifndef CONFIG_GART_IOMMU +module_init(agp_amd64_init); +module_exit(agp_amd64_cleanup); +#endif + +MODULE_AUTHOR("Dave Jones , Andi Kleen"); +module_param(agp_try_unsupported, bool, 0); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/agp/ati-agp.c b/drivers/char/agp/ati-agp.c new file mode 100644 index 000000000000..757dde006fc9 --- /dev/null +++ b/drivers/char/agp/ati-agp.c @@ -0,0 +1,548 @@ +/* + * ATi AGPGART routines. + */ + +#include +#include +#include +#include +#include +#include +#include "agp.h" + +#define ATI_GART_MMBASE_ADDR 0x14 +#define ATI_RS100_APSIZE 0xac +#define ATI_RS100_IG_AGPMODE 0xb0 +#define ATI_RS300_APSIZE 0xf8 +#define ATI_RS300_IG_AGPMODE 0xfc +#define ATI_GART_FEATURE_ID 0x00 +#define ATI_GART_BASE 0x04 +#define ATI_GART_CACHE_SZBASE 0x08 +#define ATI_GART_CACHE_CNTRL 0x0c +#define ATI_GART_CACHE_ENTRY_CNTRL 0x10 + + +static struct aper_size_info_lvl2 ati_generic_sizes[7] = +{ + {2048, 524288, 0x0000000c}, + {1024, 262144, 0x0000000a}, + {512, 131072, 0x00000008}, + {256, 65536, 0x00000006}, + {128, 32768, 0x00000004}, + {64, 16384, 0x00000002}, + {32, 8192, 0x00000000} +}; + +static struct gatt_mask ati_generic_masks[] = +{ + { .mask = 1, .type = 0} +}; + + + +typedef struct _ati_page_map { + unsigned long *real; + unsigned long __iomem *remapped; +} ati_page_map; + +static struct _ati_generic_private { + volatile u8 __iomem *registers; + ati_page_map **gatt_pages; + int num_tables; +} ati_generic_private; + +static int ati_create_page_map(ati_page_map *page_map) +{ + int i, err = 0; + + page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL); + if (page_map->real == NULL) + return -ENOMEM; + + SetPageReserved(virt_to_page(page_map->real)); + err = map_page_into_agp(virt_to_page(page_map->real)); + page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real), + PAGE_SIZE); + if (page_map->remapped == NULL || err) { + ClearPageReserved(virt_to_page(page_map->real)); + free_page((unsigned long) page_map->real); + page_map->real = NULL; + return -ENOMEM; + } + /*CACHE_FLUSH();*/ + global_cache_flush(); + + for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) { + writel(agp_bridge->scratch_page, page_map->remapped+i); + readl(page_map->remapped+i); /* PCI Posting. */ + } + + return 0; +} + + +static void ati_free_page_map(ati_page_map *page_map) +{ + unmap_page_from_agp(virt_to_page(page_map->real)); + iounmap(page_map->remapped); + ClearPageReserved(virt_to_page(page_map->real)); + free_page((unsigned long) page_map->real); +} + + +static void ati_free_gatt_pages(void) +{ + int i; + ati_page_map **tables; + ati_page_map *entry; + + tables = ati_generic_private.gatt_pages; + for(i = 0; i < ati_generic_private.num_tables; i++) { + entry = tables[i]; + if (entry != NULL) { + if (entry->real != NULL) + ati_free_page_map(entry); + kfree(entry); + } + } + kfree(tables); +} + + +static int ati_create_gatt_pages(int nr_tables) +{ + ati_page_map **tables; + ati_page_map *entry; + int retval = 0; + int i; + + tables = kmalloc((nr_tables + 1) * sizeof(ati_page_map *), + GFP_KERNEL); + if (tables == NULL) + return -ENOMEM; + + memset(tables, 0, sizeof(ati_page_map *) * (nr_tables + 1)); + for (i = 0; i < nr_tables; i++) { + entry = kmalloc(sizeof(ati_page_map), GFP_KERNEL); + if (entry == NULL) { + while (i>0) { + kfree (tables[i-1]); + i--; + } + kfree (tables); + tables = NULL; + retval = -ENOMEM; + break; + } + memset(entry, 0, sizeof(ati_page_map)); + tables[i] = entry; + retval = ati_create_page_map(entry); + if (retval != 0) break; + } + ati_generic_private.num_tables = nr_tables; + ati_generic_private.gatt_pages = tables; + + if (retval != 0) ati_free_gatt_pages(); + + return retval; +} + +static int is_r200(void) +{ + if ((agp_bridge->dev->device == PCI_DEVICE_ID_ATI_RS100) || + (agp_bridge->dev->device == PCI_DEVICE_ID_ATI_RS200) || + (agp_bridge->dev->device == PCI_DEVICE_ID_ATI_RS200_B) || + (agp_bridge->dev->device == PCI_DEVICE_ID_ATI_RS250)) + return 1; + return 0; +} + +static int ati_fetch_size(void) +{ + int i; + u32 temp; + struct aper_size_info_lvl2 *values; + + if (is_r200()) + pci_read_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, &temp); + else + pci_read_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, &temp); + + temp = (temp & 0x0000000e); + values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes); + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + + return 0; +} + +static void ati_tlbflush(struct agp_memory * mem) +{ + writel(1, ati_generic_private.registers+ATI_GART_CACHE_CNTRL); + readl(ati_generic_private.registers+ATI_GART_CACHE_CNTRL); /* PCI Posting. */ +} + +static void ati_cleanup(void) +{ + struct aper_size_info_lvl2 *previous_size; + u32 temp; + + previous_size = A_SIZE_LVL2(agp_bridge->previous_size); + + /* Write back the previous size and disable gart translation */ + if (is_r200()) { + pci_read_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, &temp); + temp = ((temp & ~(0x0000000f)) | previous_size->size_value); + pci_write_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, temp); + } else { + pci_read_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, &temp); + temp = ((temp & ~(0x0000000f)) | previous_size->size_value); + pci_write_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, temp); + } + iounmap((volatile u8 __iomem *)ati_generic_private.registers); +} + + +static int ati_configure(void) +{ + u32 temp; + + /* Get the memory mapped registers */ + pci_read_config_dword(agp_bridge->dev, ATI_GART_MMBASE_ADDR, &temp); + temp = (temp & 0xfffff000); + ati_generic_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); + + if (is_r200()) + pci_write_config_dword(agp_bridge->dev, ATI_RS100_IG_AGPMODE, 0x20000); + else + pci_write_config_dword(agp_bridge->dev, ATI_RS300_IG_AGPMODE, 0x20000); + + /* address to map too */ + /* + pci_read_config_dword(agp_bridge.dev, AGP_APBASE, &temp); + agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + printk(KERN_INFO PFX "IGP320 gart_bus_addr: %x\n", agp_bridge.gart_bus_addr); + */ + writel(0x60000, ati_generic_private.registers+ATI_GART_FEATURE_ID); + readl(ati_generic_private.registers+ATI_GART_FEATURE_ID); /* PCI Posting.*/ + + /* SIGNALED_SYSTEM_ERROR @ NB_STATUS */ + pci_read_config_dword(agp_bridge->dev, 4, &temp); + pci_write_config_dword(agp_bridge->dev, 4, temp | (1<<14)); + + /* Write out the address of the gatt table */ + writel(agp_bridge->gatt_bus_addr, ati_generic_private.registers+ATI_GART_BASE); + readl(ati_generic_private.registers+ATI_GART_BASE); /* PCI Posting. */ + + return 0; +} + + +/* + *Since we don't need contigious memory we just try + * to get the gatt table once + */ + +#define GET_PAGE_DIR_OFF(addr) (addr >> 22) +#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \ + GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr)) +#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12) +#undef GET_GATT +#define GET_GATT(addr) (ati_generic_private.gatt_pages[\ + GET_PAGE_DIR_IDX(addr)]->remapped) + +static int ati_insert_memory(struct agp_memory * mem, + off_t pg_start, int type) +{ + int i, j, num_entries; + unsigned long __iomem *cur_gatt; + unsigned long addr; + + num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; + + if (type != 0 || mem->type != 0) + return -EINVAL; + + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + + j = pg_start; + while (j < (pg_start + mem->page_count)) { + addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; + cur_gatt = GET_GATT(addr); + if (!PGE_EMPTY(agp_bridge,readl(cur_gatt+GET_GATT_OFF(addr)))) + return -EBUSY; + j++; + } + + if (mem->is_flushed == FALSE) { + /*CACHE_FLUSH(); */ + global_cache_flush(); + mem->is_flushed = TRUE; + } + + for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { + addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; + cur_gatt = GET_GATT(addr); + writel(agp_bridge->driver->mask_memory(agp_bridge, + mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr)); + readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */ + } + agp_bridge->driver->tlb_flush(mem); + return 0; +} + +static int ati_remove_memory(struct agp_memory * mem, off_t pg_start, + int type) +{ + int i; + unsigned long __iomem *cur_gatt; + unsigned long addr; + + if (type != 0 || mem->type != 0) { + return -EINVAL; + } + for (i = pg_start; i < (mem->page_count + pg_start); i++) { + addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr; + cur_gatt = GET_GATT(addr); + writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr)); + readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */ + } + + agp_bridge->driver->tlb_flush(mem); + return 0; +} + +static int ati_create_gatt_table(struct agp_bridge_data *bridge) +{ + struct aper_size_info_lvl2 *value; + ati_page_map page_dir; + unsigned long addr; + int retval; + u32 temp; + int i; + struct aper_size_info_lvl2 *current_size; + + value = A_SIZE_LVL2(agp_bridge->current_size); + retval = ati_create_page_map(&page_dir); + if (retval != 0) + return retval; + + retval = ati_create_gatt_pages(value->num_entries / 1024); + if (retval != 0) { + ati_free_page_map(&page_dir); + return retval; + } + + agp_bridge->gatt_table_real = (u32 *)page_dir.real; + agp_bridge->gatt_table = (u32 __iomem *) page_dir.remapped; + agp_bridge->gatt_bus_addr = virt_to_bus(page_dir.real); + + /* Write out the size register */ + current_size = A_SIZE_LVL2(agp_bridge->current_size); + + if (is_r200()) { + pci_read_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, &temp); + temp = (((temp & ~(0x0000000e)) | current_size->size_value) + | 0x00000001); + pci_write_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, temp); + pci_read_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, &temp); + } else { + pci_read_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, &temp); + temp = (((temp & ~(0x0000000e)) | current_size->size_value) + | 0x00000001); + pci_write_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, temp); + pci_read_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, &temp); + } + + /* + * Get the address for the gart region. + * This is a bus address even on the alpha, b/c its + * used to program the agp master not the cpu + */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + agp_bridge->gart_bus_addr = addr; + + /* Calculate the agp offset */ + for(i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) { + writel(virt_to_bus(ati_generic_private.gatt_pages[i]->real) | 1, + page_dir.remapped+GET_PAGE_DIR_OFF(addr)); + readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */ + } + + return 0; +} + +static int ati_free_gatt_table(struct agp_bridge_data *bridge) +{ + ati_page_map page_dir; + + page_dir.real = (unsigned long *)agp_bridge->gatt_table_real; + page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table; + + ati_free_gatt_pages(); + ati_free_page_map(&page_dir); + return 0; +} + +struct agp_bridge_driver ati_generic_bridge = { + .owner = THIS_MODULE, + .aperture_sizes = ati_generic_sizes, + .size_type = LVL2_APER_SIZE, + .num_aperture_sizes = 7, + .configure = ati_configure, + .fetch_size = ati_fetch_size, + .cleanup = ati_cleanup, + .tlb_flush = ati_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = ati_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = ati_create_gatt_table, + .free_gatt_table = ati_free_gatt_table, + .insert_memory = ati_insert_memory, + .remove_memory = ati_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + + +static struct agp_device_ids ati_agp_device_ids[] __devinitdata = +{ + { + .device_id = PCI_DEVICE_ID_ATI_RS100, + .chipset_name = "IGP320/M", + }, + { + .device_id = PCI_DEVICE_ID_ATI_RS200, + .chipset_name = "IGP330/340/345/350/M", + }, + { + .device_id = PCI_DEVICE_ID_ATI_RS200_B, + .chipset_name = "IGP345M", + }, + { + .device_id = PCI_DEVICE_ID_ATI_RS250, + .chipset_name = "IGP7000/M", + }, + { + .device_id = PCI_DEVICE_ID_ATI_RS300_100, + .chipset_name = "IGP9100/M", + }, + { + .device_id = PCI_DEVICE_ID_ATI_RS300_133, + .chipset_name = "IGP9100/M", + }, + { + .device_id = PCI_DEVICE_ID_ATI_RS300_166, + .chipset_name = "IGP9100/M", + }, + { + .device_id = PCI_DEVICE_ID_ATI_RS300_200, + .chipset_name = "IGP9100/M", + }, + { }, /* dummy final entry, always present */ +}; + +static int __devinit agp_ati_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_device_ids *devs = ati_agp_device_ids; + struct agp_bridge_data *bridge; + u8 cap_ptr; + int j; + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (!cap_ptr) + return -ENODEV; + + /* probe for known chipsets */ + for (j = 0; devs[j].chipset_name; j++) { + if (pdev->device == devs[j].device_id) + goto found; + } + + printk(KERN_ERR PFX + "Unsupported Ati chipset (device id: %04x)\n", pdev->device); + return -ENODEV; + +found: + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + bridge->dev = pdev; + bridge->capndx = cap_ptr; + + bridge->driver = &ati_generic_bridge; + + + printk(KERN_INFO PFX "Detected Ati %s chipset\n", + devs[j].chipset_name); + + /* Fill in the mode register */ + pci_read_config_dword(pdev, + bridge->capndx+PCI_AGP_STATUS, + &bridge->mode); + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void __devexit agp_ati_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +static struct pci_device_id agp_ati_pci_table[] = { + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_ANY_ID, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_ati_pci_table); + +static struct pci_driver agp_ati_pci_driver = { + .name = "agpgart-ati", + .id_table = agp_ati_pci_table, + .probe = agp_ati_probe, + .remove = agp_ati_remove, +}; + +static int __init agp_ati_init(void) +{ + if (agp_off) + return -EINVAL; + return pci_register_driver(&agp_ati_pci_driver); +} + +static void __exit agp_ati_cleanup(void) +{ + pci_unregister_driver(&agp_ati_pci_driver); +} + +module_init(agp_ati_init); +module_exit(agp_ati_cleanup); + +MODULE_AUTHOR("Dave Jones "); +MODULE_LICENSE("GPL and additional rights"); + diff --git a/drivers/char/agp/backend.c b/drivers/char/agp/backend.c new file mode 100644 index 000000000000..c3442f3c6480 --- /dev/null +++ b/drivers/char/agp/backend.c @@ -0,0 +1,348 @@ +/* + * AGPGART driver backend routines. + * Copyright (C) 2004 Silicon Graphics, Inc. + * Copyright (C) 2002-2003 Dave Jones. + * Copyright (C) 1999 Jeff Hartmann. + * Copyright (C) 1999 Precision Insight, Inc. + * Copyright (C) 1999 Xi Graphics, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * JEFF HARTMANN, DAVE JONES, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * TODO: + * - Allocate more than order 0 pages to avoid too much linear map splitting. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "agp.h" + +/* Due to XFree86 brain-damage, we can't go to 1.0 until they + * fix some real stupidity. It's only by chance we can bump + * past 0.99 at all due to some boolean logic error. */ +#define AGPGART_VERSION_MAJOR 0 +#define AGPGART_VERSION_MINOR 101 +static struct agp_version agp_current_version = +{ + .major = AGPGART_VERSION_MAJOR, + .minor = AGPGART_VERSION_MINOR, +}; + +struct agp_bridge_data *(*agp_find_bridge)(struct pci_dev *) = + &agp_generic_find_bridge; + +struct agp_bridge_data *agp_bridge; +LIST_HEAD(agp_bridges); +EXPORT_SYMBOL(agp_bridge); +EXPORT_SYMBOL(agp_bridges); +EXPORT_SYMBOL(agp_find_bridge); + +/** + * agp_backend_acquire - attempt to acquire an agp backend. + * + */ +struct agp_bridge_data *agp_backend_acquire(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge; + + bridge = agp_find_bridge(pdev); + + if (!bridge) + return NULL; + + if (atomic_read(&bridge->agp_in_use)) + return NULL; + atomic_inc(&bridge->agp_in_use); + return bridge; +} +EXPORT_SYMBOL(agp_backend_acquire); + + +/** + * agp_backend_release - release the lock on the agp backend. + * + * The caller must insure that the graphics aperture translation table + * is read for use by another entity. + * + * (Ensure that all memory it bound is unbound.) + */ +void agp_backend_release(struct agp_bridge_data *bridge) +{ + + if (bridge) + atomic_dec(&bridge->agp_in_use); +} +EXPORT_SYMBOL(agp_backend_release); + + +struct { int mem, agp; } maxes_table[] = { + {0, 0}, + {32, 4}, + {64, 28}, + {128, 96}, + {256, 204}, + {512, 440}, + {1024, 942}, + {2048, 1920}, + {4096, 3932} +}; + +static int agp_find_max(void) +{ + long memory, index, result; + +#if PAGE_SHIFT < 20 + memory = num_physpages >> (20 - PAGE_SHIFT); +#else + memory = num_physpages << (PAGE_SHIFT - 20); +#endif + index = 1; + + while ((memory > maxes_table[index].mem) && (index < 8)) + index++; + + result = maxes_table[index - 1].agp + + ( (memory - maxes_table[index - 1].mem) * + (maxes_table[index].agp - maxes_table[index - 1].agp)) / + (maxes_table[index].mem - maxes_table[index - 1].mem); + + result = result << (20 - PAGE_SHIFT); + return result; +} + + +static int agp_backend_initialize(struct agp_bridge_data *bridge) +{ + int size_value, rc, got_gatt=0, got_keylist=0; + + bridge->max_memory_agp = agp_find_max(); + bridge->version = &agp_current_version; + + if (bridge->driver->needs_scratch_page) { + void *addr = bridge->driver->agp_alloc_page(bridge); + + if (!addr) { + printk(KERN_ERR PFX "unable to get memory for scratch page.\n"); + return -ENOMEM; + } + + bridge->scratch_page_real = virt_to_phys(addr); + bridge->scratch_page = + bridge->driver->mask_memory(bridge, bridge->scratch_page_real, 0); + } + + size_value = bridge->driver->fetch_size(); + if (size_value == 0) { + printk(KERN_ERR PFX "unable to determine aperture size.\n"); + rc = -EINVAL; + goto err_out; + } + if (bridge->driver->create_gatt_table(bridge)) { + printk(KERN_ERR PFX + "unable to get memory for graphics translation table.\n"); + rc = -ENOMEM; + goto err_out; + } + got_gatt = 1; + + bridge->key_list = vmalloc(PAGE_SIZE * 4); + if (bridge->key_list == NULL) { + printk(KERN_ERR PFX "error allocating memory for key lists.\n"); + rc = -ENOMEM; + goto err_out; + } + got_keylist = 1; + + /* FIXME vmalloc'd memory not guaranteed contiguous */ + memset(bridge->key_list, 0, PAGE_SIZE * 4); + + if (bridge->driver->configure()) { + printk(KERN_ERR PFX "error configuring host chipset.\n"); + rc = -EINVAL; + goto err_out; + } + + return 0; + +err_out: + if (bridge->driver->needs_scratch_page) + bridge->driver->agp_destroy_page( + phys_to_virt(bridge->scratch_page_real)); + if (got_gatt) + bridge->driver->free_gatt_table(bridge); + if (got_keylist) { + vfree(bridge->key_list); + bridge->key_list = NULL; + } + return rc; +} + +/* cannot be __exit b/c as it could be called from __init code */ +static void agp_backend_cleanup(struct agp_bridge_data *bridge) +{ + if (bridge->driver->cleanup) + bridge->driver->cleanup(); + if (bridge->driver->free_gatt_table) + bridge->driver->free_gatt_table(bridge); + if (bridge->key_list) { + vfree(bridge->key_list); + bridge->key_list = NULL; + } + + if (bridge->driver->agp_destroy_page && + bridge->driver->needs_scratch_page) + bridge->driver->agp_destroy_page( + phys_to_virt(bridge->scratch_page_real)); +} + +/* When we remove the global variable agp_bridge from all drivers + * then agp_alloc_bridge and agp_generic_find_bridge need to be updated + */ + +struct agp_bridge_data *agp_alloc_bridge(void) +{ + struct agp_bridge_data *bridge = kmalloc(sizeof(*bridge), GFP_KERNEL); + + if (!bridge) + return NULL; + + memset(bridge, 0, sizeof(*bridge)); + atomic_set(&bridge->agp_in_use, 0); + atomic_set(&bridge->current_memory_agp, 0); + + if (list_empty(&agp_bridges)) + agp_bridge = bridge; + + return bridge; +} +EXPORT_SYMBOL(agp_alloc_bridge); + + +void agp_put_bridge(struct agp_bridge_data *bridge) +{ + kfree(bridge); + + if (list_empty(&agp_bridges)) + agp_bridge = NULL; +} +EXPORT_SYMBOL(agp_put_bridge); + + +int agp_add_bridge(struct agp_bridge_data *bridge) +{ + int error; + + if (agp_off) + return -ENODEV; + + if (!bridge->dev) { + printk (KERN_DEBUG PFX "Erk, registering with no pci_dev!\n"); + return -EINVAL; + } + + /* Grab reference on the chipset driver. */ + if (!try_module_get(bridge->driver->owner)) { + printk (KERN_INFO PFX "Couldn't lock chipset driver.\n"); + return -EINVAL; + } + + error = agp_backend_initialize(bridge); + if (error) { + printk (KERN_INFO PFX "agp_backend_initialize() failed.\n"); + goto err_out; + } + + if (list_empty(&agp_bridges)) { + error = agp_frontend_initialize(); + if (error) { + printk (KERN_INFO PFX "agp_frontend_initialize() failed.\n"); + goto frontend_err; + } + + printk(KERN_INFO PFX "AGP aperture is %dM @ 0x%lx\n", + bridge->driver->fetch_size(), bridge->gart_bus_addr); + + } + + list_add(&bridge->list, &agp_bridges); + return 0; + +frontend_err: + agp_backend_cleanup(bridge); +err_out: + module_put(bridge->driver->owner); + agp_put_bridge(bridge); + return error; +} +EXPORT_SYMBOL_GPL(agp_add_bridge); + + +void agp_remove_bridge(struct agp_bridge_data *bridge) +{ + agp_backend_cleanup(bridge); + list_del(&bridge->list); + if (list_empty(&agp_bridges)) + agp_frontend_cleanup(); + module_put(bridge->driver->owner); +} +EXPORT_SYMBOL_GPL(agp_remove_bridge); + +int agp_off; +int agp_try_unsupported_boot; +EXPORT_SYMBOL(agp_off); +EXPORT_SYMBOL(agp_try_unsupported_boot); + +static int __init agp_init(void) +{ + if (!agp_off) + printk(KERN_INFO "Linux agpgart interface v%d.%d (c) Dave Jones\n", + AGPGART_VERSION_MAJOR, AGPGART_VERSION_MINOR); + return 0; +} + +void __exit agp_exit(void) +{ +} + +#ifndef MODULE +static __init int agp_setup(char *s) +{ + if (!strcmp(s,"off")) + agp_off = 1; + if (!strcmp(s,"try_unsupported")) + agp_try_unsupported_boot = 1; + return 1; +} +__setup("agp=", agp_setup); +#endif + +MODULE_AUTHOR("Dave Jones "); +MODULE_DESCRIPTION("AGP GART driver"); +MODULE_LICENSE("GPL and additional rights"); +MODULE_ALIAS_MISCDEV(AGPGART_MINOR); + +module_init(agp_init); +module_exit(agp_exit); + diff --git a/drivers/char/agp/efficeon-agp.c b/drivers/char/agp/efficeon-agp.c new file mode 100644 index 000000000000..52c0a097118c --- /dev/null +++ b/drivers/char/agp/efficeon-agp.c @@ -0,0 +1,463 @@ +/* + * Transmeta's Efficeon AGPGART driver. + * + * Based upon a diff by Linus around November '02. + * + * Ported to the 2.6 kernel by Carlos Puchol + * and H. Peter Anvin . + */ + +/* + * NOTE-cpg-040217: + * + * - when compiled as a module, after loading the module, + * it will refuse to unload, indicating it is in use, + * when it is not. + * - no s3 (suspend to ram) testing. + * - tested on the efficeon integrated nothbridge for tens + * of iterations of starting x and glxgears. + * - tested with radeon 9000 and radeon mobility m9 cards + * - tested with c3/c4 enabled (with the mobility m9 card) + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agp.h" + +/* + * The real differences to the generic AGP code is + * in the GART mappings - a two-level setup with the + * first level being an on-chip 64-entry table. + * + * The page array is filled through the ATTPAGE register + * (Aperture Translation Table Page Register) at 0xB8. Bits: + * 31:20: physical page address + * 11:9: Page Attribute Table Index (PATI) + * must match the PAT index for the + * mapped pages (the 2nd level page table pages + * themselves should be just regular WB-cacheable, + * so this is normally zero.) + * 8: Present + * 7:6: reserved, write as zero + * 5:0: GATT directory index: which 1st-level entry + * + * The Efficeon AGP spec requires pages to be WB-cacheable + * but to be explicitly CLFLUSH'd after any changes. + */ +#define EFFICEON_ATTPAGE 0xb8 +#define EFFICEON_L1_SIZE 64 /* Number of PDE pages */ + +#define EFFICEON_PATI (0 << 9) +#define EFFICEON_PRESENT (1 << 8) + +static struct _efficeon_private { + unsigned long l1_table[EFFICEON_L1_SIZE]; +} efficeon_private; + +static struct gatt_mask efficeon_generic_masks[] = +{ + {.mask = 0x00000001, .type = 0} +}; + +static struct aper_size_info_lvl2 efficeon_generic_sizes[4] = +{ + {256, 65536, 0}, + {128, 32768, 32}, + {64, 16384, 48}, + {32, 8192, 56} +}; + +/* + * Control interfaces are largely identical to + * the legacy Intel 440BX.. + */ + +static int efficeon_fetch_size(void) +{ + int i; + u16 temp; + struct aper_size_info_lvl2 *values; + + pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); + values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes); + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + + return 0; +} + +static void efficeon_tlbflush(struct agp_memory * mem) +{ + printk(KERN_DEBUG PFX "efficeon_tlbflush()\n"); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); +} + +static void efficeon_cleanup(void) +{ + u16 temp; + struct aper_size_info_lvl2 *previous_size; + + printk(KERN_DEBUG PFX "efficeon_cleanup()\n"); + previous_size = A_SIZE_LVL2(agp_bridge->previous_size); + pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); + pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); + pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, + previous_size->size_value); +} + +static int efficeon_configure(void) +{ + u32 temp; + u16 temp2; + struct aper_size_info_lvl2 *current_size; + + printk(KERN_DEBUG PFX "efficeon_configure()\n"); + + current_size = A_SIZE_LVL2(agp_bridge->current_size); + + /* aperture size */ + pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, + current_size->size_value); + + /* address to map to */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* agpctrl */ + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); + + /* paccfg/nbxcfg */ + pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, + (temp2 & ~(1 << 10)) | (1 << 9) | (1 << 11)); + /* clear any possible error conditions */ + pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); + return 0; +} + +static int efficeon_free_gatt_table(struct agp_bridge_data *bridge) +{ + int index, freed = 0; + + for (index = 0; index < EFFICEON_L1_SIZE; index++) { + unsigned long page = efficeon_private.l1_table[index]; + if (page) { + efficeon_private.l1_table[index] = 0; + ClearPageReserved(virt_to_page((char *)page)); + free_page(page); + freed++; + } + printk(KERN_DEBUG PFX "efficeon_free_gatt_table(%p, %02x, %08x)\n", + agp_bridge->dev, EFFICEON_ATTPAGE, index); + pci_write_config_dword(agp_bridge->dev, + EFFICEON_ATTPAGE, index); + } + printk(KERN_DEBUG PFX "efficeon_free_gatt_table() freed %d pages\n", freed); + return 0; +} + + +/* + * Since we don't need contigious memory we just try + * to get the gatt table once + */ + +#define GET_PAGE_DIR_OFF(addr) (addr >> 22) +#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \ + GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr)) +#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12) +#undef GET_GATT +#define GET_GATT(addr) (efficeon_private.gatt_pages[\ + GET_PAGE_DIR_IDX(addr)]->remapped) + +static int efficeon_create_gatt_table(struct agp_bridge_data *bridge) +{ + int index; + const int pati = EFFICEON_PATI; + const int present = EFFICEON_PRESENT; + const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3; + int num_entries, l1_pages; + + num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; + + printk(KERN_DEBUG PFX "efficeon_create_gatt_table(%d)\n", num_entries); + + /* There are 2^10 PTE pages per PDE page */ + BUG_ON(num_entries & 0x3ff); + l1_pages = num_entries >> 10; + + for (index = 0 ; index < l1_pages ; index++) { + int offset; + unsigned long page; + unsigned long value; + + page = efficeon_private.l1_table[index]; + BUG_ON(page); + + page = get_zeroed_page(GFP_KERNEL); + if (!page) { + efficeon_free_gatt_table(agp_bridge); + return -ENOMEM; + } + SetPageReserved(virt_to_page((char *)page)); + + for (offset = 0; offset < PAGE_SIZE; offset += clflush_chunk) + asm volatile("clflush %0" : : "m" (*(char *)(page+offset))); + + efficeon_private.l1_table[index] = page; + + value = __pa(page) | pati | present | index; + + pci_write_config_dword(agp_bridge->dev, + EFFICEON_ATTPAGE, value); + } + + return 0; +} + +static int efficeon_insert_memory(struct agp_memory * mem, off_t pg_start, int type) +{ + int i, count = mem->page_count, num_entries; + unsigned int *page, *last_page; + const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3; + const unsigned long clflush_mask = ~(clflush_chunk-1); + + printk(KERN_DEBUG PFX "efficeon_insert_memory(%lx, %d)\n", pg_start, count); + + num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + if (type != 0 || mem->type != 0) + return -EINVAL; + + if (mem->is_flushed == FALSE) { + global_cache_flush(); + mem->is_flushed = TRUE; + } + + last_page = NULL; + for (i = 0; i < count; i++) { + int index = pg_start + i; + unsigned long insert = mem->memory[i]; + + page = (unsigned int *) efficeon_private.l1_table[index >> 10]; + + if (!page) + continue; + + page += (index & 0x3ff); + *page = insert; + + /* clflush is slow, so don't clflush until we have to */ + if ( last_page && + ((unsigned long)page^(unsigned long)last_page) & clflush_mask ) + asm volatile("clflush %0" : : "m" (*last_page)); + + last_page = page; + } + + if ( last_page ) + asm volatile("clflush %0" : : "m" (*last_page)); + + agp_bridge->driver->tlb_flush(mem); + return 0; +} + +static int efficeon_remove_memory(struct agp_memory * mem, off_t pg_start, int type) +{ + int i, count = mem->page_count, num_entries; + + printk(KERN_DEBUG PFX "efficeon_remove_memory(%lx, %d)\n", pg_start, count); + + num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; + + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + if (type != 0 || mem->type != 0) + return -EINVAL; + + for (i = 0; i < count; i++) { + int index = pg_start + i; + unsigned int *page = (unsigned int *) efficeon_private.l1_table[index >> 10]; + + if (!page) + continue; + page += (index & 0x3ff); + *page = 0; + } + agp_bridge->driver->tlb_flush(mem); + return 0; +} + + +struct agp_bridge_driver efficeon_driver = { + .owner = THIS_MODULE, + .aperture_sizes = efficeon_generic_sizes, + .size_type = LVL2_APER_SIZE, + .num_aperture_sizes = 4, + .configure = efficeon_configure, + .fetch_size = efficeon_fetch_size, + .cleanup = efficeon_cleanup, + .tlb_flush = efficeon_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = efficeon_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + + // Efficeon-specific GATT table setup / populate / teardown + .create_gatt_table = efficeon_create_gatt_table, + .free_gatt_table = efficeon_free_gatt_table, + .insert_memory = efficeon_insert_memory, + .remove_memory = efficeon_remove_memory, + .cant_use_aperture = 0, // 1 might be faster? + + // Generic + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + + +static int agp_efficeon_resume(struct pci_dev *pdev) +{ + printk(KERN_DEBUG PFX "agp_efficeon_resume()\n"); + return efficeon_configure(); +} + +static int __devinit agp_efficeon_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_bridge_data *bridge; + u8 cap_ptr; + struct resource *r; + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (!cap_ptr) + return -ENODEV; + + /* Probe for Efficeon controller */ + if (pdev->device != PCI_DEVICE_ID_EFFICEON) { + printk(KERN_ERR PFX "Unsupported Efficeon chipset (device id: %04x)\n", + pdev->device); + return -ENODEV; + } + + printk(KERN_INFO PFX "Detected Transmeta Efficeon TM8000 series chipset\n"); + + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + bridge->driver = &efficeon_driver; + bridge->dev = pdev; + bridge->capndx = cap_ptr; + + /* + * The following fixes the case where the BIOS has "forgotten" to + * provide an address range for the GART. + * 20030610 - hamish@zot.org + */ + r = &pdev->resource[0]; + if (!r->start && r->end) { + if(pci_assign_resource(pdev, 0)) { + printk(KERN_ERR PFX "could not assign resource 0\n"); + return -ENODEV; + } + } + + /* + * If the device has not been properly setup, the following will catch + * the problem and should stop the system from crashing. + * 20030610 - hamish@zot.org + */ + if (pci_enable_device(pdev)) { + printk(KERN_ERR PFX "Unable to Enable PCI device\n"); + return -ENODEV; + } + + /* Fill in the mode register */ + if (cap_ptr) { + pci_read_config_dword(pdev, + bridge->capndx+PCI_AGP_STATUS, + &bridge->mode); + } + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void __devexit agp_efficeon_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +static int agp_efficeon_suspend(struct pci_dev *dev, u32 state) +{ + return 0; +} + + +static struct pci_device_id agp_efficeon_pci_table[] = { + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_TRANSMETA, + .device = PCI_ANY_ID, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_efficeon_pci_table); + +static struct pci_driver agp_efficeon_pci_driver = { + .name = "agpgart-efficeon", + .id_table = agp_efficeon_pci_table, + .probe = agp_efficeon_probe, + .remove = agp_efficeon_remove, + .suspend = agp_efficeon_suspend, + .resume = agp_efficeon_resume, +}; + +static int __init agp_efficeon_init(void) +{ + static int agp_initialised=0; + + if (agp_off) + return -EINVAL; + + if (agp_initialised == 1) + return 0; + agp_initialised=1; + + return pci_register_driver(&agp_efficeon_pci_driver); +} + +static void __exit agp_efficeon_cleanup(void) +{ + pci_unregister_driver(&agp_efficeon_pci_driver); +} + +module_init(agp_efficeon_init); +module_exit(agp_efficeon_cleanup); + +MODULE_AUTHOR("Carlos Puchol "); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/agp/frontend.c b/drivers/char/agp/frontend.c new file mode 100644 index 000000000000..f633623ac802 --- /dev/null +++ b/drivers/char/agp/frontend.c @@ -0,0 +1,1103 @@ +/* + * AGPGART driver frontend + * Copyright (C) 2004 Silicon Graphics, Inc. + * Copyright (C) 2002-2003 Dave Jones + * Copyright (C) 1999 Jeff Hartmann + * Copyright (C) 1999 Precision Insight, Inc. + * Copyright (C) 1999 Xi Graphics, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "agp.h" + +static struct agp_front_data agp_fe; + +static struct agp_memory *agp_find_mem_by_key(int key) +{ + struct agp_memory *curr; + + if (agp_fe.current_controller == NULL) + return NULL; + + curr = agp_fe.current_controller->pool; + + while (curr != NULL) { + if (curr->key == key) + break; + curr = curr->next; + } + + DBG("key=%d -> mem=%p", key, curr); + return curr; +} + +static void agp_remove_from_pool(struct agp_memory *temp) +{ + struct agp_memory *prev; + struct agp_memory *next; + + /* Check to see if this is even in the memory pool */ + + DBG("mem=%p", temp); + if (agp_find_mem_by_key(temp->key) != NULL) { + next = temp->next; + prev = temp->prev; + + if (prev != NULL) { + prev->next = next; + if (next != NULL) + next->prev = prev; + + } else { + /* This is the first item on the list */ + if (next != NULL) + next->prev = NULL; + + agp_fe.current_controller->pool = next; + } + } +} + +/* + * Routines for managing each client's segment list - + * These routines handle adding and removing segments + * to each auth'ed client. + */ + +static struct +agp_segment_priv *agp_find_seg_in_client(const struct agp_client *client, + unsigned long offset, + int size, pgprot_t page_prot) +{ + struct agp_segment_priv *seg; + int num_segments, i; + off_t pg_start; + size_t pg_count; + + pg_start = offset / 4096; + pg_count = size / 4096; + seg = *(client->segments); + num_segments = client->num_segments; + + for (i = 0; i < client->num_segments; i++) { + if ((seg[i].pg_start == pg_start) && + (seg[i].pg_count == pg_count) && + (pgprot_val(seg[i].prot) == pgprot_val(page_prot))) { + return seg + i; + } + } + + return NULL; +} + +static void agp_remove_seg_from_client(struct agp_client *client) +{ + DBG("client=%p", client); + + if (client->segments != NULL) { + if (*(client->segments) != NULL) { + DBG("Freeing %p from client %p", *(client->segments), client); + kfree(*(client->segments)); + } + DBG("Freeing %p from client %p", client->segments, client); + kfree(client->segments); + client->segments = NULL; + } +} + +static void agp_add_seg_to_client(struct agp_client *client, + struct agp_segment_priv ** seg, int num_segments) +{ + struct agp_segment_priv **prev_seg; + + prev_seg = client->segments; + + if (prev_seg != NULL) + agp_remove_seg_from_client(client); + + DBG("Adding seg %p (%d segments) to client %p", seg, num_segments, client); + client->num_segments = num_segments; + client->segments = seg; +} + +/* Originally taken from linux/mm/mmap.c from the array + * protection_map. + * The original really should be exported to modules, or + * some routine which does the conversion for you + */ + +static const pgprot_t my_protect_map[16] = +{ + __P000, __P001, __P010, __P011, __P100, __P101, __P110, __P111, + __S000, __S001, __S010, __S011, __S100, __S101, __S110, __S111 +}; + +static pgprot_t agp_convert_mmap_flags(int prot) +{ +#define _trans(x,bit1,bit2) \ +((bit1==bit2)?(x&bit1):(x&bit1)?bit2:0) + + unsigned long prot_bits; + pgprot_t temp; + + prot_bits = _trans(prot, PROT_READ, VM_READ) | + _trans(prot, PROT_WRITE, VM_WRITE) | + _trans(prot, PROT_EXEC, VM_EXEC); + + prot_bits |= VM_SHARED; + + temp = my_protect_map[prot_bits & 0x0000000f]; + + return temp; +} + +static int agp_create_segment(struct agp_client *client, struct agp_region *region) +{ + struct agp_segment_priv **ret_seg; + struct agp_segment_priv *seg; + struct agp_segment *user_seg; + size_t i; + + seg = kmalloc((sizeof(struct agp_segment_priv) * region->seg_count), GFP_KERNEL); + if (seg == NULL) { + kfree(region->seg_list); + region->seg_list = NULL; + return -ENOMEM; + } + memset(seg, 0, (sizeof(struct agp_segment_priv) * region->seg_count)); + user_seg = region->seg_list; + + for (i = 0; i < region->seg_count; i++) { + seg[i].pg_start = user_seg[i].pg_start; + seg[i].pg_count = user_seg[i].pg_count; + seg[i].prot = agp_convert_mmap_flags(user_seg[i].prot); + } + kfree(region->seg_list); + region->seg_list = NULL; + + ret_seg = kmalloc(sizeof(void *), GFP_KERNEL); + if (ret_seg == NULL) { + kfree(seg); + return -ENOMEM; + } + *ret_seg = seg; + agp_add_seg_to_client(client, ret_seg, region->seg_count); + return 0; +} + +/* End - Routines for managing each client's segment list */ + +/* This function must only be called when current_controller != NULL */ +static void agp_insert_into_pool(struct agp_memory * temp) +{ + struct agp_memory *prev; + + prev = agp_fe.current_controller->pool; + + if (prev != NULL) { + prev->prev = temp; + temp->next = prev; + } + agp_fe.current_controller->pool = temp; +} + + +/* File private list routines */ + +struct agp_file_private *agp_find_private(pid_t pid) +{ + struct agp_file_private *curr; + + curr = agp_fe.file_priv_list; + + while (curr != NULL) { + if (curr->my_pid == pid) + return curr; + curr = curr->next; + } + + return NULL; +} + +void agp_insert_file_private(struct agp_file_private * priv) +{ + struct agp_file_private *prev; + + prev = agp_fe.file_priv_list; + + if (prev != NULL) + prev->prev = priv; + priv->next = prev; + agp_fe.file_priv_list = priv; +} + +void agp_remove_file_private(struct agp_file_private * priv) +{ + struct agp_file_private *next; + struct agp_file_private *prev; + + next = priv->next; + prev = priv->prev; + + if (prev != NULL) { + prev->next = next; + + if (next != NULL) + next->prev = prev; + + } else { + if (next != NULL) + next->prev = NULL; + + agp_fe.file_priv_list = next; + } +} + +/* End - File flag list routines */ + +/* + * Wrappers for agp_free_memory & agp_allocate_memory + * These make sure that internal lists are kept updated. + */ +static void agp_free_memory_wrap(struct agp_memory *memory) +{ + agp_remove_from_pool(memory); + agp_free_memory(memory); +} + +static struct agp_memory *agp_allocate_memory_wrap(size_t pg_count, u32 type) +{ + struct agp_memory *memory; + + memory = agp_allocate_memory(agp_bridge, pg_count, type); + if (memory == NULL) + return NULL; + + agp_insert_into_pool(memory); + return memory; +} + +/* Routines for managing the list of controllers - + * These routines manage the current controller, and the list of + * controllers + */ + +static struct agp_controller *agp_find_controller_by_pid(pid_t id) +{ + struct agp_controller *controller; + + controller = agp_fe.controllers; + + while (controller != NULL) { + if (controller->pid == id) + return controller; + controller = controller->next; + } + + return NULL; +} + +static struct agp_controller *agp_create_controller(pid_t id) +{ + struct agp_controller *controller; + + controller = kmalloc(sizeof(struct agp_controller), GFP_KERNEL); + + if (controller == NULL) + return NULL; + + memset(controller, 0, sizeof(struct agp_controller)); + controller->pid = id; + + return controller; +} + +static int agp_insert_controller(struct agp_controller *controller) +{ + struct agp_controller *prev_controller; + + prev_controller = agp_fe.controllers; + controller->next = prev_controller; + + if (prev_controller != NULL) + prev_controller->prev = controller; + + agp_fe.controllers = controller; + + return 0; +} + +static void agp_remove_all_clients(struct agp_controller *controller) +{ + struct agp_client *client; + struct agp_client *temp; + + client = controller->clients; + + while (client) { + struct agp_file_private *priv; + + temp = client; + agp_remove_seg_from_client(temp); + priv = agp_find_private(temp->pid); + + if (priv != NULL) { + clear_bit(AGP_FF_IS_VALID, &priv->access_flags); + clear_bit(AGP_FF_IS_CLIENT, &priv->access_flags); + } + client = client->next; + kfree(temp); + } +} + +static void agp_remove_all_memory(struct agp_controller *controller) +{ + struct agp_memory *memory; + struct agp_memory *temp; + + memory = controller->pool; + + while (memory) { + temp = memory; + memory = memory->next; + agp_free_memory_wrap(temp); + } +} + +static int agp_remove_controller(struct agp_controller *controller) +{ + struct agp_controller *prev_controller; + struct agp_controller *next_controller; + + prev_controller = controller->prev; + next_controller = controller->next; + + if (prev_controller != NULL) { + prev_controller->next = next_controller; + if (next_controller != NULL) + next_controller->prev = prev_controller; + + } else { + if (next_controller != NULL) + next_controller->prev = NULL; + + agp_fe.controllers = next_controller; + } + + agp_remove_all_memory(controller); + agp_remove_all_clients(controller); + + if (agp_fe.current_controller == controller) { + agp_fe.current_controller = NULL; + agp_fe.backend_acquired = FALSE; + agp_backend_release(agp_bridge); + } + kfree(controller); + return 0; +} + +static void agp_controller_make_current(struct agp_controller *controller) +{ + struct agp_client *clients; + + clients = controller->clients; + + while (clients != NULL) { + struct agp_file_private *priv; + + priv = agp_find_private(clients->pid); + + if (priv != NULL) { + set_bit(AGP_FF_IS_VALID, &priv->access_flags); + set_bit(AGP_FF_IS_CLIENT, &priv->access_flags); + } + clients = clients->next; + } + + agp_fe.current_controller = controller; +} + +static void agp_controller_release_current(struct agp_controller *controller, + struct agp_file_private *controller_priv) +{ + struct agp_client *clients; + + clear_bit(AGP_FF_IS_VALID, &controller_priv->access_flags); + clients = controller->clients; + + while (clients != NULL) { + struct agp_file_private *priv; + + priv = agp_find_private(clients->pid); + + if (priv != NULL) + clear_bit(AGP_FF_IS_VALID, &priv->access_flags); + + clients = clients->next; + } + + agp_fe.current_controller = NULL; + agp_fe.used_by_controller = FALSE; + agp_backend_release(agp_bridge); +} + +/* + * Routines for managing client lists - + * These routines are for managing the list of auth'ed clients. + */ + +static struct agp_client +*agp_find_client_in_controller(struct agp_controller *controller, pid_t id) +{ + struct agp_client *client; + + if (controller == NULL) + return NULL; + + client = controller->clients; + + while (client != NULL) { + if (client->pid == id) + return client; + client = client->next; + } + + return NULL; +} + +static struct agp_controller *agp_find_controller_for_client(pid_t id) +{ + struct agp_controller *controller; + + controller = agp_fe.controllers; + + while (controller != NULL) { + if ((agp_find_client_in_controller(controller, id)) != NULL) + return controller; + controller = controller->next; + } + + return NULL; +} + +static struct agp_client *agp_find_client_by_pid(pid_t id) +{ + struct agp_client *temp; + + if (agp_fe.current_controller == NULL) + return NULL; + + temp = agp_find_client_in_controller(agp_fe.current_controller, id); + return temp; +} + +static void agp_insert_client(struct agp_client *client) +{ + struct agp_client *prev_client; + + prev_client = agp_fe.current_controller->clients; + client->next = prev_client; + + if (prev_client != NULL) + prev_client->prev = client; + + agp_fe.current_controller->clients = client; + agp_fe.current_controller->num_clients++; +} + +static struct agp_client *agp_create_client(pid_t id) +{ + struct agp_client *new_client; + + new_client = kmalloc(sizeof(struct agp_client), GFP_KERNEL); + + if (new_client == NULL) + return NULL; + + memset(new_client, 0, sizeof(struct agp_client)); + new_client->pid = id; + agp_insert_client(new_client); + return new_client; +} + +static int agp_remove_client(pid_t id) +{ + struct agp_client *client; + struct agp_client *prev_client; + struct agp_client *next_client; + struct agp_controller *controller; + + controller = agp_find_controller_for_client(id); + if (controller == NULL) + return -EINVAL; + + client = agp_find_client_in_controller(controller, id); + if (client == NULL) + return -EINVAL; + + prev_client = client->prev; + next_client = client->next; + + if (prev_client != NULL) { + prev_client->next = next_client; + if (next_client != NULL) + next_client->prev = prev_client; + + } else { + if (next_client != NULL) + next_client->prev = NULL; + controller->clients = next_client; + } + + controller->num_clients--; + agp_remove_seg_from_client(client); + kfree(client); + return 0; +} + +/* End - Routines for managing client lists */ + +/* File Operations */ + +static int agp_mmap(struct file *file, struct vm_area_struct *vma) +{ + unsigned int size, current_size; + unsigned long offset; + struct agp_client *client; + struct agp_file_private *priv = file->private_data; + struct agp_kern_info kerninfo; + + down(&(agp_fe.agp_mutex)); + + if (agp_fe.backend_acquired != TRUE) + goto out_eperm; + + if (!(test_bit(AGP_FF_IS_VALID, &priv->access_flags))) + goto out_eperm; + + agp_copy_info(agp_bridge, &kerninfo); + size = vma->vm_end - vma->vm_start; + current_size = kerninfo.aper_size; + current_size = current_size * 0x100000; + offset = vma->vm_pgoff << PAGE_SHIFT; + DBG("%lx:%lx", offset, offset+size); + + if (test_bit(AGP_FF_IS_CLIENT, &priv->access_flags)) { + if ((size + offset) > current_size) + goto out_inval; + + client = agp_find_client_by_pid(current->pid); + + if (client == NULL) + goto out_eperm; + + if (!agp_find_seg_in_client(client, offset, size, vma->vm_page_prot)) + goto out_inval; + + DBG("client vm_ops=%p", kerninfo.vm_ops); + if (kerninfo.vm_ops) { + vma->vm_ops = kerninfo.vm_ops; + } else if (io_remap_pfn_range(vma, vma->vm_start, + (kerninfo.aper_base + offset) >> PAGE_SHIFT, + size, vma->vm_page_prot)) { + goto out_again; + } + up(&(agp_fe.agp_mutex)); + return 0; + } + + if (test_bit(AGP_FF_IS_CONTROLLER, &priv->access_flags)) { + if (size != current_size) + goto out_inval; + + DBG("controller vm_ops=%p", kerninfo.vm_ops); + if (kerninfo.vm_ops) { + vma->vm_ops = kerninfo.vm_ops; + } else if (io_remap_pfn_range(vma, vma->vm_start, + kerninfo.aper_base >> PAGE_SHIFT, + size, vma->vm_page_prot)) { + goto out_again; + } + up(&(agp_fe.agp_mutex)); + return 0; + } + +out_eperm: + up(&(agp_fe.agp_mutex)); + return -EPERM; + +out_inval: + up(&(agp_fe.agp_mutex)); + return -EINVAL; + +out_again: + up(&(agp_fe.agp_mutex)); + return -EAGAIN; +} + +static int agp_release(struct inode *inode, struct file *file) +{ + struct agp_file_private *priv = file->private_data; + + down(&(agp_fe.agp_mutex)); + + DBG("priv=%p", priv); + + if (test_bit(AGP_FF_IS_CONTROLLER, &priv->access_flags)) { + struct agp_controller *controller; + + controller = agp_find_controller_by_pid(priv->my_pid); + + if (controller != NULL) { + if (controller == agp_fe.current_controller) + agp_controller_release_current(controller, priv); + agp_remove_controller(controller); + controller = NULL; + } + } + + if (test_bit(AGP_FF_IS_CLIENT, &priv->access_flags)) + agp_remove_client(priv->my_pid); + + agp_remove_file_private(priv); + kfree(priv); + file->private_data = NULL; + up(&(agp_fe.agp_mutex)); + return 0; +} + +static int agp_open(struct inode *inode, struct file *file) +{ + int minor = iminor(inode); + struct agp_file_private *priv; + struct agp_client *client; + int rc = -ENXIO; + + down(&(agp_fe.agp_mutex)); + + if (minor != AGPGART_MINOR) + goto err_out; + + priv = kmalloc(sizeof(struct agp_file_private), GFP_KERNEL); + if (priv == NULL) + goto err_out_nomem; + + memset(priv, 0, sizeof(struct agp_file_private)); + set_bit(AGP_FF_ALLOW_CLIENT, &priv->access_flags); + priv->my_pid = current->pid; + + if ((current->uid == 0) || (current->suid == 0)) { + /* Root priv, can be controller */ + set_bit(AGP_FF_ALLOW_CONTROLLER, &priv->access_flags); + } + client = agp_find_client_by_pid(current->pid); + + if (client != NULL) { + set_bit(AGP_FF_IS_CLIENT, &priv->access_flags); + set_bit(AGP_FF_IS_VALID, &priv->access_flags); + } + file->private_data = (void *) priv; + agp_insert_file_private(priv); + DBG("private=%p, client=%p", priv, client); + up(&(agp_fe.agp_mutex)); + return 0; + +err_out_nomem: + rc = -ENOMEM; +err_out: + up(&(agp_fe.agp_mutex)); + return rc; +} + + +static ssize_t agp_read(struct file *file, char __user *buf, + size_t count, loff_t * ppos) +{ + return -EINVAL; +} + +static ssize_t agp_write(struct file *file, const char __user *buf, + size_t count, loff_t * ppos) +{ + return -EINVAL; +} + +static int agpioc_info_wrap(struct agp_file_private *priv, void __user *arg) +{ + struct agp_info userinfo; + struct agp_kern_info kerninfo; + + agp_copy_info(agp_bridge, &kerninfo); + + userinfo.version.major = kerninfo.version.major; + userinfo.version.minor = kerninfo.version.minor; + userinfo.bridge_id = kerninfo.device->vendor | + (kerninfo.device->device << 16); + userinfo.agp_mode = kerninfo.mode; + userinfo.aper_base = kerninfo.aper_base; + userinfo.aper_size = kerninfo.aper_size; + userinfo.pg_total = userinfo.pg_system = kerninfo.max_memory; + userinfo.pg_used = kerninfo.current_memory; + + if (copy_to_user(arg, &userinfo, sizeof(struct agp_info))) + return -EFAULT; + + return 0; +} + +static int agpioc_acquire_wrap(struct agp_file_private *priv) +{ + struct agp_controller *controller; + + DBG(""); + + if (!(test_bit(AGP_FF_ALLOW_CONTROLLER, &priv->access_flags))) + return -EPERM; + + if (agp_fe.current_controller != NULL) + return -EBUSY; + + if(!agp_bridge) + return -ENODEV; + + if (atomic_read(&agp_bridge->agp_in_use)) + return -EBUSY; + + atomic_inc(&agp_bridge->agp_in_use); + + agp_fe.backend_acquired = TRUE; + + controller = agp_find_controller_by_pid(priv->my_pid); + + if (controller != NULL) { + agp_controller_make_current(controller); + } else { + controller = agp_create_controller(priv->my_pid); + + if (controller == NULL) { + agp_fe.backend_acquired = FALSE; + agp_backend_release(agp_bridge); + return -ENOMEM; + } + agp_insert_controller(controller); + agp_controller_make_current(controller); + } + + set_bit(AGP_FF_IS_CONTROLLER, &priv->access_flags); + set_bit(AGP_FF_IS_VALID, &priv->access_flags); + return 0; +} + +static int agpioc_release_wrap(struct agp_file_private *priv) +{ + DBG(""); + agp_controller_release_current(agp_fe.current_controller, priv); + return 0; +} + +static int agpioc_setup_wrap(struct agp_file_private *priv, void __user *arg) +{ + struct agp_setup mode; + + DBG(""); + if (copy_from_user(&mode, arg, sizeof(struct agp_setup))) + return -EFAULT; + + agp_enable(agp_bridge, mode.agp_mode); + return 0; +} + +static int agpioc_reserve_wrap(struct agp_file_private *priv, void __user *arg) +{ + struct agp_region reserve; + struct agp_client *client; + struct agp_file_private *client_priv; + + DBG(""); + if (copy_from_user(&reserve, arg, sizeof(struct agp_region))) + return -EFAULT; + + if ((unsigned) reserve.seg_count >= ~0U/sizeof(struct agp_segment)) + return -EFAULT; + + client = agp_find_client_by_pid(reserve.pid); + + if (reserve.seg_count == 0) { + /* remove a client */ + client_priv = agp_find_private(reserve.pid); + + if (client_priv != NULL) { + set_bit(AGP_FF_IS_CLIENT, &client_priv->access_flags); + set_bit(AGP_FF_IS_VALID, &client_priv->access_flags); + } + if (client == NULL) { + /* client is already removed */ + return 0; + } + return agp_remove_client(reserve.pid); + } else { + struct agp_segment *segment; + + if (reserve.seg_count >= 16384) + return -EINVAL; + + segment = kmalloc((sizeof(struct agp_segment) * reserve.seg_count), + GFP_KERNEL); + + if (segment == NULL) + return -ENOMEM; + + if (copy_from_user(segment, (void __user *) reserve.seg_list, + sizeof(struct agp_segment) * reserve.seg_count)) { + kfree(segment); + return -EFAULT; + } + reserve.seg_list = segment; + + if (client == NULL) { + /* Create the client and add the segment */ + client = agp_create_client(reserve.pid); + + if (client == NULL) { + kfree(segment); + return -ENOMEM; + } + client_priv = agp_find_private(reserve.pid); + + if (client_priv != NULL) { + set_bit(AGP_FF_IS_CLIENT, &client_priv->access_flags); + set_bit(AGP_FF_IS_VALID, &client_priv->access_flags); + } + } + return agp_create_segment(client, &reserve); + } + /* Will never really happen */ + return -EINVAL; +} + +static int agpioc_protect_wrap(struct agp_file_private *priv) +{ + DBG(""); + /* This function is not currently implemented */ + return -EINVAL; +} + +static int agpioc_allocate_wrap(struct agp_file_private *priv, void __user *arg) +{ + struct agp_memory *memory; + struct agp_allocate alloc; + + DBG(""); + if (copy_from_user(&alloc, arg, sizeof(struct agp_allocate))) + return -EFAULT; + + memory = agp_allocate_memory_wrap(alloc.pg_count, alloc.type); + + if (memory == NULL) + return -ENOMEM; + + alloc.key = memory->key; + alloc.physical = memory->physical; + + if (copy_to_user(arg, &alloc, sizeof(struct agp_allocate))) { + agp_free_memory_wrap(memory); + return -EFAULT; + } + return 0; +} + +static int agpioc_deallocate_wrap(struct agp_file_private *priv, int arg) +{ + struct agp_memory *memory; + + DBG(""); + memory = agp_find_mem_by_key(arg); + + if (memory == NULL) + return -EINVAL; + + agp_free_memory_wrap(memory); + return 0; +} + +static int agpioc_bind_wrap(struct agp_file_private *priv, void __user *arg) +{ + struct agp_bind bind_info; + struct agp_memory *memory; + + DBG(""); + if (copy_from_user(&bind_info, arg, sizeof(struct agp_bind))) + return -EFAULT; + + memory = agp_find_mem_by_key(bind_info.key); + + if (memory == NULL) + return -EINVAL; + + return agp_bind_memory(memory, bind_info.pg_start); +} + +static int agpioc_unbind_wrap(struct agp_file_private *priv, void __user *arg) +{ + struct agp_memory *memory; + struct agp_unbind unbind; + + DBG(""); + if (copy_from_user(&unbind, arg, sizeof(struct agp_unbind))) + return -EFAULT; + + memory = agp_find_mem_by_key(unbind.key); + + if (memory == NULL) + return -EINVAL; + + return agp_unbind_memory(memory); +} + +static int agp_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + struct agp_file_private *curr_priv = file->private_data; + int ret_val = -ENOTTY; + + DBG("priv=%p, cmd=%x", curr_priv, cmd); + down(&(agp_fe.agp_mutex)); + + if ((agp_fe.current_controller == NULL) && + (cmd != AGPIOC_ACQUIRE)) { + ret_val = -EINVAL; + goto ioctl_out; + } + if ((agp_fe.backend_acquired != TRUE) && + (cmd != AGPIOC_ACQUIRE)) { + ret_val = -EBUSY; + goto ioctl_out; + } + if (cmd != AGPIOC_ACQUIRE) { + if (!(test_bit(AGP_FF_IS_CONTROLLER, &curr_priv->access_flags))) { + ret_val = -EPERM; + goto ioctl_out; + } + /* Use the original pid of the controller, + * in case it's threaded */ + + if (agp_fe.current_controller->pid != curr_priv->my_pid) { + ret_val = -EBUSY; + goto ioctl_out; + } + } + + switch (cmd) { + case AGPIOC_INFO: + ret_val = agpioc_info_wrap(curr_priv, (void __user *) arg); + break; + + case AGPIOC_ACQUIRE: + ret_val = agpioc_acquire_wrap(curr_priv); + break; + + case AGPIOC_RELEASE: + ret_val = agpioc_release_wrap(curr_priv); + break; + + case AGPIOC_SETUP: + ret_val = agpioc_setup_wrap(curr_priv, (void __user *) arg); + break; + + case AGPIOC_RESERVE: + ret_val = agpioc_reserve_wrap(curr_priv, (void __user *) arg); + break; + + case AGPIOC_PROTECT: + ret_val = agpioc_protect_wrap(curr_priv); + break; + + case AGPIOC_ALLOCATE: + ret_val = agpioc_allocate_wrap(curr_priv, (void __user *) arg); + break; + + case AGPIOC_DEALLOCATE: + ret_val = agpioc_deallocate_wrap(curr_priv, (int) arg); + break; + + case AGPIOC_BIND: + ret_val = agpioc_bind_wrap(curr_priv, (void __user *) arg); + break; + + case AGPIOC_UNBIND: + ret_val = agpioc_unbind_wrap(curr_priv, (void __user *) arg); + break; + } + +ioctl_out: + DBG("ioctl returns %d\n", ret_val); + up(&(agp_fe.agp_mutex)); + return ret_val; +} + +static struct file_operations agp_fops = +{ + .owner = THIS_MODULE, + .llseek = no_llseek, + .read = agp_read, + .write = agp_write, + .ioctl = agp_ioctl, + .mmap = agp_mmap, + .open = agp_open, + .release = agp_release, +}; + +static struct miscdevice agp_miscdev = +{ + .minor = AGPGART_MINOR, + .name = "agpgart", + .fops = &agp_fops +}; + +int agp_frontend_initialize(void) +{ + memset(&agp_fe, 0, sizeof(struct agp_front_data)); + sema_init(&(agp_fe.agp_mutex), 1); + + if (misc_register(&agp_miscdev)) { + printk(KERN_ERR PFX "unable to get minor: %d\n", AGPGART_MINOR); + return -EIO; + } + return 0; +} + +void agp_frontend_cleanup(void) +{ + misc_deregister(&agp_miscdev); +} diff --git a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c new file mode 100644 index 000000000000..c321a924e38a --- /dev/null +++ b/drivers/char/agp/generic.c @@ -0,0 +1,1222 @@ +/* + * AGPGART driver. + * Copyright (C) 2004 Silicon Graphics, Inc. + * Copyright (C) 2002-2005 Dave Jones. + * Copyright (C) 1999 Jeff Hartmann. + * Copyright (C) 1999 Precision Insight, Inc. + * Copyright (C) 1999 Xi Graphics, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * TODO: + * - Allocate more than order 0 pages to avoid too much linear map splitting. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "agp.h" + +__u32 *agp_gatt_table; +int agp_memory_reserved; + +/* + * Needed by the Nforce GART driver for the time being. Would be + * nice to do this some other way instead of needing this export. + */ +EXPORT_SYMBOL_GPL(agp_memory_reserved); + +#if defined(CONFIG_X86) +int map_page_into_agp(struct page *page) +{ + int i; + i = change_page_attr(page, 1, PAGE_KERNEL_NOCACHE); + global_flush_tlb(); + return i; +} +EXPORT_SYMBOL_GPL(map_page_into_agp); + +int unmap_page_from_agp(struct page *page) +{ + int i; + i = change_page_attr(page, 1, PAGE_KERNEL); + global_flush_tlb(); + return i; +} +EXPORT_SYMBOL_GPL(unmap_page_from_agp); +#endif + +/* + * Generic routines for handling agp_memory structures - + * They use the basic page allocation routines to do the brunt of the work. + */ + +void agp_free_key(int key) +{ + if (key < 0) + return; + + if (key < MAXKEY) + clear_bit(key, agp_bridge->key_list); +} +EXPORT_SYMBOL(agp_free_key); + + +static int agp_get_key(void) +{ + int bit; + + bit = find_first_zero_bit(agp_bridge->key_list, MAXKEY); + if (bit < MAXKEY) { + set_bit(bit, agp_bridge->key_list); + return bit; + } + return -1; +} + + +struct agp_memory *agp_create_memory(int scratch_pages) +{ + struct agp_memory *new; + + new = kmalloc(sizeof(struct agp_memory), GFP_KERNEL); + + if (new == NULL) + return NULL; + + memset(new, 0, sizeof(struct agp_memory)); + new->key = agp_get_key(); + + if (new->key < 0) { + kfree(new); + return NULL; + } + new->memory = vmalloc(PAGE_SIZE * scratch_pages); + + if (new->memory == NULL) { + agp_free_key(new->key); + kfree(new); + return NULL; + } + new->num_scratch_pages = scratch_pages; + return new; +} +EXPORT_SYMBOL(agp_create_memory); + +/** + * agp_free_memory - free memory associated with an agp_memory pointer. + * + * @curr: agp_memory pointer to be freed. + * + * It is the only function that can be called when the backend is not owned + * by the caller. (So it can free memory on client death.) + */ +void agp_free_memory(struct agp_memory *curr) +{ + size_t i; + + if (curr == NULL) + return; + + if (curr->is_bound == TRUE) + agp_unbind_memory(curr); + + if (curr->type != 0) { + curr->bridge->driver->free_by_type(curr); + return; + } + if (curr->page_count != 0) { + for (i = 0; i < curr->page_count; i++) { + curr->bridge->driver->agp_destroy_page(phys_to_virt(curr->memory[i])); + } + } + agp_free_key(curr->key); + vfree(curr->memory); + kfree(curr); +} +EXPORT_SYMBOL(agp_free_memory); + +#define ENTRIES_PER_PAGE (PAGE_SIZE / sizeof(unsigned long)) + +/** + * agp_allocate_memory - allocate a group of pages of a certain type. + * + * @page_count: size_t argument of the number of pages + * @type: u32 argument of the type of memory to be allocated. + * + * Every agp bridge device will allow you to allocate AGP_NORMAL_MEMORY which + * maps to physical ram. Any other type is device dependent. + * + * It returns NULL whenever memory is unavailable. + */ +struct agp_memory *agp_allocate_memory(struct agp_bridge_data *bridge, + size_t page_count, u32 type) +{ + int scratch_pages; + struct agp_memory *new; + size_t i; + + if (!bridge) + return NULL; + + if ((atomic_read(&bridge->current_memory_agp) + page_count) > bridge->max_memory_agp) + return NULL; + + if (type != 0) { + new = bridge->driver->alloc_by_type(page_count, type); + if (new) + new->bridge = bridge; + return new; + } + + scratch_pages = (page_count + ENTRIES_PER_PAGE - 1) / ENTRIES_PER_PAGE; + + new = agp_create_memory(scratch_pages); + + if (new == NULL) + return NULL; + + for (i = 0; i < page_count; i++) { + void *addr = bridge->driver->agp_alloc_page(bridge); + + if (addr == NULL) { + agp_free_memory(new); + return NULL; + } + new->memory[i] = virt_to_phys(addr); + new->page_count++; + } + new->bridge = bridge; + + flush_agp_mappings(); + + return new; +} +EXPORT_SYMBOL(agp_allocate_memory); + + +/* End - Generic routines for handling agp_memory structures */ + + +static int agp_return_size(void) +{ + int current_size; + void *temp; + + temp = agp_bridge->current_size; + + switch (agp_bridge->driver->size_type) { + case U8_APER_SIZE: + current_size = A_SIZE_8(temp)->size; + break; + case U16_APER_SIZE: + current_size = A_SIZE_16(temp)->size; + break; + case U32_APER_SIZE: + current_size = A_SIZE_32(temp)->size; + break; + case LVL2_APER_SIZE: + current_size = A_SIZE_LVL2(temp)->size; + break; + case FIXED_APER_SIZE: + current_size = A_SIZE_FIX(temp)->size; + break; + default: + current_size = 0; + break; + } + + current_size -= (agp_memory_reserved / (1024*1024)); + if (current_size <0) + current_size = 0; + return current_size; +} + + +int agp_num_entries(void) +{ + int num_entries; + void *temp; + + temp = agp_bridge->current_size; + + switch (agp_bridge->driver->size_type) { + case U8_APER_SIZE: + num_entries = A_SIZE_8(temp)->num_entries; + break; + case U16_APER_SIZE: + num_entries = A_SIZE_16(temp)->num_entries; + break; + case U32_APER_SIZE: + num_entries = A_SIZE_32(temp)->num_entries; + break; + case LVL2_APER_SIZE: + num_entries = A_SIZE_LVL2(temp)->num_entries; + break; + case FIXED_APER_SIZE: + num_entries = A_SIZE_FIX(temp)->num_entries; + break; + default: + num_entries = 0; + break; + } + + num_entries -= agp_memory_reserved>>PAGE_SHIFT; + if (num_entries<0) + num_entries = 0; + return num_entries; +} +EXPORT_SYMBOL_GPL(agp_num_entries); + + +static int check_bridge_mode(struct pci_dev *dev) +{ + u32 agp3; + u8 cap_ptr; + + cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP); + pci_read_config_dword(dev, cap_ptr+AGPSTAT, &agp3); + if (agp3 & AGPSTAT_MODE_3_0) + return 1; + return 0; +} + + +/** + * agp_copy_info - copy bridge state information + * + * @info: agp_kern_info pointer. The caller should insure that this pointer is valid. + * + * This function copies information about the agp bridge device and the state of + * the agp backend into an agp_kern_info pointer. + */ +int agp_copy_info(struct agp_bridge_data *bridge, struct agp_kern_info *info) +{ + memset(info, 0, sizeof(struct agp_kern_info)); + if (!bridge) { + info->chipset = NOT_SUPPORTED; + return -EIO; + } + + info->version.major = bridge->version->major; + info->version.minor = bridge->version->minor; + info->chipset = SUPPORTED; + info->device = bridge->dev; + if (check_bridge_mode(bridge->dev)) + info->mode = bridge->mode & ~AGP3_RESERVED_MASK; + else + info->mode = bridge->mode & ~AGP2_RESERVED_MASK; + info->mode = bridge->mode; + info->aper_base = bridge->gart_bus_addr; + info->aper_size = agp_return_size(); + info->max_memory = bridge->max_memory_agp; + info->current_memory = atomic_read(&bridge->current_memory_agp); + info->cant_use_aperture = bridge->driver->cant_use_aperture; + info->vm_ops = bridge->vm_ops; + info->page_mask = ~0UL; + return 0; +} +EXPORT_SYMBOL(agp_copy_info); + +/* End - Routine to copy over information structure */ + +/* + * Routines for handling swapping of agp_memory into the GATT - + * These routines take agp_memory and insert them into the GATT. + * They call device specific routines to actually write to the GATT. + */ + +/** + * agp_bind_memory - Bind an agp_memory structure into the GATT. + * + * @curr: agp_memory pointer + * @pg_start: an offset into the graphics aperture translation table + * + * It returns -EINVAL if the pointer == NULL. + * It returns -EBUSY if the area of the table requested is already in use. + */ +int agp_bind_memory(struct agp_memory *curr, off_t pg_start) +{ + int ret_val; + + if (curr == NULL) + return -EINVAL; + + if (curr->is_bound == TRUE) { + printk (KERN_INFO PFX "memory %p is already bound!\n", curr); + return -EINVAL; + } + if (curr->is_flushed == FALSE) { + curr->bridge->driver->cache_flush(); + curr->is_flushed = TRUE; + } + ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type); + + if (ret_val != 0) + return ret_val; + + curr->is_bound = TRUE; + curr->pg_start = pg_start; + return 0; +} +EXPORT_SYMBOL(agp_bind_memory); + + +/** + * agp_unbind_memory - Removes an agp_memory structure from the GATT + * + * @curr: agp_memory pointer to be removed from the GATT. + * + * It returns -EINVAL if this piece of agp_memory is not currently bound to + * the graphics aperture translation table or if the agp_memory pointer == NULL + */ +int agp_unbind_memory(struct agp_memory *curr) +{ + int ret_val; + + if (curr == NULL) + return -EINVAL; + + if (curr->is_bound != TRUE) { + printk (KERN_INFO PFX "memory %p was not bound!\n", curr); + return -EINVAL; + } + + ret_val = curr->bridge->driver->remove_memory(curr, curr->pg_start, curr->type); + + if (ret_val != 0) + return ret_val; + + curr->is_bound = FALSE; + curr->pg_start = 0; + return 0; +} +EXPORT_SYMBOL(agp_unbind_memory); + +/* End - Routines for handling swapping of agp_memory into the GATT */ + + +/* Generic Agp routines - Start */ +static void agp_v2_parse_one(u32 *requested_mode, u32 *bridge_agpstat, u32 *vga_agpstat) +{ + u32 tmp; + + if (*requested_mode & AGP2_RESERVED_MASK) { + printk (KERN_INFO PFX "reserved bits set in mode 0x%x. Fixed.\n", *requested_mode); + *requested_mode &= ~AGP2_RESERVED_MASK; + } + + /* Check the speed bits make sense. Only one should be set. */ + tmp = *requested_mode & 7; + switch (tmp) { + case 0: + printk (KERN_INFO PFX "%s tried to set rate=x0. Setting to x1 mode.\n", current->comm); + *requested_mode |= AGPSTAT2_1X; + break; + case 1: + case 2: + break; + case 3: + *requested_mode &= ~(AGPSTAT2_1X); /* rate=2 */ + break; + case 4: + break; + case 5: + case 6: + case 7: + *requested_mode &= ~(AGPSTAT2_1X|AGPSTAT2_2X); /* rate=4*/ + break; + } + + /* disable SBA if it's not supported */ + if (!((*bridge_agpstat & AGPSTAT_SBA) && (*vga_agpstat & AGPSTAT_SBA) && (*requested_mode & AGPSTAT_SBA))) + *bridge_agpstat &= ~AGPSTAT_SBA; + + /* Set rate */ + if (!((*bridge_agpstat & AGPSTAT2_4X) && (*vga_agpstat & AGPSTAT2_4X) && (*requested_mode & AGPSTAT2_4X))) + *bridge_agpstat &= ~AGPSTAT2_4X; + + if (!((*bridge_agpstat & AGPSTAT2_2X) && (*vga_agpstat & AGPSTAT2_2X) && (*requested_mode & AGPSTAT2_2X))) + *bridge_agpstat &= ~AGPSTAT2_2X; + + if (!((*bridge_agpstat & AGPSTAT2_1X) && (*vga_agpstat & AGPSTAT2_1X) && (*requested_mode & AGPSTAT2_1X))) + *bridge_agpstat &= ~AGPSTAT2_1X; + + /* Now we know what mode it should be, clear out the unwanted bits. */ + if (*bridge_agpstat & AGPSTAT2_4X) + *bridge_agpstat &= ~(AGPSTAT2_1X | AGPSTAT2_2X); /* 4X */ + + if (*bridge_agpstat & AGPSTAT2_2X) + *bridge_agpstat &= ~(AGPSTAT2_1X | AGPSTAT2_4X); /* 2X */ + + if (*bridge_agpstat & AGPSTAT2_1X) + *bridge_agpstat &= ~(AGPSTAT2_2X | AGPSTAT2_4X); /* 1X */ + + /* Apply any errata. */ + if (agp_bridge->flags & AGP_ERRATA_FASTWRITES) + *bridge_agpstat &= ~AGPSTAT_FW; + + if (agp_bridge->flags & AGP_ERRATA_SBA) + *bridge_agpstat &= ~AGPSTAT_SBA; + + if (agp_bridge->flags & AGP_ERRATA_1X) { + *bridge_agpstat &= ~(AGPSTAT2_2X | AGPSTAT2_4X); + *bridge_agpstat |= AGPSTAT2_1X; + } + + /* If we've dropped down to 1X, disable fast writes. */ + if (*bridge_agpstat & AGPSTAT2_1X) + *bridge_agpstat &= ~AGPSTAT_FW; +} + +/* + * requested_mode = Mode requested by (typically) X. + * bridge_agpstat = PCI_AGP_STATUS from agp bridge. + * vga_agpstat = PCI_AGP_STATUS from graphic card. + */ +static void agp_v3_parse_one(u32 *requested_mode, u32 *bridge_agpstat, u32 *vga_agpstat) +{ + u32 origbridge=*bridge_agpstat, origvga=*vga_agpstat; + u32 tmp; + + if (*requested_mode & AGP3_RESERVED_MASK) { + printk (KERN_INFO PFX "reserved bits set in mode 0x%x. Fixed.\n", *requested_mode); + *requested_mode &= ~AGP3_RESERVED_MASK; + } + + /* Check the speed bits make sense. */ + tmp = *requested_mode & 7; + if (tmp == 0) { + printk (KERN_INFO PFX "%s tried to set rate=x0. Setting to AGP3 x4 mode.\n", current->comm); + *requested_mode |= AGPSTAT3_4X; + } + if (tmp >= 3) { + printk (KERN_INFO PFX "%s tried to set rate=x%d. Setting to AGP3 x8 mode.\n", current->comm, tmp * 4); + *requested_mode = (*requested_mode & ~7) | AGPSTAT3_8X; + } + + /* ARQSZ - Set the value to the maximum one. + * Don't allow the mode register to override values. */ + *bridge_agpstat = ((*bridge_agpstat & ~AGPSTAT_ARQSZ) | + max_t(u32,(*bridge_agpstat & AGPSTAT_ARQSZ),(*vga_agpstat & AGPSTAT_ARQSZ))); + + /* Calibration cycle. + * Don't allow the mode register to override values. */ + *bridge_agpstat = ((*bridge_agpstat & ~AGPSTAT_CAL_MASK) | + min_t(u32,(*bridge_agpstat & AGPSTAT_CAL_MASK),(*vga_agpstat & AGPSTAT_CAL_MASK))); + + /* SBA *must* be supported for AGP v3 */ + *bridge_agpstat |= AGPSTAT_SBA; + + /* + * Set speed. + * Check for invalid speeds. This can happen when applications + * written before the AGP 3.0 standard pass AGP2.x modes to AGP3 hardware + */ + if (*requested_mode & AGPSTAT_MODE_3_0) { + /* + * Caller hasn't a clue what it is doing. Bridge is in 3.0 mode, + * have been passed a 3.0 mode, but with 2.x speed bits set. + * AGP2.x 4x -> AGP3.0 4x. + */ + if (*requested_mode & AGPSTAT2_4X) { + printk (KERN_INFO PFX "%s passes broken AGP3 flags (%x). Fixed.\n", + current->comm, *requested_mode); + *requested_mode &= ~AGPSTAT2_4X; + *requested_mode |= AGPSTAT3_4X; + } + } else { + /* + * The caller doesn't know what they are doing. We are in 3.0 mode, + * but have been passed an AGP 2.x mode. + * Convert AGP 1x,2x,4x -> AGP 3.0 4x. + */ + printk (KERN_INFO PFX "%s passes broken AGP2 flags (%x) in AGP3 mode. Fixed.\n", + current->comm, *requested_mode); + *requested_mode &= ~(AGPSTAT2_4X | AGPSTAT2_2X | AGPSTAT2_1X); + *requested_mode |= AGPSTAT3_4X; + } + + if (*requested_mode & AGPSTAT3_8X) { + if (!(*bridge_agpstat & AGPSTAT3_8X)) { + *bridge_agpstat &= ~(AGPSTAT3_8X | AGPSTAT3_RSVD); + *bridge_agpstat |= AGPSTAT3_4X; + printk ("%s requested AGPx8 but bridge not capable.\n", current->comm); + return; + } + if (!(*vga_agpstat & AGPSTAT3_8X)) { + *bridge_agpstat &= ~(AGPSTAT3_8X | AGPSTAT3_RSVD); + *bridge_agpstat |= AGPSTAT3_4X; + printk ("%s requested AGPx8 but graphic card not capable.\n", current->comm); + return; + } + /* All set, bridge & device can do AGP x8*/ + *bridge_agpstat &= ~(AGPSTAT3_4X | AGPSTAT3_RSVD); + goto done; + + } else { + + /* + * If we didn't specify AGPx8, we can only do x4. + * If the hardware can't do x4, we're up shit creek, and never + * should have got this far. + */ + *bridge_agpstat &= ~(AGPSTAT3_8X | AGPSTAT3_RSVD); + if ((*bridge_agpstat & AGPSTAT3_4X) && (*vga_agpstat & AGPSTAT3_4X)) + *bridge_agpstat |= AGPSTAT3_4X; + else { + printk (KERN_INFO PFX "Badness. Don't know which AGP mode to set. " + "[bridge_agpstat:%x vga_agpstat:%x fell back to:- bridge_agpstat:%x vga_agpstat:%x]\n", + origbridge, origvga, *bridge_agpstat, *vga_agpstat); + if (!(*bridge_agpstat & AGPSTAT3_4X)) + printk (KERN_INFO PFX "Bridge couldn't do AGP x4.\n"); + if (!(*vga_agpstat & AGPSTAT3_4X)) + printk (KERN_INFO PFX "Graphic card couldn't do AGP x4.\n"); + return; + } + } + +done: + /* Apply any errata. */ + if (agp_bridge->flags & AGP_ERRATA_FASTWRITES) + *bridge_agpstat &= ~AGPSTAT_FW; + + if (agp_bridge->flags & AGP_ERRATA_SBA) + *bridge_agpstat &= ~AGPSTAT_SBA; + + if (agp_bridge->flags & AGP_ERRATA_1X) { + *bridge_agpstat &= ~(AGPSTAT2_2X | AGPSTAT2_4X); + *bridge_agpstat |= AGPSTAT2_1X; + } +} + + +/** + * agp_collect_device_status - determine correct agp_cmd from various agp_stat's + * @bridge: an agp_bridge_data struct allocated for the AGP host bridge. + * @requested_mode: requested agp_stat from userspace (Typically from X) + * @bridge_agpstat: current agp_stat from AGP bridge. + * + * This function will hunt for an AGP graphics card, and try to match + * the requested mode to the capabilities of both the bridge and the card. + */ +u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 requested_mode, u32 bridge_agpstat) +{ + struct pci_dev *device = NULL; + u32 vga_agpstat; + u8 cap_ptr; + + for (;;) { + device = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, device); + if (!device) { + printk (KERN_INFO PFX "Couldn't find an AGP VGA controller.\n"); + return 0; + } + cap_ptr = pci_find_capability(device, PCI_CAP_ID_AGP); + if (cap_ptr) + break; + } + + /* + * Ok, here we have a AGP device. Disable impossible + * settings, and adjust the readqueue to the minimum. + */ + pci_read_config_dword(device, cap_ptr+PCI_AGP_STATUS, &vga_agpstat); + + /* adjust RQ depth */ + bridge_agpstat = ((bridge_agpstat & ~AGPSTAT_RQ_DEPTH) | + min_t(u32, (requested_mode & AGPSTAT_RQ_DEPTH), + min_t(u32, (bridge_agpstat & AGPSTAT_RQ_DEPTH), (vga_agpstat & AGPSTAT_RQ_DEPTH)))); + + /* disable FW if it's not supported */ + if (!((bridge_agpstat & AGPSTAT_FW) && + (vga_agpstat & AGPSTAT_FW) && + (requested_mode & AGPSTAT_FW))) + bridge_agpstat &= ~AGPSTAT_FW; + + /* Check to see if we are operating in 3.0 mode */ + if (check_bridge_mode(agp_bridge->dev)) + agp_v3_parse_one(&requested_mode, &bridge_agpstat, &vga_agpstat); + else + agp_v2_parse_one(&requested_mode, &bridge_agpstat, &vga_agpstat); + + pci_dev_put(device); + return bridge_agpstat; +} +EXPORT_SYMBOL(agp_collect_device_status); + + +void agp_device_command(u32 bridge_agpstat, int agp_v3) +{ + struct pci_dev *device = NULL; + int mode; + + mode = bridge_agpstat & 0x7; + if (agp_v3) + mode *= 4; + + for_each_pci_dev(device) { + u8 agp = pci_find_capability(device, PCI_CAP_ID_AGP); + if (!agp) + continue; + + printk(KERN_INFO PFX "Putting AGP V%d device at %s into %dx mode\n", + agp_v3 ? 3 : 2, pci_name(device), mode); + pci_write_config_dword(device, agp + PCI_AGP_COMMAND, bridge_agpstat); + } +} +EXPORT_SYMBOL(agp_device_command); + + +void get_agp_version(struct agp_bridge_data *bridge) +{ + u32 ncapid; + + /* Exit early if already set by errata workarounds. */ + if (bridge->major_version != 0) + return; + + pci_read_config_dword(bridge->dev, bridge->capndx, &ncapid); + bridge->major_version = (ncapid >> AGP_MAJOR_VERSION_SHIFT) & 0xf; + bridge->minor_version = (ncapid >> AGP_MINOR_VERSION_SHIFT) & 0xf; +} +EXPORT_SYMBOL(get_agp_version); + + +void agp_generic_enable(struct agp_bridge_data *bridge, u32 requested_mode) +{ + u32 bridge_agpstat, temp; + + get_agp_version(agp_bridge); + + printk(KERN_INFO PFX "Found an AGP %d.%d compliant device at %s.\n", + agp_bridge->major_version, + agp_bridge->minor_version, + pci_name(agp_bridge->dev)); + + pci_read_config_dword(agp_bridge->dev, + agp_bridge->capndx + PCI_AGP_STATUS, &bridge_agpstat); + + bridge_agpstat = agp_collect_device_status(agp_bridge, requested_mode, bridge_agpstat); + if (bridge_agpstat == 0) + /* Something bad happened. FIXME: Return error code? */ + return; + + bridge_agpstat |= AGPSTAT_AGP_ENABLE; + + /* Do AGP version specific frobbing. */ + if (bridge->major_version >= 3) { + if (check_bridge_mode(bridge->dev)) { + /* If we have 3.5, we can do the isoch stuff. */ + if (bridge->minor_version >= 5) + agp_3_5_enable(bridge); + agp_device_command(bridge_agpstat, TRUE); + return; + } else { + /* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/ + bridge_agpstat &= ~(7<<10) ; + pci_read_config_dword(bridge->dev, + bridge->capndx+AGPCTRL, &temp); + temp |= (1<<9); + pci_write_config_dword(bridge->dev, + bridge->capndx+AGPCTRL, temp); + + printk (KERN_INFO PFX "Device is in legacy mode," + " falling back to 2.x\n"); + } + } + + /* AGP v<3 */ + agp_device_command(bridge_agpstat, FALSE); +} +EXPORT_SYMBOL(agp_generic_enable); + + +int agp_generic_create_gatt_table(struct agp_bridge_data *bridge) +{ + char *table; + char *table_end; + int size; + int page_order; + int num_entries; + int i; + void *temp; + struct page *page; + + /* The generic routines can't handle 2 level gatt's */ + if (bridge->driver->size_type == LVL2_APER_SIZE) + return -EINVAL; + + table = NULL; + i = bridge->aperture_size_idx; + temp = bridge->current_size; + size = page_order = num_entries = 0; + + if (bridge->driver->size_type != FIXED_APER_SIZE) { + do { + switch (bridge->driver->size_type) { + case U8_APER_SIZE: + size = A_SIZE_8(temp)->size; + page_order = + A_SIZE_8(temp)->page_order; + num_entries = + A_SIZE_8(temp)->num_entries; + break; + case U16_APER_SIZE: + size = A_SIZE_16(temp)->size; + page_order = A_SIZE_16(temp)->page_order; + num_entries = A_SIZE_16(temp)->num_entries; + break; + case U32_APER_SIZE: + size = A_SIZE_32(temp)->size; + page_order = A_SIZE_32(temp)->page_order; + num_entries = A_SIZE_32(temp)->num_entries; + break; + /* This case will never really happen. */ + case FIXED_APER_SIZE: + case LVL2_APER_SIZE: + default: + size = page_order = num_entries = 0; + break; + } + + table = (char *) __get_free_pages(GFP_KERNEL, + page_order); + + if (table == NULL) { + i++; + switch (bridge->driver->size_type) { + case U8_APER_SIZE: + bridge->current_size = A_IDX8(bridge); + break; + case U16_APER_SIZE: + bridge->current_size = A_IDX16(bridge); + break; + case U32_APER_SIZE: + bridge->current_size = A_IDX32(bridge); + break; + /* This case will never really happen. */ + case FIXED_APER_SIZE: + case LVL2_APER_SIZE: + default: + bridge->current_size = + bridge->current_size; + break; + } + temp = bridge->current_size; + } else { + bridge->aperture_size_idx = i; + } + } while (!table && (i < bridge->driver->num_aperture_sizes)); + } else { + size = ((struct aper_size_info_fixed *) temp)->size; + page_order = ((struct aper_size_info_fixed *) temp)->page_order; + num_entries = ((struct aper_size_info_fixed *) temp)->num_entries; + table = (char *) __get_free_pages(GFP_KERNEL, page_order); + } + + if (table == NULL) + return -ENOMEM; + + table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); + + for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) + SetPageReserved(page); + + bridge->gatt_table_real = (u32 *) table; + agp_gatt_table = (void *)table; + + bridge->driver->cache_flush(); + bridge->gatt_table = ioremap_nocache(virt_to_phys(table), + (PAGE_SIZE * (1 << page_order))); + bridge->driver->cache_flush(); + + if (bridge->gatt_table == NULL) { + for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) + ClearPageReserved(page); + + free_pages((unsigned long) table, page_order); + + return -ENOMEM; + } + bridge->gatt_bus_addr = virt_to_phys(bridge->gatt_table_real); + + /* AK: bogus, should encode addresses > 4GB */ + for (i = 0; i < num_entries; i++) { + writel(bridge->scratch_page, bridge->gatt_table+i); + readl(bridge->gatt_table+i); /* PCI Posting. */ + } + + return 0; +} +EXPORT_SYMBOL(agp_generic_create_gatt_table); + +int agp_generic_free_gatt_table(struct agp_bridge_data *bridge) +{ + int page_order; + char *table, *table_end; + void *temp; + struct page *page; + + temp = bridge->current_size; + + switch (bridge->driver->size_type) { + case U8_APER_SIZE: + page_order = A_SIZE_8(temp)->page_order; + break; + case U16_APER_SIZE: + page_order = A_SIZE_16(temp)->page_order; + break; + case U32_APER_SIZE: + page_order = A_SIZE_32(temp)->page_order; + break; + case FIXED_APER_SIZE: + page_order = A_SIZE_FIX(temp)->page_order; + break; + case LVL2_APER_SIZE: + /* The generic routines can't deal with 2 level gatt's */ + return -EINVAL; + break; + default: + page_order = 0; + break; + } + + /* Do not worry about freeing memory, because if this is + * called, then all agp memory is deallocated and removed + * from the table. */ + + iounmap(bridge->gatt_table); + table = (char *) bridge->gatt_table_real; + table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); + + for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) + ClearPageReserved(page); + + free_pages((unsigned long) bridge->gatt_table_real, page_order); + + agp_gatt_table = NULL; + bridge->gatt_table = NULL; + bridge->gatt_table_real = NULL; + bridge->gatt_bus_addr = 0; + + return 0; +} +EXPORT_SYMBOL(agp_generic_free_gatt_table); + + +int agp_generic_insert_memory(struct agp_memory * mem, off_t pg_start, int type) +{ + int num_entries; + size_t i; + off_t j; + void *temp; + struct agp_bridge_data *bridge; + + bridge = mem->bridge; + if (!bridge) + return -EINVAL; + + temp = bridge->current_size; + + switch (bridge->driver->size_type) { + case U8_APER_SIZE: + num_entries = A_SIZE_8(temp)->num_entries; + break; + case U16_APER_SIZE: + num_entries = A_SIZE_16(temp)->num_entries; + break; + case U32_APER_SIZE: + num_entries = A_SIZE_32(temp)->num_entries; + break; + case FIXED_APER_SIZE: + num_entries = A_SIZE_FIX(temp)->num_entries; + break; + case LVL2_APER_SIZE: + /* The generic routines can't deal with 2 level gatt's */ + return -EINVAL; + break; + default: + num_entries = 0; + break; + } + + num_entries -= agp_memory_reserved/PAGE_SIZE; + if (num_entries < 0) num_entries = 0; + + if (type != 0 || mem->type != 0) { + /* The generic routines know nothing of memory types */ + return -EINVAL; + } + + /* AK: could wrap */ + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + + j = pg_start; + + while (j < (pg_start + mem->page_count)) { + if (!PGE_EMPTY(bridge, readl(bridge->gatt_table+j))) + return -EBUSY; + j++; + } + + if (mem->is_flushed == FALSE) { + bridge->driver->cache_flush(); + mem->is_flushed = TRUE; + } + + for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { + writel(bridge->driver->mask_memory(bridge, mem->memory[i], mem->type), bridge->gatt_table+j); + readl(bridge->gatt_table+j); /* PCI Posting. */ + } + + bridge->driver->tlb_flush(mem); + return 0; +} +EXPORT_SYMBOL(agp_generic_insert_memory); + + +int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type) +{ + size_t i; + struct agp_bridge_data *bridge; + + bridge = mem->bridge; + if (!bridge) + return -EINVAL; + + if (type != 0 || mem->type != 0) { + /* The generic routines know nothing of memory types */ + return -EINVAL; + } + + /* AK: bogus, should encode addresses > 4GB */ + for (i = pg_start; i < (mem->page_count + pg_start); i++) { + writel(bridge->scratch_page, bridge->gatt_table+i); + readl(bridge->gatt_table+i); /* PCI Posting. */ + } + + global_cache_flush(); + bridge->driver->tlb_flush(mem); + return 0; +} +EXPORT_SYMBOL(agp_generic_remove_memory); + + +struct agp_memory *agp_generic_alloc_by_type(size_t page_count, int type) +{ + return NULL; +} +EXPORT_SYMBOL(agp_generic_alloc_by_type); + + +void agp_generic_free_by_type(struct agp_memory *curr) +{ + vfree(curr->memory); + agp_free_key(curr->key); + kfree(curr); +} +EXPORT_SYMBOL(agp_generic_free_by_type); + + +/* + * Basic Page Allocation Routines - + * These routines handle page allocation and by default they reserve the allocated + * memory. They also handle incrementing the current_memory_agp value, Which is checked + * against a maximum value. + */ + +void *agp_generic_alloc_page(struct agp_bridge_data *bridge) +{ + struct page * page; + + page = alloc_page(GFP_KERNEL); + if (page == NULL) + return NULL; + + map_page_into_agp(page); + + get_page(page); + SetPageLocked(page); + atomic_inc(&agp_bridge->current_memory_agp); + return page_address(page); +} +EXPORT_SYMBOL(agp_generic_alloc_page); + + +void agp_generic_destroy_page(void *addr) +{ + struct page *page; + + if (addr == NULL) + return; + + page = virt_to_page(addr); + unmap_page_from_agp(page); + put_page(page); + unlock_page(page); + free_page((unsigned long)addr); + atomic_dec(&agp_bridge->current_memory_agp); +} +EXPORT_SYMBOL(agp_generic_destroy_page); + +/* End Basic Page Allocation Routines */ + + +/** + * agp_enable - initialise the agp point-to-point connection. + * + * @mode: agp mode register value to configure with. + */ +void agp_enable(struct agp_bridge_data *bridge, u32 mode) +{ + if (!bridge) + return; + bridge->driver->agp_enable(bridge, mode); +} +EXPORT_SYMBOL(agp_enable); + +/* When we remove the global variable agp_bridge from all drivers + * then agp_alloc_bridge and agp_generic_find_bridge need to be updated + */ + +struct agp_bridge_data *agp_generic_find_bridge(struct pci_dev *pdev) +{ + if (list_empty(&agp_bridges)) + return NULL; + + return agp_bridge; +} + +static void ipi_handler(void *null) +{ + flush_agp_cache(); +} + +void global_cache_flush(void) +{ + if (on_each_cpu(ipi_handler, NULL, 1, 1) != 0) + panic(PFX "timed out waiting for the other CPUs!\n"); +} +EXPORT_SYMBOL(global_cache_flush); + +unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge, + unsigned long addr, int type) +{ + /* memory type is ignored in the generic routine */ + if (bridge->driver->masks) + return addr | bridge->driver->masks[0].mask; + else + return addr; +} +EXPORT_SYMBOL(agp_generic_mask_memory); + +/* + * These functions are implemented according to the AGPv3 spec, + * which covers implementation details that had previously been + * left open. + */ + +int agp3_generic_fetch_size(void) +{ + u16 temp_size; + int i; + struct aper_size_info_16 *values; + + pci_read_config_word(agp_bridge->dev, agp_bridge->capndx+AGPAPSIZE, &temp_size); + values = A_SIZE_16(agp_bridge->driver->aperture_sizes); + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp_size == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + return 0; +} +EXPORT_SYMBOL(agp3_generic_fetch_size); + +void agp3_generic_tlbflush(struct agp_memory *mem) +{ + u32 ctrl; + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+AGPCTRL, &ctrl); + pci_write_config_dword(agp_bridge->dev, agp_bridge->capndx+AGPCTRL, ctrl & ~AGPCTRL_GTLBEN); + pci_write_config_dword(agp_bridge->dev, agp_bridge->capndx+AGPCTRL, ctrl); +} +EXPORT_SYMBOL(agp3_generic_tlbflush); + +int agp3_generic_configure(void) +{ + u32 temp; + struct aper_size_info_16 *current_size; + + current_size = A_SIZE_16(agp_bridge->current_size); + + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* set aperture size */ + pci_write_config_word(agp_bridge->dev, agp_bridge->capndx+AGPAPSIZE, current_size->size_value); + /* set gart pointer */ + pci_write_config_dword(agp_bridge->dev, agp_bridge->capndx+AGPGARTLO, agp_bridge->gatt_bus_addr); + /* enable aperture and GTLB */ + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+AGPCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, agp_bridge->capndx+AGPCTRL, temp | AGPCTRL_APERENB | AGPCTRL_GTLBEN); + return 0; +} +EXPORT_SYMBOL(agp3_generic_configure); + +void agp3_generic_cleanup(void) +{ + u32 ctrl; + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+AGPCTRL, &ctrl); + pci_write_config_dword(agp_bridge->dev, agp_bridge->capndx+AGPCTRL, ctrl & ~AGPCTRL_APERENB); +} +EXPORT_SYMBOL(agp3_generic_cleanup); + +struct aper_size_info_16 agp3_generic_sizes[AGP_GENERIC_SIZES_ENTRIES] = +{ + {4096, 1048576, 10,0x000}, + {2048, 524288, 9, 0x800}, + {1024, 262144, 8, 0xc00}, + { 512, 131072, 7, 0xe00}, + { 256, 65536, 6, 0xf00}, + { 128, 32768, 5, 0xf20}, + { 64, 16384, 4, 0xf30}, + { 32, 8192, 3, 0xf38}, + { 16, 4096, 2, 0xf3c}, + { 8, 2048, 1, 0xf3e}, + { 4, 1024, 0, 0xf3f} +}; +EXPORT_SYMBOL(agp3_generic_sizes); + diff --git a/drivers/char/agp/hp-agp.c b/drivers/char/agp/hp-agp.c new file mode 100644 index 000000000000..6052bfa04c72 --- /dev/null +++ b/drivers/char/agp/hp-agp.c @@ -0,0 +1,552 @@ +/* + * HP zx1 AGPGART routines. + * + * (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P. + * Bjorn Helgaas + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include "agp.h" + +#ifndef log2 +#define log2(x) ffz(~(x)) +#endif + +#define HP_ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */ + +/* HP ZX1 IOC registers */ +#define HP_ZX1_IBASE 0x300 +#define HP_ZX1_IMASK 0x308 +#define HP_ZX1_PCOM 0x310 +#define HP_ZX1_TCNFG 0x318 +#define HP_ZX1_PDIR_BASE 0x320 + +#define HP_ZX1_IOVA_BASE GB(1UL) +#define HP_ZX1_IOVA_SIZE GB(1UL) +#define HP_ZX1_GART_SIZE (HP_ZX1_IOVA_SIZE / 2) +#define HP_ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL + +#define HP_ZX1_PDIR_VALID_BIT 0x8000000000000000UL +#define HP_ZX1_IOVA_TO_PDIR(va) ((va - hp_private.iova_base) >> hp_private.io_tlb_shift) + +#define AGP8X_MODE_BIT 3 +#define AGP8X_MODE (1 << AGP8X_MODE_BIT) + +/* AGP bridge need not be PCI device, but DRM thinks it is. */ +static struct pci_dev fake_bridge_dev; + +static int hp_zx1_gart_found; + +static struct aper_size_info_fixed hp_zx1_sizes[] = +{ + {0, 0, 0}, /* filled in by hp_zx1_fetch_size() */ +}; + +static struct gatt_mask hp_zx1_masks[] = +{ + {.mask = HP_ZX1_PDIR_VALID_BIT, .type = 0} +}; + +static struct _hp_private { + volatile u8 __iomem *ioc_regs; + volatile u8 __iomem *lba_regs; + int lba_cap_offset; + u64 *io_pdir; // PDIR for entire IOVA + u64 *gatt; // PDIR just for GART (subset of above) + u64 gatt_entries; + u64 iova_base; + u64 gart_base; + u64 gart_size; + u64 io_pdir_size; + int io_pdir_owner; // do we own it, or share it with sba_iommu? + int io_page_size; + int io_tlb_shift; + int io_tlb_ps; // IOC ps config + int io_pages_per_kpage; +} hp_private; + +static int __init hp_zx1_ioc_shared(void) +{ + struct _hp_private *hp = &hp_private; + + printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR shared with sba_iommu\n"); + + /* + * IOC already configured by sba_iommu module; just use + * its setup. We assume: + * - IOVA space is 1Gb in size + * - first 512Mb is IOMMU, second 512Mb is GART + */ + hp->io_tlb_ps = readq(hp->ioc_regs+HP_ZX1_TCNFG); + switch (hp->io_tlb_ps) { + case 0: hp->io_tlb_shift = 12; break; + case 1: hp->io_tlb_shift = 13; break; + case 2: hp->io_tlb_shift = 14; break; + case 3: hp->io_tlb_shift = 16; break; + default: + printk(KERN_ERR PFX "Invalid IOTLB page size " + "configuration 0x%x\n", hp->io_tlb_ps); + hp->gatt = NULL; + hp->gatt_entries = 0; + return -ENODEV; + } + hp->io_page_size = 1 << hp->io_tlb_shift; + hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size; + + hp->iova_base = readq(hp->ioc_regs+HP_ZX1_IBASE) & ~0x1; + hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - HP_ZX1_GART_SIZE; + + hp->gart_size = HP_ZX1_GART_SIZE; + hp->gatt_entries = hp->gart_size / hp->io_page_size; + + hp->io_pdir = phys_to_virt(readq(hp->ioc_regs+HP_ZX1_PDIR_BASE)); + hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)]; + + if (hp->gatt[0] != HP_ZX1_SBA_IOMMU_COOKIE) { + /* Normal case when no AGP device in system */ + hp->gatt = NULL; + hp->gatt_entries = 0; + printk(KERN_ERR PFX "No reserved IO PDIR entry found; " + "GART disabled\n"); + return -ENODEV; + } + + return 0; +} + +static int __init +hp_zx1_ioc_owner (void) +{ + struct _hp_private *hp = &hp_private; + + printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR dedicated to GART\n"); + + /* + * Select an IOV page size no larger than system page size. + */ + if (PAGE_SIZE >= KB(64)) { + hp->io_tlb_shift = 16; + hp->io_tlb_ps = 3; + } else if (PAGE_SIZE >= KB(16)) { + hp->io_tlb_shift = 14; + hp->io_tlb_ps = 2; + } else if (PAGE_SIZE >= KB(8)) { + hp->io_tlb_shift = 13; + hp->io_tlb_ps = 1; + } else { + hp->io_tlb_shift = 12; + hp->io_tlb_ps = 0; + } + hp->io_page_size = 1 << hp->io_tlb_shift; + hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size; + + hp->iova_base = HP_ZX1_IOVA_BASE; + hp->gart_size = HP_ZX1_GART_SIZE; + hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - hp->gart_size; + + hp->gatt_entries = hp->gart_size / hp->io_page_size; + hp->io_pdir_size = (HP_ZX1_IOVA_SIZE / hp->io_page_size) * sizeof(u64); + + return 0; +} + +static int __init +hp_zx1_ioc_init (u64 hpa) +{ + struct _hp_private *hp = &hp_private; + + hp->ioc_regs = ioremap(hpa, 1024); + if (!hp->ioc_regs) + return -ENOMEM; + + /* + * If the IOTLB is currently disabled, we can take it over. + * Otherwise, we have to share with sba_iommu. + */ + hp->io_pdir_owner = (readq(hp->ioc_regs+HP_ZX1_IBASE) & 0x1) == 0; + + if (hp->io_pdir_owner) + return hp_zx1_ioc_owner(); + + return hp_zx1_ioc_shared(); +} + +static int +hp_zx1_lba_find_capability (volatile u8 __iomem *hpa, int cap) +{ + u16 status; + u8 pos, id; + int ttl = 48; + + status = readw(hpa+PCI_STATUS); + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + pos = readb(hpa+PCI_CAPABILITY_LIST); + while (ttl-- && pos >= 0x40) { + pos &= ~3; + id = readb(hpa+pos+PCI_CAP_LIST_ID); + if (id == 0xff) + break; + if (id == cap) + return pos; + pos = readb(hpa+pos+PCI_CAP_LIST_NEXT); + } + return 0; +} + +static int __init +hp_zx1_lba_init (u64 hpa) +{ + struct _hp_private *hp = &hp_private; + int cap; + + hp->lba_regs = ioremap(hpa, 256); + if (!hp->lba_regs) + return -ENOMEM; + + hp->lba_cap_offset = hp_zx1_lba_find_capability(hp->lba_regs, PCI_CAP_ID_AGP); + + cap = readl(hp->lba_regs+hp->lba_cap_offset) & 0xff; + if (cap != PCI_CAP_ID_AGP) { + printk(KERN_ERR PFX "Invalid capability ID 0x%02x at 0x%x\n", + cap, hp->lba_cap_offset); + return -ENODEV; + } + + return 0; +} + +static int +hp_zx1_fetch_size(void) +{ + int size; + + size = hp_private.gart_size / MB(1); + hp_zx1_sizes[0].size = size; + agp_bridge->current_size = (void *) &hp_zx1_sizes[0]; + return size; +} + +static int +hp_zx1_configure (void) +{ + struct _hp_private *hp = &hp_private; + + agp_bridge->gart_bus_addr = hp->gart_base; + agp_bridge->capndx = hp->lba_cap_offset; + agp_bridge->mode = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS); + + if (hp->io_pdir_owner) { + writel(virt_to_phys(hp->io_pdir), hp->ioc_regs+HP_ZX1_PDIR_BASE); + readl(hp->ioc_regs+HP_ZX1_PDIR_BASE); + writel(hp->io_tlb_ps, hp->ioc_regs+HP_ZX1_TCNFG); + readl(hp->ioc_regs+HP_ZX1_TCNFG); + writel(~(HP_ZX1_IOVA_SIZE-1), hp->ioc_regs+HP_ZX1_IMASK); + readl(hp->ioc_regs+HP_ZX1_IMASK); + writel(hp->iova_base|1, hp->ioc_regs+HP_ZX1_IBASE); + readl(hp->ioc_regs+HP_ZX1_IBASE); + writel(hp->iova_base|log2(HP_ZX1_IOVA_SIZE), hp->ioc_regs+HP_ZX1_PCOM); + readl(hp->ioc_regs+HP_ZX1_PCOM); + } + + return 0; +} + +static void +hp_zx1_cleanup (void) +{ + struct _hp_private *hp = &hp_private; + + if (hp->ioc_regs) { + if (hp->io_pdir_owner) { + writeq(0, hp->ioc_regs+HP_ZX1_IBASE); + readq(hp->ioc_regs+HP_ZX1_IBASE); + } + iounmap(hp->ioc_regs); + } + if (hp->lba_regs) + iounmap(hp->lba_regs); +} + +static void +hp_zx1_tlbflush (struct agp_memory *mem) +{ + struct _hp_private *hp = &hp_private; + + writeq(hp->gart_base | log2(hp->gart_size), hp->ioc_regs+HP_ZX1_PCOM); + readq(hp->ioc_regs+HP_ZX1_PCOM); +} + +static int +hp_zx1_create_gatt_table (struct agp_bridge_data *bridge) +{ + struct _hp_private *hp = &hp_private; + int i; + + if (hp->io_pdir_owner) { + hp->io_pdir = (u64 *) __get_free_pages(GFP_KERNEL, + get_order(hp->io_pdir_size)); + if (!hp->io_pdir) { + printk(KERN_ERR PFX "Couldn't allocate contiguous " + "memory for I/O PDIR\n"); + hp->gatt = NULL; + hp->gatt_entries = 0; + return -ENOMEM; + } + memset(hp->io_pdir, 0, hp->io_pdir_size); + + hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)]; + } + + for (i = 0; i < hp->gatt_entries; i++) { + hp->gatt[i] = (unsigned long) agp_bridge->scratch_page; + } + + return 0; +} + +static int +hp_zx1_free_gatt_table (struct agp_bridge_data *bridge) +{ + struct _hp_private *hp = &hp_private; + + if (hp->io_pdir_owner) + free_pages((unsigned long) hp->io_pdir, + get_order(hp->io_pdir_size)); + else + hp->gatt[0] = HP_ZX1_SBA_IOMMU_COOKIE; + return 0; +} + +static int +hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type) +{ + struct _hp_private *hp = &hp_private; + int i, k; + off_t j, io_pg_start; + int io_pg_count; + + if (type != 0 || mem->type != 0) { + return -EINVAL; + } + + io_pg_start = hp->io_pages_per_kpage * pg_start; + io_pg_count = hp->io_pages_per_kpage * mem->page_count; + if ((io_pg_start + io_pg_count) > hp->gatt_entries) { + return -EINVAL; + } + + j = io_pg_start; + while (j < (io_pg_start + io_pg_count)) { + if (hp->gatt[j]) { + return -EBUSY; + } + j++; + } + + if (mem->is_flushed == FALSE) { + global_cache_flush(); + mem->is_flushed = TRUE; + } + + for (i = 0, j = io_pg_start; i < mem->page_count; i++) { + unsigned long paddr; + + paddr = mem->memory[i]; + for (k = 0; + k < hp->io_pages_per_kpage; + k++, j++, paddr += hp->io_page_size) { + hp->gatt[j] = + agp_bridge->driver->mask_memory(agp_bridge, + paddr, type); + } + } + + agp_bridge->driver->tlb_flush(mem); + return 0; +} + +static int +hp_zx1_remove_memory (struct agp_memory *mem, off_t pg_start, int type) +{ + struct _hp_private *hp = &hp_private; + int i, io_pg_start, io_pg_count; + + if (type != 0 || mem->type != 0) { + return -EINVAL; + } + + io_pg_start = hp->io_pages_per_kpage * pg_start; + io_pg_count = hp->io_pages_per_kpage * mem->page_count; + for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) { + hp->gatt[i] = agp_bridge->scratch_page; + } + + agp_bridge->driver->tlb_flush(mem); + return 0; +} + +static unsigned long +hp_zx1_mask_memory (struct agp_bridge_data *bridge, + unsigned long addr, int type) +{ + return HP_ZX1_PDIR_VALID_BIT | addr; +} + +static void +hp_zx1_enable (struct agp_bridge_data *bridge, u32 mode) +{ + struct _hp_private *hp = &hp_private; + u32 command; + + command = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS); + command = agp_collect_device_status(bridge, mode, command); + command |= 0x00000100; + + writel(command, hp->lba_regs+hp->lba_cap_offset+PCI_AGP_COMMAND); + + agp_device_command(command, (mode & AGP8X_MODE) != 0); +} + +struct agp_bridge_driver hp_zx1_driver = { + .owner = THIS_MODULE, + .size_type = FIXED_APER_SIZE, + .configure = hp_zx1_configure, + .fetch_size = hp_zx1_fetch_size, + .cleanup = hp_zx1_cleanup, + .tlb_flush = hp_zx1_tlbflush, + .mask_memory = hp_zx1_mask_memory, + .masks = hp_zx1_masks, + .agp_enable = hp_zx1_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = hp_zx1_create_gatt_table, + .free_gatt_table = hp_zx1_free_gatt_table, + .insert_memory = hp_zx1_insert_memory, + .remove_memory = hp_zx1_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, + .cant_use_aperture = 1, +}; + +static int __init +hp_zx1_setup (u64 ioc_hpa, u64 lba_hpa) +{ + struct agp_bridge_data *bridge; + int error = 0; + + error = hp_zx1_ioc_init(ioc_hpa); + if (error) + goto fail; + + error = hp_zx1_lba_init(lba_hpa); + if (error) + goto fail; + + bridge = agp_alloc_bridge(); + if (!bridge) { + error = -ENOMEM; + goto fail; + } + bridge->driver = &hp_zx1_driver; + + fake_bridge_dev.vendor = PCI_VENDOR_ID_HP; + fake_bridge_dev.device = PCI_DEVICE_ID_HP_PCIX_LBA; + bridge->dev = &fake_bridge_dev; + + error = agp_add_bridge(bridge); + fail: + if (error) + hp_zx1_cleanup(); + return error; +} + +static acpi_status __init +zx1_gart_probe (acpi_handle obj, u32 depth, void *context, void **ret) +{ + acpi_handle handle, parent; + acpi_status status; + struct acpi_buffer buffer; + struct acpi_device_info *info; + u64 lba_hpa, sba_hpa, length; + int match; + + status = hp_acpi_csr_space(obj, &lba_hpa, &length); + if (ACPI_FAILURE(status)) + return AE_OK; /* keep looking for another bridge */ + + /* Look for an enclosing IOC scope and find its CSR space */ + handle = obj; + do { + buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER; + status = acpi_get_object_info(handle, &buffer); + if (ACPI_SUCCESS(status)) { + /* TBD check _CID also */ + info = buffer.pointer; + info->hardware_id.value[sizeof(info->hardware_id)-1] = '\0'; + match = (strcmp(info->hardware_id.value, "HWP0001") == 0); + ACPI_MEM_FREE(info); + if (match) { + status = hp_acpi_csr_space(handle, &sba_hpa, &length); + if (ACPI_SUCCESS(status)) + break; + else { + printk(KERN_ERR PFX "Detected HP ZX1 " + "AGP LBA but no IOC.\n"); + return AE_OK; + } + } + } + + status = acpi_get_parent(handle, &parent); + handle = parent; + } while (ACPI_SUCCESS(status)); + + if (hp_zx1_setup(sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa)) + return AE_OK; + + printk(KERN_INFO PFX "Detected HP ZX1 %s AGP chipset (ioc=%lx, lba=%lx)\n", + (char *) context, sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa); + + hp_zx1_gart_found = 1; + return AE_CTRL_TERMINATE; /* we only support one bridge; quit looking */ +} + +static int __init +agp_hp_init (void) +{ + if (agp_off) + return -EINVAL; + + acpi_get_devices("HWP0003", zx1_gart_probe, "HWP0003", NULL); + if (hp_zx1_gart_found) + return 0; + + acpi_get_devices("HWP0007", zx1_gart_probe, "HWP0007", NULL); + if (hp_zx1_gart_found) + return 0; + + return -ENODEV; +} + +static void __exit +agp_hp_cleanup (void) +{ +} + +module_init(agp_hp_init); +module_exit(agp_hp_cleanup); + +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/agp/i460-agp.c b/drivers/char/agp/i460-agp.c new file mode 100644 index 000000000000..adbea896c0d2 --- /dev/null +++ b/drivers/char/agp/i460-agp.c @@ -0,0 +1,642 @@ +/* + * For documentation on the i460 AGP interface, see Chapter 7 (AGP Subsystem) of + * the "Intel 460GTX Chipset Software Developer's Manual": + * http://developer.intel.com/design/itanium/downloads/24870401s.htm + */ +/* + * 460GX support by Chris Ahna + * Clean up & simplification by David Mosberger-Tang + */ +#include +#include +#include +#include + +#include "agp.h" + +#define INTEL_I460_BAPBASE 0x98 +#define INTEL_I460_GXBCTL 0xa0 +#define INTEL_I460_AGPSIZ 0xa2 +#define INTEL_I460_ATTBASE 0xfe200000 +#define INTEL_I460_GATT_VALID (1UL << 24) +#define INTEL_I460_GATT_COHERENT (1UL << 25) + +/* + * The i460 can operate with large (4MB) pages, but there is no sane way to support this + * within the current kernel/DRM environment, so we disable the relevant code for now. + * See also comments in ia64_alloc_page()... + */ +#define I460_LARGE_IO_PAGES 0 + +#if I460_LARGE_IO_PAGES +# define I460_IO_PAGE_SHIFT i460.io_page_shift +#else +# define I460_IO_PAGE_SHIFT 12 +#endif + +#define I460_IOPAGES_PER_KPAGE (PAGE_SIZE >> I460_IO_PAGE_SHIFT) +#define I460_KPAGES_PER_IOPAGE (1 << (I460_IO_PAGE_SHIFT - PAGE_SHIFT)) +#define I460_SRAM_IO_DISABLE (1 << 4) +#define I460_BAPBASE_ENABLE (1 << 3) +#define I460_AGPSIZ_MASK 0x7 +#define I460_4M_PS (1 << 1) + +/* Control bits for Out-Of-GART coherency and Burst Write Combining */ +#define I460_GXBCTL_OOG (1UL << 0) +#define I460_GXBCTL_BWC (1UL << 2) + +/* + * gatt_table entries are 32-bits wide on the i460; the generic code ought to declare the + * gatt_table and gatt_table_real pointers a "void *"... + */ +#define RD_GATT(index) readl((u32 *) i460.gatt + (index)) +#define WR_GATT(index, val) writel((val), (u32 *) i460.gatt + (index)) +/* + * The 460 spec says we have to read the last location written to make sure that all + * writes have taken effect + */ +#define WR_FLUSH_GATT(index) RD_GATT(index) + +#define log2(x) ffz(~(x)) + +static struct { + void *gatt; /* ioremap'd GATT area */ + + /* i460 supports multiple GART page sizes, so GART pageshift is dynamic: */ + u8 io_page_shift; + + /* BIOS configures chipset to one of 2 possible apbase values: */ + u8 dynamic_apbase; + + /* structure for tracking partial use of 4MB GART pages: */ + struct lp_desc { + unsigned long *alloced_map; /* bitmap of kernel-pages in use */ + int refcount; /* number of kernel pages using the large page */ + u64 paddr; /* physical address of large page */ + } *lp_desc; +} i460; + +static struct aper_size_info_8 i460_sizes[3] = +{ + /* + * The 32GB aperture is only available with a 4M GART page size. Due to the + * dynamic GART page size, we can't figure out page_order or num_entries until + * runtime. + */ + {32768, 0, 0, 4}, + {1024, 0, 0, 2}, + {256, 0, 0, 1} +}; + +static struct gatt_mask i460_masks[] = +{ + { + .mask = INTEL_I460_GATT_VALID | INTEL_I460_GATT_COHERENT, + .type = 0 + } +}; + +static int i460_fetch_size (void) +{ + int i; + u8 temp; + struct aper_size_info_8 *values; + + /* Determine the GART page size */ + pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp); + i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12; + pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift); + + if (i460.io_page_shift != I460_IO_PAGE_SHIFT) { + printk(KERN_ERR PFX + "I/O (GART) page-size %ZuKB doesn't match expected size %ZuKB\n", + 1UL << (i460.io_page_shift - 10), 1UL << (I460_IO_PAGE_SHIFT)); + return 0; + } + + values = A_SIZE_8(agp_bridge->driver->aperture_sizes); + + pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp); + + /* Exit now if the IO drivers for the GART SRAMS are turned off */ + if (temp & I460_SRAM_IO_DISABLE) { + printk(KERN_ERR PFX "GART SRAMS disabled on 460GX chipset\n"); + printk(KERN_ERR PFX "AGPGART operation not possible\n"); + return 0; + } + + /* Make sure we don't try to create an 2 ^ 23 entry GATT */ + if ((i460.io_page_shift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) { + printk(KERN_ERR PFX "We can't have a 32GB aperture with 4KB GART pages\n"); + return 0; + } + + /* Determine the proper APBASE register */ + if (temp & I460_BAPBASE_ENABLE) + i460.dynamic_apbase = INTEL_I460_BAPBASE; + else + i460.dynamic_apbase = AGP_APBASE; + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + /* + * Dynamically calculate the proper num_entries and page_order values for + * the define aperture sizes. Take care not to shift off the end of + * values[i].size. + */ + values[i].num_entries = (values[i].size << 8) >> (I460_IO_PAGE_SHIFT - 12); + values[i].page_order = log2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT); + } + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + /* Neglect control bits when matching up size_value */ + if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) { + agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + + return 0; +} + +/* There isn't anything to do here since 460 has no GART TLB. */ +static void i460_tlb_flush (struct agp_memory *mem) +{ + return; +} + +/* + * This utility function is needed to prevent corruption of the control bits + * which are stored along with the aperture size in 460's AGPSIZ register + */ +static void i460_write_agpsiz (u8 size_value) +{ + u8 temp; + + pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp); + pci_write_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, + ((temp & ~I460_AGPSIZ_MASK) | size_value)); +} + +static void i460_cleanup (void) +{ + struct aper_size_info_8 *previous_size; + + previous_size = A_SIZE_8(agp_bridge->previous_size); + i460_write_agpsiz(previous_size->size_value); + + if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) + kfree(i460.lp_desc); +} + +static int i460_configure (void) +{ + union { + u32 small[2]; + u64 large; + } temp; + size_t size; + u8 scratch; + struct aper_size_info_8 *current_size; + + temp.large = 0; + + current_size = A_SIZE_8(agp_bridge->current_size); + i460_write_agpsiz(current_size->size_value); + + /* + * Do the necessary rigmarole to read all eight bytes of APBASE. + * This has to be done since the AGP aperture can be above 4GB on + * 460 based systems. + */ + pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0])); + pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1])); + + /* Clear BAR control bits */ + agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1); + + pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch); + pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, + (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC); + + /* + * Initialize partial allocation trackers if a GART page is bigger than a kernel + * page. + */ + if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) { + size = current_size->num_entries * sizeof(i460.lp_desc[0]); + i460.lp_desc = kmalloc(size, GFP_KERNEL); + if (!i460.lp_desc) + return -ENOMEM; + memset(i460.lp_desc, 0, size); + } + return 0; +} + +static int i460_create_gatt_table (struct agp_bridge_data *bridge) +{ + int page_order, num_entries, i; + void *temp; + + /* + * Load up the fixed address of the GART SRAMS which hold our GATT table. + */ + temp = agp_bridge->current_size; + page_order = A_SIZE_8(temp)->page_order; + num_entries = A_SIZE_8(temp)->num_entries; + + i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order); + + /* These are no good, the should be removed from the agp_bridge strucure... */ + agp_bridge->gatt_table_real = NULL; + agp_bridge->gatt_table = NULL; + agp_bridge->gatt_bus_addr = 0; + + for (i = 0; i < num_entries; ++i) + WR_GATT(i, 0); + WR_FLUSH_GATT(i - 1); + return 0; +} + +static int i460_free_gatt_table (struct agp_bridge_data *bridge) +{ + int num_entries, i; + void *temp; + + temp = agp_bridge->current_size; + + num_entries = A_SIZE_8(temp)->num_entries; + + for (i = 0; i < num_entries; ++i) + WR_GATT(i, 0); + WR_FLUSH_GATT(num_entries - 1); + + iounmap(i460.gatt); + return 0; +} + +/* + * The following functions are called when the I/O (GART) page size is smaller than + * PAGE_SIZE. + */ + +static int i460_insert_memory_small_io_page (struct agp_memory *mem, + off_t pg_start, int type) +{ + unsigned long paddr, io_pg_start, io_page_size; + int i, j, k, num_entries; + void *temp; + + pr_debug("i460_insert_memory_small_io_page(mem=%p, pg_start=%ld, type=%d, paddr0=0x%lx)\n", + mem, pg_start, type, mem->memory[0]); + + io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start; + + temp = agp_bridge->current_size; + num_entries = A_SIZE_8(temp)->num_entries; + + if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) { + printk(KERN_ERR PFX "Looks like we're out of AGP memory\n"); + return -EINVAL; + } + + j = io_pg_start; + while (j < (io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count)) { + if (!PGE_EMPTY(agp_bridge, RD_GATT(j))) { + pr_debug("i460_insert_memory_small_io_page: GATT[%d]=0x%x is busy\n", + j, RD_GATT(j)); + return -EBUSY; + } + j++; + } + + io_page_size = 1UL << I460_IO_PAGE_SHIFT; + for (i = 0, j = io_pg_start; i < mem->page_count; i++) { + paddr = mem->memory[i]; + for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size) + WR_GATT(j, agp_bridge->driver->mask_memory(agp_bridge, + paddr, mem->type)); + } + WR_FLUSH_GATT(j - 1); + return 0; +} + +static int i460_remove_memory_small_io_page(struct agp_memory *mem, + off_t pg_start, int type) +{ + int i; + + pr_debug("i460_remove_memory_small_io_page(mem=%p, pg_start=%ld, type=%d)\n", + mem, pg_start, type); + + pg_start = I460_IOPAGES_PER_KPAGE * pg_start; + + for (i = pg_start; i < (pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count); i++) + WR_GATT(i, 0); + WR_FLUSH_GATT(i - 1); + return 0; +} + +#if I460_LARGE_IO_PAGES + +/* + * These functions are called when the I/O (GART) page size exceeds PAGE_SIZE. + * + * This situation is interesting since AGP memory allocations that are smaller than a + * single GART page are possible. The i460.lp_desc array tracks partial allocation of the + * large GART pages to work around this issue. + * + * i460.lp_desc[pg_num].refcount tracks the number of kernel pages in use within GART page + * pg_num. i460.lp_desc[pg_num].paddr is the physical address of the large page and + * i460.lp_desc[pg_num].alloced_map is a bitmap of kernel pages that are in use (allocated). + */ + +static int i460_alloc_large_page (struct lp_desc *lp) +{ + unsigned long order = I460_IO_PAGE_SHIFT - PAGE_SHIFT; + size_t map_size; + void *lpage; + + lpage = (void *) __get_free_pages(GFP_KERNEL, order); + if (!lpage) { + printk(KERN_ERR PFX "Couldn't alloc 4M GART page...\n"); + return -ENOMEM; + } + + map_size = ((I460_KPAGES_PER_IOPAGE + BITS_PER_LONG - 1) & -BITS_PER_LONG)/8; + lp->alloced_map = kmalloc(map_size, GFP_KERNEL); + if (!lp->alloced_map) { + free_pages((unsigned long) lpage, order); + printk(KERN_ERR PFX "Out of memory, we're in trouble...\n"); + return -ENOMEM; + } + memset(lp->alloced_map, 0, map_size); + + lp->paddr = virt_to_phys(lpage); + lp->refcount = 0; + atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp); + return 0; +} + +static void i460_free_large_page (struct lp_desc *lp) +{ + kfree(lp->alloced_map); + lp->alloced_map = NULL; + + free_pages((unsigned long) phys_to_virt(lp->paddr), I460_IO_PAGE_SHIFT - PAGE_SHIFT); + atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp); +} + +static int i460_insert_memory_large_io_page (struct agp_memory *mem, + off_t pg_start, int type) +{ + int i, start_offset, end_offset, idx, pg, num_entries; + struct lp_desc *start, *end, *lp; + void *temp; + + temp = agp_bridge->current_size; + num_entries = A_SIZE_8(temp)->num_entries; + + /* Figure out what pg_start means in terms of our large GART pages */ + start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE]; + end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE]; + start_offset = pg_start % I460_KPAGES_PER_IOPAGE; + end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE; + + if (end > i460.lp_desc + num_entries) { + printk(KERN_ERR PFX "Looks like we're out of AGP memory\n"); + return -EINVAL; + } + + /* Check if the requested region of the aperture is free */ + for (lp = start; lp <= end; ++lp) { + if (!lp->alloced_map) + continue; /* OK, the entire large page is available... */ + + for (idx = ((lp == start) ? start_offset : 0); + idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE); + idx++) + { + if (test_bit(idx, lp->alloced_map)) + return -EBUSY; + } + } + + for (lp = start, i = 0; lp <= end; ++lp) { + if (!lp->alloced_map) { + /* Allocate new GART pages... */ + if (i460_alloc_large_page(lp) < 0) + return -ENOMEM; + pg = lp - i460.lp_desc; + WR_GATT(pg, agp_bridge->driver->mask_memory(agp_bridge, + lp->paddr, 0)); + WR_FLUSH_GATT(pg); + } + + for (idx = ((lp == start) ? start_offset : 0); + idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE); + idx++, i++) + { + mem->memory[i] = lp->paddr + idx*PAGE_SIZE; + __set_bit(idx, lp->alloced_map); + ++lp->refcount; + } + } + return 0; +} + +static int i460_remove_memory_large_io_page (struct agp_memory *mem, + off_t pg_start, int type) +{ + int i, pg, start_offset, end_offset, idx, num_entries; + struct lp_desc *start, *end, *lp; + void *temp; + + temp = agp_bridge->driver->current_size; + num_entries = A_SIZE_8(temp)->num_entries; + + /* Figure out what pg_start means in terms of our large GART pages */ + start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE]; + end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE]; + start_offset = pg_start % I460_KPAGES_PER_IOPAGE; + end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE; + + for (i = 0, lp = start; lp <= end; ++lp) { + for (idx = ((lp == start) ? start_offset : 0); + idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE); + idx++, i++) + { + mem->memory[i] = 0; + __clear_bit(idx, lp->alloced_map); + --lp->refcount; + } + + /* Free GART pages if they are unused */ + if (lp->refcount == 0) { + pg = lp - i460.lp_desc; + WR_GATT(pg, 0); + WR_FLUSH_GATT(pg); + i460_free_large_page(lp); + } + } + return 0; +} + +/* Wrapper routines to call the approriate {small_io_page,large_io_page} function */ + +static int i460_insert_memory (struct agp_memory *mem, + off_t pg_start, int type) +{ + if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) + return i460_insert_memory_small_io_page(mem, pg_start, type); + else + return i460_insert_memory_large_io_page(mem, pg_start, type); +} + +static int i460_remove_memory (struct agp_memory *mem, + off_t pg_start, int type) +{ + if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) + return i460_remove_memory_small_io_page(mem, pg_start, type); + else + return i460_remove_memory_large_io_page(mem, pg_start, type); +} + +/* + * If the I/O (GART) page size is bigger than the kernel page size, we don't want to + * allocate memory until we know where it is to be bound in the aperture (a + * multi-kernel-page alloc might fit inside of an already allocated GART page). + * + * Let's just hope nobody counts on the allocated AGP memory being there before bind time + * (I don't think current drivers do)... + */ +static void *i460_alloc_page (struct agp_bridge_data *bridge) +{ + void *page; + + if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) + page = agp_generic_alloc_page(agp_bridge); + else + /* Returning NULL would cause problems */ + /* AK: really dubious code. */ + page = (void *)~0UL; + return page; +} + +static void i460_destroy_page (void *page) +{ + if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) + agp_generic_destroy_page(page); +} + +#endif /* I460_LARGE_IO_PAGES */ + +static unsigned long i460_mask_memory (struct agp_bridge_data *bridge, + unsigned long addr, int type) +{ + /* Make sure the returned address is a valid GATT entry */ + return bridge->driver->masks[0].mask + | (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xffffff000) >> 12); +} + +struct agp_bridge_driver intel_i460_driver = { + .owner = THIS_MODULE, + .aperture_sizes = i460_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 3, + .configure = i460_configure, + .fetch_size = i460_fetch_size, + .cleanup = i460_cleanup, + .tlb_flush = i460_tlb_flush, + .mask_memory = i460_mask_memory, + .masks = i460_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = i460_create_gatt_table, + .free_gatt_table = i460_free_gatt_table, +#if I460_LARGE_IO_PAGES + .insert_memory = i460_insert_memory, + .remove_memory = i460_remove_memory, + .agp_alloc_page = i460_alloc_page, + .agp_destroy_page = i460_destroy_page, +#else + .insert_memory = i460_insert_memory_small_io_page, + .remove_memory = i460_remove_memory_small_io_page, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +#endif + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .cant_use_aperture = 1, +}; + +static int __devinit agp_intel_i460_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_bridge_data *bridge; + u8 cap_ptr; + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (!cap_ptr) + return -ENODEV; + + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + bridge->driver = &intel_i460_driver; + bridge->dev = pdev; + bridge->capndx = cap_ptr; + + printk(KERN_INFO PFX "Detected Intel 460GX chipset\n"); + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void __devexit agp_intel_i460_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +static struct pci_device_id agp_intel_i460_pci_table[] = { + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_84460GX, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_intel_i460_pci_table); + +static struct pci_driver agp_intel_i460_pci_driver = { + .name = "agpgart-intel-i460", + .id_table = agp_intel_i460_pci_table, + .probe = agp_intel_i460_probe, + .remove = __devexit_p(agp_intel_i460_remove), +}; + +static int __init agp_intel_i460_init(void) +{ + if (agp_off) + return -EINVAL; + return pci_register_driver(&agp_intel_i460_pci_driver); +} + +static void __exit agp_intel_i460_cleanup(void) +{ + pci_unregister_driver(&agp_intel_i460_pci_driver); +} + +module_init(agp_intel_i460_init); +module_exit(agp_intel_i460_cleanup); + +MODULE_AUTHOR("Chris Ahna "); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c new file mode 100644 index 000000000000..8c7d727432bb --- /dev/null +++ b/drivers/char/agp/intel-agp.c @@ -0,0 +1,1833 @@ +/* + * Intel AGPGART routines. + */ + +/* + * Intel(R) 855GM/852GM and 865G support added by David Dawes + * . + * + * Intel(R) 915G/915GM support added by Alan Hourihane + * . + */ + +#include +#include +#include +#include +#include +#include "agp.h" + +/* Intel 815 register */ +#define INTEL_815_APCONT 0x51 +#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF + +/* Intel i820 registers */ +#define INTEL_I820_RDCR 0x51 +#define INTEL_I820_ERRSTS 0xc8 + +/* Intel i840 registers */ +#define INTEL_I840_MCHCFG 0x50 +#define INTEL_I840_ERRSTS 0xc8 + +/* Intel i850 registers */ +#define INTEL_I850_MCHCFG 0x50 +#define INTEL_I850_ERRSTS 0xc8 + +/* intel 915G registers */ +#define I915_GMADDR 0x18 +#define I915_MMADDR 0x10 +#define I915_PTEADDR 0x1C +#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) +#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) + + +/* Intel 7505 registers */ +#define INTEL_I7505_APSIZE 0x74 +#define INTEL_I7505_NCAPID 0x60 +#define INTEL_I7505_NISTAT 0x6c +#define INTEL_I7505_ATTBASE 0x78 +#define INTEL_I7505_ERRSTS 0x42 +#define INTEL_I7505_AGPCTRL 0x70 +#define INTEL_I7505_MCHCFG 0x50 + +static struct aper_size_info_fixed intel_i810_sizes[] = +{ + {64, 16384, 4}, + /* The 32M mode still requires a 64k gatt */ + {32, 8192, 4} +}; + +#define AGP_DCACHE_MEMORY 1 +#define AGP_PHYS_MEMORY 2 + +static struct gatt_mask intel_i810_masks[] = +{ + {.mask = I810_PTE_VALID, .type = 0}, + {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, + {.mask = I810_PTE_VALID, .type = 0} +}; + +static struct _intel_i810_private { + struct pci_dev *i810_dev; /* device one */ + volatile u8 __iomem *registers; + int num_dcache_entries; +} intel_i810_private; + +static int intel_i810_fetch_size(void) +{ + u32 smram_miscc; + struct aper_size_info_fixed *values; + + pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); + values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); + + if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { + printk(KERN_WARNING PFX "i810 is disabled\n"); + return 0; + } + if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + 1); + agp_bridge->aperture_size_idx = 1; + return values[1].size; + } else { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values); + agp_bridge->aperture_size_idx = 0; + return values[0].size; + } + + return 0; +} + +static int intel_i810_configure(void) +{ + struct aper_size_info_fixed *current_size; + u32 temp; + int i; + + current_size = A_SIZE_FIX(agp_bridge->current_size); + + pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp); + temp &= 0xfff80000; + + intel_i810_private.registers = ioremap(temp, 128 * 4096); + if (!intel_i810_private.registers) { + printk(KERN_ERR PFX "Unable to remap memory.\n"); + return -ENOMEM; + } + + if ((readl(intel_i810_private.registers+I810_DRAM_CTL) + & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { + /* This will need to be dynamically assigned */ + printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n"); + intel_i810_private.num_dcache_entries = 1024; + } + pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_i810_private.registers+I810_PGETBL_CTL); + readl(intel_i810_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ + + if (agp_bridge->driver->needs_scratch_page) { + for (i = 0; i < current_size->num_entries; i++) { + writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4)); + readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */ + } + } + global_cache_flush(); + return 0; +} + +static void intel_i810_cleanup(void) +{ + writel(0, intel_i810_private.registers+I810_PGETBL_CTL); + readl(intel_i810_private.registers); /* PCI Posting. */ + iounmap(intel_i810_private.registers); +} + +static void intel_i810_tlbflush(struct agp_memory *mem) +{ + return; +} + +static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) +{ + return; +} + +/* Exists to support ARGB cursors */ +static void *i8xx_alloc_pages(void) +{ + struct page * page; + + page = alloc_pages(GFP_KERNEL, 2); + if (page == NULL) + return NULL; + + if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) { + global_flush_tlb(); + __free_page(page); + return NULL; + } + global_flush_tlb(); + get_page(page); + SetPageLocked(page); + atomic_inc(&agp_bridge->current_memory_agp); + return page_address(page); +} + +static void i8xx_destroy_pages(void *addr) +{ + struct page *page; + + if (addr == NULL) + return; + + page = virt_to_page(addr); + change_page_attr(page, 4, PAGE_KERNEL); + global_flush_tlb(); + put_page(page); + unlock_page(page); + free_pages((unsigned long)addr, 2); + atomic_dec(&agp_bridge->current_memory_agp); +} + +static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, + int type) +{ + int i, j, num_entries; + void *temp; + + temp = agp_bridge->current_size; + num_entries = A_SIZE_FIX(temp)->num_entries; + + if ((pg_start + mem->page_count) > num_entries) { + return -EINVAL; + } + for (j = pg_start; j < (pg_start + mem->page_count); j++) { + if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) + return -EBUSY; + } + + if (type != 0 || mem->type != 0) { + if ((type == AGP_DCACHE_MEMORY) && (mem->type == AGP_DCACHE_MEMORY)) { + /* special insert */ + global_cache_flush(); + for (i = pg_start; i < (pg_start + mem->page_count); i++) { + writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, intel_i810_private.registers+I810_PTE_BASE+(i*4)); + readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ + } + global_cache_flush(); + agp_bridge->driver->tlb_flush(mem); + return 0; + } + if((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY)) + goto insert; + return -EINVAL; + } + +insert: + global_cache_flush(); + for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { + writel(agp_bridge->driver->mask_memory(agp_bridge, + mem->memory[i], mem->type), + intel_i810_private.registers+I810_PTE_BASE+(j*4)); + readl(intel_i810_private.registers+I810_PTE_BASE+(j*4)); /* PCI Posting. */ + } + global_cache_flush(); + + agp_bridge->driver->tlb_flush(mem); + return 0; +} + +static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, + int type) +{ + int i; + + for (i = pg_start; i < (mem->page_count + pg_start); i++) { + writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4)); + readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ + } + + global_cache_flush(); + agp_bridge->driver->tlb_flush(mem); + return 0; +} + +/* + * The i810/i830 requires a physical address to program its mouse + * pointer into hardware. + * However the Xserver still writes to it through the agp aperture. + */ +static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) +{ + struct agp_memory *new; + void *addr; + + if (pg_count != 1 && pg_count != 4) + return NULL; + + switch (pg_count) { + case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge); + break; + case 4: + /* kludge to get 4 physical pages for ARGB cursor */ + addr = i8xx_alloc_pages(); + break; + default: + return NULL; + } + + if (addr == NULL) + return NULL; + + new = agp_create_memory(pg_count); + if (new == NULL) + return NULL; + + new->memory[0] = virt_to_phys(addr); + if (pg_count == 4) { + /* kludge to get 4 physical pages for ARGB cursor */ + new->memory[1] = new->memory[0] + PAGE_SIZE; + new->memory[2] = new->memory[1] + PAGE_SIZE; + new->memory[3] = new->memory[2] + PAGE_SIZE; + } + new->page_count = pg_count; + new->num_scratch_pages = pg_count; + new->type = AGP_PHYS_MEMORY; + new->physical = new->memory[0]; + return new; +} + +static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) +{ + struct agp_memory *new; + + if (type == AGP_DCACHE_MEMORY) { + if (pg_count != intel_i810_private.num_dcache_entries) + return NULL; + + new = agp_create_memory(1); + if (new == NULL) + return NULL; + + new->type = AGP_DCACHE_MEMORY; + new->page_count = pg_count; + new->num_scratch_pages = 0; + vfree(new->memory); + return new; + } + if (type == AGP_PHYS_MEMORY) + return alloc_agpphysmem_i8xx(pg_count, type); + + return NULL; +} + +static void intel_i810_free_by_type(struct agp_memory *curr) +{ + agp_free_key(curr->key); + if(curr->type == AGP_PHYS_MEMORY) { + if (curr->page_count == 4) + i8xx_destroy_pages(phys_to_virt(curr->memory[0])); + else + agp_bridge->driver->agp_destroy_page( + phys_to_virt(curr->memory[0])); + vfree(curr->memory); + } + kfree(curr); +} + +static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, + unsigned long addr, int type) +{ + /* Type checking must be done elsewhere */ + return addr | bridge->driver->masks[type].mask; +} + +static struct aper_size_info_fixed intel_i830_sizes[] = +{ + {128, 32768, 5}, + /* The 64M mode still requires a 128k gatt */ + {64, 16384, 5}, + {256, 65536, 6}, +}; + +static struct _intel_i830_private { + struct pci_dev *i830_dev; /* device one */ + volatile u8 __iomem *registers; + volatile u32 __iomem *gtt; /* I915G */ + int gtt_entries; +} intel_i830_private; + +static void intel_i830_init_gtt_entries(void) +{ + u16 gmch_ctrl; + int gtt_entries; + u8 rdct; + int local = 0; + static const int ddt[4] = { 0, 16, 32, 64 }; + int size; + + pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); + + /* We obtain the size of the GTT, which is also stored (for some + * reason) at the top of stolen memory. Then we add 4KB to that + * for the video BIOS popup, which is also stored in there. */ + size = agp_bridge->driver->fetch_size() + 4; + + if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { + switch (gmch_ctrl & I830_GMCH_GMS_MASK) { + case I830_GMCH_GMS_STOLEN_512: + gtt_entries = KB(512) - KB(size); + break; + case I830_GMCH_GMS_STOLEN_1024: + gtt_entries = MB(1) - KB(size); + break; + case I830_GMCH_GMS_STOLEN_8192: + gtt_entries = MB(8) - KB(size); + break; + case I830_GMCH_GMS_LOCAL: + rdct = readb(intel_i830_private.registers+I830_RDRAM_CHANNEL_TYPE); + gtt_entries = (I830_RDRAM_ND(rdct) + 1) * + MB(ddt[I830_RDRAM_DDT(rdct)]); + local = 1; + break; + default: + gtt_entries = 0; + break; + } + } else { + switch (gmch_ctrl & I830_GMCH_GMS_MASK) { + case I855_GMCH_GMS_STOLEN_1M: + gtt_entries = MB(1) - KB(size); + break; + case I855_GMCH_GMS_STOLEN_4M: + gtt_entries = MB(4) - KB(size); + break; + case I855_GMCH_GMS_STOLEN_8M: + gtt_entries = MB(8) - KB(size); + break; + case I855_GMCH_GMS_STOLEN_16M: + gtt_entries = MB(16) - KB(size); + break; + case I855_GMCH_GMS_STOLEN_32M: + gtt_entries = MB(32) - KB(size); + break; + case I915_GMCH_GMS_STOLEN_48M: + /* Check it's really I915G */ + if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) + gtt_entries = MB(48) - KB(size); + else + gtt_entries = 0; + break; + case I915_GMCH_GMS_STOLEN_64M: + /* Check it's really I915G */ + if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) + gtt_entries = MB(64) - KB(size); + else + gtt_entries = 0; + default: + gtt_entries = 0; + break; + } + } + if (gtt_entries > 0) + printk(KERN_INFO PFX "Detected %dK %s memory.\n", + gtt_entries / KB(1), local ? "local" : "stolen"); + else + printk(KERN_INFO PFX + "No pre-allocated video memory detected.\n"); + gtt_entries /= KB(4); + + intel_i830_private.gtt_entries = gtt_entries; +} + +/* The intel i830 automatically initializes the agp aperture during POST. + * Use the memory already set aside for in the GTT. + */ +static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) +{ + int page_order; + struct aper_size_info_fixed *size; + int num_entries; + u32 temp; + + size = agp_bridge->current_size; + page_order = size->page_order; + num_entries = size->num_entries; + agp_bridge->gatt_table_real = NULL; + + pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp); + temp &= 0xfff80000; + + intel_i830_private.registers = ioremap(temp,128 * 4096); + if (!intel_i830_private.registers) + return -ENOMEM; + + temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; + global_cache_flush(); /* FIXME: ?? */ + + /* we have to call this as early as possible after the MMIO base address is known */ + intel_i830_init_gtt_entries(); + + agp_bridge->gatt_table = NULL; + + agp_bridge->gatt_bus_addr = temp; + + return 0; +} + +/* Return the gatt table to a sane state. Use the top of stolen + * memory for the GTT. + */ +static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) +{ + return 0; +} + +static int intel_i830_fetch_size(void) +{ + u16 gmch_ctrl; + struct aper_size_info_fixed *values; + + values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); + + if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && + agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { + /* 855GM/852GM/865G has 128MB aperture size */ + agp_bridge->previous_size = agp_bridge->current_size = (void *) values; + agp_bridge->aperture_size_idx = 0; + return values[0].size; + } + + pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); + + if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { + agp_bridge->previous_size = agp_bridge->current_size = (void *) values; + agp_bridge->aperture_size_idx = 0; + return values[0].size; + } else { + agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); + agp_bridge->aperture_size_idx = 1; + return values[1].size; + } + + return 0; +} + +static int intel_i830_configure(void) +{ + struct aper_size_info_fixed *current_size; + u32 temp; + u16 gmch_ctrl; + int i; + + current_size = A_SIZE_FIX(agp_bridge->current_size); + + pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); + gmch_ctrl |= I830_GMCH_ENABLED; + pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); + + writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL); + readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ + + if (agp_bridge->driver->needs_scratch_page) { + for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) { + writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4)); + readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ + } + } + + global_cache_flush(); + return 0; +} + +static void intel_i830_cleanup(void) +{ + iounmap(intel_i830_private.registers); +} + +static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type) +{ + int i,j,num_entries; + void *temp; + + temp = agp_bridge->current_size; + num_entries = A_SIZE_FIX(temp)->num_entries; + + if (pg_start < intel_i830_private.gtt_entries) { + printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n", + pg_start,intel_i830_private.gtt_entries); + + printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); + return -EINVAL; + } + + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + + /* The i830 can't check the GTT for entries since its read only, + * depend on the caller to make the correct offset decisions. + */ + + if ((type != 0 && type != AGP_PHYS_MEMORY) || + (mem->type != 0 && mem->type != AGP_PHYS_MEMORY)) + return -EINVAL; + + global_cache_flush(); /* FIXME: Necessary ?*/ + + for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { + writel(agp_bridge->driver->mask_memory(agp_bridge, + mem->memory[i], mem->type), + intel_i830_private.registers+I810_PTE_BASE+(j*4)); + readl(intel_i830_private.registers+I810_PTE_BASE+(j*4)); /* PCI Posting. */ + } + + global_cache_flush(); + agp_bridge->driver->tlb_flush(mem); + return 0; +} + +static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start, + int type) +{ + int i; + + global_cache_flush(); + + if (pg_start < intel_i830_private.gtt_entries) { + printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); + return -EINVAL; + } + + for (i = pg_start; i < (mem->page_count + pg_start); i++) { + writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4)); + readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ + } + + global_cache_flush(); + agp_bridge->driver->tlb_flush(mem); + return 0; +} + +static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type) +{ + if (type == AGP_PHYS_MEMORY) + return alloc_agpphysmem_i8xx(pg_count, type); + + /* always return NULL for other allocation types for now */ + return NULL; +} + +static int intel_i915_configure(void) +{ + struct aper_size_info_fixed *current_size; + u32 temp; + u16 gmch_ctrl; + int i; + + current_size = A_SIZE_FIX(agp_bridge->current_size); + + pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp); + + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); + gmch_ctrl |= I830_GMCH_ENABLED; + pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); + + writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL); + readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ + + if (agp_bridge->driver->needs_scratch_page) { + for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) { + writel(agp_bridge->scratch_page, intel_i830_private.gtt+i); + readl(intel_i830_private.gtt+i); /* PCI Posting. */ + } + } + + global_cache_flush(); + return 0; +} + +static void intel_i915_cleanup(void) +{ + iounmap(intel_i830_private.gtt); + iounmap(intel_i830_private.registers); +} + +static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start, + int type) +{ + int i,j,num_entries; + void *temp; + + temp = agp_bridge->current_size; + num_entries = A_SIZE_FIX(temp)->num_entries; + + if (pg_start < intel_i830_private.gtt_entries) { + printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n", + pg_start,intel_i830_private.gtt_entries); + + printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); + return -EINVAL; + } + + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + + /* The i830 can't check the GTT for entries since its read only, + * depend on the caller to make the correct offset decisions. + */ + + if ((type != 0 && type != AGP_PHYS_MEMORY) || + (mem->type != 0 && mem->type != AGP_PHYS_MEMORY)) + return -EINVAL; + + global_cache_flush(); + + for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { + writel(agp_bridge->driver->mask_memory(agp_bridge, + mem->memory[i], mem->type), intel_i830_private.gtt+j); + readl(intel_i830_private.gtt+j); /* PCI Posting. */ + } + + global_cache_flush(); + agp_bridge->driver->tlb_flush(mem); + return 0; +} + +static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start, + int type) +{ + int i; + + global_cache_flush(); + + if (pg_start < intel_i830_private.gtt_entries) { + printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); + return -EINVAL; + } + + for (i = pg_start; i < (mem->page_count + pg_start); i++) { + writel(agp_bridge->scratch_page, intel_i830_private.gtt+i); + readl(intel_i830_private.gtt+i); + } + + global_cache_flush(); + agp_bridge->driver->tlb_flush(mem); + return 0; +} + +static int intel_i915_fetch_size(void) +{ + struct aper_size_info_fixed *values; + u32 temp, offset = 0; + +#define I915_256MB_ADDRESS_MASK (1<<27) + + values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); + + pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp); + if (temp & I915_256MB_ADDRESS_MASK) + offset = 0; /* 128MB aperture */ + else + offset = 2; /* 256MB aperture */ + agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset); + return values[offset].size; +} + +/* The intel i915 automatically initializes the agp aperture during POST. + * Use the memory already set aside for in the GTT. + */ +static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) +{ + int page_order; + struct aper_size_info_fixed *size; + int num_entries; + u32 temp, temp2; + + size = agp_bridge->current_size; + page_order = size->page_order; + num_entries = size->num_entries; + agp_bridge->gatt_table_real = NULL; + + pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp); + pci_read_config_dword(intel_i830_private.i830_dev, I915_PTEADDR,&temp2); + + intel_i830_private.gtt = ioremap(temp2, 256 * 1024); + if (!intel_i830_private.gtt) + return -ENOMEM; + + temp &= 0xfff80000; + + intel_i830_private.registers = ioremap(temp,128 * 4096); + if (!intel_i830_private.registers) + return -ENOMEM; + + temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; + global_cache_flush(); /* FIXME: ? */ + + /* we have to call this as early as possible after the MMIO base address is known */ + intel_i830_init_gtt_entries(); + + agp_bridge->gatt_table = NULL; + + agp_bridge->gatt_bus_addr = temp; + + return 0; +} + +static int intel_fetch_size(void) +{ + int i; + u16 temp; + struct aper_size_info_16 *values; + + pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); + values = A_SIZE_16(agp_bridge->driver->aperture_sizes); + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + + return 0; +} + +static int __intel_8xx_fetch_size(u8 temp) +{ + int i; + struct aper_size_info_8 *values; + + values = A_SIZE_8(agp_bridge->driver->aperture_sizes); + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + return 0; +} + +static int intel_8xx_fetch_size(void) +{ + u8 temp; + + pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); + return __intel_8xx_fetch_size(temp); +} + +static int intel_815_fetch_size(void) +{ + u8 temp; + + /* Intel 815 chipsets have a _weird_ APSIZE register with only + * one non-reserved bit, so mask the others out ... */ + pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); + temp &= (1 << 3); + + return __intel_8xx_fetch_size(temp); +} + +static void intel_tlbflush(struct agp_memory *mem) +{ + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); +} + + +static void intel_8xx_tlbflush(struct agp_memory *mem) +{ + u32 temp; + pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); + pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); +} + + +static void intel_cleanup(void) +{ + u16 temp; + struct aper_size_info_16 *previous_size; + + previous_size = A_SIZE_16(agp_bridge->previous_size); + pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); + pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); + pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); +} + + +static void intel_8xx_cleanup(void) +{ + u16 temp; + struct aper_size_info_8 *previous_size; + + previous_size = A_SIZE_8(agp_bridge->previous_size); + pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); + pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); +} + + +static int intel_configure(void) +{ + u32 temp; + u16 temp2; + struct aper_size_info_16 *current_size; + + current_size = A_SIZE_16(agp_bridge->current_size); + + /* aperture size */ + pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); + + /* address to map to */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* attbase - aperture base */ + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); + + /* agpctrl */ + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); + + /* paccfg/nbxcfg */ + pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, + (temp2 & ~(1 << 10)) | (1 << 9)); + /* clear any possible error conditions */ + pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); + return 0; +} + +static int intel_815_configure(void) +{ + u32 temp, addr; + u8 temp2; + struct aper_size_info_8 *current_size; + + /* attbase - aperture base */ + /* the Intel 815 chipset spec. says that bits 29-31 in the + * ATTBASE register are reserved -> try not to write them */ + if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { + printk (KERN_EMERG PFX "gatt bus addr too high"); + return -EINVAL; + } + + current_size = A_SIZE_8(agp_bridge->current_size); + + /* aperture size */ + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, + current_size->size_value); + + /* address to map to */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); + addr &= INTEL_815_ATTBASE_MASK; + addr |= agp_bridge->gatt_bus_addr; + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); + + /* agpctrl */ + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); + + /* apcont */ + pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); + pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); + + /* clear any possible error conditions */ + /* Oddness : this chipset seems to have no ERRSTS register ! */ + return 0; +} + +static void intel_820_tlbflush(struct agp_memory *mem) +{ + return; +} + +static void intel_820_cleanup(void) +{ + u8 temp; + struct aper_size_info_8 *previous_size; + + previous_size = A_SIZE_8(agp_bridge->previous_size); + pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); + pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, + temp & ~(1 << 1)); + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, + previous_size->size_value); +} + + +static int intel_820_configure(void) +{ + u32 temp; + u8 temp2; + struct aper_size_info_8 *current_size; + + current_size = A_SIZE_8(agp_bridge->current_size); + + /* aperture size */ + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); + + /* address to map to */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* attbase - aperture base */ + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); + + /* agpctrl */ + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); + + /* global enable aperture access */ + /* This flag is not accessed through MCHCFG register as in */ + /* i850 chipset. */ + pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); + pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); + /* clear any possible AGP-related error conditions */ + pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); + return 0; +} + +static int intel_840_configure(void) +{ + u32 temp; + u16 temp2; + struct aper_size_info_8 *current_size; + + current_size = A_SIZE_8(agp_bridge->current_size); + + /* aperture size */ + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); + + /* address to map to */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* attbase - aperture base */ + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); + + /* agpctrl */ + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); + + /* mcgcfg */ + pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); + /* clear any possible error conditions */ + pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); + return 0; +} + +static int intel_845_configure(void) +{ + u32 temp; + u8 temp2; + struct aper_size_info_8 *current_size; + + current_size = A_SIZE_8(agp_bridge->current_size); + + /* aperture size */ + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); + + /* address to map to */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* attbase - aperture base */ + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); + + /* agpctrl */ + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); + + /* agpm */ + pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); + pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); + /* clear any possible error conditions */ + pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); + return 0; +} + +static int intel_850_configure(void) +{ + u32 temp; + u16 temp2; + struct aper_size_info_8 *current_size; + + current_size = A_SIZE_8(agp_bridge->current_size); + + /* aperture size */ + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); + + /* address to map to */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* attbase - aperture base */ + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); + + /* agpctrl */ + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); + + /* mcgcfg */ + pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); + /* clear any possible AGP-related error conditions */ + pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); + return 0; +} + +static int intel_860_configure(void) +{ + u32 temp; + u16 temp2; + struct aper_size_info_8 *current_size; + + current_size = A_SIZE_8(agp_bridge->current_size); + + /* aperture size */ + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); + + /* address to map to */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* attbase - aperture base */ + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); + + /* agpctrl */ + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); + + /* mcgcfg */ + pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); + /* clear any possible AGP-related error conditions */ + pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); + return 0; +} + +static int intel_830mp_configure(void) +{ + u32 temp; + u16 temp2; + struct aper_size_info_8 *current_size; + + current_size = A_SIZE_8(agp_bridge->current_size); + + /* aperture size */ + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); + + /* address to map to */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* attbase - aperture base */ + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); + + /* agpctrl */ + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); + + /* gmch */ + pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); + /* clear any possible AGP-related error conditions */ + pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); + return 0; +} + +static int intel_7505_configure(void) +{ + u32 temp; + u16 temp2; + struct aper_size_info_8 *current_size; + + current_size = A_SIZE_8(agp_bridge->current_size); + + /* aperture size */ + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); + + /* address to map to */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* attbase - aperture base */ + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); + + /* agpctrl */ + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); + + /* mchcfg */ + pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); + + return 0; +} + +/* Setup function */ +static struct gatt_mask intel_generic_masks[] = +{ + {.mask = 0x00000017, .type = 0} +}; + +static struct aper_size_info_8 intel_815_sizes[2] = +{ + {64, 16384, 4, 0}, + {32, 8192, 3, 8}, +}; + +static struct aper_size_info_8 intel_8xx_sizes[7] = +{ + {256, 65536, 6, 0}, + {128, 32768, 5, 32}, + {64, 16384, 4, 48}, + {32, 8192, 3, 56}, + {16, 4096, 2, 60}, + {8, 2048, 1, 62}, + {4, 1024, 0, 63} +}; + +static struct aper_size_info_16 intel_generic_sizes[7] = +{ + {256, 65536, 6, 0}, + {128, 32768, 5, 32}, + {64, 16384, 4, 48}, + {32, 8192, 3, 56}, + {16, 4096, 2, 60}, + {8, 2048, 1, 62}, + {4, 1024, 0, 63} +}; + +static struct aper_size_info_8 intel_830mp_sizes[4] = +{ + {256, 65536, 6, 0}, + {128, 32768, 5, 32}, + {64, 16384, 4, 48}, + {32, 8192, 3, 56} +}; + +static struct agp_bridge_driver intel_generic_driver = { + .owner = THIS_MODULE, + .aperture_sizes = intel_generic_sizes, + .size_type = U16_APER_SIZE, + .num_aperture_sizes = 7, + .configure = intel_configure, + .fetch_size = intel_fetch_size, + .cleanup = intel_cleanup, + .tlb_flush = intel_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = intel_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_bridge_driver intel_810_driver = { + .owner = THIS_MODULE, + .aperture_sizes = intel_i810_sizes, + .size_type = FIXED_APER_SIZE, + .num_aperture_sizes = 2, + .needs_scratch_page = TRUE, + .configure = intel_i810_configure, + .fetch_size = intel_i810_fetch_size, + .cleanup = intel_i810_cleanup, + .tlb_flush = intel_i810_tlbflush, + .mask_memory = intel_i810_mask_memory, + .masks = intel_i810_masks, + .agp_enable = intel_i810_agp_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = intel_i810_insert_entries, + .remove_memory = intel_i810_remove_entries, + .alloc_by_type = intel_i810_alloc_by_type, + .free_by_type = intel_i810_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_bridge_driver intel_815_driver = { + .owner = THIS_MODULE, + .aperture_sizes = intel_815_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 2, + .configure = intel_815_configure, + .fetch_size = intel_815_fetch_size, + .cleanup = intel_8xx_cleanup, + .tlb_flush = intel_8xx_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = intel_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_bridge_driver intel_830_driver = { + .owner = THIS_MODULE, + .aperture_sizes = intel_i830_sizes, + .size_type = FIXED_APER_SIZE, + .num_aperture_sizes = 3, + .needs_scratch_page = TRUE, + .configure = intel_i830_configure, + .fetch_size = intel_i830_fetch_size, + .cleanup = intel_i830_cleanup, + .tlb_flush = intel_i810_tlbflush, + .mask_memory = intel_i810_mask_memory, + .masks = intel_i810_masks, + .agp_enable = intel_i810_agp_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = intel_i830_create_gatt_table, + .free_gatt_table = intel_i830_free_gatt_table, + .insert_memory = intel_i830_insert_entries, + .remove_memory = intel_i830_remove_entries, + .alloc_by_type = intel_i830_alloc_by_type, + .free_by_type = intel_i810_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_bridge_driver intel_820_driver = { + .owner = THIS_MODULE, + .aperture_sizes = intel_8xx_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 7, + .configure = intel_820_configure, + .fetch_size = intel_8xx_fetch_size, + .cleanup = intel_820_cleanup, + .tlb_flush = intel_820_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = intel_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_bridge_driver intel_830mp_driver = { + .owner = THIS_MODULE, + .aperture_sizes = intel_830mp_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 4, + .configure = intel_830mp_configure, + .fetch_size = intel_8xx_fetch_size, + .cleanup = intel_8xx_cleanup, + .tlb_flush = intel_8xx_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = intel_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_bridge_driver intel_840_driver = { + .owner = THIS_MODULE, + .aperture_sizes = intel_8xx_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 7, + .configure = intel_840_configure, + .fetch_size = intel_8xx_fetch_size, + .cleanup = intel_8xx_cleanup, + .tlb_flush = intel_8xx_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = intel_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_bridge_driver intel_845_driver = { + .owner = THIS_MODULE, + .aperture_sizes = intel_8xx_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 7, + .configure = intel_845_configure, + .fetch_size = intel_8xx_fetch_size, + .cleanup = intel_8xx_cleanup, + .tlb_flush = intel_8xx_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = intel_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_bridge_driver intel_850_driver = { + .owner = THIS_MODULE, + .aperture_sizes = intel_8xx_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 7, + .configure = intel_850_configure, + .fetch_size = intel_8xx_fetch_size, + .cleanup = intel_8xx_cleanup, + .tlb_flush = intel_8xx_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = intel_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_bridge_driver intel_860_driver = { + .owner = THIS_MODULE, + .aperture_sizes = intel_8xx_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 7, + .configure = intel_860_configure, + .fetch_size = intel_8xx_fetch_size, + .cleanup = intel_8xx_cleanup, + .tlb_flush = intel_8xx_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = intel_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_bridge_driver intel_915_driver = { + .owner = THIS_MODULE, + .aperture_sizes = intel_i830_sizes, + .size_type = FIXED_APER_SIZE, + .num_aperture_sizes = 3, + .needs_scratch_page = TRUE, + .configure = intel_i915_configure, + .fetch_size = intel_i915_fetch_size, + .cleanup = intel_i915_cleanup, + .tlb_flush = intel_i810_tlbflush, + .mask_memory = intel_i810_mask_memory, + .masks = intel_i810_masks, + .agp_enable = intel_i810_agp_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = intel_i915_create_gatt_table, + .free_gatt_table = intel_i830_free_gatt_table, + .insert_memory = intel_i915_insert_entries, + .remove_memory = intel_i915_remove_entries, + .alloc_by_type = intel_i830_alloc_by_type, + .free_by_type = intel_i810_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + + +static struct agp_bridge_driver intel_7505_driver = { + .owner = THIS_MODULE, + .aperture_sizes = intel_8xx_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 7, + .configure = intel_7505_configure, + .fetch_size = intel_8xx_fetch_size, + .cleanup = intel_8xx_cleanup, + .tlb_flush = intel_8xx_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = intel_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static int find_i810(u16 device) +{ + struct pci_dev *i810_dev; + + i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); + if (!i810_dev) + return 0; + intel_i810_private.i810_dev = i810_dev; + return 1; +} + +static int find_i830(u16 device) +{ + struct pci_dev *i830_dev; + + i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); + if (i830_dev && PCI_FUNC(i830_dev->devfn) != 0) { + i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, + device, i830_dev); + } + + if (!i830_dev) + return 0; + + intel_i830_private.i830_dev = i830_dev; + return 1; +} + +static int __devinit agp_intel_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_bridge_data *bridge; + char *name = "(unknown)"; + u8 cap_ptr = 0; + struct resource *r; + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + switch (pdev->device) { + case PCI_DEVICE_ID_INTEL_82443LX_0: + bridge->driver = &intel_generic_driver; + name = "440LX"; + break; + case PCI_DEVICE_ID_INTEL_82443BX_0: + bridge->driver = &intel_generic_driver; + name = "440BX"; + break; + case PCI_DEVICE_ID_INTEL_82443GX_0: + bridge->driver = &intel_generic_driver; + name = "440GX"; + break; + case PCI_DEVICE_ID_INTEL_82810_MC1: + name = "i810"; + if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG1)) + goto fail; + bridge->driver = &intel_810_driver; + break; + case PCI_DEVICE_ID_INTEL_82810_MC3: + name = "i810 DC100"; + if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG3)) + goto fail; + bridge->driver = &intel_810_driver; + break; + case PCI_DEVICE_ID_INTEL_82810E_MC: + name = "i810 E"; + if (!find_i810(PCI_DEVICE_ID_INTEL_82810E_IG)) + goto fail; + bridge->driver = &intel_810_driver; + break; + case PCI_DEVICE_ID_INTEL_82815_MC: + /* + * The i815 can operate either as an i810 style + * integrated device, or as an AGP4X motherboard. + */ + if (find_i810(PCI_DEVICE_ID_INTEL_82815_CGC)) + bridge->driver = &intel_810_driver; + else + bridge->driver = &intel_815_driver; + name = "i815"; + break; + case PCI_DEVICE_ID_INTEL_82820_HB: + case PCI_DEVICE_ID_INTEL_82820_UP_HB: + bridge->driver = &intel_820_driver; + name = "i820"; + break; + case PCI_DEVICE_ID_INTEL_82830_HB: + if (find_i830(PCI_DEVICE_ID_INTEL_82830_CGC)) { + bridge->driver = &intel_830_driver; + } else { + bridge->driver = &intel_830mp_driver; + } + name = "830M"; + break; + case PCI_DEVICE_ID_INTEL_82840_HB: + bridge->driver = &intel_840_driver; + name = "i840"; + break; + case PCI_DEVICE_ID_INTEL_82845_HB: + bridge->driver = &intel_845_driver; + name = "i845"; + break; + case PCI_DEVICE_ID_INTEL_82845G_HB: + if (find_i830(PCI_DEVICE_ID_INTEL_82845G_IG)) { + bridge->driver = &intel_830_driver; + } else { + bridge->driver = &intel_845_driver; + } + name = "845G"; + break; + case PCI_DEVICE_ID_INTEL_82850_HB: + bridge->driver = &intel_850_driver; + name = "i850"; + break; + case PCI_DEVICE_ID_INTEL_82855PM_HB: + bridge->driver = &intel_845_driver; + name = "855PM"; + break; + case PCI_DEVICE_ID_INTEL_82855GM_HB: + if (find_i830(PCI_DEVICE_ID_INTEL_82855GM_IG)) { + bridge->driver = &intel_830_driver; + name = "855"; + } else { + bridge->driver = &intel_845_driver; + name = "855GM"; + } + break; + case PCI_DEVICE_ID_INTEL_82860_HB: + bridge->driver = &intel_860_driver; + name = "i860"; + break; + case PCI_DEVICE_ID_INTEL_82865_HB: + if (find_i830(PCI_DEVICE_ID_INTEL_82865_IG)) { + bridge->driver = &intel_830_driver; + } else { + bridge->driver = &intel_845_driver; + } + name = "865"; + break; + case PCI_DEVICE_ID_INTEL_82875_HB: + bridge->driver = &intel_845_driver; + name = "i875"; + break; + case PCI_DEVICE_ID_INTEL_82915G_HB: + if (find_i830(PCI_DEVICE_ID_INTEL_82915G_IG)) { + bridge->driver = &intel_915_driver; + } else { + bridge->driver = &intel_845_driver; + } + name = "915G"; + break; + case PCI_DEVICE_ID_INTEL_82915GM_HB: + if (find_i830(PCI_DEVICE_ID_INTEL_82915GM_IG)) { + bridge->driver = &intel_915_driver; + } else { + bridge->driver = &intel_845_driver; + } + name = "915GM"; + break; + case PCI_DEVICE_ID_INTEL_7505_0: + bridge->driver = &intel_7505_driver; + name = "E7505"; + break; + case PCI_DEVICE_ID_INTEL_7205_0: + bridge->driver = &intel_7505_driver; + name = "E7205"; + break; + default: + if (cap_ptr) + printk(KERN_WARNING PFX "Unsupported Intel chipset (device id: %04x)\n", + pdev->device); + agp_put_bridge(bridge); + return -ENODEV; + }; + + bridge->dev = pdev; + bridge->capndx = cap_ptr; + + if (bridge->driver == &intel_810_driver) + bridge->dev_private_data = &intel_i810_private; + else if (bridge->driver == &intel_830_driver) + bridge->dev_private_data = &intel_i830_private; + + printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name); + + /* + * The following fixes the case where the BIOS has "forgotten" to + * provide an address range for the GART. + * 20030610 - hamish@zot.org + */ + r = &pdev->resource[0]; + if (!r->start && r->end) { + if(pci_assign_resource(pdev, 0)) { + printk(KERN_ERR PFX "could not assign resource 0\n"); + agp_put_bridge(bridge); + return -ENODEV; + } + } + + /* + * If the device has not been properly setup, the following will catch + * the problem and should stop the system from crashing. + * 20030610 - hamish@zot.org + */ + if (pci_enable_device(pdev)) { + printk(KERN_ERR PFX "Unable to Enable PCI device\n"); + agp_put_bridge(bridge); + return -ENODEV; + } + + /* Fill in the mode register */ + if (cap_ptr) { + pci_read_config_dword(pdev, + bridge->capndx+PCI_AGP_STATUS, + &bridge->mode); + } + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); + +fail: + printk(KERN_ERR PFX "Detected an Intel %s chipset, " + "but could not find the secondary device.\n", name); + agp_put_bridge(bridge); + return -ENODEV; +} + +static void __devexit agp_intel_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + + if (intel_i810_private.i810_dev) + pci_dev_put(intel_i810_private.i810_dev); + if (intel_i830_private.i830_dev) + pci_dev_put(intel_i830_private.i830_dev); + + agp_put_bridge(bridge); +} + +static int agp_intel_resume(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + pci_restore_state(pdev); + + if (bridge->driver == &intel_generic_driver) + intel_configure(); + else if (bridge->driver == &intel_850_driver) + intel_850_configure(); + else if (bridge->driver == &intel_845_driver) + intel_845_configure(); + else if (bridge->driver == &intel_830mp_driver) + intel_830mp_configure(); + else if (bridge->driver == &intel_915_driver) + intel_i915_configure(); + else if (bridge->driver == &intel_830_driver) + intel_i830_configure(); + else if (bridge->driver == &intel_810_driver) + intel_i810_configure(); + + return 0; +} + +static struct pci_device_id agp_intel_pci_table[] = { +#define ID(x) \ + { \ + .class = (PCI_CLASS_BRIDGE_HOST << 8), \ + .class_mask = ~0, \ + .vendor = PCI_VENDOR_ID_INTEL, \ + .device = x, \ + .subvendor = PCI_ANY_ID, \ + .subdevice = PCI_ANY_ID, \ + } + ID(PCI_DEVICE_ID_INTEL_82443LX_0), + ID(PCI_DEVICE_ID_INTEL_82443BX_0), + ID(PCI_DEVICE_ID_INTEL_82443GX_0), + ID(PCI_DEVICE_ID_INTEL_82810_MC1), + ID(PCI_DEVICE_ID_INTEL_82810_MC3), + ID(PCI_DEVICE_ID_INTEL_82810E_MC), + ID(PCI_DEVICE_ID_INTEL_82815_MC), + ID(PCI_DEVICE_ID_INTEL_82820_HB), + ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), + ID(PCI_DEVICE_ID_INTEL_82830_HB), + ID(PCI_DEVICE_ID_INTEL_82840_HB), + ID(PCI_DEVICE_ID_INTEL_82845_HB), + ID(PCI_DEVICE_ID_INTEL_82845G_HB), + ID(PCI_DEVICE_ID_INTEL_82850_HB), + ID(PCI_DEVICE_ID_INTEL_82855PM_HB), + ID(PCI_DEVICE_ID_INTEL_82855GM_HB), + ID(PCI_DEVICE_ID_INTEL_82860_HB), + ID(PCI_DEVICE_ID_INTEL_82865_HB), + ID(PCI_DEVICE_ID_INTEL_82875_HB), + ID(PCI_DEVICE_ID_INTEL_7505_0), + ID(PCI_DEVICE_ID_INTEL_7205_0), + ID(PCI_DEVICE_ID_INTEL_82915G_HB), + ID(PCI_DEVICE_ID_INTEL_82915GM_HB), + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); + +static struct pci_driver agp_intel_pci_driver = { + .name = "agpgart-intel", + .id_table = agp_intel_pci_table, + .probe = agp_intel_probe, + .remove = __devexit_p(agp_intel_remove), + .resume = agp_intel_resume, +}; + +static int __init agp_intel_init(void) +{ + if (agp_off) + return -EINVAL; + return pci_register_driver(&agp_intel_pci_driver); +} + +static void __exit agp_intel_cleanup(void) +{ + pci_unregister_driver(&agp_intel_pci_driver); +} + +module_init(agp_intel_init); +module_exit(agp_intel_cleanup); + +MODULE_AUTHOR("Dave Jones "); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/agp/isoch.c b/drivers/char/agp/isoch.c new file mode 100644 index 000000000000..c9ac731504f2 --- /dev/null +++ b/drivers/char/agp/isoch.c @@ -0,0 +1,470 @@ +/* + * Setup routines for AGP 3.5 compliant bridges. + */ + +#include +#include +#include +#include + +#include "agp.h" + +/* Generic AGP 3.5 enabling routines */ + +struct agp_3_5_dev { + struct list_head list; + u8 capndx; + u32 maxbw; + struct pci_dev *dev; +}; + +static void agp_3_5_dev_list_insert(struct list_head *head, struct list_head *new) +{ + struct agp_3_5_dev *cur, *n = list_entry(new, struct agp_3_5_dev, list); + struct list_head *pos; + + list_for_each(pos, head) { + cur = list_entry(pos, struct agp_3_5_dev, list); + if(cur->maxbw > n->maxbw) + break; + } + list_add_tail(new, pos); +} + +static void agp_3_5_dev_list_sort(struct agp_3_5_dev *list, unsigned int ndevs) +{ + struct agp_3_5_dev *cur; + struct pci_dev *dev; + struct list_head *pos, *tmp, *head = &list->list, *start = head->next; + u32 nistat; + + INIT_LIST_HEAD(head); + + for (pos=start; pos!=head; ) { + cur = list_entry(pos, struct agp_3_5_dev, list); + dev = cur->dev; + + pci_read_config_dword(dev, cur->capndx+AGPNISTAT, &nistat); + cur->maxbw = (nistat >> 16) & 0xff; + + tmp = pos; + pos = pos->next; + agp_3_5_dev_list_insert(head, tmp); + } +} + +/* + * Initialize all isochronous transfer parameters for an AGP 3.0 + * node (i.e. a host bridge in combination with the adapters + * lying behind it...) + */ + +static int agp_3_5_isochronous_node_enable(struct agp_bridge_data *bridge, + struct agp_3_5_dev *dev_list, unsigned int ndevs) +{ + /* + * Convenience structure to make the calculations clearer + * here. The field names come straight from the AGP 3.0 spec. + */ + struct isoch_data { + u32 maxbw; + u32 n; + u32 y; + u32 l; + u32 rq; + struct agp_3_5_dev *dev; + }; + + struct pci_dev *td = bridge->dev, *dev; + struct list_head *head = &dev_list->list, *pos; + struct agp_3_5_dev *cur; + struct isoch_data *master, target; + unsigned int cdev = 0; + u32 mnistat, tnistat, tstatus, mcmd; + u16 tnicmd, mnicmd; + u8 mcapndx; + u32 tot_bw = 0, tot_n = 0, tot_rq = 0, y_max, rq_isoch, rq_async; + u32 step, rem, rem_isoch, rem_async; + int ret = 0; + + /* + * We'll work with an array of isoch_data's (one for each + * device in dev_list) throughout this function. + */ + if ((master = kmalloc(ndevs * sizeof(*master), GFP_KERNEL)) == NULL) { + ret = -ENOMEM; + goto get_out; + } + + /* + * Sort the device list by maxbw. We need to do this because the + * spec suggests that the devices with the smallest requirements + * have their resources allocated first, with all remaining resources + * falling to the device with the largest requirement. + * + * We don't exactly do this, we divide target resources by ndevs + * and split them amongst the AGP 3.0 devices. The remainder of such + * division operations are dropped on the last device, sort of like + * the spec mentions it should be done. + * + * We can't do this sort when we initially construct the dev_list + * because we don't know until this function whether isochronous + * transfers are enabled and consequently whether maxbw will mean + * anything. + */ + agp_3_5_dev_list_sort(dev_list, ndevs); + + pci_read_config_dword(td, bridge->capndx+AGPNISTAT, &tnistat); + pci_read_config_dword(td, bridge->capndx+AGPSTAT, &tstatus); + + /* Extract power-on defaults from the target */ + target.maxbw = (tnistat >> 16) & 0xff; + target.n = (tnistat >> 8) & 0xff; + target.y = (tnistat >> 6) & 0x3; + target.l = (tnistat >> 3) & 0x7; + target.rq = (tstatus >> 24) & 0xff; + + y_max = target.y; + + /* + * Extract power-on defaults for each device in dev_list. Along + * the way, calculate the total isochronous bandwidth required + * by these devices and the largest requested payload size. + */ + list_for_each(pos, head) { + cur = list_entry(pos, struct agp_3_5_dev, list); + dev = cur->dev; + + mcapndx = cur->capndx; + + pci_read_config_dword(dev, cur->capndx+AGPNISTAT, &mnistat); + + master[cdev].maxbw = (mnistat >> 16) & 0xff; + master[cdev].n = (mnistat >> 8) & 0xff; + master[cdev].y = (mnistat >> 6) & 0x3; + master[cdev].dev = cur; + + tot_bw += master[cdev].maxbw; + y_max = max(y_max, master[cdev].y); + + cdev++; + } + + /* Check if this configuration has any chance of working */ + if (tot_bw > target.maxbw) { + printk(KERN_ERR PFX "isochronous bandwidth required " + "by AGP 3.0 devices exceeds that which is supported by " + "the AGP 3.0 bridge!\n"); + ret = -ENODEV; + goto free_and_exit; + } + + target.y = y_max; + + /* + * Write the calculated payload size into the target's NICMD + * register. Doing this directly effects the ISOCH_N value + * in the target's NISTAT register, so we need to do this now + * to get an accurate value for ISOCH_N later. + */ + pci_read_config_word(td, bridge->capndx+AGPNICMD, &tnicmd); + tnicmd &= ~(0x3 << 6); + tnicmd |= target.y << 6; + pci_write_config_word(td, bridge->capndx+AGPNICMD, tnicmd); + + /* Reread the target's ISOCH_N */ + pci_read_config_dword(td, bridge->capndx+AGPNISTAT, &tnistat); + target.n = (tnistat >> 8) & 0xff; + + /* Calculate the minimum ISOCH_N needed by each master */ + for (cdev=0; cdev target.n) { + printk(KERN_ERR PFX "number of isochronous " + "transactions per period required by AGP 3.0 devices " + "exceeds that which is supported by the AGP 3.0 " + "bridge!\n"); + ret = -ENODEV; + goto free_and_exit; + } + + /* Calculate left over ISOCH_N capability in the target. We'll give + * this to the hungriest device (as per the spec) */ + rem = target.n - tot_n; + + /* + * Calculate the minimum isochronous RQ depth needed by each master. + * Along the way, distribute the extra ISOCH_N capability calculated + * above. + */ + for (cdev=0; cdev 64B, then ISOCH_Y + * byte isochronous writes will be broken into 64B pieces. + * This means we need to budget more RQ depth to account for + * these kind of writes (each isochronous write is actually + * many writes on the AGP bus). + */ + master[cdev].rq = master[cdev].n; + if(master[cdev].y > 0x1) + master[cdev].rq *= (1 << (master[cdev].y - 1)); + + tot_rq += master[cdev].rq; + + if (cdev == ndevs-1) + master[cdev].n += rem; + } + + /* Figure the number of isochronous and asynchronous RQ slots the + * target is providing. */ + rq_isoch = (target.y > 0x1) ? target.n * (1 << (target.y - 1)) : target.n; + rq_async = target.rq - rq_isoch; + + /* Exit if the minimal RQ needs of the masters exceeds what the target + * can provide. */ + if (tot_rq > rq_isoch) { + printk(KERN_ERR PFX "number of request queue slots " + "required by the isochronous bandwidth requested by " + "AGP 3.0 devices exceeds the number provided by the " + "AGP 3.0 bridge!\n"); + ret = -ENODEV; + goto free_and_exit; + } + + /* Calculate asynchronous RQ capability in the target (per master) as + * well as the total number of leftover isochronous RQ slots. */ + step = rq_async / ndevs; + rem_async = step + (rq_async % ndevs); + rem_isoch = rq_isoch - tot_rq; + + /* Distribute the extra RQ slots calculated above and write our + * isochronous settings out to the actual devices. */ + for (cdev=0; cdevdev; + + mcapndx = cur->capndx; + + master[cdev].rq += (cdev == ndevs - 1) + ? (rem_async + rem_isoch) : step; + + pci_read_config_word(dev, cur->capndx+AGPNICMD, &mnicmd); + pci_read_config_dword(dev, cur->capndx+AGPCMD, &mcmd); + + mnicmd &= ~(0xff << 8); + mnicmd &= ~(0x3 << 6); + mcmd &= ~(0xff << 24); + + mnicmd |= master[cdev].n << 8; + mnicmd |= master[cdev].y << 6; + mcmd |= master[cdev].rq << 24; + + pci_write_config_dword(dev, cur->capndx+AGPCMD, mcmd); + pci_write_config_word(dev, cur->capndx+AGPNICMD, mnicmd); + } + +free_and_exit: + kfree(master); + +get_out: + return ret; +} + +/* + * This function basically allocates request queue slots among the + * AGP 3.0 systems in nonisochronous nodes. The algorithm is + * pretty stupid, divide the total number of RQ slots provided by the + * target by ndevs. Distribute this many slots to each AGP 3.0 device, + * giving any left over slots to the last device in dev_list. + */ +static void agp_3_5_nonisochronous_node_enable(struct agp_bridge_data *bridge, + struct agp_3_5_dev *dev_list, unsigned int ndevs) +{ + struct agp_3_5_dev *cur; + struct list_head *head = &dev_list->list, *pos; + u32 tstatus, mcmd; + u32 trq, mrq, rem; + unsigned int cdev = 0; + + pci_read_config_dword(bridge->dev, bridge->capndx+AGPSTAT, &tstatus); + + trq = (tstatus >> 24) & 0xff; + mrq = trq / ndevs; + + rem = mrq + (trq % ndevs); + + for (pos=head->next; cdevnext) { + cur = list_entry(pos, struct agp_3_5_dev, list); + + pci_read_config_dword(cur->dev, cur->capndx+AGPCMD, &mcmd); + mcmd &= ~(0xff << 24); + mcmd |= ((cdev == ndevs - 1) ? rem : mrq) << 24; + pci_write_config_dword(cur->dev, cur->capndx+AGPCMD, mcmd); + } +} + +/* + * Fully configure and enable an AGP 3.0 host bridge and all the devices + * lying behind it. + */ +int agp_3_5_enable(struct agp_bridge_data *bridge) +{ + struct pci_dev *td = bridge->dev, *dev = NULL; + u8 mcapndx; + u32 isoch, arqsz; + u32 tstatus, mstatus, ncapid; + u32 mmajor; + u16 mpstat; + struct agp_3_5_dev *dev_list, *cur; + struct list_head *head, *pos; + unsigned int ndevs = 0; + int ret = 0; + + /* Extract some power-on defaults from the target */ + pci_read_config_dword(td, bridge->capndx+AGPSTAT, &tstatus); + isoch = (tstatus >> 17) & 0x1; + if (isoch == 0) /* isoch xfers not available, bail out. */ + return -ENODEV; + + arqsz = (tstatus >> 13) & 0x7; + + /* + * Allocate a head for our AGP 3.5 device list + * (multiple AGP v3 devices are allowed behind a single bridge). + */ + if ((dev_list = kmalloc(sizeof(*dev_list), GFP_KERNEL)) == NULL) { + ret = -ENOMEM; + goto get_out; + } + head = &dev_list->list; + INIT_LIST_HEAD(head); + + /* Find all AGP devices, and add them to dev_list. */ + for_each_pci_dev(dev) { + mcapndx = pci_find_capability(dev, PCI_CAP_ID_AGP); + if (mcapndx == 0) + continue; + + switch ((dev->class >>8) & 0xff00) { + case 0x0600: /* Bridge */ + /* Skip bridges. We should call this function for each one. */ + continue; + + case 0x0001: /* Unclassified device */ + /* Don't know what this is, but log it for investigation. */ + if (mcapndx != 0) { + printk (KERN_INFO PFX "Wacky, found unclassified AGP device. %x:%x\n", + dev->vendor, dev->device); + } + continue; + + case 0x0300: /* Display controller */ + case 0x0400: /* Multimedia controller */ + if((cur = kmalloc(sizeof(*cur), GFP_KERNEL)) == NULL) { + ret = -ENOMEM; + goto free_and_exit; + } + cur->dev = dev; + + pos = &cur->list; + list_add(pos, head); + ndevs++; + continue; + + default: + continue; + } + } + + /* + * Take an initial pass through the devices lying behind our host + * bridge. Make sure each one is actually an AGP 3.0 device, otherwise + * exit with an error message. Along the way store the AGP 3.0 + * cap_ptr for each device + */ + list_for_each(pos, head) { + cur = list_entry(pos, struct agp_3_5_dev, list); + dev = cur->dev; + + pci_read_config_word(dev, PCI_STATUS, &mpstat); + if ((mpstat & PCI_STATUS_CAP_LIST) == 0) + continue; + + pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &mcapndx); + if (mcapndx != 0) { + do { + pci_read_config_dword(dev, mcapndx, &ncapid); + if ((ncapid & 0xff) != 2) + mcapndx = (ncapid >> 8) & 0xff; + } + while (((ncapid & 0xff) != 2) && (mcapndx != 0)); + } + + if (mcapndx == 0) { + printk(KERN_ERR PFX "woah! Non-AGP device " + "found on the secondary bus of an AGP 3.5 bridge!\n"); + ret = -ENODEV; + goto free_and_exit; + } + + mmajor = (ncapid >> AGP_MAJOR_VERSION_SHIFT) & 0xf; + if (mmajor < 3) { + printk(KERN_ERR PFX "woah! AGP 2.0 device " + "found on the secondary bus of an AGP 3.5 " + "bridge operating with AGP 3.0 electricals!\n"); + ret = -ENODEV; + goto free_and_exit; + } + + cur->capndx = mcapndx; + + pci_read_config_dword(dev, cur->capndx+AGPSTAT, &mstatus); + + if (((mstatus >> 3) & 0x1) == 0) { + printk(KERN_ERR PFX "woah! AGP 3.x device " + "not operating in AGP 3.x mode found on the " + "secondary bus of an AGP 3.5 bridge operating " + "with AGP 3.0 electricals!\n"); + ret = -ENODEV; + goto free_and_exit; + } + } + + /* + * Call functions to divide target resources amongst the AGP 3.0 + * masters. This process is dramatically different depending on + * whether isochronous transfers are supported. + */ + if (isoch) { + ret = agp_3_5_isochronous_node_enable(bridge, dev_list, ndevs); + if (ret) { + printk(KERN_INFO PFX "Something bad happened setting " + "up isochronous xfers. Falling back to " + "non-isochronous xfer mode.\n"); + } else { + goto free_and_exit; + } + } + agp_3_5_nonisochronous_node_enable(bridge, dev_list, ndevs); + +free_and_exit: + /* Be sure to free the dev_list */ + for (pos=head->next; pos!=head; ) { + cur = list_entry(pos, struct agp_3_5_dev, list); + + pos = pos->next; + kfree(cur); + } + kfree(dev_list); + +get_out: + return ret; +} + diff --git a/drivers/char/agp/nvidia-agp.c b/drivers/char/agp/nvidia-agp.c new file mode 100644 index 000000000000..4f7a3e8bc919 --- /dev/null +++ b/drivers/char/agp/nvidia-agp.c @@ -0,0 +1,424 @@ +/* + * Nvidia AGPGART routines. + * Based upon a 2.4 agpgart diff by the folks from NVIDIA, and hacked up + * to work in 2.5 by Dave Jones + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agp.h" + +/* NVIDIA registers */ +#define NVIDIA_0_APSIZE 0x80 +#define NVIDIA_1_WBC 0xf0 +#define NVIDIA_2_GARTCTRL 0xd0 +#define NVIDIA_2_APBASE 0xd8 +#define NVIDIA_2_APLIMIT 0xdc +#define NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4) +#define NVIDIA_3_APBASE 0x50 +#define NVIDIA_3_APLIMIT 0x54 + + +static struct _nvidia_private { + struct pci_dev *dev_1; + struct pci_dev *dev_2; + struct pci_dev *dev_3; + volatile u32 __iomem *aperture; + int num_active_entries; + off_t pg_offset; + u32 wbc_mask; +} nvidia_private; + + +static int nvidia_fetch_size(void) +{ + int i; + u8 size_value; + struct aper_size_info_8 *values; + + pci_read_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE, &size_value); + size_value &= 0x0f; + values = A_SIZE_8(agp_bridge->driver->aperture_sizes); + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (size_value == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + + return 0; +} + +#define SYSCFG 0xC0010010 +#define IORR_BASE0 0xC0010016 +#define IORR_MASK0 0xC0010017 +#define AMD_K7_NUM_IORR 2 + +static int nvidia_init_iorr(u32 base, u32 size) +{ + u32 base_hi, base_lo; + u32 mask_hi, mask_lo; + u32 sys_hi, sys_lo; + u32 iorr_addr, free_iorr_addr; + + /* Find the iorr that is already used for the base */ + /* If not found, determine the uppermost available iorr */ + free_iorr_addr = AMD_K7_NUM_IORR; + for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) { + rdmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi); + rdmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi); + + if ((base_lo & 0xfffff000) == (base & 0xfffff000)) + break; + + if ((mask_lo & 0x00000800) == 0) + free_iorr_addr = iorr_addr; + } + + if (iorr_addr >= AMD_K7_NUM_IORR) { + iorr_addr = free_iorr_addr; + if (iorr_addr >= AMD_K7_NUM_IORR) + return -EINVAL; + } + base_hi = 0x0; + base_lo = (base & ~0xfff) | 0x18; + mask_hi = 0xf; + mask_lo = ((~(size - 1)) & 0xfffff000) | 0x800; + wrmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi); + wrmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi); + + rdmsr(SYSCFG, sys_lo, sys_hi); + sys_lo |= 0x00100000; + wrmsr(SYSCFG, sys_lo, sys_hi); + + return 0; +} + +static int nvidia_configure(void) +{ + int i, rc, num_dirs; + u32 apbase, aplimit; + struct aper_size_info_8 *current_size; + u32 temp; + + current_size = A_SIZE_8(agp_bridge->current_size); + + /* aperture size */ + pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE, + current_size->size_value); + + /* address to map to */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &apbase); + apbase &= PCI_BASE_ADDRESS_MEM_MASK; + agp_bridge->gart_bus_addr = apbase; + aplimit = apbase + (current_size->size * 1024 * 1024) - 1; + pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase); + pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APLIMIT, aplimit); + pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APBASE, apbase); + pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APLIMIT, aplimit); + if (0 != (rc = nvidia_init_iorr(apbase, current_size->size * 1024 * 1024))) + return rc; + + /* directory size is 64k */ + num_dirs = current_size->size / 64; + nvidia_private.num_active_entries = current_size->num_entries; + nvidia_private.pg_offset = 0; + if (num_dirs == 0) { + num_dirs = 1; + nvidia_private.num_active_entries /= (64 / current_size->size); + nvidia_private.pg_offset = (apbase & (64 * 1024 * 1024 - 1) & + ~(current_size->size * 1024 * 1024 - 1)) / PAGE_SIZE; + } + + /* attbase */ + for(i = 0; i < 8; i++) { + pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i), + (agp_bridge->gatt_bus_addr + (i % num_dirs) * 64 * 1024) | 1); + } + + /* gtlb control */ + pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp); + pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp | 0x11); + + /* gart control */ + pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp); + pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100); + + /* map aperture */ + nvidia_private.aperture = + (volatile u32 __iomem *) ioremap(apbase, 33 * PAGE_SIZE); + + return 0; +} + +static void nvidia_cleanup(void) +{ + struct aper_size_info_8 *previous_size; + u32 temp; + + /* gart control */ + pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp); + pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp & ~(0x100)); + + /* gtlb control */ + pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp); + pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp & ~(0x11)); + + /* unmap aperture */ + iounmap((void __iomem *) nvidia_private.aperture); + + /* restore previous aperture size */ + previous_size = A_SIZE_8(agp_bridge->previous_size); + pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE, + previous_size->size_value); + + /* restore iorr for previous aperture size */ + nvidia_init_iorr(agp_bridge->gart_bus_addr, + previous_size->size * 1024 * 1024); +} + + +/* + * Note we can't use the generic routines, even though they are 99% the same. + * Aperture sizes <64M still requires a full 64k GART directory, but + * only use the portion of the TLB entries that correspond to the apertures + * alignment inside the surrounding 64M block. + */ +extern int agp_memory_reserved; + +static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type) +{ + int i, j; + + if ((type != 0) || (mem->type != 0)) + return -EINVAL; + + if ((pg_start + mem->page_count) > + (nvidia_private.num_active_entries - agp_memory_reserved/PAGE_SIZE)) + return -EINVAL; + + for(j = pg_start; j < (pg_start + mem->page_count); j++) { + if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j))) + return -EBUSY; + } + + if (mem->is_flushed == FALSE) { + global_cache_flush(); + mem->is_flushed = TRUE; + } + for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { + writel(agp_bridge->driver->mask_memory(agp_bridge, + mem->memory[i], mem->type), + agp_bridge->gatt_table+nvidia_private.pg_offset+j); + readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j); /* PCI Posting. */ + } + agp_bridge->driver->tlb_flush(mem); + return 0; +} + + +static int nvidia_remove_memory(struct agp_memory *mem, off_t pg_start, int type) +{ + int i; + + if ((type != 0) || (mem->type != 0)) + return -EINVAL; + + for (i = pg_start; i < (mem->page_count + pg_start); i++) + writel(agp_bridge->scratch_page, agp_bridge->gatt_table+nvidia_private.pg_offset+i); + + agp_bridge->driver->tlb_flush(mem); + return 0; +} + + +static void nvidia_tlbflush(struct agp_memory *mem) +{ + unsigned long end; + u32 wbc_reg, temp; + int i; + + /* flush chipset */ + if (nvidia_private.wbc_mask) { + pci_read_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, &wbc_reg); + wbc_reg |= nvidia_private.wbc_mask; + pci_write_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, wbc_reg); + + end = jiffies + 3*HZ; + do { + pci_read_config_dword(nvidia_private.dev_1, + NVIDIA_1_WBC, &wbc_reg); + if ((signed)(end - jiffies) <= 0) { + printk(KERN_ERR PFX + "TLB flush took more than 3 seconds.\n"); + } + } while (wbc_reg & nvidia_private.wbc_mask); + } + + /* flush TLB entries */ + for(i = 0; i < 32 + 1; i++) + temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32))); + for(i = 0; i < 32 + 1; i++) + temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32))); +} + + +static struct aper_size_info_8 nvidia_generic_sizes[5] = +{ + {512, 131072, 7, 0}, + {256, 65536, 6, 8}, + {128, 32768, 5, 12}, + {64, 16384, 4, 14}, + /* The 32M mode still requires a 64k gatt */ + {32, 16384, 4, 15} +}; + + +static struct gatt_mask nvidia_generic_masks[] = +{ + { .mask = 1, .type = 0} +}; + + +struct agp_bridge_driver nvidia_driver = { + .owner = THIS_MODULE, + .aperture_sizes = nvidia_generic_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 5, + .configure = nvidia_configure, + .fetch_size = nvidia_fetch_size, + .cleanup = nvidia_cleanup, + .tlb_flush = nvidia_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = nvidia_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = nvidia_insert_memory, + .remove_memory = nvidia_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static int __devinit agp_nvidia_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_bridge_data *bridge; + u8 cap_ptr; + + nvidia_private.dev_1 = + pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 1)); + nvidia_private.dev_2 = + pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 2)); + nvidia_private.dev_3 = + pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(30, 0)); + + if (!nvidia_private.dev_1 || !nvidia_private.dev_2 || !nvidia_private.dev_3) { + printk(KERN_INFO PFX "Detected an NVIDIA nForce/nForce2 " + "chipset, but could not find the secondary devices.\n"); + return -ENODEV; + } + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (!cap_ptr) + return -ENODEV; + + switch (pdev->device) { + case PCI_DEVICE_ID_NVIDIA_NFORCE: + printk(KERN_INFO PFX "Detected NVIDIA nForce chipset\n"); + nvidia_private.wbc_mask = 0x00010000; + break; + case PCI_DEVICE_ID_NVIDIA_NFORCE2: + printk(KERN_INFO PFX "Detected NVIDIA nForce2 chipset\n"); + nvidia_private.wbc_mask = 0x80000000; + break; + default: + printk(KERN_ERR PFX "Unsupported NVIDIA chipset (device id: %04x)\n", + pdev->device); + return -ENODEV; + } + + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + bridge->driver = &nvidia_driver; + bridge->dev_private_data = &nvidia_private, + bridge->dev = pdev; + bridge->capndx = cap_ptr; + + /* Fill in the mode register */ + pci_read_config_dword(pdev, + bridge->capndx+PCI_AGP_STATUS, + &bridge->mode); + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void __devexit agp_nvidia_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +static struct pci_device_id agp_nvidia_pci_table[] = { + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_NFORCE, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_NFORCE2, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_nvidia_pci_table); + +static struct pci_driver agp_nvidia_pci_driver = { + .name = "agpgart-nvidia", + .id_table = agp_nvidia_pci_table, + .probe = agp_nvidia_probe, + .remove = agp_nvidia_remove, +}; + +static int __init agp_nvidia_init(void) +{ + if (agp_off) + return -EINVAL; + return pci_register_driver(&agp_nvidia_pci_driver); +} + +static void __exit agp_nvidia_cleanup(void) +{ + pci_unregister_driver(&agp_nvidia_pci_driver); +} + +module_init(agp_nvidia_init); +module_exit(agp_nvidia_cleanup); + +MODULE_LICENSE("GPL and additional rights"); +MODULE_AUTHOR("NVIDIA Corporation"); + diff --git a/drivers/char/agp/sgi-agp.c b/drivers/char/agp/sgi-agp.c new file mode 100644 index 000000000000..4b3eda267976 --- /dev/null +++ b/drivers/char/agp/sgi-agp.c @@ -0,0 +1,331 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved. + */ + +/* + * SGI TIOCA AGPGART routines. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "agp.h" + +extern int agp_memory_reserved; +extern uint32_t tioca_gart_found; +extern struct list_head tioca_list; +static struct agp_bridge_data **sgi_tioca_agp_bridges; + +/* + * The aperature size and related information is set up at TIOCA init time. + * Values for this table will be extracted and filled in at + * sgi_tioca_fetch_size() time. + */ + +static struct aper_size_info_fixed sgi_tioca_sizes[] = { + {0, 0, 0}, +}; + +static void *sgi_tioca_alloc_page(struct agp_bridge_data *bridge) +{ + struct page *page; + int nid; + struct tioca_kernel *info = + (struct tioca_kernel *)bridge->dev_private_data; + + nid = info->ca_closest_node; + page = alloc_pages_node(nid, GFP_KERNEL, 0); + if (page == NULL) { + return 0; + } + + get_page(page); + SetPageLocked(page); + atomic_inc(&agp_bridge->current_memory_agp); + return page_address(page); +} + +/* + * Flush GART tlb's. Cannot selectively flush based on memory so the mem + * arg is ignored. + */ + +static void sgi_tioca_tlbflush(struct agp_memory *mem) +{ + tioca_tlbflush(mem->bridge->dev_private_data); +} + +/* + * Given an address of a host physical page, turn it into a valid gart + * entry. + */ +static unsigned long +sgi_tioca_mask_memory(struct agp_bridge_data *bridge, + unsigned long addr, int type) +{ + return tioca_physpage_to_gart(addr); +} + +static void sgi_tioca_agp_enable(struct agp_bridge_data *bridge, u32 mode) +{ + tioca_fastwrite_enable(bridge->dev_private_data); +} + +/* + * sgi_tioca_configure() doesn't have anything to do since the base CA driver + * has alreay set up the GART. + */ + +static int sgi_tioca_configure(void) +{ + return 0; +} + +/* + * Determine gfx aperature size. This has already been determined by the + * CA driver init, so just need to set agp_bridge values accordingly. + */ + +static int sgi_tioca_fetch_size(void) +{ + struct tioca_kernel *info = + (struct tioca_kernel *)agp_bridge->dev_private_data; + + sgi_tioca_sizes[0].size = info->ca_gfxap_size / MB(1); + sgi_tioca_sizes[0].num_entries = info->ca_gfxgart_entries; + + return sgi_tioca_sizes[0].size; +} + +static int sgi_tioca_create_gatt_table(struct agp_bridge_data *bridge) +{ + struct tioca_kernel *info = + (struct tioca_kernel *)bridge->dev_private_data; + + bridge->gatt_table_real = (u32 *) info->ca_gfxgart; + bridge->gatt_table = bridge->gatt_table_real; + bridge->gatt_bus_addr = info->ca_gfxgart_base; + + return 0; +} + +static int sgi_tioca_free_gatt_table(struct agp_bridge_data *bridge) +{ + return 0; +} + +static int sgi_tioca_insert_memory(struct agp_memory *mem, off_t pg_start, + int type) +{ + int num_entries; + size_t i; + off_t j; + void *temp; + struct agp_bridge_data *bridge; + + bridge = mem->bridge; + if (!bridge) + return -EINVAL; + + temp = bridge->current_size; + + switch (bridge->driver->size_type) { + case U8_APER_SIZE: + num_entries = A_SIZE_8(temp)->num_entries; + break; + case U16_APER_SIZE: + num_entries = A_SIZE_16(temp)->num_entries; + break; + case U32_APER_SIZE: + num_entries = A_SIZE_32(temp)->num_entries; + break; + case FIXED_APER_SIZE: + num_entries = A_SIZE_FIX(temp)->num_entries; + break; + case LVL2_APER_SIZE: + return -EINVAL; + break; + default: + num_entries = 0; + break; + } + + num_entries -= agp_memory_reserved / PAGE_SIZE; + if (num_entries < 0) + num_entries = 0; + + if (type != 0 || mem->type != 0) { + return -EINVAL; + } + + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + + j = pg_start; + + while (j < (pg_start + mem->page_count)) { + if (*(bridge->gatt_table + j)) + return -EBUSY; + j++; + } + + if (mem->is_flushed == FALSE) { + bridge->driver->cache_flush(); + mem->is_flushed = TRUE; + } + + for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { + *(bridge->gatt_table + j) = + bridge->driver->mask_memory(bridge, mem->memory[i], + mem->type); + } + + bridge->driver->tlb_flush(mem); + return 0; +} + +static int sgi_tioca_remove_memory(struct agp_memory *mem, off_t pg_start, + int type) +{ + size_t i; + struct agp_bridge_data *bridge; + + bridge = mem->bridge; + if (!bridge) + return -EINVAL; + + if (type != 0 || mem->type != 0) { + return -EINVAL; + } + + for (i = pg_start; i < (mem->page_count + pg_start); i++) { + *(bridge->gatt_table + i) = 0; + } + + bridge->driver->tlb_flush(mem); + return 0; +} + +static void sgi_tioca_cache_flush(void) +{ +} + +/* + * Cleanup. Nothing to do as the CA driver owns the GART. + */ + +static void sgi_tioca_cleanup(void) +{ +} + +static struct agp_bridge_data *sgi_tioca_find_bridge(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge; + + list_for_each_entry(bridge, &agp_bridges, list) { + if (bridge->dev->bus == pdev->bus) + break; + } + return bridge; +} + +struct agp_bridge_driver sgi_tioca_driver = { + .owner = THIS_MODULE, + .size_type = U16_APER_SIZE, + .configure = sgi_tioca_configure, + .fetch_size = sgi_tioca_fetch_size, + .cleanup = sgi_tioca_cleanup, + .tlb_flush = sgi_tioca_tlbflush, + .mask_memory = sgi_tioca_mask_memory, + .agp_enable = sgi_tioca_agp_enable, + .cache_flush = sgi_tioca_cache_flush, + .create_gatt_table = sgi_tioca_create_gatt_table, + .free_gatt_table = sgi_tioca_free_gatt_table, + .insert_memory = sgi_tioca_insert_memory, + .remove_memory = sgi_tioca_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = sgi_tioca_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, + .cant_use_aperture = 1, + .needs_scratch_page = 0, + .num_aperture_sizes = 1, +}; + +static int __devinit agp_sgi_init(void) +{ + unsigned int j; + struct tioca_kernel *info; + struct pci_dev *pdev = NULL; + + if (tioca_gart_found) + printk(KERN_INFO PFX "SGI TIO CA GART driver initialized.\n"); + else + return 0; + + sgi_tioca_agp_bridges = + (struct agp_bridge_data **)kmalloc(tioca_gart_found * + sizeof(struct agp_bridge_data *), + GFP_KERNEL); + + j = 0; + list_for_each_entry(info, &tioca_list, ca_list) { + struct list_head *tmp; + list_for_each(tmp, info->ca_devices) { + u8 cap_ptr; + pdev = pci_dev_b(tmp); + if (pdev->class != (PCI_CLASS_DISPLAY_VGA << 8)) + continue; + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (!cap_ptr) + continue; + } + sgi_tioca_agp_bridges[j] = agp_alloc_bridge(); + printk(KERN_INFO PFX "bridge %d = 0x%p\n", j, + sgi_tioca_agp_bridges[j]); + if (sgi_tioca_agp_bridges[j]) { + sgi_tioca_agp_bridges[j]->dev = pdev; + sgi_tioca_agp_bridges[j]->dev_private_data = info; + sgi_tioca_agp_bridges[j]->driver = &sgi_tioca_driver; + sgi_tioca_agp_bridges[j]->gart_bus_addr = + info->ca_gfxap_base; + sgi_tioca_agp_bridges[j]->mode = (0x7D << 24) | /* 126 requests */ + (0x1 << 9) | /* SBA supported */ + (0x1 << 5) | /* 64-bit addresses supported */ + (0x1 << 4) | /* FW supported */ + (0x1 << 3) | /* AGP 3.0 mode */ + 0x2; /* 8x transfer only */ + sgi_tioca_agp_bridges[j]->current_size = + sgi_tioca_agp_bridges[j]->previous_size = + (void *)&sgi_tioca_sizes[0]; + agp_add_bridge(sgi_tioca_agp_bridges[j]); + } + j++; + } + + agp_find_bridge = &sgi_tioca_find_bridge; + return 0; +} + +static void __devexit agp_sgi_cleanup(void) +{ + if(sgi_tioca_agp_bridges) + kfree(sgi_tioca_agp_bridges); + sgi_tioca_agp_bridges=NULL; +} + +module_init(agp_sgi_init); +module_exit(agp_sgi_cleanup); + +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/agp/sis-agp.c b/drivers/char/agp/sis-agp.c new file mode 100644 index 000000000000..cfccacb2a647 --- /dev/null +++ b/drivers/char/agp/sis-agp.c @@ -0,0 +1,360 @@ +/* + * SiS AGPGART routines. + */ + +#include +#include +#include +#include +#include +#include "agp.h" + +#define SIS_ATTBASE 0x90 +#define SIS_APSIZE 0x94 +#define SIS_TLBCNTRL 0x97 +#define SIS_TLBFLUSH 0x98 + +static int __devinitdata agp_sis_force_delay = 0; +static int __devinitdata agp_sis_agp_spec = -1; + +static int sis_fetch_size(void) +{ + u8 temp_size; + int i; + struct aper_size_info_8 *values; + + pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size); + values = A_SIZE_8(agp_bridge->driver->aperture_sizes); + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if ((temp_size == values[i].size_value) || + ((temp_size & ~(0x03)) == + (values[i].size_value & ~(0x03)))) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + + return 0; +} + +static void sis_tlbflush(struct agp_memory *mem) +{ + pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02); +} + +static int sis_configure(void) +{ + u32 temp; + struct aper_size_info_8 *current_size; + + current_size = A_SIZE_8(agp_bridge->current_size); + pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05); + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE, + agp_bridge->gatt_bus_addr); + pci_write_config_byte(agp_bridge->dev, SIS_APSIZE, + current_size->size_value); + return 0; +} + +static void sis_cleanup(void) +{ + struct aper_size_info_8 *previous_size; + + previous_size = A_SIZE_8(agp_bridge->previous_size); + pci_write_config_byte(agp_bridge->dev, SIS_APSIZE, + (previous_size->size_value & ~(0x03))); +} + +static void sis_delayed_enable(struct agp_bridge_data *bridge, u32 mode) +{ + struct pci_dev *device = NULL; + u32 command; + int rate; + + printk(KERN_INFO PFX "Found an AGP %d.%d compliant device at %s.\n", + agp_bridge->major_version, + agp_bridge->minor_version, + pci_name(agp_bridge->dev)); + + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + PCI_AGP_STATUS, &command); + command = agp_collect_device_status(bridge, mode, command); + command |= AGPSTAT_AGP_ENABLE; + rate = (command & 0x7) << 2; + + for_each_pci_dev(device) { + u8 agp = pci_find_capability(device, PCI_CAP_ID_AGP); + if (!agp) + continue; + + printk(KERN_INFO PFX "Putting AGP V3 device at %s into %dx mode\n", + pci_name(device), rate); + + pci_write_config_dword(device, agp + PCI_AGP_COMMAND, command); + + /* + * Weird: on some sis chipsets any rate change in the target + * command register triggers a 5ms screwup during which the master + * cannot be configured + */ + if (device->device == bridge->dev->device) { + printk(KERN_INFO PFX "SiS delay workaround: giving bridge time to recover.\n"); + msleep(10); + } + } +} + +static struct aper_size_info_8 sis_generic_sizes[7] = +{ + {256, 65536, 6, 99}, + {128, 32768, 5, 83}, + {64, 16384, 4, 67}, + {32, 8192, 3, 51}, + {16, 4096, 2, 35}, + {8, 2048, 1, 19}, + {4, 1024, 0, 3} +}; + +struct agp_bridge_driver sis_driver = { + .owner = THIS_MODULE, + .aperture_sizes = sis_generic_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 7, + .configure = sis_configure, + .fetch_size = sis_fetch_size, + .cleanup = sis_cleanup, + .tlb_flush = sis_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = NULL, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_device_ids sis_agp_device_ids[] __devinitdata = +{ + { + .device_id = PCI_DEVICE_ID_SI_5591_AGP, + .chipset_name = "5591", + }, + { + .device_id = PCI_DEVICE_ID_SI_530, + .chipset_name = "530", + }, + { + .device_id = PCI_DEVICE_ID_SI_540, + .chipset_name = "540", + }, + { + .device_id = PCI_DEVICE_ID_SI_550, + .chipset_name = "550", + }, + { + .device_id = PCI_DEVICE_ID_SI_620, + .chipset_name = "620", + }, + { + .device_id = PCI_DEVICE_ID_SI_630, + .chipset_name = "630", + }, + { + .device_id = PCI_DEVICE_ID_SI_635, + .chipset_name = "635", + }, + { + .device_id = PCI_DEVICE_ID_SI_645, + .chipset_name = "645", + }, + { + .device_id = PCI_DEVICE_ID_SI_646, + .chipset_name = "646", + }, + { + .device_id = PCI_DEVICE_ID_SI_648, + .chipset_name = "648", + }, + { + .device_id = PCI_DEVICE_ID_SI_650, + .chipset_name = "650", + }, + { + .device_id = PCI_DEVICE_ID_SI_651, + .chipset_name = "651", + }, + { + .device_id = PCI_DEVICE_ID_SI_655, + .chipset_name = "655", + }, + { + .device_id = PCI_DEVICE_ID_SI_661, + .chipset_name = "661", + }, + { + .device_id = PCI_DEVICE_ID_SI_730, + .chipset_name = "730", + }, + { + .device_id = PCI_DEVICE_ID_SI_735, + .chipset_name = "735", + }, + { + .device_id = PCI_DEVICE_ID_SI_740, + .chipset_name = "740", + }, + { + .device_id = PCI_DEVICE_ID_SI_741, + .chipset_name = "741", + }, + { + .device_id = PCI_DEVICE_ID_SI_745, + .chipset_name = "745", + }, + { + .device_id = PCI_DEVICE_ID_SI_746, + .chipset_name = "746", + }, + { + .device_id = PCI_DEVICE_ID_SI_760, + .chipset_name = "760", + }, + { }, /* dummy final entry, always present */ +}; + + +// chipsets that require the 'delay hack' +static int sis_broken_chipsets[] __devinitdata = { + PCI_DEVICE_ID_SI_648, + PCI_DEVICE_ID_SI_746, + 0 // terminator +}; + +static void __devinit sis_get_driver(struct agp_bridge_data *bridge) +{ + int i; + + for(i=0; sis_broken_chipsets[i]!=0; ++i) + if(bridge->dev->device==sis_broken_chipsets[i]) + break; + + if(sis_broken_chipsets[i] || agp_sis_force_delay) + sis_driver.agp_enable=sis_delayed_enable; + + // sis chipsets that indicate less than agp3.5 + // are not actually fully agp3 compliant + if ((agp_bridge->major_version == 3 && agp_bridge->minor_version >= 5 + && agp_sis_agp_spec!=0) || agp_sis_agp_spec==1) { + sis_driver.aperture_sizes = agp3_generic_sizes; + sis_driver.size_type = U16_APER_SIZE; + sis_driver.num_aperture_sizes = AGP_GENERIC_SIZES_ENTRIES; + sis_driver.configure = agp3_generic_configure; + sis_driver.fetch_size = agp3_generic_fetch_size; + sis_driver.cleanup = agp3_generic_cleanup; + sis_driver.tlb_flush = agp3_generic_tlbflush; + } +} + + +static int __devinit agp_sis_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_device_ids *devs = sis_agp_device_ids; + struct agp_bridge_data *bridge; + u8 cap_ptr; + int j; + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (!cap_ptr) + return -ENODEV; + + /* probe for known chipsets */ + for (j = 0; devs[j].chipset_name; j++) { + if (pdev->device == devs[j].device_id) { + printk(KERN_INFO PFX "Detected SiS %s chipset\n", + devs[j].chipset_name); + goto found; + } + } + + printk(KERN_ERR PFX "Unsupported SiS chipset (device id: %04x)\n", + pdev->device); + return -ENODEV; + +found: + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + bridge->driver = &sis_driver; + bridge->dev = pdev; + bridge->capndx = cap_ptr; + + get_agp_version(bridge); + + /* Fill in the mode register */ + pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); + sis_get_driver(bridge); + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void __devexit agp_sis_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +static struct pci_device_id agp_sis_pci_table[] = { + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_SI, + .device = PCI_ANY_ID, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_sis_pci_table); + +static struct pci_driver agp_sis_pci_driver = { + .name = "agpgart-sis", + .id_table = agp_sis_pci_table, + .probe = agp_sis_probe, + .remove = agp_sis_remove, +}; + +static int __init agp_sis_init(void) +{ + if (agp_off) + return -EINVAL; + return pci_register_driver(&agp_sis_pci_driver); +} + +static void __exit agp_sis_cleanup(void) +{ + pci_unregister_driver(&agp_sis_pci_driver); +} + +module_init(agp_sis_init); +module_exit(agp_sis_cleanup); + +module_param(agp_sis_force_delay, bool, 0); +MODULE_PARM_DESC(agp_sis_force_delay,"forces sis delay hack"); +module_param(agp_sis_agp_spec, int, 0); +MODULE_PARM_DESC(agp_sis_agp_spec,"0=force sis init, 1=force generic agp3 init, default: autodetect"); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/agp/sworks-agp.c b/drivers/char/agp/sworks-agp.c new file mode 100644 index 000000000000..bb338d9134e0 --- /dev/null +++ b/drivers/char/agp/sworks-agp.c @@ -0,0 +1,556 @@ +/* + * Serverworks AGPGART routines. + */ + +#include +#include +#include +#include +#include "agp.h" + +#define SVWRKS_COMMAND 0x04 +#define SVWRKS_APSIZE 0x10 +#define SVWRKS_MMBASE 0x14 +#define SVWRKS_CACHING 0x4b +#define SVWRKS_AGP_ENABLE 0x60 +#define SVWRKS_FEATURE 0x68 + +#define SVWRKS_SIZE_MASK 0xfe000000 + +/* Memory mapped registers */ +#define SVWRKS_GART_CACHE 0x02 +#define SVWRKS_GATTBASE 0x04 +#define SVWRKS_TLBFLUSH 0x10 +#define SVWRKS_POSTFLUSH 0x14 +#define SVWRKS_DIRFLUSH 0x0c + + +struct serverworks_page_map { + unsigned long *real; + unsigned long __iomem *remapped; +}; + +static struct _serverworks_private { + struct pci_dev *svrwrks_dev; /* device one */ + volatile u8 __iomem *registers; + struct serverworks_page_map **gatt_pages; + int num_tables; + struct serverworks_page_map scratch_dir; + + int gart_addr_ofs; + int mm_addr_ofs; +} serverworks_private; + +static int serverworks_create_page_map(struct serverworks_page_map *page_map) +{ + int i; + + page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL); + if (page_map->real == NULL) { + return -ENOMEM; + } + SetPageReserved(virt_to_page(page_map->real)); + global_cache_flush(); + page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real), + PAGE_SIZE); + if (page_map->remapped == NULL) { + ClearPageReserved(virt_to_page(page_map->real)); + free_page((unsigned long) page_map->real); + page_map->real = NULL; + return -ENOMEM; + } + global_cache_flush(); + + for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) + writel(agp_bridge->scratch_page, page_map->remapped+i); + + return 0; +} + +static void serverworks_free_page_map(struct serverworks_page_map *page_map) +{ + iounmap(page_map->remapped); + ClearPageReserved(virt_to_page(page_map->real)); + free_page((unsigned long) page_map->real); +} + +static void serverworks_free_gatt_pages(void) +{ + int i; + struct serverworks_page_map **tables; + struct serverworks_page_map *entry; + + tables = serverworks_private.gatt_pages; + for(i = 0; i < serverworks_private.num_tables; i++) { + entry = tables[i]; + if (entry != NULL) { + if (entry->real != NULL) { + serverworks_free_page_map(entry); + } + kfree(entry); + } + } + kfree(tables); +} + +static int serverworks_create_gatt_pages(int nr_tables) +{ + struct serverworks_page_map **tables; + struct serverworks_page_map *entry; + int retval = 0; + int i; + + tables = kmalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *), + GFP_KERNEL); + if (tables == NULL) { + return -ENOMEM; + } + memset(tables, 0, sizeof(struct serverworks_page_map *) * (nr_tables + 1)); + for (i = 0; i < nr_tables; i++) { + entry = kmalloc(sizeof(struct serverworks_page_map), GFP_KERNEL); + if (entry == NULL) { + retval = -ENOMEM; + break; + } + memset(entry, 0, sizeof(struct serverworks_page_map)); + tables[i] = entry; + retval = serverworks_create_page_map(entry); + if (retval != 0) break; + } + serverworks_private.num_tables = nr_tables; + serverworks_private.gatt_pages = tables; + + if (retval != 0) serverworks_free_gatt_pages(); + + return retval; +} + +#define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\ + GET_PAGE_DIR_IDX(addr)]->remapped) + +#ifndef GET_PAGE_DIR_OFF +#define GET_PAGE_DIR_OFF(addr) (addr >> 22) +#endif + +#ifndef GET_PAGE_DIR_IDX +#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \ + GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr)) +#endif + +#ifndef GET_GATT_OFF +#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12) +#endif + +static int serverworks_create_gatt_table(struct agp_bridge_data *bridge) +{ + struct aper_size_info_lvl2 *value; + struct serverworks_page_map page_dir; + int retval; + u32 temp; + int i; + + value = A_SIZE_LVL2(agp_bridge->current_size); + retval = serverworks_create_page_map(&page_dir); + if (retval != 0) { + return retval; + } + retval = serverworks_create_page_map(&serverworks_private.scratch_dir); + if (retval != 0) { + serverworks_free_page_map(&page_dir); + return retval; + } + /* Create a fake scratch directory */ + for(i = 0; i < 1024; i++) { + writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i); + writel(virt_to_phys(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i); + } + + retval = serverworks_create_gatt_pages(value->num_entries / 1024); + if (retval != 0) { + serverworks_free_page_map(&page_dir); + serverworks_free_page_map(&serverworks_private.scratch_dir); + return retval; + } + + agp_bridge->gatt_table_real = (u32 *)page_dir.real; + agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped; + agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real); + + /* Get the address for the gart region. + * This is a bus address even on the alpha, b/c its + * used to program the agp master not the cpu + */ + + pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* Calculate the agp offset */ + + for(i = 0; i < value->num_entries / 1024; i++) + writel(virt_to_phys(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i); + + return 0; +} + +static int serverworks_free_gatt_table(struct agp_bridge_data *bridge) +{ + struct serverworks_page_map page_dir; + + page_dir.real = (unsigned long *)agp_bridge->gatt_table_real; + page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table; + + serverworks_free_gatt_pages(); + serverworks_free_page_map(&page_dir); + serverworks_free_page_map(&serverworks_private.scratch_dir); + return 0; +} + +static int serverworks_fetch_size(void) +{ + int i; + u32 temp; + u32 temp2; + struct aper_size_info_lvl2 *values; + + values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes); + pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp); + pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs, + SVWRKS_SIZE_MASK); + pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2); + pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp); + temp2 &= SVWRKS_SIZE_MASK; + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp2 == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + + return 0; +} + +/* + * This routine could be implemented by taking the addresses + * written to the GATT, and flushing them individually. However + * currently it just flushes the whole table. Which is probably + * more efficent, since agp_memory blocks can be a large number of + * entries. + */ +static void serverworks_tlbflush(struct agp_memory *temp) +{ + writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH); + while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) + cpu_relax(); + + writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH); + while(readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) + cpu_relax(); +} + +static int serverworks_configure(void) +{ + struct aper_size_info_lvl2 *current_size; + u32 temp; + u8 enable_reg; + u16 cap_reg; + + current_size = A_SIZE_LVL2(agp_bridge->current_size); + + /* Get the memory mapped registers */ + pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp); + temp = (temp & PCI_BASE_ADDRESS_MEM_MASK); + serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); + if (!serverworks_private.registers) { + printk (KERN_ERR PFX "Unable to ioremap() memory.\n"); + return -ENOMEM; + } + + writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE); + readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */ + + writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE); + readl(serverworks_private.registers+SVWRKS_GATTBASE); /* PCI Posting. */ + + cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND); + cap_reg &= ~0x0007; + cap_reg |= 0x4; + writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND); + readw(serverworks_private.registers+SVWRKS_COMMAND); + + pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg); + enable_reg |= 0x1; /* Agp Enable bit */ + pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg); + serverworks_tlbflush(NULL); + + agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP); + + /* Fill in the mode register */ + pci_read_config_dword(serverworks_private.svrwrks_dev, + agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode); + + pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg); + enable_reg &= ~0x3; + pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg); + + pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg); + enable_reg |= (1<<6); + pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg); + + return 0; +} + +static void serverworks_cleanup(void) +{ + iounmap((void __iomem *) serverworks_private.registers); +} + +static int serverworks_insert_memory(struct agp_memory *mem, + off_t pg_start, int type) +{ + int i, j, num_entries; + unsigned long __iomem *cur_gatt; + unsigned long addr; + + num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; + + if (type != 0 || mem->type != 0) { + return -EINVAL; + } + if ((pg_start + mem->page_count) > num_entries) { + return -EINVAL; + } + + j = pg_start; + while (j < (pg_start + mem->page_count)) { + addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; + cur_gatt = SVRWRKS_GET_GATT(addr); + if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr)))) + return -EBUSY; + j++; + } + + if (mem->is_flushed == FALSE) { + global_cache_flush(); + mem->is_flushed = TRUE; + } + + for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { + addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; + cur_gatt = SVRWRKS_GET_GATT(addr); + writel(agp_bridge->driver->mask_memory(agp_bridge, mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr)); + } + serverworks_tlbflush(mem); + return 0; +} + +static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start, + int type) +{ + int i; + unsigned long __iomem *cur_gatt; + unsigned long addr; + + if (type != 0 || mem->type != 0) { + return -EINVAL; + } + + global_cache_flush(); + serverworks_tlbflush(mem); + + for (i = pg_start; i < (mem->page_count + pg_start); i++) { + addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr; + cur_gatt = SVRWRKS_GET_GATT(addr); + writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr)); + } + + serverworks_tlbflush(mem); + return 0; +} + +static struct gatt_mask serverworks_masks[] = +{ + {.mask = 1, .type = 0} +}; + +static struct aper_size_info_lvl2 serverworks_sizes[7] = +{ + {2048, 524288, 0x80000000}, + {1024, 262144, 0xc0000000}, + {512, 131072, 0xe0000000}, + {256, 65536, 0xf0000000}, + {128, 32768, 0xf8000000}, + {64, 16384, 0xfc000000}, + {32, 8192, 0xfe000000} +}; + +static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode) +{ + u32 command; + + pci_read_config_dword(serverworks_private.svrwrks_dev, + bridge->capndx + PCI_AGP_STATUS, + &command); + + command = agp_collect_device_status(bridge, mode, command); + + command &= ~0x10; /* disable FW */ + command &= ~0x08; + + command |= 0x100; + + pci_write_config_dword(serverworks_private.svrwrks_dev, + bridge->capndx + PCI_AGP_COMMAND, + command); + + agp_device_command(command, 0); +} + +struct agp_bridge_driver sworks_driver = { + .owner = THIS_MODULE, + .aperture_sizes = serverworks_sizes, + .size_type = LVL2_APER_SIZE, + .num_aperture_sizes = 7, + .configure = serverworks_configure, + .fetch_size = serverworks_fetch_size, + .cleanup = serverworks_cleanup, + .tlb_flush = serverworks_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = serverworks_masks, + .agp_enable = serverworks_agp_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = serverworks_create_gatt_table, + .free_gatt_table = serverworks_free_gatt_table, + .insert_memory = serverworks_insert_memory, + .remove_memory = serverworks_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static int __devinit agp_serverworks_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_bridge_data *bridge; + struct pci_dev *bridge_dev; + u32 temp, temp2; + u8 cap_ptr = 0; + + /* Everything is on func 1 here so we are hardcoding function one */ + bridge_dev = pci_find_slot((unsigned int)pdev->bus->number, + PCI_DEVFN(0, 1)); + if (!bridge_dev) { + printk(KERN_INFO PFX "Detected a Serverworks chipset " + "but could not find the secondary device.\n"); + return -ENODEV; + } + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + + switch (pdev->device) { + case 0x0006: + /* ServerWorks CNB20HE + Fail silently.*/ + printk (KERN_ERR PFX "Detected ServerWorks CNB20HE chipset: No AGP present.\n"); + return -ENODEV; + + case PCI_DEVICE_ID_SERVERWORKS_HE: + case PCI_DEVICE_ID_SERVERWORKS_LE: + case 0x0007: + break; + + default: + if (cap_ptr) + printk(KERN_ERR PFX "Unsupported Serverworks chipset " + "(device id: %04x)\n", pdev->device); + return -ENODEV; + } + + serverworks_private.svrwrks_dev = bridge_dev; + serverworks_private.gart_addr_ofs = 0x10; + + pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp); + if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) { + pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2); + if (temp2 != 0) { + printk(KERN_INFO PFX "Detected 64 bit aperture address, " + "but top bits are not zero. Disabling agp\n"); + return -ENODEV; + } + serverworks_private.mm_addr_ofs = 0x18; + } else + serverworks_private.mm_addr_ofs = 0x14; + + pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp); + if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) { + pci_read_config_dword(pdev, + serverworks_private.mm_addr_ofs + 4, &temp2); + if (temp2 != 0) { + printk(KERN_INFO PFX "Detected 64 bit MMIO address, " + "but top bits are not zero. Disabling agp\n"); + return -ENODEV; + } + } + + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + bridge->driver = &sworks_driver; + bridge->dev_private_data = &serverworks_private, + bridge->dev = pdev; + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void __devexit agp_serverworks_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +static struct pci_device_id agp_serverworks_pci_table[] = { + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_ANY_ID, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table); + +static struct pci_driver agp_serverworks_pci_driver = { + .name = "agpgart-serverworks", + .id_table = agp_serverworks_pci_table, + .probe = agp_serverworks_probe, + .remove = agp_serverworks_remove, +}; + +static int __init agp_serverworks_init(void) +{ + if (agp_off) + return -EINVAL; + return pci_register_driver(&agp_serverworks_pci_driver); +} + +static void __exit agp_serverworks_cleanup(void) +{ + pci_unregister_driver(&agp_serverworks_pci_driver); +} + +module_init(agp_serverworks_init); +module_exit(agp_serverworks_cleanup); + +MODULE_LICENSE("GPL and additional rights"); + diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c new file mode 100644 index 000000000000..0f248239b4ba --- /dev/null +++ b/drivers/char/agp/uninorth-agp.c @@ -0,0 +1,647 @@ +/* + * UniNorth AGPGART routines. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "agp.h" + +/* + * NOTES for uninorth3 (G5 AGP) supports : + * + * There maybe also possibility to have bigger cache line size for + * agp (see pmac_pci.c and look for cache line). Need to be investigated + * by someone. + * + * PAGE size are hardcoded but this may change, see asm/page.h. + * + * Jerome Glisse + */ +static int uninorth_rev; +static int is_u3; + +static int uninorth_fetch_size(void) +{ + int i; + u32 temp; + struct aper_size_info_32 *values; + + pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_BASE, &temp); + temp &= ~(0xfffff000); + values = A_SIZE_32(agp_bridge->driver->aperture_sizes); + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + 1); + agp_bridge->aperture_size_idx = 1; + return values[1].size; + + return 0; +} + +static void uninorth_tlbflush(struct agp_memory *mem) +{ + u32 ctrl = UNI_N_CFG_GART_ENABLE; + + if (is_u3) + ctrl |= U3_N_CFG_GART_PERFRD; + pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, + ctrl | UNI_N_CFG_GART_INVAL); + pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl); + + if (uninorth_rev <= 0x30) { + pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, + ctrl | UNI_N_CFG_GART_2xRESET); + pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, + ctrl); + } +} + +static void uninorth_cleanup(void) +{ + u32 tmp; + + pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp); + if (!(tmp & UNI_N_CFG_GART_ENABLE)) + return; + tmp |= UNI_N_CFG_GART_INVAL; + pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp); + pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0); + + if (uninorth_rev <= 0x30) { + pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, + UNI_N_CFG_GART_2xRESET); + pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, + 0); + } +} + +static int uninorth_configure(void) +{ + struct aper_size_info_32 *current_size; + + current_size = A_SIZE_32(agp_bridge->current_size); + + printk(KERN_INFO PFX "configuring for size idx: %d\n", + current_size->size_value); + + /* aperture size and gatt addr */ + pci_write_config_dword(agp_bridge->dev, + UNI_N_CFG_GART_BASE, + (agp_bridge->gatt_bus_addr & 0xfffff000) + | current_size->size_value); + + /* HACK ALERT + * UniNorth seem to be buggy enough not to handle properly when + * the AGP aperture isn't mapped at bus physical address 0 + */ + agp_bridge->gart_bus_addr = 0; +#ifdef CONFIG_PPC64 + /* Assume U3 or later on PPC64 systems */ + /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */ + pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE, + (agp_bridge->gatt_bus_addr >> 32) & 0xf); +#else + pci_write_config_dword(agp_bridge->dev, + UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr); +#endif + + if (is_u3) { + pci_write_config_dword(agp_bridge->dev, + UNI_N_CFG_GART_DUMMY_PAGE, + agp_bridge->scratch_page_real >> 12); + } + + return 0; +} + +static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, + int type) +{ + int i, j, num_entries; + void *temp; + + temp = agp_bridge->current_size; + num_entries = A_SIZE_32(temp)->num_entries; + + if (type != 0 || mem->type != 0) + /* We know nothing of memory types */ + return -EINVAL; + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + + j = pg_start; + + while (j < (pg_start + mem->page_count)) { + if (agp_bridge->gatt_table[j]) + return -EBUSY; + j++; + } + + for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { + agp_bridge->gatt_table[j] = + cpu_to_le32((mem->memory[i] & 0xFFFFF000UL) | 0x1UL); + flush_dcache_range((unsigned long)__va(mem->memory[i]), + (unsigned long)__va(mem->memory[i])+0x1000); + } + (void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]); + mb(); + flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start], + (unsigned long)&agp_bridge->gatt_table[pg_start + mem->page_count]); + + uninorth_tlbflush(mem); + return 0; +} + +static int u3_insert_memory(struct agp_memory *mem, off_t pg_start, int type) +{ + int i, num_entries; + void *temp; + u32 *gp; + + temp = agp_bridge->current_size; + num_entries = A_SIZE_32(temp)->num_entries; + + if (type != 0 || mem->type != 0) + /* We know nothing of memory types */ + return -EINVAL; + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + + gp = (u32 *) &agp_bridge->gatt_table[pg_start]; + for (i = 0; i < mem->page_count; ++i) { + if (gp[i]) { + printk("u3_insert_memory: entry 0x%x occupied (%x)\n", + i, gp[i]); + return -EBUSY; + } + } + + for (i = 0; i < mem->page_count; i++) { + gp[i] = (mem->memory[i] >> PAGE_SHIFT) | 0x80000000UL; + flush_dcache_range((unsigned long)__va(mem->memory[i]), + (unsigned long)__va(mem->memory[i])+0x1000); + } + mb(); + flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]); + uninorth_tlbflush(mem); + + return 0; +} + +int u3_remove_memory(struct agp_memory *mem, off_t pg_start, int type) +{ + size_t i; + u32 *gp; + + if (type != 0 || mem->type != 0) + /* We know nothing of memory types */ + return -EINVAL; + + gp = (u32 *) &agp_bridge->gatt_table[pg_start]; + for (i = 0; i < mem->page_count; ++i) + gp[i] = 0; + mb(); + flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]); + uninorth_tlbflush(mem); + + return 0; +} + +static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode) +{ + u32 command, scratch, status; + int timeout; + + pci_read_config_dword(bridge->dev, + bridge->capndx + PCI_AGP_STATUS, + &status); + + command = agp_collect_device_status(bridge, mode, status); + command |= PCI_AGP_COMMAND_AGP; + + if (uninorth_rev == 0x21) { + /* + * Darwin disable AGP 4x on this revision, thus we + * may assume it's broken. This is an AGP2 controller. + */ + command &= ~AGPSTAT2_4X; + } + + if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) { + /* + * We need to to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1, + * 2.2 and 2.3, Darwin do so. + */ + if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7) + command = (command & ~AGPSTAT_RQ_DEPTH) + | (7 << AGPSTAT_RQ_DEPTH_SHIFT); + } + + uninorth_tlbflush(NULL); + + timeout = 0; + do { + pci_write_config_dword(bridge->dev, + bridge->capndx + PCI_AGP_COMMAND, + command); + pci_read_config_dword(bridge->dev, + bridge->capndx + PCI_AGP_COMMAND, + &scratch); + } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000); + if ((scratch & PCI_AGP_COMMAND_AGP) == 0) + printk(KERN_ERR PFX "failed to write UniNorth AGP command reg\n"); + + if (uninorth_rev >= 0x30) { + /* This is an AGP V3 */ + agp_device_command(command, (status & AGPSTAT_MODE_3_0)); + } else { + /* AGP V2 */ + agp_device_command(command, 0); + } + + uninorth_tlbflush(NULL); +} + +#ifdef CONFIG_PM +static int agp_uninorth_suspend(struct pci_dev *pdev, pm_message_t state) +{ + u32 cmd; + u8 agp; + struct pci_dev *device = NULL; + + if (state != PMSG_SUSPEND) + return 0; + + /* turn off AGP on the video chip, if it was enabled */ + for_each_pci_dev(device) { + /* Don't touch the bridge yet, device first */ + if (device == pdev) + continue; + /* Only deal with devices on the same bus here, no Mac has a P2P + * bridge on the AGP port, and mucking around the entire PCI + * tree is source of problems on some machines because of a bug + * in some versions of pci_find_capability() when hitting a dead + * device + */ + if (device->bus != pdev->bus) + continue; + agp = pci_find_capability(device, PCI_CAP_ID_AGP); + if (!agp) + continue; + pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd); + if (!(cmd & PCI_AGP_COMMAND_AGP)) + continue; + printk("uninorth-agp: disabling AGP on device %s\n", + pci_name(device)); + cmd &= ~PCI_AGP_COMMAND_AGP; + pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd); + } + + /* turn off AGP on the bridge */ + agp = pci_find_capability(pdev, PCI_CAP_ID_AGP); + pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd); + if (cmd & PCI_AGP_COMMAND_AGP) { + printk("uninorth-agp: disabling AGP on bridge %s\n", + pci_name(pdev)); + cmd &= ~PCI_AGP_COMMAND_AGP; + pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd); + } + /* turn off the GART */ + uninorth_cleanup(); + + return 0; +} + +static int agp_uninorth_resume(struct pci_dev *pdev) +{ + return 0; +} +#endif + +static int uninorth_create_gatt_table(struct agp_bridge_data *bridge) +{ + char *table; + char *table_end; + int size; + int page_order; + int num_entries; + int i; + void *temp; + struct page *page; + + /* We can't handle 2 level gatt's */ + if (bridge->driver->size_type == LVL2_APER_SIZE) + return -EINVAL; + + table = NULL; + i = bridge->aperture_size_idx; + temp = bridge->current_size; + size = page_order = num_entries = 0; + + do { + size = A_SIZE_32(temp)->size; + page_order = A_SIZE_32(temp)->page_order; + num_entries = A_SIZE_32(temp)->num_entries; + + table = (char *) __get_free_pages(GFP_KERNEL, page_order); + + if (table == NULL) { + i++; + bridge->current_size = A_IDX32(bridge); + } else { + bridge->aperture_size_idx = i; + } + } while (!table && (i < bridge->driver->num_aperture_sizes)); + + if (table == NULL) + return -ENOMEM; + + table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); + + for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) + SetPageReserved(page); + + bridge->gatt_table_real = (u32 *) table; + bridge->gatt_table = (u32 *)table; + bridge->gatt_bus_addr = virt_to_phys(table); + + for (i = 0; i < num_entries; i++) + bridge->gatt_table[i] = 0; + + flush_dcache_range((unsigned long)table, (unsigned long)table_end); + + return 0; +} + +static int uninorth_free_gatt_table(struct agp_bridge_data *bridge) +{ + int page_order; + char *table, *table_end; + void *temp; + struct page *page; + + temp = bridge->current_size; + page_order = A_SIZE_32(temp)->page_order; + + /* Do not worry about freeing memory, because if this is + * called, then all agp memory is deallocated and removed + * from the table. + */ + + table = (char *) bridge->gatt_table_real; + table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); + + for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) + ClearPageReserved(page); + + free_pages((unsigned long) bridge->gatt_table_real, page_order); + + return 0; +} + +void null_cache_flush(void) +{ + mb(); +} + +/* Setup function */ + +static struct aper_size_info_32 uninorth_sizes[7] = +{ +#if 0 /* Not sure uninorth supports that high aperture sizes */ + {256, 65536, 6, 64}, + {128, 32768, 5, 32}, + {64, 16384, 4, 16}, +#endif + {32, 8192, 3, 8}, + {16, 4096, 2, 4}, + {8, 2048, 1, 2}, + {4, 1024, 0, 1} +}; + +/* + * Not sure that u3 supports that high aperture sizes but it + * would strange if it did not :) + */ +static struct aper_size_info_32 u3_sizes[8] = +{ + {512, 131072, 7, 128}, + {256, 65536, 6, 64}, + {128, 32768, 5, 32}, + {64, 16384, 4, 16}, + {32, 8192, 3, 8}, + {16, 4096, 2, 4}, + {8, 2048, 1, 2}, + {4, 1024, 0, 1} +}; + +struct agp_bridge_driver uninorth_agp_driver = { + .owner = THIS_MODULE, + .aperture_sizes = (void *)uninorth_sizes, + .size_type = U32_APER_SIZE, + .num_aperture_sizes = 4, + .configure = uninorth_configure, + .fetch_size = uninorth_fetch_size, + .cleanup = uninorth_cleanup, + .tlb_flush = uninorth_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = NULL, + .cache_flush = null_cache_flush, + .agp_enable = uninorth_agp_enable, + .create_gatt_table = uninorth_create_gatt_table, + .free_gatt_table = uninorth_free_gatt_table, + .insert_memory = uninorth_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, + .cant_use_aperture = 1, +}; + +struct agp_bridge_driver u3_agp_driver = { + .owner = THIS_MODULE, + .aperture_sizes = (void *)u3_sizes, + .size_type = U32_APER_SIZE, + .num_aperture_sizes = 8, + .configure = uninorth_configure, + .fetch_size = uninorth_fetch_size, + .cleanup = uninorth_cleanup, + .tlb_flush = uninorth_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = NULL, + .cache_flush = null_cache_flush, + .agp_enable = uninorth_agp_enable, + .create_gatt_table = uninorth_create_gatt_table, + .free_gatt_table = uninorth_free_gatt_table, + .insert_memory = u3_insert_memory, + .remove_memory = u3_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, + .cant_use_aperture = 1, + .needs_scratch_page = 1, +}; + +static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = { + { + .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP, + .chipset_name = "UniNorth", + }, + { + .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P, + .chipset_name = "UniNorth/Pangea", + }, + { + .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP15, + .chipset_name = "UniNorth 1.5", + }, + { + .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2, + .chipset_name = "UniNorth 2", + }, + { + .device_id = PCI_DEVICE_ID_APPLE_U3_AGP, + .chipset_name = "U3", + }, + { + .device_id = PCI_DEVICE_ID_APPLE_U3L_AGP, + .chipset_name = "U3L", + }, + { + .device_id = PCI_DEVICE_ID_APPLE_U3H_AGP, + .chipset_name = "U3H", + }, +}; + +static int __devinit agp_uninorth_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_device_ids *devs = uninorth_agp_device_ids; + struct agp_bridge_data *bridge; + struct device_node *uninorth_node; + u8 cap_ptr; + int j; + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (cap_ptr == 0) + return -ENODEV; + + /* probe for known chipsets */ + for (j = 0; devs[j].chipset_name != NULL; ++j) { + if (pdev->device == devs[j].device_id) { + printk(KERN_INFO PFX "Detected Apple %s chipset\n", + devs[j].chipset_name); + goto found; + } + } + + printk(KERN_ERR PFX "Unsupported Apple chipset (device id: %04x).\n", + pdev->device); + return -ENODEV; + + found: + /* Set revision to 0 if we could not read it. */ + uninorth_rev = 0; + is_u3 = 0; + /* Locate core99 Uni-N */ + uninorth_node = of_find_node_by_name(NULL, "uni-n"); + /* Locate G5 u3 */ + if (uninorth_node == NULL) { + is_u3 = 1; + uninorth_node = of_find_node_by_name(NULL, "u3"); + } + if (uninorth_node) { + int *revprop = (int *) + get_property(uninorth_node, "device-rev", NULL); + if (revprop != NULL) + uninorth_rev = *revprop & 0x3f; + of_node_put(uninorth_node); + } + + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + if (is_u3) + bridge->driver = &u3_agp_driver; + else + bridge->driver = &uninorth_agp_driver; + + bridge->dev = pdev; + bridge->capndx = cap_ptr; + bridge->flags = AGP_ERRATA_FASTWRITES; + + /* Fill in the mode register */ + pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode); + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void __devexit agp_uninorth_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +static struct pci_device_id agp_uninorth_pci_table[] = { + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_APPLE, + .device = PCI_ANY_ID, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table); + +static struct pci_driver agp_uninorth_pci_driver = { + .name = "agpgart-uninorth", + .id_table = agp_uninorth_pci_table, + .probe = agp_uninorth_probe, + .remove = agp_uninorth_remove, +#ifdef CONFIG_PM + .suspend = agp_uninorth_suspend, + .resume = agp_uninorth_resume, +#endif +}; + +static int __init agp_uninorth_init(void) +{ + if (agp_off) + return -EINVAL; + return pci_register_driver(&agp_uninorth_pci_driver); +} + +static void __exit agp_uninorth_cleanup(void) +{ + pci_unregister_driver(&agp_uninorth_pci_driver); +} + +module_init(agp_uninorth_init); +module_exit(agp_uninorth_cleanup); + +MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras"); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/agp/via-agp.c b/drivers/char/agp/via-agp.c new file mode 100644 index 000000000000..e1451dd9b6a7 --- /dev/null +++ b/drivers/char/agp/via-agp.c @@ -0,0 +1,548 @@ +/* + * VIA AGPGART routines. + */ + +#include +#include +#include +#include +#include +#include "agp.h" + +static struct pci_device_id agp_via_pci_table[]; + +#define VIA_GARTCTRL 0x80 +#define VIA_APSIZE 0x84 +#define VIA_ATTBASE 0x88 + +#define VIA_AGP3_GARTCTRL 0x90 +#define VIA_AGP3_APSIZE 0x94 +#define VIA_AGP3_ATTBASE 0x98 +#define VIA_AGPSEL 0xfd + +static int via_fetch_size(void) +{ + int i; + u8 temp; + struct aper_size_info_8 *values; + + values = A_SIZE_8(agp_bridge->driver->aperture_sizes); + pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp); + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp); + return 0; +} + + +static int via_configure(void) +{ + u32 temp; + struct aper_size_info_8 *current_size; + + current_size = A_SIZE_8(agp_bridge->current_size); + /* aperture size */ + pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, + current_size->size_value); + /* address to map too */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* GART control register */ + pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f); + + /* attbase - aperture GATT base */ + pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE, + (agp_bridge->gatt_bus_addr & 0xfffff000) | 3); + return 0; +} + + +static void via_cleanup(void) +{ + struct aper_size_info_8 *previous_size; + + previous_size = A_SIZE_8(agp_bridge->previous_size); + pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, + previous_size->size_value); + /* Do not disable by writing 0 to VIA_ATTBASE, it screws things up + * during reinitialization. + */ +} + + +static void via_tlbflush(struct agp_memory *mem) +{ + u32 temp; + + pci_read_config_dword(agp_bridge->dev, VIA_GARTCTRL, &temp); + temp |= (1<<7); + pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp); + temp &= ~(1<<7); + pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp); +} + + +static struct aper_size_info_8 via_generic_sizes[9] = +{ + {256, 65536, 6, 0}, + {128, 32768, 5, 128}, + {64, 16384, 4, 192}, + {32, 8192, 3, 224}, + {16, 4096, 2, 240}, + {8, 2048, 1, 248}, + {4, 1024, 0, 252}, + {2, 512, 0, 254}, + {1, 256, 0, 255} +}; + + +static int via_fetch_size_agp3(void) +{ + int i; + u16 temp; + struct aper_size_info_16 *values; + + values = A_SIZE_16(agp_bridge->driver->aperture_sizes); + pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp); + temp &= 0xfff; + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + return 0; +} + + +static int via_configure_agp3(void) +{ + u32 temp; + struct aper_size_info_16 *current_size; + + current_size = A_SIZE_16(agp_bridge->current_size); + + /* address to map too */ + pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* attbase - aperture GATT base */ + pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE, + agp_bridge->gatt_bus_addr & 0xfffff000); + + /* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch + * translation table first. + * 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the + * graphics AGP aperture for the AGP3.0 port. + */ + pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp | (3<<7)); + return 0; +} + + +static void via_cleanup_agp3(void) +{ + struct aper_size_info_16 *previous_size; + + previous_size = A_SIZE_16(agp_bridge->previous_size); + pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value); +} + + +static void via_tlbflush_agp3(struct agp_memory *mem) +{ + u32 temp; + + pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7)); + pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp); +} + + +struct agp_bridge_driver via_agp3_driver = { + .owner = THIS_MODULE, + .aperture_sizes = agp3_generic_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 10, + .configure = via_configure_agp3, + .fetch_size = via_fetch_size_agp3, + .cleanup = via_cleanup_agp3, + .tlb_flush = via_tlbflush_agp3, + .mask_memory = agp_generic_mask_memory, + .masks = NULL, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +struct agp_bridge_driver via_driver = { + .owner = THIS_MODULE, + .aperture_sizes = via_generic_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 9, + .configure = via_configure, + .fetch_size = via_fetch_size, + .cleanup = via_cleanup, + .tlb_flush = via_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = NULL, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_destroy_page = agp_generic_destroy_page, +}; + +static struct agp_device_ids via_agp_device_ids[] __devinitdata = +{ + { + .device_id = PCI_DEVICE_ID_VIA_82C597_0, + .chipset_name = "Apollo VP3", + }, + + { + .device_id = PCI_DEVICE_ID_VIA_82C598_0, + .chipset_name = "Apollo MVP3", + }, + + { + .device_id = PCI_DEVICE_ID_VIA_8501_0, + .chipset_name = "Apollo MVP4", + }, + + /* VT8601 */ + { + .device_id = PCI_DEVICE_ID_VIA_8601_0, + .chipset_name = "Apollo ProMedia/PLE133Ta", + }, + + /* VT82C693A / VT28C694T */ + { + .device_id = PCI_DEVICE_ID_VIA_82C691_0, + .chipset_name = "Apollo Pro 133", + }, + + { + .device_id = PCI_DEVICE_ID_VIA_8371_0, + .chipset_name = "KX133", + }, + + /* VT8633 */ + { + .device_id = PCI_DEVICE_ID_VIA_8633_0, + .chipset_name = "Pro 266", + }, + + { + .device_id = PCI_DEVICE_ID_VIA_XN266, + .chipset_name = "Apollo Pro266", + }, + + /* VT8361 */ + { + .device_id = PCI_DEVICE_ID_VIA_8361, + .chipset_name = "KLE133", + }, + + /* VT8365 / VT8362 */ + { + .device_id = PCI_DEVICE_ID_VIA_8363_0, + .chipset_name = "Twister-K/KT133x/KM133", + }, + + /* VT8753A */ + { + .device_id = PCI_DEVICE_ID_VIA_8753_0, + .chipset_name = "P4X266", + }, + + /* VT8366 */ + { + .device_id = PCI_DEVICE_ID_VIA_8367_0, + .chipset_name = "KT266/KY266x/KT333", + }, + + /* VT8633 (for CuMine/ Celeron) */ + { + .device_id = PCI_DEVICE_ID_VIA_8653_0, + .chipset_name = "Pro266T", + }, + + /* KM266 / PM266 */ + { + .device_id = PCI_DEVICE_ID_VIA_XM266, + .chipset_name = "PM266/KM266", + }, + + /* CLE266 */ + { + .device_id = PCI_DEVICE_ID_VIA_862X_0, + .chipset_name = "CLE266", + }, + + { + .device_id = PCI_DEVICE_ID_VIA_8377_0, + .chipset_name = "KT400/KT400A/KT600", + }, + + /* VT8604 / VT8605 / VT8603 + * (Apollo Pro133A chipset with S3 Savage4) */ + { + .device_id = PCI_DEVICE_ID_VIA_8605_0, + .chipset_name = "ProSavage PM133/PL133/PN133" + }, + + /* P4M266x/P4N266 */ + { + .device_id = PCI_DEVICE_ID_VIA_8703_51_0, + .chipset_name = "P4M266x/P4N266", + }, + + /* VT8754 */ + { + .device_id = PCI_DEVICE_ID_VIA_8754C_0, + .chipset_name = "PT800", + }, + + /* P4X600 */ + { + .device_id = PCI_DEVICE_ID_VIA_8763_0, + .chipset_name = "P4X600" + }, + + /* KM400 */ + { + .device_id = PCI_DEVICE_ID_VIA_8378_0, + .chipset_name = "KM400/KM400A", + }, + + /* PT880 */ + { + .device_id = PCI_DEVICE_ID_VIA_PT880, + .chipset_name = "PT880", + }, + + /* PT890 */ + { + .device_id = PCI_DEVICE_ID_VIA_8783_0, + .chipset_name = "PT890", + }, + + /* PM800/PN800/PM880/PN880 */ + { + .device_id = PCI_DEVICE_ID_VIA_PX8X0_0, + .chipset_name = "PM800/PN800/PM880/PN880", + }, + /* KT880 */ + { + .device_id = PCI_DEVICE_ID_VIA_3269_0, + .chipset_name = "KT880", + }, + /* KTxxx/Px8xx */ + { + .device_id = PCI_DEVICE_ID_VIA_83_87XX_1, + .chipset_name = "VT83xx/VT87xx/KTxxx/Px8xx", + }, + /* P4M800 */ + { + .device_id = PCI_DEVICE_ID_VIA_3296_0, + .chipset_name = "P4M800", + }, + + { }, /* dummy final entry, always present */ +}; + + +/* + * VIA's AGP3 chipsets do magick to put the AGP bridge compliant + * with the same standards version as the graphics card. + */ +static void check_via_agp3 (struct agp_bridge_data *bridge) +{ + u8 reg; + + pci_read_config_byte(bridge->dev, VIA_AGPSEL, ®); + /* Check AGP 2.0 compatibility mode. */ + if ((reg & (1<<1))==0) + bridge->driver = &via_agp3_driver; +} + + +static int __devinit agp_via_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_device_ids *devs = via_agp_device_ids; + struct agp_bridge_data *bridge; + int j = 0; + u8 cap_ptr; + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (!cap_ptr) + return -ENODEV; + + j = ent - agp_via_pci_table; + printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name); + + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + bridge->dev = pdev; + bridge->capndx = cap_ptr; + bridge->driver = &via_driver; + + /* + * Garg, there are KT400s with KT266 IDs. + */ + if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) { + /* Is there a KT400 subsystem ? */ + if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) { + printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n"); + check_via_agp3(bridge); + } + } + + /* If this is an AGP3 bridge, check which mode its in and adjust. */ + get_agp_version(bridge); + if (bridge->major_version >= 3) + check_via_agp3(bridge); + + /* Fill in the mode register */ + pci_read_config_dword(pdev, + bridge->capndx+PCI_AGP_STATUS, &bridge->mode); + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void __devexit agp_via_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +#ifdef CONFIG_PM + +static int agp_via_suspend(struct pci_dev *pdev, pm_message_t state) +{ + pci_save_state (pdev); + pci_set_power_state (pdev, PCI_D3hot); + + return 0; +} + +static int agp_via_resume(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + pci_set_power_state (pdev, PCI_D0); + pci_restore_state(pdev); + + if (bridge->driver == &via_agp3_driver) + return via_configure_agp3(); + else if (bridge->driver == &via_driver) + return via_configure(); + + return 0; +} + +#endif /* CONFIG_PM */ + +/* must be the same order as name table above */ +static struct pci_device_id agp_via_pci_table[] = { +#define ID(x) \ + { \ + .class = (PCI_CLASS_BRIDGE_HOST << 8), \ + .class_mask = ~0, \ + .vendor = PCI_VENDOR_ID_VIA, \ + .device = x, \ + .subvendor = PCI_ANY_ID, \ + .subdevice = PCI_ANY_ID, \ + } + ID(PCI_DEVICE_ID_VIA_82C597_0), + ID(PCI_DEVICE_ID_VIA_82C598_0), + ID(PCI_DEVICE_ID_VIA_8501_0), + ID(PCI_DEVICE_ID_VIA_8601_0), + ID(PCI_DEVICE_ID_VIA_82C691_0), + ID(PCI_DEVICE_ID_VIA_8371_0), + ID(PCI_DEVICE_ID_VIA_8633_0), + ID(PCI_DEVICE_ID_VIA_XN266), + ID(PCI_DEVICE_ID_VIA_8361), + ID(PCI_DEVICE_ID_VIA_8363_0), + ID(PCI_DEVICE_ID_VIA_8753_0), + ID(PCI_DEVICE_ID_VIA_8367_0), + ID(PCI_DEVICE_ID_VIA_8653_0), + ID(PCI_DEVICE_ID_VIA_XM266), + ID(PCI_DEVICE_ID_VIA_862X_0), + ID(PCI_DEVICE_ID_VIA_8377_0), + ID(PCI_DEVICE_ID_VIA_8605_0), + ID(PCI_DEVICE_ID_VIA_8703_51_0), + ID(PCI_DEVICE_ID_VIA_8754C_0), + ID(PCI_DEVICE_ID_VIA_8763_0), + ID(PCI_DEVICE_ID_VIA_8378_0), + ID(PCI_DEVICE_ID_VIA_PT880), + ID(PCI_DEVICE_ID_VIA_8783_0), + ID(PCI_DEVICE_ID_VIA_PX8X0_0), + ID(PCI_DEVICE_ID_VIA_3269_0), + ID(PCI_DEVICE_ID_VIA_83_87XX_1), + ID(PCI_DEVICE_ID_VIA_3296_0), + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_via_pci_table); + + +static struct pci_driver agp_via_pci_driver = { + .name = "agpgart-via", + .id_table = agp_via_pci_table, + .probe = agp_via_probe, + .remove = agp_via_remove, +#ifdef CONFIG_PM + .suspend = agp_via_suspend, + .resume = agp_via_resume, +#endif +}; + + +static int __init agp_via_init(void) +{ + if (agp_off) + return -EINVAL; + return pci_register_driver(&agp_via_pci_driver); +} + +static void __exit agp_via_cleanup(void) +{ + pci_unregister_driver(&agp_via_pci_driver); +} + +module_init(agp_via_init); +module_exit(agp_via_cleanup); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Dave Jones "); diff --git a/drivers/char/amiserial.c b/drivers/char/amiserial.c new file mode 100644 index 000000000000..1dc4259213a6 --- /dev/null +++ b/drivers/char/amiserial.c @@ -0,0 +1,2179 @@ +/* + * linux/drivers/char/amiserial.c + * + * Serial driver for the amiga builtin port. + * + * This code was created by taking serial.c version 4.30 from kernel + * release 2.3.22, replacing all hardware related stuff with the + * corresponding amiga hardware actions, and removing all irrelevant + * code. As a consequence, it uses many of the constants and names + * associated with the registers and bits of 16550 compatible UARTS - + * but only to keep track of status, etc in the state variables. It + * was done this was to make it easier to keep the code in line with + * (non hardware specific) changes to serial.c. + * + * The port is registered with the tty driver as minor device 64, and + * therefore other ports should should only use 65 upwards. + * + * Richard Lucock 28/12/99 + * + * Copyright (C) 1991, 1992 Linus Torvalds + * Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, + * 1998, 1999 Theodore Ts'o + * + */ + +/* + * Serial driver configuration section. Here are the various options: + * + * SERIAL_PARANOIA_CHECK + * Check the magic number for the async_structure where + * ever possible. + */ + +#include +#include + +#undef SERIAL_PARANOIA_CHECK +#define SERIAL_DO_RESTART + +/* Set of debugging defines */ + +#undef SERIAL_DEBUG_INTR +#undef SERIAL_DEBUG_OPEN +#undef SERIAL_DEBUG_FLOW +#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT + +/* Sanity checks */ + +#define SERIAL_INLINE + +#if defined(MODULE) && defined(SERIAL_DEBUG_MCOUNT) +#define DBG_CNT(s) printk("(%s): [%x] refc=%d, serc=%d, ttyc=%d -> %s\n", \ + tty->name, (info->flags), serial_driver->refcount,info->count,tty->count,s) +#else +#define DBG_CNT(s) +#endif + +/* + * End of serial driver configuration section. + */ + +#include + +#include +#include +#include +#include +static char *serial_version = "4.30"; + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +#include +#include + +#ifdef SERIAL_INLINE +#define _INLINE_ inline +#endif + +static char *serial_name = "Amiga-builtin serial driver"; + +static struct tty_driver *serial_driver; + +/* number of characters left in xmit buffer before we ask for more */ +#define WAKEUP_CHARS 256 + +static struct async_struct *IRQ_ports; + +static unsigned char current_ctl_bits; + +static void change_speed(struct async_struct *info, struct termios *old); +static void rs_wait_until_sent(struct tty_struct *tty, int timeout); + + +static struct serial_state rs_table[1]; + +#define NR_PORTS (sizeof(rs_table)/sizeof(struct serial_state)) + +/* + * tmp_buf is used as a temporary buffer by serial_write. We need to + * lock it in case the copy_from_user blocks while swapping in a page, + * and some other program tries to do a serial write at the same time. + * Since the lock will only come under contention when the system is + * swapping and available memory is low, it makes sense to share one + * buffer across all the serial ports, since it significantly saves + * memory if large numbers of serial ports are open. + */ +static unsigned char *tmp_buf; +static DECLARE_MUTEX(tmp_buf_sem); + +#include + +#define serial_isroot() (capable(CAP_SYS_ADMIN)) + + +static inline int serial_paranoia_check(struct async_struct *info, + char *name, const char *routine) +{ +#ifdef SERIAL_PARANOIA_CHECK + static const char *badmagic = + "Warning: bad magic number for serial struct (%s) in %s\n"; + static const char *badinfo = + "Warning: null async_struct for (%s) in %s\n"; + + if (!info) { + printk(badinfo, name, routine); + return 1; + } + if (info->magic != SERIAL_MAGIC) { + printk(badmagic, name, routine); + return 1; + } +#endif + return 0; +} + +/* some serial hardware definitions */ +#define SDR_OVRUN (1<<15) +#define SDR_RBF (1<<14) +#define SDR_TBE (1<<13) +#define SDR_TSRE (1<<12) + +#define SERPER_PARENB (1<<15) + +#define AC_SETCLR (1<<15) +#define AC_UARTBRK (1<<11) + +#define SER_DTR (1<<7) +#define SER_RTS (1<<6) +#define SER_DCD (1<<5) +#define SER_CTS (1<<4) +#define SER_DSR (1<<3) + +static __inline__ void rtsdtr_ctrl(int bits) +{ + ciab.pra = ((bits & (SER_RTS | SER_DTR)) ^ (SER_RTS | SER_DTR)) | (ciab.pra & ~(SER_RTS | SER_DTR)); +} + +/* + * ------------------------------------------------------------ + * rs_stop() and rs_start() + * + * This routines are called before setting or resetting tty->stopped. + * They enable or disable transmitter interrupts, as necessary. + * ------------------------------------------------------------ + */ +static void rs_stop(struct tty_struct *tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (serial_paranoia_check(info, tty->name, "rs_stop")) + return; + + local_irq_save(flags); + if (info->IER & UART_IER_THRI) { + info->IER &= ~UART_IER_THRI; + /* disable Tx interrupt and remove any pending interrupts */ + custom.intena = IF_TBE; + mb(); + custom.intreq = IF_TBE; + mb(); + } + local_irq_restore(flags); +} + +static void rs_start(struct tty_struct *tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (serial_paranoia_check(info, tty->name, "rs_start")) + return; + + local_irq_save(flags); + if (info->xmit.head != info->xmit.tail + && info->xmit.buf + && !(info->IER & UART_IER_THRI)) { + info->IER |= UART_IER_THRI; + custom.intena = IF_SETCLR | IF_TBE; + mb(); + /* set a pending Tx Interrupt, transmitter should restart now */ + custom.intreq = IF_SETCLR | IF_TBE; + mb(); + } + local_irq_restore(flags); +} + +/* + * ---------------------------------------------------------------------- + * + * Here starts the interrupt handling routines. All of the following + * subroutines are declared as inline and are folded into + * rs_interrupt(). They were separated out for readability's sake. + * + * Note: rs_interrupt() is a "fast" interrupt, which means that it + * runs with interrupts turned off. People who may want to modify + * rs_interrupt() should try to keep the interrupt handler as fast as + * possible. After you are done making modifications, it is not a bad + * idea to do: + * + * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c + * + * and look at the resulting assemble code in serial.s. + * + * - Ted Ts'o (tytso@mit.edu), 7-Mar-93 + * ----------------------------------------------------------------------- + */ + +/* + * This routine is used by the interrupt handler to schedule + * processing in the software interrupt portion of the driver. + */ +static _INLINE_ void rs_sched_event(struct async_struct *info, + int event) +{ + info->event |= 1 << event; + tasklet_schedule(&info->tlet); +} + +static _INLINE_ void receive_chars(struct async_struct *info) +{ + int status; + int serdatr; + struct tty_struct *tty = info->tty; + unsigned char ch; + struct async_icount *icount; + + icount = &info->state->icount; + + status = UART_LSR_DR; /* We obviously have a character! */ + serdatr = custom.serdatr; + mb(); + custom.intreq = IF_RBF; + mb(); + + if((serdatr & 0x1ff) == 0) + status |= UART_LSR_BI; + if(serdatr & SDR_OVRUN) + status |= UART_LSR_OE; + + ch = serdatr & 0xff; + if (tty->flip.count >= TTY_FLIPBUF_SIZE) + goto ignore_char; + *tty->flip.char_buf_ptr = ch; + icount->rx++; + +#ifdef SERIAL_DEBUG_INTR + printk("DR%02x:%02x...", ch, status); +#endif + *tty->flip.flag_buf_ptr = 0; + + /* + * We don't handle parity or frame errors - but I have left + * the code in, since I'm not sure that the errors can't be + * detected. + */ + + if (status & (UART_LSR_BI | UART_LSR_PE | + UART_LSR_FE | UART_LSR_OE)) { + /* + * For statistics only + */ + if (status & UART_LSR_BI) { + status &= ~(UART_LSR_FE | UART_LSR_PE); + icount->brk++; + } else if (status & UART_LSR_PE) + icount->parity++; + else if (status & UART_LSR_FE) + icount->frame++; + if (status & UART_LSR_OE) + icount->overrun++; + + /* + * Now check to see if character should be + * ignored, and mask off conditions which + * should be ignored. + */ + if (status & info->ignore_status_mask) + goto ignore_char; + + status &= info->read_status_mask; + + if (status & (UART_LSR_BI)) { +#ifdef SERIAL_DEBUG_INTR + printk("handling break...."); +#endif + *tty->flip.flag_buf_ptr = TTY_BREAK; + if (info->flags & ASYNC_SAK) + do_SAK(tty); + } else if (status & UART_LSR_PE) + *tty->flip.flag_buf_ptr = TTY_PARITY; + else if (status & UART_LSR_FE) + *tty->flip.flag_buf_ptr = TTY_FRAME; + if (status & UART_LSR_OE) { + /* + * Overrun is special, since it's + * reported immediately, and doesn't + * affect the current character + */ + if (tty->flip.count < TTY_FLIPBUF_SIZE) { + tty->flip.count++; + tty->flip.flag_buf_ptr++; + tty->flip.char_buf_ptr++; + *tty->flip.flag_buf_ptr = TTY_OVERRUN; + } + } + } + tty->flip.flag_buf_ptr++; + tty->flip.char_buf_ptr++; + tty->flip.count++; + ignore_char: + + tty_flip_buffer_push(tty); +} + +static _INLINE_ void transmit_chars(struct async_struct *info) +{ + custom.intreq = IF_TBE; + mb(); + if (info->x_char) { + custom.serdat = info->x_char | 0x100; + mb(); + info->state->icount.tx++; + info->x_char = 0; + return; + } + if (info->xmit.head == info->xmit.tail + || info->tty->stopped + || info->tty->hw_stopped) { + info->IER &= ~UART_IER_THRI; + custom.intena = IF_TBE; + mb(); + return; + } + + custom.serdat = info->xmit.buf[info->xmit.tail++] | 0x100; + mb(); + info->xmit.tail = info->xmit.tail & (SERIAL_XMIT_SIZE-1); + info->state->icount.tx++; + + if (CIRC_CNT(info->xmit.head, + info->xmit.tail, + SERIAL_XMIT_SIZE) < WAKEUP_CHARS) + rs_sched_event(info, RS_EVENT_WRITE_WAKEUP); + +#ifdef SERIAL_DEBUG_INTR + printk("THRE..."); +#endif + if (info->xmit.head == info->xmit.tail) { + custom.intena = IF_TBE; + mb(); + info->IER &= ~UART_IER_THRI; + } +} + +static _INLINE_ void check_modem_status(struct async_struct *info) +{ + unsigned char status = ciab.pra & (SER_DCD | SER_CTS | SER_DSR); + unsigned char dstatus; + struct async_icount *icount; + + /* Determine bits that have changed */ + dstatus = status ^ current_ctl_bits; + current_ctl_bits = status; + + if (dstatus) { + icount = &info->state->icount; + /* update input line counters */ + if (dstatus & SER_DSR) + icount->dsr++; + if (dstatus & SER_DCD) { + icount->dcd++; +#ifdef CONFIG_HARD_PPS + if ((info->flags & ASYNC_HARDPPS_CD) && + !(status & SER_DCD)) + hardpps(); +#endif + } + if (dstatus & SER_CTS) + icount->cts++; + wake_up_interruptible(&info->delta_msr_wait); + } + + if ((info->flags & ASYNC_CHECK_CD) && (dstatus & SER_DCD)) { +#if (defined(SERIAL_DEBUG_OPEN) || defined(SERIAL_DEBUG_INTR)) + printk("ttyS%d CD now %s...", info->line, + (!(status & SER_DCD)) ? "on" : "off"); +#endif + if (!(status & SER_DCD)) + wake_up_interruptible(&info->open_wait); + else { +#ifdef SERIAL_DEBUG_OPEN + printk("doing serial hangup..."); +#endif + if (info->tty) + tty_hangup(info->tty); + } + } + if (info->flags & ASYNC_CTS_FLOW) { + if (info->tty->hw_stopped) { + if (!(status & SER_CTS)) { +#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW)) + printk("CTS tx start..."); +#endif + info->tty->hw_stopped = 0; + info->IER |= UART_IER_THRI; + custom.intena = IF_SETCLR | IF_TBE; + mb(); + /* set a pending Tx Interrupt, transmitter should restart now */ + custom.intreq = IF_SETCLR | IF_TBE; + mb(); + rs_sched_event(info, RS_EVENT_WRITE_WAKEUP); + return; + } + } else { + if ((status & SER_CTS)) { +#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW)) + printk("CTS tx stop..."); +#endif + info->tty->hw_stopped = 1; + info->IER &= ~UART_IER_THRI; + /* disable Tx interrupt and remove any pending interrupts */ + custom.intena = IF_TBE; + mb(); + custom.intreq = IF_TBE; + mb(); + } + } + } +} + +static irqreturn_t ser_vbl_int( int irq, void *data, struct pt_regs *regs) +{ + /* vbl is just a periodic interrupt we tie into to update modem status */ + struct async_struct * info = IRQ_ports; + /* + * TBD - is it better to unregister from this interrupt or to + * ignore it if MSI is clear ? + */ + if(info->IER & UART_IER_MSI) + check_modem_status(info); + return IRQ_HANDLED; +} + +static irqreturn_t ser_rx_int(int irq, void *dev_id, struct pt_regs * regs) +{ + struct async_struct * info; + +#ifdef SERIAL_DEBUG_INTR + printk("ser_rx_int..."); +#endif + + info = IRQ_ports; + if (!info || !info->tty) + return IRQ_NONE; + + receive_chars(info); + info->last_active = jiffies; +#ifdef SERIAL_DEBUG_INTR + printk("end.\n"); +#endif + return IRQ_HANDLED; +} + +static irqreturn_t ser_tx_int(int irq, void *dev_id, struct pt_regs * regs) +{ + struct async_struct * info; + + if (custom.serdatr & SDR_TBE) { +#ifdef SERIAL_DEBUG_INTR + printk("ser_tx_int..."); +#endif + + info = IRQ_ports; + if (!info || !info->tty) + return IRQ_NONE; + + transmit_chars(info); + info->last_active = jiffies; +#ifdef SERIAL_DEBUG_INTR + printk("end.\n"); +#endif + } + return IRQ_HANDLED; +} + +/* + * ------------------------------------------------------------------- + * Here ends the serial interrupt routines. + * ------------------------------------------------------------------- + */ + +/* + * This routine is used to handle the "bottom half" processing for the + * serial driver, known also the "software interrupt" processing. + * This processing is done at the kernel interrupt level, after the + * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This + * is where time-consuming activities which can not be done in the + * interrupt driver proper are done; the interrupt driver schedules + * them using rs_sched_event(), and they get done here. + */ + +static void do_softint(unsigned long private_) +{ + struct async_struct *info = (struct async_struct *) private_; + struct tty_struct *tty; + + tty = info->tty; + if (!tty) + return; + + if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event)) { + tty_wakeup(tty); + wake_up_interruptible(&tty->write_wait); + } +} + +/* + * --------------------------------------------------------------- + * Low level utility subroutines for the serial driver: routines to + * figure out the appropriate timeout for an interrupt chain, routines + * to initialize and startup a serial port, and routines to shutdown a + * serial port. Useful stuff like that. + * --------------------------------------------------------------- + */ + +static int startup(struct async_struct * info) +{ + unsigned long flags; + int retval=0; + unsigned long page; + + page = get_zeroed_page(GFP_KERNEL); + if (!page) + return -ENOMEM; + + local_irq_save(flags); + + if (info->flags & ASYNC_INITIALIZED) { + free_page(page); + goto errout; + } + + if (info->xmit.buf) + free_page(page); + else + info->xmit.buf = (unsigned char *) page; + +#ifdef SERIAL_DEBUG_OPEN + printk("starting up ttys%d ...", info->line); +#endif + + /* Clear anything in the input buffer */ + + custom.intreq = IF_RBF; + mb(); + + retval = request_irq(IRQ_AMIGA_VERTB, ser_vbl_int, 0, "serial status", info); + if (retval) { + if (serial_isroot()) { + if (info->tty) + set_bit(TTY_IO_ERROR, + &info->tty->flags); + retval = 0; + } + goto errout; + } + + /* enable both Rx and Tx interrupts */ + custom.intena = IF_SETCLR | IF_RBF | IF_TBE; + mb(); + info->IER = UART_IER_MSI; + + /* remember current state of the DCD and CTS bits */ + current_ctl_bits = ciab.pra & (SER_DCD | SER_CTS | SER_DSR); + + IRQ_ports = info; + + info->MCR = 0; + if (info->tty->termios->c_cflag & CBAUD) + info->MCR = SER_DTR | SER_RTS; + rtsdtr_ctrl(info->MCR); + + if (info->tty) + clear_bit(TTY_IO_ERROR, &info->tty->flags); + info->xmit.head = info->xmit.tail = 0; + + /* + * Set up the tty->alt_speed kludge + */ + if (info->tty) { + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI) + info->tty->alt_speed = 57600; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI) + info->tty->alt_speed = 115200; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI) + info->tty->alt_speed = 230400; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP) + info->tty->alt_speed = 460800; + } + + /* + * and set the speed of the serial port + */ + change_speed(info, NULL); + + info->flags |= ASYNC_INITIALIZED; + local_irq_restore(flags); + return 0; + +errout: + local_irq_restore(flags); + return retval; +} + +/* + * This routine will shutdown a serial port; interrupts are disabled, and + * DTR is dropped if the hangup on close termio flag is on. + */ +static void shutdown(struct async_struct * info) +{ + unsigned long flags; + struct serial_state *state; + + if (!(info->flags & ASYNC_INITIALIZED)) + return; + + state = info->state; + +#ifdef SERIAL_DEBUG_OPEN + printk("Shutting down serial port %d ....\n", info->line); +#endif + + local_irq_save(flags); /* Disable interrupts */ + + /* + * clear delta_msr_wait queue to avoid mem leaks: we may free the irq + * here so the queue might never be waken up + */ + wake_up_interruptible(&info->delta_msr_wait); + + IRQ_ports = NULL; + + /* + * Free the IRQ, if necessary + */ + free_irq(IRQ_AMIGA_VERTB, info); + + if (info->xmit.buf) { + free_page((unsigned long) info->xmit.buf); + info->xmit.buf = NULL; + } + + info->IER = 0; + custom.intena = IF_RBF | IF_TBE; + mb(); + + /* disable break condition */ + custom.adkcon = AC_UARTBRK; + mb(); + + if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) + info->MCR &= ~(SER_DTR|SER_RTS); + rtsdtr_ctrl(info->MCR); + + if (info->tty) + set_bit(TTY_IO_ERROR, &info->tty->flags); + + info->flags &= ~ASYNC_INITIALIZED; + local_irq_restore(flags); +} + + +/* + * This routine is called to set the UART divisor registers to match + * the specified baud rate for a serial port. + */ +static void change_speed(struct async_struct *info, + struct termios *old_termios) +{ + int quot = 0, baud_base, baud; + unsigned cflag, cval = 0; + int bits; + unsigned long flags; + + if (!info->tty || !info->tty->termios) + return; + cflag = info->tty->termios->c_cflag; + + /* Byte size is always 8 bits plus parity bit if requested */ + + cval = 3; bits = 10; + if (cflag & CSTOPB) { + cval |= 0x04; + bits++; + } + if (cflag & PARENB) { + cval |= UART_LCR_PARITY; + bits++; + } + if (!(cflag & PARODD)) + cval |= UART_LCR_EPAR; +#ifdef CMSPAR + if (cflag & CMSPAR) + cval |= UART_LCR_SPAR; +#endif + + /* Determine divisor based on baud rate */ + baud = tty_get_baud_rate(info->tty); + if (!baud) + baud = 9600; /* B0 transition handled in rs_set_termios */ + baud_base = info->state->baud_base; + if (baud == 38400 && + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) + quot = info->state->custom_divisor; + else { + if (baud == 134) + /* Special case since 134 is really 134.5 */ + quot = (2*baud_base / 269); + else if (baud) + quot = baud_base / baud; + } + /* If the quotient is zero refuse the change */ + if (!quot && old_termios) { + info->tty->termios->c_cflag &= ~CBAUD; + info->tty->termios->c_cflag |= (old_termios->c_cflag & CBAUD); + baud = tty_get_baud_rate(info->tty); + if (!baud) + baud = 9600; + if (baud == 38400 && + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) + quot = info->state->custom_divisor; + else { + if (baud == 134) + /* Special case since 134 is really 134.5 */ + quot = (2*baud_base / 269); + else if (baud) + quot = baud_base / baud; + } + } + /* As a last resort, if the quotient is zero, default to 9600 bps */ + if (!quot) + quot = baud_base / 9600; + info->quot = quot; + info->timeout = ((info->xmit_fifo_size*HZ*bits*quot) / baud_base); + info->timeout += HZ/50; /* Add .02 seconds of slop */ + + /* CTS flow control flag and modem status interrupts */ + info->IER &= ~UART_IER_MSI; + if (info->flags & ASYNC_HARDPPS_CD) + info->IER |= UART_IER_MSI; + if (cflag & CRTSCTS) { + info->flags |= ASYNC_CTS_FLOW; + info->IER |= UART_IER_MSI; + } else + info->flags &= ~ASYNC_CTS_FLOW; + if (cflag & CLOCAL) + info->flags &= ~ASYNC_CHECK_CD; + else { + info->flags |= ASYNC_CHECK_CD; + info->IER |= UART_IER_MSI; + } + /* TBD: + * Does clearing IER_MSI imply that we should disbale the VBL interrupt ? + */ + + /* + * Set up parity check flag + */ +#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) + + info->read_status_mask = UART_LSR_OE | UART_LSR_DR; + if (I_INPCK(info->tty)) + info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; + if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) + info->read_status_mask |= UART_LSR_BI; + + /* + * Characters to ignore + */ + info->ignore_status_mask = 0; + if (I_IGNPAR(info->tty)) + info->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; + if (I_IGNBRK(info->tty)) { + info->ignore_status_mask |= UART_LSR_BI; + /* + * If we're ignore parity and break indicators, ignore + * overruns too. (For real raw support). + */ + if (I_IGNPAR(info->tty)) + info->ignore_status_mask |= UART_LSR_OE; + } + /* + * !!! ignore all characters if CREAD is not set + */ + if ((cflag & CREAD) == 0) + info->ignore_status_mask |= UART_LSR_DR; + local_irq_save(flags); + + { + short serper; + + /* Set up the baud rate */ + serper = quot - 1; + + /* Enable or disable parity bit */ + + if(cval & UART_LCR_PARITY) + serper |= (SERPER_PARENB); + + custom.serper = serper; + mb(); + } + + info->LCR = cval; /* Save LCR */ + local_irq_restore(flags); +} + +static void rs_put_char(struct tty_struct *tty, unsigned char ch) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (serial_paranoia_check(info, tty->name, "rs_put_char")) + return; + + if (!tty || !info->xmit.buf) + return; + + local_irq_save(flags); + if (CIRC_SPACE(info->xmit.head, + info->xmit.tail, + SERIAL_XMIT_SIZE) == 0) { + local_irq_restore(flags); + return; + } + + info->xmit.buf[info->xmit.head++] = ch; + info->xmit.head &= SERIAL_XMIT_SIZE-1; + local_irq_restore(flags); +} + +static void rs_flush_chars(struct tty_struct *tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (serial_paranoia_check(info, tty->name, "rs_flush_chars")) + return; + + if (info->xmit.head == info->xmit.tail + || tty->stopped + || tty->hw_stopped + || !info->xmit.buf) + return; + + local_irq_save(flags); + info->IER |= UART_IER_THRI; + custom.intena = IF_SETCLR | IF_TBE; + mb(); + /* set a pending Tx Interrupt, transmitter should restart now */ + custom.intreq = IF_SETCLR | IF_TBE; + mb(); + local_irq_restore(flags); +} + +static int rs_write(struct tty_struct * tty, const unsigned char *buf, int count) +{ + int c, ret = 0; + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (serial_paranoia_check(info, tty->name, "rs_write")) + return 0; + + if (!tty || !info->xmit.buf || !tmp_buf) + return 0; + + local_save_flags(flags); + local_irq_disable(); + while (1) { + c = CIRC_SPACE_TO_END(info->xmit.head, + info->xmit.tail, + SERIAL_XMIT_SIZE); + if (count < c) + c = count; + if (c <= 0) { + break; + } + memcpy(info->xmit.buf + info->xmit.head, buf, c); + info->xmit.head = ((info->xmit.head + c) & + (SERIAL_XMIT_SIZE-1)); + buf += c; + count -= c; + ret += c; + } + local_irq_restore(flags); + + if (info->xmit.head != info->xmit.tail + && !tty->stopped + && !tty->hw_stopped + && !(info->IER & UART_IER_THRI)) { + info->IER |= UART_IER_THRI; + local_irq_disable(); + custom.intena = IF_SETCLR | IF_TBE; + mb(); + /* set a pending Tx Interrupt, transmitter should restart now */ + custom.intreq = IF_SETCLR | IF_TBE; + mb(); + local_irq_restore(flags); + } + return ret; +} + +static int rs_write_room(struct tty_struct *tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + + if (serial_paranoia_check(info, tty->name, "rs_write_room")) + return 0; + return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); +} + +static int rs_chars_in_buffer(struct tty_struct *tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + + if (serial_paranoia_check(info, tty->name, "rs_chars_in_buffer")) + return 0; + return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); +} + +static void rs_flush_buffer(struct tty_struct *tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (serial_paranoia_check(info, tty->name, "rs_flush_buffer")) + return; + local_irq_save(flags); + info->xmit.head = info->xmit.tail = 0; + local_irq_restore(flags); + wake_up_interruptible(&tty->write_wait); + tty_wakeup(tty); +} + +/* + * This function is used to send a high-priority XON/XOFF character to + * the device + */ +static void rs_send_xchar(struct tty_struct *tty, char ch) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (serial_paranoia_check(info, tty->name, "rs_send_char")) + return; + + info->x_char = ch; + if (ch) { + /* Make sure transmit interrupts are on */ + + /* Check this ! */ + local_irq_save(flags); + if(!(custom.intenar & IF_TBE)) { + custom.intena = IF_SETCLR | IF_TBE; + mb(); + /* set a pending Tx Interrupt, transmitter should restart now */ + custom.intreq = IF_SETCLR | IF_TBE; + mb(); + } + local_irq_restore(flags); + + info->IER |= UART_IER_THRI; + } +} + +/* + * ------------------------------------------------------------ + * rs_throttle() + * + * This routine is called by the upper-layer tty layer to signal that + * incoming characters should be throttled. + * ------------------------------------------------------------ + */ +static void rs_throttle(struct tty_struct * tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; +#ifdef SERIAL_DEBUG_THROTTLE + char buf[64]; + + printk("throttle %s: %d....\n", tty_name(tty, buf), + tty->ldisc.chars_in_buffer(tty)); +#endif + + if (serial_paranoia_check(info, tty->name, "rs_throttle")) + return; + + if (I_IXOFF(tty)) + rs_send_xchar(tty, STOP_CHAR(tty)); + + if (tty->termios->c_cflag & CRTSCTS) + info->MCR &= ~SER_RTS; + + local_irq_save(flags); + rtsdtr_ctrl(info->MCR); + local_irq_restore(flags); +} + +static void rs_unthrottle(struct tty_struct * tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; +#ifdef SERIAL_DEBUG_THROTTLE + char buf[64]; + + printk("unthrottle %s: %d....\n", tty_name(tty, buf), + tty->ldisc.chars_in_buffer(tty)); +#endif + + if (serial_paranoia_check(info, tty->name, "rs_unthrottle")) + return; + + if (I_IXOFF(tty)) { + if (info->x_char) + info->x_char = 0; + else + rs_send_xchar(tty, START_CHAR(tty)); + } + if (tty->termios->c_cflag & CRTSCTS) + info->MCR |= SER_RTS; + local_irq_save(flags); + rtsdtr_ctrl(info->MCR); + local_irq_restore(flags); +} + +/* + * ------------------------------------------------------------ + * rs_ioctl() and friends + * ------------------------------------------------------------ + */ + +static int get_serial_info(struct async_struct * info, + struct serial_struct * retinfo) +{ + struct serial_struct tmp; + struct serial_state *state = info->state; + + if (!retinfo) + return -EFAULT; + memset(&tmp, 0, sizeof(tmp)); + tmp.type = state->type; + tmp.line = state->line; + tmp.port = state->port; + tmp.irq = state->irq; + tmp.flags = state->flags; + tmp.xmit_fifo_size = state->xmit_fifo_size; + tmp.baud_base = state->baud_base; + tmp.close_delay = state->close_delay; + tmp.closing_wait = state->closing_wait; + tmp.custom_divisor = state->custom_divisor; + if (copy_to_user(retinfo,&tmp,sizeof(*retinfo))) + return -EFAULT; + return 0; +} + +static int set_serial_info(struct async_struct * info, + struct serial_struct * new_info) +{ + struct serial_struct new_serial; + struct serial_state old_state, *state; + unsigned int change_irq,change_port; + int retval = 0; + + if (copy_from_user(&new_serial,new_info,sizeof(new_serial))) + return -EFAULT; + state = info->state; + old_state = *state; + + change_irq = new_serial.irq != state->irq; + change_port = (new_serial.port != state->port); + if(change_irq || change_port || (new_serial.xmit_fifo_size != state->xmit_fifo_size)) + return -EINVAL; + + if (!serial_isroot()) { + if ((new_serial.baud_base != state->baud_base) || + (new_serial.close_delay != state->close_delay) || + (new_serial.xmit_fifo_size != state->xmit_fifo_size) || + ((new_serial.flags & ~ASYNC_USR_MASK) != + (state->flags & ~ASYNC_USR_MASK))) + return -EPERM; + state->flags = ((state->flags & ~ASYNC_USR_MASK) | + (new_serial.flags & ASYNC_USR_MASK)); + info->flags = ((info->flags & ~ASYNC_USR_MASK) | + (new_serial.flags & ASYNC_USR_MASK)); + state->custom_divisor = new_serial.custom_divisor; + goto check_and_exit; + } + + if (new_serial.baud_base < 9600) + return -EINVAL; + + /* + * OK, past this point, all the error checking has been done. + * At this point, we start making changes..... + */ + + state->baud_base = new_serial.baud_base; + state->flags = ((state->flags & ~ASYNC_FLAGS) | + (new_serial.flags & ASYNC_FLAGS)); + info->flags = ((state->flags & ~ASYNC_INTERNAL_FLAGS) | + (info->flags & ASYNC_INTERNAL_FLAGS)); + state->custom_divisor = new_serial.custom_divisor; + state->close_delay = new_serial.close_delay * HZ/100; + state->closing_wait = new_serial.closing_wait * HZ/100; + info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; + +check_and_exit: + if (info->flags & ASYNC_INITIALIZED) { + if (((old_state.flags & ASYNC_SPD_MASK) != + (state->flags & ASYNC_SPD_MASK)) || + (old_state.custom_divisor != state->custom_divisor)) { + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI) + info->tty->alt_speed = 57600; + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI) + info->tty->alt_speed = 115200; + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI) + info->tty->alt_speed = 230400; + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP) + info->tty->alt_speed = 460800; + change_speed(info, NULL); + } + } else + retval = startup(info); + return retval; +} + + +/* + * get_lsr_info - get line status register info + * + * Purpose: Let user call ioctl() to get info when the UART physically + * is emptied. On bus types like RS485, the transmitter must + * release the bus after transmitting. This must be done when + * the transmit shift register is empty, not be done when the + * transmit holding register is empty. This functionality + * allows an RS485 driver to be written in user space. + */ +static int get_lsr_info(struct async_struct * info, unsigned int *value) +{ + unsigned char status; + unsigned int result; + unsigned long flags; + + local_irq_save(flags); + status = custom.serdatr; + mb(); + local_irq_restore(flags); + result = ((status & SDR_TSRE) ? TIOCSER_TEMT : 0); + if (copy_to_user(value, &result, sizeof(int))) + return -EFAULT; + return 0; +} + + +static int rs_tiocmget(struct tty_struct *tty, struct file *file) +{ + struct async_struct * info = (struct async_struct *)tty->driver_data; + unsigned char control, status; + unsigned long flags; + + if (serial_paranoia_check(info, tty->name, "rs_ioctl")) + return -ENODEV; + if (tty->flags & (1 << TTY_IO_ERROR)) + return -EIO; + + control = info->MCR; + local_irq_save(flags); + status = ciab.pra; + local_irq_restore(flags); + return ((control & SER_RTS) ? TIOCM_RTS : 0) + | ((control & SER_DTR) ? TIOCM_DTR : 0) + | (!(status & SER_DCD) ? TIOCM_CAR : 0) + | (!(status & SER_DSR) ? TIOCM_DSR : 0) + | (!(status & SER_CTS) ? TIOCM_CTS : 0); +} + +static int rs_tiocmset(struct tty_struct *tty, struct file *file, + unsigned int set, unsigned int clear) +{ + struct async_struct * info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (serial_paranoia_check(info, tty->name, "rs_ioctl")) + return -ENODEV; + if (tty->flags & (1 << TTY_IO_ERROR)) + return -EIO; + + local_irq_save(flags); + if (set & TIOCM_RTS) + info->MCR |= SER_RTS; + if (set & TIOCM_DTR) + info->MCR |= SER_DTR; + if (clear & TIOCM_RTS) + info->MCR &= ~SER_RTS; + if (clear & TIOCM_DTR) + info->MCR &= ~SER_DTR; + rtsdtr_ctrl(info->MCR); + local_irq_restore(flags); + return 0; +} + +/* + * rs_break() --- routine which turns the break handling on or off + */ +static void rs_break(struct tty_struct *tty, int break_state) +{ + struct async_struct * info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (serial_paranoia_check(info, tty->name, "rs_break")) + return; + + local_irq_save(flags); + if (break_state == -1) + custom.adkcon = AC_SETCLR | AC_UARTBRK; + else + custom.adkcon = AC_UARTBRK; + mb(); + local_irq_restore(flags); +} + + +static int rs_ioctl(struct tty_struct *tty, struct file * file, + unsigned int cmd, unsigned long arg) +{ + struct async_struct * info = (struct async_struct *)tty->driver_data; + struct async_icount cprev, cnow; /* kernel counter temps */ + struct serial_icounter_struct icount; + unsigned long flags; + + if (serial_paranoia_check(info, tty->name, "rs_ioctl")) + return -ENODEV; + + if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && + (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGSTRUCT) && + (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { + if (tty->flags & (1 << TTY_IO_ERROR)) + return -EIO; + } + + switch (cmd) { + case TIOCGSERIAL: + return get_serial_info(info, + (struct serial_struct *) arg); + case TIOCSSERIAL: + return set_serial_info(info, + (struct serial_struct *) arg); + case TIOCSERCONFIG: + return 0; + + case TIOCSERGETLSR: /* Get line status register */ + return get_lsr_info(info, (unsigned int *) arg); + + case TIOCSERGSTRUCT: + if (copy_to_user((struct async_struct *) arg, + info, sizeof(struct async_struct))) + return -EFAULT; + return 0; + + /* + * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change + * - mask passed in arg for lines of interest + * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) + * Caller should use TIOCGICOUNT to see which one it was + */ + case TIOCMIWAIT: + local_irq_save(flags); + /* note the counters on entry */ + cprev = info->state->icount; + local_irq_restore(flags); + while (1) { + interruptible_sleep_on(&info->delta_msr_wait); + /* see if a signal did it */ + if (signal_pending(current)) + return -ERESTARTSYS; + local_irq_save(flags); + cnow = info->state->icount; /* atomic copy */ + local_irq_restore(flags); + if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && + cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) + return -EIO; /* no change => error */ + if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) || + ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) || + ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) || + ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)) ) { + return 0; + } + cprev = cnow; + } + /* NOTREACHED */ + + /* + * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) + * Return: write counters to the user passed counter struct + * NB: both 1->0 and 0->1 transitions are counted except for + * RI where only 0->1 is counted. + */ + case TIOCGICOUNT: + local_irq_save(flags); + cnow = info->state->icount; + local_irq_restore(flags); + icount.cts = cnow.cts; + icount.dsr = cnow.dsr; + icount.rng = cnow.rng; + icount.dcd = cnow.dcd; + icount.rx = cnow.rx; + icount.tx = cnow.tx; + icount.frame = cnow.frame; + icount.overrun = cnow.overrun; + icount.parity = cnow.parity; + icount.brk = cnow.brk; + icount.buf_overrun = cnow.buf_overrun; + + if (copy_to_user((void *)arg, &icount, sizeof(icount))) + return -EFAULT; + return 0; + case TIOCSERGWILD: + case TIOCSERSWILD: + /* "setserial -W" is called in Debian boot */ + printk ("TIOCSER?WILD ioctl obsolete, ignored.\n"); + return 0; + + default: + return -ENOIOCTLCMD; + } + return 0; +} + +static void rs_set_termios(struct tty_struct *tty, struct termios *old_termios) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + unsigned int cflag = tty->termios->c_cflag; + + if ( (cflag == old_termios->c_cflag) + && ( RELEVANT_IFLAG(tty->termios->c_iflag) + == RELEVANT_IFLAG(old_termios->c_iflag))) + return; + + change_speed(info, old_termios); + + /* Handle transition to B0 status */ + if ((old_termios->c_cflag & CBAUD) && + !(cflag & CBAUD)) { + info->MCR &= ~(SER_DTR|SER_RTS); + local_irq_save(flags); + rtsdtr_ctrl(info->MCR); + local_irq_restore(flags); + } + + /* Handle transition away from B0 status */ + if (!(old_termios->c_cflag & CBAUD) && + (cflag & CBAUD)) { + info->MCR |= SER_DTR; + if (!(tty->termios->c_cflag & CRTSCTS) || + !test_bit(TTY_THROTTLED, &tty->flags)) { + info->MCR |= SER_RTS; + } + local_irq_save(flags); + rtsdtr_ctrl(info->MCR); + local_irq_restore(flags); + } + + /* Handle turning off CRTSCTS */ + if ((old_termios->c_cflag & CRTSCTS) && + !(tty->termios->c_cflag & CRTSCTS)) { + tty->hw_stopped = 0; + rs_start(tty); + } + +#if 0 + /* + * No need to wake up processes in open wait, since they + * sample the CLOCAL flag once, and don't recheck it. + * XXX It's not clear whether the current behavior is correct + * or not. Hence, this may change..... + */ + if (!(old_termios->c_cflag & CLOCAL) && + (tty->termios->c_cflag & CLOCAL)) + wake_up_interruptible(&info->open_wait); +#endif +} + +/* + * ------------------------------------------------------------ + * rs_close() + * + * This routine is called when the serial port gets closed. First, we + * wait for the last remaining data to be sent. Then, we unlink its + * async structure from the interrupt chain if necessary, and we free + * that IRQ if nothing is left in the chain. + * ------------------------------------------------------------ + */ +static void rs_close(struct tty_struct *tty, struct file * filp) +{ + struct async_struct * info = (struct async_struct *)tty->driver_data; + struct serial_state *state; + unsigned long flags; + + if (!info || serial_paranoia_check(info, tty->name, "rs_close")) + return; + + state = info->state; + + local_irq_save(flags); + + if (tty_hung_up_p(filp)) { + DBG_CNT("before DEC-hung"); + local_irq_restore(flags); + return; + } + +#ifdef SERIAL_DEBUG_OPEN + printk("rs_close ttys%d, count = %d\n", info->line, state->count); +#endif + if ((tty->count == 1) && (state->count != 1)) { + /* + * Uh, oh. tty->count is 1, which means that the tty + * structure will be freed. state->count should always + * be one in these conditions. If it's greater than + * one, we've got real problems, since it means the + * serial port won't be shutdown. + */ + printk("rs_close: bad serial port count; tty->count is 1, " + "state->count is %d\n", state->count); + state->count = 1; + } + if (--state->count < 0) { + printk("rs_close: bad serial port count for ttys%d: %d\n", + info->line, state->count); + state->count = 0; + } + if (state->count) { + DBG_CNT("before DEC-2"); + local_irq_restore(flags); + return; + } + info->flags |= ASYNC_CLOSING; + /* + * Now we wait for the transmit buffer to clear; and we notify + * the line discipline to only process XON/XOFF characters. + */ + tty->closing = 1; + if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) + tty_wait_until_sent(tty, info->closing_wait); + /* + * At this point we stop accepting input. To do this, we + * disable the receive line status interrupts, and tell the + * interrupt driver to stop checking the data ready bit in the + * line status register. + */ + info->read_status_mask &= ~UART_LSR_DR; + if (info->flags & ASYNC_INITIALIZED) { + /* disable receive interrupts */ + custom.intena = IF_RBF; + mb(); + /* clear any pending receive interrupt */ + custom.intreq = IF_RBF; + mb(); + + /* + * Before we drop DTR, make sure the UART transmitter + * has completely drained; this is especially + * important if there is a transmit FIFO! + */ + rs_wait_until_sent(tty, info->timeout); + } + shutdown(info); + if (tty->driver->flush_buffer) + tty->driver->flush_buffer(tty); + + tty_ldisc_flush(tty); + tty->closing = 0; + info->event = 0; + info->tty = NULL; + if (info->blocked_open) { + if (info->close_delay) { + msleep_interruptible(jiffies_to_msecs(info->close_delay)); + } + wake_up_interruptible(&info->open_wait); + } + info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING); + wake_up_interruptible(&info->close_wait); + local_irq_restore(flags); +} + +/* + * rs_wait_until_sent() --- wait until the transmitter is empty + */ +static void rs_wait_until_sent(struct tty_struct *tty, int timeout) +{ + struct async_struct * info = (struct async_struct *)tty->driver_data; + unsigned long orig_jiffies, char_time; + int lsr; + + if (serial_paranoia_check(info, tty->name, "rs_wait_until_sent")) + return; + + if (info->xmit_fifo_size == 0) + return; /* Just in case.... */ + + orig_jiffies = jiffies; + /* + * Set the check interval to be 1/5 of the estimated time to + * send a single character, and make it at least 1. The check + * interval should also be less than the timeout. + * + * Note: we have to use pretty tight timings here to satisfy + * the NIST-PCTS. + */ + char_time = (info->timeout - HZ/50) / info->xmit_fifo_size; + char_time = char_time / 5; + if (char_time == 0) + char_time = 1; + if (timeout) + char_time = min_t(unsigned long, char_time, timeout); + /* + * If the transmitter hasn't cleared in twice the approximate + * amount of time to send the entire FIFO, it probably won't + * ever clear. This assumes the UART isn't doing flow + * control, which is currently the case. Hence, if it ever + * takes longer than info->timeout, this is probably due to a + * UART bug of some kind. So, we clamp the timeout parameter at + * 2*info->timeout. + */ + if (!timeout || timeout > 2*info->timeout) + timeout = 2*info->timeout; +#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT + printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time); + printk("jiff=%lu...", jiffies); +#endif + while(!((lsr = custom.serdatr) & SDR_TSRE)) { +#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT + printk("serdatr = %d (jiff=%lu)...", lsr, jiffies); +#endif + msleep_interruptible(jiffies_to_msecs(char_time)); + if (signal_pending(current)) + break; + if (timeout && time_after(jiffies, orig_jiffies + timeout)) + break; + } + current->state = TASK_RUNNING; +#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT + printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies); +#endif +} + +/* + * rs_hangup() --- called by tty_hangup() when a hangup is signaled. + */ +static void rs_hangup(struct tty_struct *tty) +{ + struct async_struct * info = (struct async_struct *)tty->driver_data; + struct serial_state *state = info->state; + + if (serial_paranoia_check(info, tty->name, "rs_hangup")) + return; + + state = info->state; + + rs_flush_buffer(tty); + shutdown(info); + info->event = 0; + state->count = 0; + info->flags &= ~ASYNC_NORMAL_ACTIVE; + info->tty = NULL; + wake_up_interruptible(&info->open_wait); +} + +/* + * ------------------------------------------------------------ + * rs_open() and friends + * ------------------------------------------------------------ + */ +static int block_til_ready(struct tty_struct *tty, struct file * filp, + struct async_struct *info) +{ +#ifdef DECLARE_WAITQUEUE + DECLARE_WAITQUEUE(wait, current); +#else + struct wait_queue wait = { current, NULL }; +#endif + struct serial_state *state = info->state; + int retval; + int do_clocal = 0, extra_count = 0; + unsigned long flags; + + /* + * If the device is in the middle of being closed, then block + * until it's done, and then try again. + */ + if (tty_hung_up_p(filp) || + (info->flags & ASYNC_CLOSING)) { + if (info->flags & ASYNC_CLOSING) + interruptible_sleep_on(&info->close_wait); +#ifdef SERIAL_DO_RESTART + return ((info->flags & ASYNC_HUP_NOTIFY) ? + -EAGAIN : -ERESTARTSYS); +#else + return -EAGAIN; +#endif + } + + /* + * If non-blocking mode is set, or the port is not enabled, + * then make the check up front and then exit. + */ + if ((filp->f_flags & O_NONBLOCK) || + (tty->flags & (1 << TTY_IO_ERROR))) { + info->flags |= ASYNC_NORMAL_ACTIVE; + return 0; + } + + if (tty->termios->c_cflag & CLOCAL) + do_clocal = 1; + + /* + * Block waiting for the carrier detect and the line to become + * free (i.e., not in use by the callout). While we are in + * this loop, state->count is dropped by one, so that + * rs_close() knows when to free things. We restore it upon + * exit, either normal or abnormal. + */ + retval = 0; + add_wait_queue(&info->open_wait, &wait); +#ifdef SERIAL_DEBUG_OPEN + printk("block_til_ready before block: ttys%d, count = %d\n", + state->line, state->count); +#endif + local_irq_save(flags); + if (!tty_hung_up_p(filp)) { + extra_count = 1; + state->count--; + } + local_irq_restore(flags); + info->blocked_open++; + while (1) { + local_irq_save(flags); + if (tty->termios->c_cflag & CBAUD) + rtsdtr_ctrl(SER_DTR|SER_RTS); + local_irq_restore(flags); + set_current_state(TASK_INTERRUPTIBLE); + if (tty_hung_up_p(filp) || + !(info->flags & ASYNC_INITIALIZED)) { +#ifdef SERIAL_DO_RESTART + if (info->flags & ASYNC_HUP_NOTIFY) + retval = -EAGAIN; + else + retval = -ERESTARTSYS; +#else + retval = -EAGAIN; +#endif + break; + } + if (!(info->flags & ASYNC_CLOSING) && + (do_clocal || (!(ciab.pra & SER_DCD)) )) + break; + if (signal_pending(current)) { + retval = -ERESTARTSYS; + break; + } +#ifdef SERIAL_DEBUG_OPEN + printk("block_til_ready blocking: ttys%d, count = %d\n", + info->line, state->count); +#endif + schedule(); + } + current->state = TASK_RUNNING; + remove_wait_queue(&info->open_wait, &wait); + if (extra_count) + state->count++; + info->blocked_open--; +#ifdef SERIAL_DEBUG_OPEN + printk("block_til_ready after blocking: ttys%d, count = %d\n", + info->line, state->count); +#endif + if (retval) + return retval; + info->flags |= ASYNC_NORMAL_ACTIVE; + return 0; +} + +static int get_async_struct(int line, struct async_struct **ret_info) +{ + struct async_struct *info; + struct serial_state *sstate; + + sstate = rs_table + line; + sstate->count++; + if (sstate->info) { + *ret_info = sstate->info; + return 0; + } + info = kmalloc(sizeof(struct async_struct), GFP_KERNEL); + if (!info) { + sstate->count--; + return -ENOMEM; + } + memset(info, 0, sizeof(struct async_struct)); +#ifdef DECLARE_WAITQUEUE + init_waitqueue_head(&info->open_wait); + init_waitqueue_head(&info->close_wait); + init_waitqueue_head(&info->delta_msr_wait); +#endif + info->magic = SERIAL_MAGIC; + info->port = sstate->port; + info->flags = sstate->flags; + info->xmit_fifo_size = sstate->xmit_fifo_size; + info->line = line; + tasklet_init(&info->tlet, do_softint, (unsigned long)info); + info->state = sstate; + if (sstate->info) { + kfree(info); + *ret_info = sstate->info; + return 0; + } + *ret_info = sstate->info = info; + return 0; +} + +/* + * This routine is called whenever a serial port is opened. It + * enables interrupts for a serial port, linking in its async structure into + * the IRQ chain. It also performs the serial-specific + * initialization for the tty structure. + */ +static int rs_open(struct tty_struct *tty, struct file * filp) +{ + struct async_struct *info; + int retval, line; + unsigned long page; + + line = tty->index; + if ((line < 0) || (line >= NR_PORTS)) { + return -ENODEV; + } + retval = get_async_struct(line, &info); + if (retval) { + return retval; + } + tty->driver_data = info; + info->tty = tty; + if (serial_paranoia_check(info, tty->name, "rs_open")) + return -ENODEV; + +#ifdef SERIAL_DEBUG_OPEN + printk("rs_open %s, count = %d\n", tty->name, info->state->count); +#endif + info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; + + if (!tmp_buf) { + page = get_zeroed_page(GFP_KERNEL); + if (!page) { + return -ENOMEM; + } + if (tmp_buf) + free_page(page); + else + tmp_buf = (unsigned char *) page; + } + + /* + * If the port is the middle of closing, bail out now + */ + if (tty_hung_up_p(filp) || + (info->flags & ASYNC_CLOSING)) { + if (info->flags & ASYNC_CLOSING) + interruptible_sleep_on(&info->close_wait); +#ifdef SERIAL_DO_RESTART + return ((info->flags & ASYNC_HUP_NOTIFY) ? + -EAGAIN : -ERESTARTSYS); +#else + return -EAGAIN; +#endif + } + + /* + * Start up serial port + */ + retval = startup(info); + if (retval) { + return retval; + } + + retval = block_til_ready(tty, filp, info); + if (retval) { +#ifdef SERIAL_DEBUG_OPEN + printk("rs_open returning after block_til_ready with %d\n", + retval); +#endif + return retval; + } + +#ifdef SERIAL_DEBUG_OPEN + printk("rs_open %s successful...", tty->name); +#endif + return 0; +} + +/* + * /proc fs routines.... + */ + +static inline int line_info(char *buf, struct serial_state *state) +{ + struct async_struct *info = state->info, scr_info; + char stat_buf[30], control, status; + int ret; + unsigned long flags; + + ret = sprintf(buf, "%d: uart:amiga_builtin",state->line); + + /* + * Figure out the current RS-232 lines + */ + if (!info) { + info = &scr_info; /* This is just for serial_{in,out} */ + + info->magic = SERIAL_MAGIC; + info->flags = state->flags; + info->quot = 0; + info->tty = NULL; + } + local_irq_save(flags); + status = ciab.pra; + control = info ? info->MCR : status; + local_irq_restore(flags); + + stat_buf[0] = 0; + stat_buf[1] = 0; + if(!(control & SER_RTS)) + strcat(stat_buf, "|RTS"); + if(!(status & SER_CTS)) + strcat(stat_buf, "|CTS"); + if(!(control & SER_DTR)) + strcat(stat_buf, "|DTR"); + if(!(status & SER_DSR)) + strcat(stat_buf, "|DSR"); + if(!(status & SER_DCD)) + strcat(stat_buf, "|CD"); + + if (info->quot) { + ret += sprintf(buf+ret, " baud:%d", + state->baud_base / info->quot); + } + + ret += sprintf(buf+ret, " tx:%d rx:%d", + state->icount.tx, state->icount.rx); + + if (state->icount.frame) + ret += sprintf(buf+ret, " fe:%d", state->icount.frame); + + if (state->icount.parity) + ret += sprintf(buf+ret, " pe:%d", state->icount.parity); + + if (state->icount.brk) + ret += sprintf(buf+ret, " brk:%d", state->icount.brk); + + if (state->icount.overrun) + ret += sprintf(buf+ret, " oe:%d", state->icount.overrun); + + /* + * Last thing is the RS-232 status lines + */ + ret += sprintf(buf+ret, " %s\n", stat_buf+1); + return ret; +} + +static int rs_read_proc(char *page, char **start, off_t off, int count, + int *eof, void *data) +{ + int len = 0, l; + off_t begin = 0; + + len += sprintf(page, "serinfo:1.0 driver:%s\n", serial_version); + l = line_info(page + len, &rs_table[0]); + len += l; + if (len+begin > off+count) + goto done; + if (len+begin < off) { + begin += len; + len = 0; + } + *eof = 1; +done: + if (off >= len+begin) + return 0; + *start = page + (off-begin); + return ((count < begin+len-off) ? count : begin+len-off); +} + +/* + * --------------------------------------------------------------------- + * rs_init() and friends + * + * rs_init() is called at boot-time to initialize the serial driver. + * --------------------------------------------------------------------- + */ + +/* + * This routine prints out the appropriate serial driver version + * number, and identifies which options were configured into this + * driver. + */ +static _INLINE_ void show_serial_version(void) +{ + printk(KERN_INFO "%s version %s\n", serial_name, serial_version); +} + + +int register_serial(struct serial_struct *req); +void unregister_serial(int line); + + +static struct tty_operations serial_ops = { + .open = rs_open, + .close = rs_close, + .write = rs_write, + .put_char = rs_put_char, + .flush_chars = rs_flush_chars, + .write_room = rs_write_room, + .chars_in_buffer = rs_chars_in_buffer, + .flush_buffer = rs_flush_buffer, + .ioctl = rs_ioctl, + .throttle = rs_throttle, + .unthrottle = rs_unthrottle, + .set_termios = rs_set_termios, + .stop = rs_stop, + .start = rs_start, + .hangup = rs_hangup, + .break_ctl = rs_break, + .send_xchar = rs_send_xchar, + .wait_until_sent = rs_wait_until_sent, + .read_proc = rs_read_proc, + .tiocmget = rs_tiocmget, + .tiocmset = rs_tiocmset, +}; + +/* + * The serial driver boot-time initialization code! + */ +static int __init rs_init(void) +{ + unsigned long flags; + struct serial_state * state; + + if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(AMI_SERIAL)) + return -ENODEV; + + serial_driver = alloc_tty_driver(1); + if (!serial_driver) + return -ENOMEM; + + /* + * We request SERDAT and SERPER only, because the serial registers are + * too spreaded over the custom register space + */ + if (!request_mem_region(CUSTOM_PHYSADDR+0x30, 4, "amiserial [Paula]")) + return -EBUSY; + + IRQ_ports = NULL; + + show_serial_version(); + + /* Initialize the tty_driver structure */ + + serial_driver->owner = THIS_MODULE; + serial_driver->driver_name = "amiserial"; + serial_driver->name = "ttyS"; + serial_driver->major = TTY_MAJOR; + serial_driver->minor_start = 64; + serial_driver->type = TTY_DRIVER_TYPE_SERIAL; + serial_driver->subtype = SERIAL_TYPE_NORMAL; + serial_driver->init_termios = tty_std_termios; + serial_driver->init_termios.c_cflag = + B9600 | CS8 | CREAD | HUPCL | CLOCAL; + serial_driver->flags = TTY_DRIVER_REAL_RAW; + tty_set_operations(serial_driver, &serial_ops); + + if (tty_register_driver(serial_driver)) + panic("Couldn't register serial driver\n"); + + state = rs_table; + state->magic = SSTATE_MAGIC; + state->port = (int)&custom.serdatr; /* Just to give it a value */ + state->line = 0; + state->custom_divisor = 0; + state->close_delay = 5*HZ/10; + state->closing_wait = 30*HZ; + state->icount.cts = state->icount.dsr = + state->icount.rng = state->icount.dcd = 0; + state->icount.rx = state->icount.tx = 0; + state->icount.frame = state->icount.parity = 0; + state->icount.overrun = state->icount.brk = 0; + /* + if(state->port && check_region(state->port,REGION_LENGTH(state))) + continue; + */ + + printk(KERN_INFO "ttyS%d is the amiga builtin serial port\n", + state->line); + + /* Hardware set up */ + + state->baud_base = amiga_colorclock; + state->xmit_fifo_size = 1; + + local_irq_save(flags); + + /* set ISRs, and then disable the rx interrupts */ + request_irq(IRQ_AMIGA_TBE, ser_tx_int, 0, "serial TX", state); + request_irq(IRQ_AMIGA_RBF, ser_rx_int, SA_INTERRUPT, "serial RX", state); + + /* turn off Rx and Tx interrupts */ + custom.intena = IF_RBF | IF_TBE; + mb(); + + /* clear any pending interrupt */ + custom.intreq = IF_RBF | IF_TBE; + mb(); + + local_irq_restore(flags); + + /* + * set the appropriate directions for the modem control flags, + * and clear RTS and DTR + */ + ciab.ddra |= (SER_DTR | SER_RTS); /* outputs */ + ciab.ddra &= ~(SER_DCD | SER_CTS | SER_DSR); /* inputs */ + + return 0; +} + +static __exit void rs_exit(void) +{ + int error; + struct async_struct *info = rs_table[0].info; + + /* printk("Unloading %s: version %s\n", serial_name, serial_version); */ + tasklet_kill(&info->tlet); + if ((error = tty_unregister_driver(serial_driver))) + printk("SERIAL: failed to unregister serial driver (%d)\n", + error); + put_tty_driver(serial_driver); + + if (info) { + rs_table[0].info = NULL; + kfree(info); + } + + if (tmp_buf) { + free_page((unsigned long) tmp_buf); + tmp_buf = NULL; + } + + release_mem_region(CUSTOM_PHYSADDR+0x30, 4); +} + +module_init(rs_init) +module_exit(rs_exit) + + +/* + * ------------------------------------------------------------ + * Serial console driver + * ------------------------------------------------------------ + */ +#ifdef CONFIG_SERIAL_CONSOLE + +static void amiga_serial_putc(char c) +{ + custom.serdat = (unsigned char)c | 0x100; + while (!(custom.serdatr & 0x2000)) + barrier(); +} + +/* + * Print a string to the serial port trying not to disturb + * any possible real use of the port... + * + * The console must be locked when we get here. + */ +static void serial_console_write(struct console *co, const char *s, + unsigned count) +{ + unsigned short intena = custom.intenar; + + custom.intena = IF_TBE; + + while (count--) { + if (*s == '\n') + amiga_serial_putc('\r'); + amiga_serial_putc(*s++); + } + + custom.intena = IF_SETCLR | (intena & IF_TBE); +} + +static struct tty_driver *serial_console_device(struct console *c, int *index) +{ + *index = 0; + return serial_driver; +} + +static struct console sercons = { + .name = "ttyS", + .write = serial_console_write, + .device = serial_console_device, + .flags = CON_PRINTBUFFER, + .index = -1, +}; + +/* + * Register console. + */ +static int __init amiserial_console_init(void) +{ + register_console(&sercons); + return 0; +} +console_initcall(amiserial_console_init); +#endif + +MODULE_LICENSE("GPL"); diff --git a/drivers/char/applicom.c b/drivers/char/applicom.c new file mode 100644 index 000000000000..6bf2e27dc23a --- /dev/null +++ b/drivers/char/applicom.c @@ -0,0 +1,862 @@ +/* Derived from Applicom driver ac.c for SCO Unix */ +/* Ported by David Woodhouse, Axiom (Cambridge) Ltd. */ +/* dwmw2@infradead.org 30/8/98 */ +/* $Id: ac.c,v 1.30 2000/03/22 16:03:57 dwmw2 Exp $ */ +/* This module is for Linux 2.1 and 2.2 series kernels. */ +/*****************************************************************************/ +/* J PAGET 18/02/94 passage V2.4.2 ioctl avec code 2 reset to les interrupt */ +/* ceci pour reseter correctement apres une sortie sauvage */ +/* J PAGET 02/05/94 passage V2.4.3 dans le traitement de d'interruption, */ +/* LoopCount n'etait pas initialise a 0. */ +/* F LAFORSE 04/07/95 version V2.6.0 lecture bidon apres acces a une carte */ +/* pour liberer le bus */ +/* J.PAGET 19/11/95 version V2.6.1 Nombre, addresse,irq n'est plus configure */ +/* et passe en argument a acinit, mais est scrute sur le bus pour s'adapter */ +/* au nombre de cartes presentes sur le bus. IOCL code 6 affichait V2.4.3 */ +/* F.LAFORSE 28/11/95 creation de fichiers acXX.o avec les differentes */ +/* adresses de base des cartes, IOCTL 6 plus complet */ +/* J.PAGET le 19/08/96 copie de la version V2.6 en V2.8.0 sans modification */ +/* de code autre que le texte V2.6.1 en V2.8.0 */ +/*****************************************************************************/ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "applicom.h" + + +/* NOTE: We use for loops with {write,read}b() instead of + memcpy_{from,to}io throughout this driver. This is because + the board doesn't correctly handle word accesses - only + bytes. +*/ + + +#undef DEBUG + +#define MAX_BOARD 8 /* maximum of pc board possible */ +#define MAX_ISA_BOARD 4 +#define LEN_RAM_IO 0x800 +#define AC_MINOR 157 + +#ifndef PCI_VENDOR_ID_APPLICOM +#define PCI_VENDOR_ID_APPLICOM 0x1389 +#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001 +#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002 +#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003 +#endif +#define MAX_PCI_DEVICE_NUM 3 + +static char *applicom_pci_devnames[] = { + "PCI board", + "PCI2000IBS / PCI2000CAN", + "PCI2000PFB" +}; + +static struct pci_device_id applicom_pci_tbl[] = { + { PCI_VENDOR_ID_APPLICOM, PCI_DEVICE_ID_APPLICOM_PCIGENERIC, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, + { PCI_VENDOR_ID_APPLICOM, PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, + { PCI_VENDOR_ID_APPLICOM, PCI_DEVICE_ID_APPLICOM_PCI2000PFB, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, + { 0 } +}; +MODULE_DEVICE_TABLE(pci, applicom_pci_tbl); + +MODULE_AUTHOR("David Woodhouse & Applicom International"); +MODULE_DESCRIPTION("Driver for Applicom Profibus card"); +MODULE_LICENSE("GPL"); + +MODULE_SUPPORTED_DEVICE("ac"); + + +static struct applicom_board { + unsigned long PhysIO; + void __iomem *RamIO; + wait_queue_head_t FlagSleepSend; + long irq; + spinlock_t mutex; +} apbs[MAX_BOARD]; + +static unsigned int irq = 0; /* interrupt number IRQ */ +static unsigned long mem = 0; /* physical segment of board */ + +module_param(irq, uint, 0); +MODULE_PARM_DESC(irq, "IRQ of the Applicom board"); +module_param(mem, ulong, 0); +MODULE_PARM_DESC(mem, "Shared Memory Address of Applicom board"); + +static unsigned int numboards; /* number of installed boards */ +static volatile unsigned char Dummy; +static DECLARE_WAIT_QUEUE_HEAD(FlagSleepRec); +static unsigned int WriteErrorCount; /* number of write error */ +static unsigned int ReadErrorCount; /* number of read error */ +static unsigned int DeviceErrorCount; /* number of device error */ + +static ssize_t ac_read (struct file *, char __user *, size_t, loff_t *); +static ssize_t ac_write (struct file *, const char __user *, size_t, loff_t *); +static int ac_ioctl(struct inode *, struct file *, unsigned int, + unsigned long); +static irqreturn_t ac_interrupt(int, void *, struct pt_regs *); + +static struct file_operations ac_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .read = ac_read, + .write = ac_write, + .ioctl = ac_ioctl, +}; + +static struct miscdevice ac_miscdev = { + AC_MINOR, + "ac", + &ac_fops +}; + +static int dummy; /* dev_id for request_irq() */ + +static int ac_register_board(unsigned long physloc, void __iomem *loc, + unsigned char boardno) +{ + volatile unsigned char byte_reset_it; + + if((readb(loc + CONF_END_TEST) != 0x00) || + (readb(loc + CONF_END_TEST + 1) != 0x55) || + (readb(loc + CONF_END_TEST + 2) != 0xAA) || + (readb(loc + CONF_END_TEST + 3) != 0xFF)) + return 0; + + if (!boardno) + boardno = readb(loc + NUMCARD_OWNER_TO_PC); + + if (!boardno && boardno > MAX_BOARD) { + printk(KERN_WARNING "Board #%d (at 0x%lx) is out of range (1 <= x <= %d).\n", + boardno, physloc, MAX_BOARD); + return 0; + } + + if (apbs[boardno - 1].RamIO) { + printk(KERN_WARNING "Board #%d (at 0x%lx) conflicts with previous board #%d (at 0x%lx)\n", + boardno, physloc, boardno, apbs[boardno-1].PhysIO); + return 0; + } + + boardno--; + + apbs[boardno].PhysIO = physloc; + apbs[boardno].RamIO = loc; + init_waitqueue_head(&apbs[boardno].FlagSleepSend); + spin_lock_init(&apbs[boardno].mutex); + byte_reset_it = readb(loc + RAM_IT_TO_PC); + + numboards++; + return boardno + 1; +} + +#ifdef MODULE + +#define applicom_init init_module + +void cleanup_module(void) +{ + int i; + + misc_deregister(&ac_miscdev); + + for (i = 0; i < MAX_BOARD; i++) { + + if (!apbs[i].RamIO) + continue; + + if (apbs[i].irq) + free_irq(apbs[i].irq, &dummy); + + iounmap(apbs[i].RamIO); + } +} + +#endif /* MODULE */ + +int __init applicom_init(void) +{ + int i, numisa = 0; + struct pci_dev *dev = NULL; + void __iomem *RamIO; + int boardno; + + printk(KERN_INFO "Applicom driver: $Id: ac.c,v 1.30 2000/03/22 16:03:57 dwmw2 Exp $\n"); + + /* No mem and irq given - check for a PCI card */ + + while ( (dev = pci_get_class(PCI_CLASS_OTHERS << 16, dev))) { + + if (dev->vendor != PCI_VENDOR_ID_APPLICOM) + continue; + + if (dev->device > MAX_PCI_DEVICE_NUM || dev->device == 0) + continue; + + if (pci_enable_device(dev)) + return -EIO; + + RamIO = ioremap(dev->resource[0].start, LEN_RAM_IO); + + if (!RamIO) { + printk(KERN_INFO "ac.o: Failed to ioremap PCI memory space at 0x%lx\n", dev->resource[0].start); + pci_disable_device(dev); + return -EIO; + } + + printk(KERN_INFO "Applicom %s found at mem 0x%lx, irq %d\n", + applicom_pci_devnames[dev->device-1], dev->resource[0].start, + dev->irq); + + boardno = ac_register_board(dev->resource[0].start, RamIO,0); + if (!boardno) { + printk(KERN_INFO "ac.o: PCI Applicom device doesn't have correct signature.\n"); + iounmap(RamIO); + pci_disable_device(dev); + continue; + } + + if (request_irq(dev->irq, &ac_interrupt, SA_SHIRQ, "Applicom PCI", &dummy)) { + printk(KERN_INFO "Could not allocate IRQ %d for PCI Applicom device.\n", dev->irq); + iounmap(RamIO); + pci_disable_device(dev); + apbs[boardno - 1].RamIO = NULL; + continue; + } + + /* Enable interrupts. */ + + writeb(0x40, apbs[boardno - 1].RamIO + RAM_IT_FROM_PC); + + apbs[boardno - 1].irq = dev->irq; + } + + /* Finished with PCI cards. If none registered, + * and there was no mem/irq specified, exit */ + + if (!mem || !irq) { + if (numboards) + goto fin; + else { + printk(KERN_INFO "ac.o: No PCI boards found.\n"); + printk(KERN_INFO "ac.o: For an ISA board you must supply memory and irq parameters.\n"); + return -ENXIO; + } + } + + /* Now try the specified ISA cards */ + + for (i = 0; i < MAX_ISA_BOARD; i++) { + RamIO = ioremap(mem + (LEN_RAM_IO * i), LEN_RAM_IO); + + if (!RamIO) { + printk(KERN_INFO "ac.o: Failed to ioremap the ISA card's memory space (slot #%d)\n", i + 1); + continue; + } + + if (!(boardno = ac_register_board((unsigned long)mem+ (LEN_RAM_IO*i), + RamIO,i+1))) { + iounmap(RamIO); + continue; + } + + printk(KERN_NOTICE "Applicom ISA card found at mem 0x%lx, irq %d\n", mem + (LEN_RAM_IO*i), irq); + + if (!numisa) { + if (request_irq(irq, &ac_interrupt, SA_SHIRQ, "Applicom ISA", &dummy)) { + printk(KERN_WARNING "Could not allocate IRQ %d for ISA Applicom device.\n", irq); + iounmap(RamIO); + apbs[boardno - 1].RamIO = NULL; + } + else + apbs[boardno - 1].irq = irq; + } + else + apbs[boardno - 1].irq = 0; + + numisa++; + } + + if (!numisa) + printk(KERN_WARNING"ac.o: No valid ISA Applicom boards found at mem 0x%lx\n",mem); + + fin: + init_waitqueue_head(&FlagSleepRec); + + WriteErrorCount = 0; + ReadErrorCount = 0; + DeviceErrorCount = 0; + + if (numboards) { + misc_register(&ac_miscdev); + for (i = 0; i < MAX_BOARD; i++) { + int serial; + char boardname[(SERIAL_NUMBER - TYPE_CARD) + 1]; + + if (!apbs[i].RamIO) + continue; + + for (serial = 0; serial < SERIAL_NUMBER - TYPE_CARD; serial++) + boardname[serial] = readb(apbs[i].RamIO + TYPE_CARD + serial); + + boardname[serial] = 0; + + + printk(KERN_INFO "Applicom board %d: %s, PROM V%d.%d", + i+1, boardname, + (int)(readb(apbs[i].RamIO + VERS) >> 4), + (int)(readb(apbs[i].RamIO + VERS) & 0xF)); + + serial = (readb(apbs[i].RamIO + SERIAL_NUMBER) << 16) + + (readb(apbs[i].RamIO + SERIAL_NUMBER + 1) << 8) + + (readb(apbs[i].RamIO + SERIAL_NUMBER + 2) ); + + if (serial != 0) + printk(" S/N %d\n", serial); + else + printk("\n"); + } + return 0; + } + + else + return -ENXIO; +} + + +#ifndef MODULE +__initcall(applicom_init); +#endif + +static ssize_t ac_write(struct file *file, const char __user *buf, size_t count, loff_t * ppos) +{ + unsigned int NumCard; /* Board number 1 -> 8 */ + unsigned int IndexCard; /* Index board number 0 -> 7 */ + unsigned char TicCard; /* Board TIC to send */ + unsigned long flags; /* Current priority */ + struct st_ram_io st_loc; + struct mailbox tmpmailbox; +#ifdef DEBUG + int c; +#endif + DECLARE_WAITQUEUE(wait, current); + + if (count != sizeof(struct st_ram_io) + sizeof(struct mailbox)) { + static int warncount = 5; + if (warncount) { + printk(KERN_INFO "Hmmm. write() of Applicom card, length %zd != expected %zd\n", + count, sizeof(struct st_ram_io) + sizeof(struct mailbox)); + warncount--; + } + return -EINVAL; + } + + if(copy_from_user(&st_loc, buf, sizeof(struct st_ram_io))) + return -EFAULT; + + if(copy_from_user(&tmpmailbox, &buf[sizeof(struct st_ram_io)], + sizeof(struct mailbox))) + return -EFAULT; + + NumCard = st_loc.num_card; /* board number to send */ + TicCard = st_loc.tic_des_from_pc; /* tic number to send */ + IndexCard = NumCard - 1; + + if((NumCard < 1) || (NumCard > MAX_BOARD) || !apbs[IndexCard].RamIO) + return -EINVAL; + +#ifdef DEBUG + printk("Write to applicom card #%d. struct st_ram_io follows:", + IndexCard+1); + + for (c = 0; c < sizeof(struct st_ram_io);) { + + printk("\n%5.5X: %2.2X", c, ((unsigned char *) &st_loc)[c]); + + for (c++; c % 8 && c < sizeof(struct st_ram_io); c++) { + printk(" %2.2X", ((unsigned char *) &st_loc)[c]); + } + } + + printk("\nstruct mailbox follows:"); + + for (c = 0; c < sizeof(struct mailbox);) { + printk("\n%5.5X: %2.2X", c, ((unsigned char *) &tmpmailbox)[c]); + + for (c++; c % 8 && c < sizeof(struct mailbox); c++) { + printk(" %2.2X", ((unsigned char *) &tmpmailbox)[c]); + } + } + + printk("\n"); +#endif + + spin_lock_irqsave(&apbs[IndexCard].mutex, flags); + + /* Test octet ready correct */ + if(readb(apbs[IndexCard].RamIO + DATA_FROM_PC_READY) > 2) { + Dummy = readb(apbs[IndexCard].RamIO + VERS); + spin_unlock_irqrestore(&apbs[IndexCard].mutex, flags); + printk(KERN_WARNING "APPLICOM driver write error board %d, DataFromPcReady = %d\n", + IndexCard,(int)readb(apbs[IndexCard].RamIO + DATA_FROM_PC_READY)); + DeviceErrorCount++; + return -EIO; + } + + /* Place ourselves on the wait queue */ + set_current_state(TASK_INTERRUPTIBLE); + add_wait_queue(&apbs[IndexCard].FlagSleepSend, &wait); + + /* Check whether the card is ready for us */ + while (readb(apbs[IndexCard].RamIO + DATA_FROM_PC_READY) != 0) { + Dummy = readb(apbs[IndexCard].RamIO + VERS); + /* It's busy. Sleep. */ + + spin_unlock_irqrestore(&apbs[IndexCard].mutex, flags); + schedule(); + if (signal_pending(current)) { + remove_wait_queue(&apbs[IndexCard].FlagSleepSend, + &wait); + return -EINTR; + } + spin_lock_irqsave(&apbs[IndexCard].mutex, flags); + set_current_state(TASK_INTERRUPTIBLE); + } + + /* We may not have actually slept */ + set_current_state(TASK_RUNNING); + remove_wait_queue(&apbs[IndexCard].FlagSleepSend, &wait); + + writeb(1, apbs[IndexCard].RamIO + DATA_FROM_PC_READY); + + /* Which is best - lock down the pages with rawio and then + copy directly, or use bounce buffers? For now we do the latter + because it works with 2.2 still */ + { + unsigned char *from = (unsigned char *) &tmpmailbox; + void __iomem *to = apbs[IndexCard].RamIO + RAM_FROM_PC; + int c; + + for (c = 0; c < sizeof(struct mailbox); c++) + writeb(*(from++), to++); + } + + writeb(0x20, apbs[IndexCard].RamIO + TIC_OWNER_FROM_PC); + writeb(0xff, apbs[IndexCard].RamIO + NUMCARD_OWNER_FROM_PC); + writeb(TicCard, apbs[IndexCard].RamIO + TIC_DES_FROM_PC); + writeb(NumCard, apbs[IndexCard].RamIO + NUMCARD_DES_FROM_PC); + writeb(2, apbs[IndexCard].RamIO + DATA_FROM_PC_READY); + writeb(1, apbs[IndexCard].RamIO + RAM_IT_FROM_PC); + Dummy = readb(apbs[IndexCard].RamIO + VERS); + spin_unlock_irqrestore(&apbs[IndexCard].mutex, flags); + return 0; +} + +static int do_ac_read(int IndexCard, char __user *buf, + struct st_ram_io *st_loc, struct mailbox *mailbox) +{ + void __iomem *from = apbs[IndexCard].RamIO + RAM_TO_PC; + unsigned char *to = (unsigned char *)&mailbox; +#ifdef DEBUG + int c; +#endif + + st_loc->tic_owner_to_pc = readb(apbs[IndexCard].RamIO + TIC_OWNER_TO_PC); + st_loc->numcard_owner_to_pc = readb(apbs[IndexCard].RamIO + NUMCARD_OWNER_TO_PC); + + + { + int c; + + for (c = 0; c < sizeof(struct mailbox); c++) + *(to++) = readb(from++); + } + writeb(1, apbs[IndexCard].RamIO + ACK_FROM_PC_READY); + writeb(1, apbs[IndexCard].RamIO + TYP_ACK_FROM_PC); + writeb(IndexCard+1, apbs[IndexCard].RamIO + NUMCARD_ACK_FROM_PC); + writeb(readb(apbs[IndexCard].RamIO + TIC_OWNER_TO_PC), + apbs[IndexCard].RamIO + TIC_ACK_FROM_PC); + writeb(2, apbs[IndexCard].RamIO + ACK_FROM_PC_READY); + writeb(0, apbs[IndexCard].RamIO + DATA_TO_PC_READY); + writeb(2, apbs[IndexCard].RamIO + RAM_IT_FROM_PC); + Dummy = readb(apbs[IndexCard].RamIO + VERS); + +#ifdef DEBUG + printk("Read from applicom card #%d. struct st_ram_io follows:", NumCard); + + for (c = 0; c < sizeof(struct st_ram_io);) { + printk("\n%5.5X: %2.2X", c, ((unsigned char *)st_loc)[c]); + + for (c++; c % 8 && c < sizeof(struct st_ram_io); c++) { + printk(" %2.2X", ((unsigned char *)st_loc)[c]); + } + } + + printk("\nstruct mailbox follows:"); + + for (c = 0; c < sizeof(struct mailbox);) { + printk("\n%5.5X: %2.2X", c, ((unsigned char *)mailbox)[c]); + + for (c++; c % 8 && c < sizeof(struct mailbox); c++) { + printk(" %2.2X", ((unsigned char *)mailbox)[c]); + } + } + printk("\n"); +#endif + return (sizeof(struct st_ram_io) + sizeof(struct mailbox)); +} + +static ssize_t ac_read (struct file *filp, char __user *buf, size_t count, loff_t *ptr) +{ + unsigned long flags; + unsigned int i; + unsigned char tmp; + int ret = 0; + DECLARE_WAITQUEUE(wait, current); +#ifdef DEBUG + int loopcount=0; +#endif + /* No need to ratelimit this. Only root can trigger it anyway */ + if (count != sizeof(struct st_ram_io) + sizeof(struct mailbox)) { + printk( KERN_WARNING "Hmmm. read() of Applicom card, length %zd != expected %zd\n", + count,sizeof(struct st_ram_io) + sizeof(struct mailbox)); + return -EINVAL; + } + + while(1) { + /* Stick ourself on the wait queue */ + set_current_state(TASK_INTERRUPTIBLE); + add_wait_queue(&FlagSleepRec, &wait); + + /* Scan each board, looking for one which has a packet for us */ + for (i=0; i < MAX_BOARD; i++) { + if (!apbs[i].RamIO) + continue; + spin_lock_irqsave(&apbs[i].mutex, flags); + + tmp = readb(apbs[i].RamIO + DATA_TO_PC_READY); + + if (tmp == 2) { + struct st_ram_io st_loc; + struct mailbox mailbox; + + /* Got a packet for us */ + ret = do_ac_read(i, buf, &st_loc, &mailbox); + spin_unlock_irqrestore(&apbs[i].mutex, flags); + set_current_state(TASK_RUNNING); + remove_wait_queue(&FlagSleepRec, &wait); + + if (copy_to_user(buf, &st_loc, sizeof(st_loc))) + return -EFAULT; + if (copy_to_user(buf + sizeof(st_loc), &mailbox, sizeof(mailbox))) + return -EFAULT; + return tmp; + } + + if (tmp > 2) { + /* Got an error */ + Dummy = readb(apbs[i].RamIO + VERS); + + spin_unlock_irqrestore(&apbs[i].mutex, flags); + set_current_state(TASK_RUNNING); + remove_wait_queue(&FlagSleepRec, &wait); + + printk(KERN_WARNING "APPLICOM driver read error board %d, DataToPcReady = %d\n", + i,(int)readb(apbs[i].RamIO + DATA_TO_PC_READY)); + DeviceErrorCount++; + return -EIO; + } + + /* Nothing for us. Try the next board */ + Dummy = readb(apbs[i].RamIO + VERS); + spin_unlock_irqrestore(&apbs[i].mutex, flags); + + } /* per board */ + + /* OK - No boards had data for us. Sleep now */ + + schedule(); + remove_wait_queue(&FlagSleepRec, &wait); + + if (signal_pending(current)) + return -EINTR; + +#ifdef DEBUG + if (loopcount++ > 2) { + printk("Looping in ac_read. loopcount %d\n", loopcount); + } +#endif + } +} + +static irqreturn_t ac_interrupt(int vec, void *dev_instance, struct pt_regs *regs) +{ + unsigned int i; + unsigned int FlagInt; + unsigned int LoopCount; + int handled = 0; + + // printk("Applicom interrupt on IRQ %d occurred\n", vec); + + LoopCount = 0; + + do { + FlagInt = 0; + for (i = 0; i < MAX_BOARD; i++) { + + /* Skip if this board doesn't exist */ + if (!apbs[i].RamIO) + continue; + + spin_lock(&apbs[i].mutex); + + /* Skip if this board doesn't want attention */ + if(readb(apbs[i].RamIO + RAM_IT_TO_PC) == 0) { + spin_unlock(&apbs[i].mutex); + continue; + } + + handled = 1; + FlagInt = 1; + writeb(0, apbs[i].RamIO + RAM_IT_TO_PC); + + if (readb(apbs[i].RamIO + DATA_TO_PC_READY) > 2) { + printk(KERN_WARNING "APPLICOM driver interrupt err board %d, DataToPcReady = %d\n", + i+1,(int)readb(apbs[i].RamIO + DATA_TO_PC_READY)); + DeviceErrorCount++; + } + + if((readb(apbs[i].RamIO + DATA_FROM_PC_READY) > 2) && + (readb(apbs[i].RamIO + DATA_FROM_PC_READY) != 6)) { + + printk(KERN_WARNING "APPLICOM driver interrupt err board %d, DataFromPcReady = %d\n", + i+1,(int)readb(apbs[i].RamIO + DATA_FROM_PC_READY)); + DeviceErrorCount++; + } + + if (readb(apbs[i].RamIO + DATA_TO_PC_READY) == 2) { /* mailbox sent by the card ? */ + if (waitqueue_active(&FlagSleepRec)) { + wake_up_interruptible(&FlagSleepRec); + } + } + + if (readb(apbs[i].RamIO + DATA_FROM_PC_READY) == 0) { /* ram i/o free for write by pc ? */ + if (waitqueue_active(&apbs[i].FlagSleepSend)) { /* process sleep during read ? */ + wake_up_interruptible(&apbs[i].FlagSleepSend); + } + } + Dummy = readb(apbs[i].RamIO + VERS); + + if(readb(apbs[i].RamIO + RAM_IT_TO_PC)) { + /* There's another int waiting on this card */ + spin_unlock(&apbs[i].mutex); + i--; + } else { + spin_unlock(&apbs[i].mutex); + } + } + if (FlagInt) + LoopCount = 0; + else + LoopCount++; + } while(LoopCount < 2); + return IRQ_RETVAL(handled); +} + + + +static int ac_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) + +{ /* @ ADG ou ATO selon le cas */ + int i; + unsigned char IndexCard; + void __iomem *pmem; + int ret = 0; + volatile unsigned char byte_reset_it; + struct st_ram_io *adgl; + void __user *argp = (void __user *)arg; + + /* In general, the device is only openable by root anyway, so we're not + particularly concerned that bogus ioctls can flood the console. */ + + adgl = kmalloc(sizeof(struct st_ram_io), GFP_KERNEL); + if (!adgl) + return -ENOMEM; + + if (copy_from_user(adgl, argp, sizeof(struct st_ram_io))) { + kfree(adgl); + return -EFAULT; + } + + IndexCard = adgl->num_card-1; + + if(cmd != 0 && cmd != 6 && + ((IndexCard >= MAX_BOARD) || !apbs[IndexCard].RamIO)) { + static int warncount = 10; + if (warncount) { + printk( KERN_WARNING "APPLICOM driver IOCTL, bad board number %d\n",(int)IndexCard+1); + warncount--; + } + kfree(adgl); + return -EINVAL; + } + + switch (cmd) { + + case 0: + pmem = apbs[IndexCard].RamIO; + for (i = 0; i < sizeof(struct st_ram_io); i++) + ((unsigned char *)adgl)[i]=readb(pmem++); + if (copy_to_user(argp, adgl, sizeof(struct st_ram_io))) + ret = -EFAULT; + break; + case 1: + pmem = apbs[IndexCard].RamIO + CONF_END_TEST; + for (i = 0; i < 4; i++) + adgl->conf_end_test[i] = readb(pmem++); + for (i = 0; i < 2; i++) + adgl->error_code[i] = readb(pmem++); + for (i = 0; i < 4; i++) + adgl->parameter_error[i] = readb(pmem++); + pmem = apbs[IndexCard].RamIO + VERS; + adgl->vers = readb(pmem); + pmem = apbs[IndexCard].RamIO + TYPE_CARD; + for (i = 0; i < 20; i++) + adgl->reserv1[i] = readb(pmem++); + *(int *)&adgl->reserv1[20] = + (readb(apbs[IndexCard].RamIO + SERIAL_NUMBER) << 16) + + (readb(apbs[IndexCard].RamIO + SERIAL_NUMBER + 1) << 8) + + (readb(apbs[IndexCard].RamIO + SERIAL_NUMBER + 2) ); + + if (copy_to_user(argp, adgl, sizeof(struct st_ram_io))) + ret = -EFAULT; + break; + case 2: + pmem = apbs[IndexCard].RamIO + CONF_END_TEST; + for (i = 0; i < 10; i++) + writeb(0xff, pmem++); + writeb(adgl->data_from_pc_ready, + apbs[IndexCard].RamIO + DATA_FROM_PC_READY); + + writeb(1, apbs[IndexCard].RamIO + RAM_IT_FROM_PC); + + for (i = 0; i < MAX_BOARD; i++) { + if (apbs[i].RamIO) { + byte_reset_it = readb(apbs[i].RamIO + RAM_IT_TO_PC); + } + } + break; + case 3: + pmem = apbs[IndexCard].RamIO + TIC_DES_FROM_PC; + writeb(adgl->tic_des_from_pc, pmem); + break; + case 4: + pmem = apbs[IndexCard].RamIO + TIC_OWNER_TO_PC; + adgl->tic_owner_to_pc = readb(pmem++); + adgl->numcard_owner_to_pc = readb(pmem); + if (copy_to_user(argp, adgl,sizeof(struct st_ram_io))) + ret = -EFAULT; + break; + case 5: + writeb(adgl->num_card, apbs[IndexCard].RamIO + NUMCARD_OWNER_TO_PC); + writeb(adgl->num_card, apbs[IndexCard].RamIO + NUMCARD_DES_FROM_PC); + writeb(adgl->num_card, apbs[IndexCard].RamIO + NUMCARD_ACK_FROM_PC); + writeb(4, apbs[IndexCard].RamIO + DATA_FROM_PC_READY); + writeb(1, apbs[IndexCard].RamIO + RAM_IT_FROM_PC); + break; + case 6: + printk(KERN_INFO "APPLICOM driver release .... V2.8.0 ($Revision: 1.30 $)\n"); + printk(KERN_INFO "Number of installed boards . %d\n", (int) numboards); + printk(KERN_INFO "Segment of board ........... %X\n", (int) mem); + printk(KERN_INFO "Interrupt IRQ number ....... %d\n", (int) irq); + for (i = 0; i < MAX_BOARD; i++) { + int serial; + char boardname[(SERIAL_NUMBER - TYPE_CARD) + 1]; + + if (!apbs[i].RamIO) + continue; + + for (serial = 0; serial < SERIAL_NUMBER - TYPE_CARD; serial++) + boardname[serial] = readb(apbs[i].RamIO + TYPE_CARD + serial); + boardname[serial] = 0; + + printk(KERN_INFO "Prom version board %d ....... V%d.%d %s", + i+1, + (int)(readb(apbs[IndexCard].RamIO + VERS) >> 4), + (int)(readb(apbs[IndexCard].RamIO + VERS) & 0xF), + boardname); + + + serial = (readb(apbs[i].RamIO + SERIAL_NUMBER) << 16) + + (readb(apbs[i].RamIO + SERIAL_NUMBER + 1) << 8) + + (readb(apbs[i].RamIO + SERIAL_NUMBER + 2) ); + + if (serial != 0) + printk(" S/N %d\n", serial); + else + printk("\n"); + } + if (DeviceErrorCount != 0) + printk(KERN_INFO "DeviceErrorCount ........... %d\n", DeviceErrorCount); + if (ReadErrorCount != 0) + printk(KERN_INFO "ReadErrorCount ............. %d\n", ReadErrorCount); + if (WriteErrorCount != 0) + printk(KERN_INFO "WriteErrorCount ............ %d\n", WriteErrorCount); + if (waitqueue_active(&FlagSleepRec)) + printk(KERN_INFO "Process in read pending\n"); + for (i = 0; i < MAX_BOARD; i++) { + if (apbs[i].RamIO && waitqueue_active(&apbs[i].FlagSleepSend)) + printk(KERN_INFO "Process in write pending board %d\n",i+1); + } + break; + default: + printk(KERN_INFO "APPLICOM driver ioctl, unknown function code %d\n",cmd) ; + ret = -EINVAL; + break; + } + Dummy = readb(apbs[IndexCard].RamIO + VERS); + kfree(adgl); + return 0; +} + +#ifndef MODULE +static int __init applicom_setup(char *str) +{ + int ints[4]; + + (void) get_options(str, 4, ints); + + if (ints[0] > 2) { + printk(KERN_WARNING "Too many arguments to 'applicom=', expected mem,irq only.\n"); + } + + if (ints[0] < 2) { + printk(KERN_INFO"applicom numargs: %d\n", ints[0]); + return 0; + } + + mem = ints[1]; + irq = ints[2]; + return 1; +} + +__setup("applicom=", applicom_setup); + +#endif /* MODULE */ + diff --git a/drivers/char/applicom.h b/drivers/char/applicom.h new file mode 100644 index 000000000000..35530b3d9bd6 --- /dev/null +++ b/drivers/char/applicom.h @@ -0,0 +1,85 @@ +/* $Id: applicom.h,v 1.2 1999/08/28 15:09:49 dwmw2 Exp $ */ + + +#ifndef __LINUX_APPLICOM_H__ +#define __LINUX_APPLICOM_H__ + + +#define DATA_TO_PC_READY 0x00 +#define TIC_OWNER_TO_PC 0x01 +#define NUMCARD_OWNER_TO_PC 0x02 +#define TIC_DES_TO_PC 0x03 +#define NUMCARD_DES_TO_PC 0x04 +#define DATA_FROM_PC_READY 0x05 +#define TIC_OWNER_FROM_PC 0x06 +#define NUMCARD_OWNER_FROM_PC 0x07 +#define TIC_DES_FROM_PC 0x08 +#define NUMCARD_DES_FROM_PC 0x09 +#define ACK_FROM_PC_READY 0x0E +#define TIC_ACK_FROM_PC 0x0F +#define NUMCARD_ACK_FROM_PC 0x010 +#define TYP_ACK_FROM_PC 0x011 +#define CONF_END_TEST 0x012 +#define ERROR_CODE 0x016 +#define PARAMETER_ERROR 0x018 +#define VERS 0x01E +#define RAM_TO_PC 0x040 +#define RAM_FROM_PC 0x0170 +#define TYPE_CARD 0x03C0 +#define SERIAL_NUMBER 0x03DA +#define RAM_IT_FROM_PC 0x03FE +#define RAM_IT_TO_PC 0x03FF + +struct mailbox{ + u16 stjb_codef; /* offset 00 */ + s16 stjb_status; /* offset 02 */ + u16 stjb_ticuser_root; /* offset 04 */ + u8 stjb_piduser[4]; /* offset 06 */ + u16 stjb_mode; /* offset 0A */ + u16 stjb_time; /* offset 0C */ + u16 stjb_stop; /* offset 0E */ + u16 stjb_nfonc; /* offset 10 */ + u16 stjb_ncard; /* offset 12 */ + u16 stjb_nchan; /* offset 14 */ + u16 stjb_nes; /* offset 16 */ + u16 stjb_nb; /* offset 18 */ + u16 stjb_typvar; /* offset 1A */ + u32 stjb_adr; /* offset 1C */ + u16 stjb_ticuser_dispcyc; /* offset 20 */ + u16 stjb_ticuser_protocol; /* offset 22 */ + u8 stjb_filler[12]; /* offset 24 */ + u8 stjb_data[256]; /* offset 30 */ + }; + +struct st_ram_io +{ + unsigned char data_to_pc_ready; + unsigned char tic_owner_to_pc; + unsigned char numcard_owner_to_pc; + unsigned char tic_des_to_pc; + unsigned char numcard_des_to_pc; + unsigned char data_from_pc_ready; + unsigned char tic_owner_from_pc; + unsigned char numcard_owner_from_pc; + unsigned char tic_des_from_pc; + unsigned char numcard_des_from_pc; + unsigned char ack_to_pc_ready; + unsigned char tic_ack_to_pc; + unsigned char numcard_ack_to_pc; + unsigned char typ_ack_to_pc; + unsigned char ack_from_pc_ready; + unsigned char tic_ack_from_pc; + unsigned char numcard_ack_from_pc; + unsigned char typ_ack_from_pc; + unsigned char conf_end_test[4]; + unsigned char error_code[2]; + unsigned char parameter_error[4]; + unsigned char time_base; + unsigned char nul_inc; + unsigned char vers; + unsigned char num_card; + unsigned char reserv1[32]; +}; + + +#endif /* __LINUX_APPLICOM_H__ */ diff --git a/drivers/char/cd1865.h b/drivers/char/cd1865.h new file mode 100644 index 000000000000..9940966e7a1d --- /dev/null +++ b/drivers/char/cd1865.h @@ -0,0 +1,263 @@ +/* + * linux/drivers/char/cd1865.h -- Definitions relating to the CD1865 + * for the Specialix IO8+ multiport serial driver. + * + * Copyright (C) 1997 Roger Wolff (R.E.Wolff@BitWizard.nl) + * Copyright (C) 1994-1996 Dmitry Gorodchanin (pgmdsg@ibi.com) + * + * Specialix pays for the development and support of this driver. + * Please DO contact io8-linux@specialix.co.uk if you require + * support. + * + * This driver was developped in the BitWizard linux device + * driver service. If you require a linux device driver for your + * product, please contact devices@BitWizard.nl for a quote. + * + */ + +/* + * Definitions for Driving CD180/CD1864/CD1865 based eightport serial cards. + */ + + +/* Values of choice for Interrupt ACKs */ +/* These values are "obligatory" if you use the register based + * interrupt acknowledgements. See page 99-101 of V2.0 of the CD1865 + * databook */ +#define SX_ACK_MINT 0x75 /* goes to PILR1 */ +#define SX_ACK_TINT 0x76 /* goes to PILR2 */ +#define SX_ACK_RINT 0x77 /* goes to PILR3 */ + +/* Chip ID (is used when chips ar daisy chained.) */ +#define SX_ID 0x10 + +/* Definitions for Cirrus Logic CL-CD186x 8-port async mux chip */ + +#define CD186x_NCH 8 /* Total number of channels */ +#define CD186x_TPC 16 /* Ticks per character */ +#define CD186x_NFIFO 8 /* TX FIFO size */ + + +/* Global registers */ + +#define CD186x_GIVR 0x40 /* Global Interrupt Vector Register */ +#define CD186x_GICR 0x41 /* Global Interrupting Channel Register */ +#define CD186x_PILR1 0x61 /* Priority Interrupt Level Register 1 */ +#define CD186x_PILR2 0x62 /* Priority Interrupt Level Register 2 */ +#define CD186x_PILR3 0x63 /* Priority Interrupt Level Register 3 */ +#define CD186x_CAR 0x64 /* Channel Access Register */ +#define CD186x_SRSR 0x65 /* Channel Access Register */ +#define CD186x_GFRCR 0x6b /* Global Firmware Revision Code Register */ +#define CD186x_PPRH 0x70 /* Prescaler Period Register High */ +#define CD186x_PPRL 0x71 /* Prescaler Period Register Low */ +#define CD186x_RDR 0x78 /* Receiver Data Register */ +#define CD186x_RCSR 0x7a /* Receiver Character Status Register */ +#define CD186x_TDR 0x7b /* Transmit Data Register */ +#define CD186x_EOIR 0x7f /* End of Interrupt Register */ +#define CD186x_MRAR 0x75 /* Modem Request Acknowledge register */ +#define CD186x_TRAR 0x76 /* Transmit Request Acknowledge register */ +#define CD186x_RRAR 0x77 /* Receive Request Acknowledge register */ +#define CD186x_SRCR 0x66 /* Service Request Configuration register */ + +/* Channel Registers */ + +#define CD186x_CCR 0x01 /* Channel Command Register */ +#define CD186x_IER 0x02 /* Interrupt Enable Register */ +#define CD186x_COR1 0x03 /* Channel Option Register 1 */ +#define CD186x_COR2 0x04 /* Channel Option Register 2 */ +#define CD186x_COR3 0x05 /* Channel Option Register 3 */ +#define CD186x_CCSR 0x06 /* Channel Control Status Register */ +#define CD186x_RDCR 0x07 /* Receive Data Count Register */ +#define CD186x_SCHR1 0x09 /* Special Character Register 1 */ +#define CD186x_SCHR2 0x0a /* Special Character Register 2 */ +#define CD186x_SCHR3 0x0b /* Special Character Register 3 */ +#define CD186x_SCHR4 0x0c /* Special Character Register 4 */ +#define CD186x_MCOR1 0x10 /* Modem Change Option 1 Register */ +#define CD186x_MCOR2 0x11 /* Modem Change Option 2 Register */ +#define CD186x_MCR 0x12 /* Modem Change Register */ +#define CD186x_RTPR 0x18 /* Receive Timeout Period Register */ +#define CD186x_MSVR 0x28 /* Modem Signal Value Register */ +#define CD186x_MSVRTS 0x29 /* Modem Signal Value Register */ +#define CD186x_MSVDTR 0x2a /* Modem Signal Value Register */ +#define CD186x_RBPRH 0x31 /* Receive Baud Rate Period Register High */ +#define CD186x_RBPRL 0x32 /* Receive Baud Rate Period Register Low */ +#define CD186x_TBPRH 0x39 /* Transmit Baud Rate Period Register High */ +#define CD186x_TBPRL 0x3a /* Transmit Baud Rate Period Register Low */ + + +/* Global Interrupt Vector Register (R/W) */ + +#define GIVR_ITMASK 0x07 /* Interrupt type mask */ +#define GIVR_IT_MODEM 0x01 /* Modem Signal Change Interrupt */ +#define GIVR_IT_TX 0x02 /* Transmit Data Interrupt */ +#define GIVR_IT_RCV 0x03 /* Receive Good Data Interrupt */ +#define GIVR_IT_REXC 0x07 /* Receive Exception Interrupt */ + + +/* Global Interrupt Channel Register (R/W) */ + +#define GICR_CHAN 0x1c /* Channel Number Mask */ +#define GICR_CHAN_OFF 2 /* Channel Number shift */ + + +/* Channel Address Register (R/W) */ + +#define CAR_CHAN 0x07 /* Channel Number Mask */ +#define CAR_A7 0x08 /* A7 Address Extension (unused) */ + + +/* Receive Character Status Register (R/O) */ + +#define RCSR_TOUT 0x80 /* Rx Timeout */ +#define RCSR_SCDET 0x70 /* Special Character Detected Mask */ +#define RCSR_NO_SC 0x00 /* No Special Characters Detected */ +#define RCSR_SC_1 0x10 /* Special Char 1 (or 1 & 3) Detected */ +#define RCSR_SC_2 0x20 /* Special Char 2 (or 2 & 4) Detected */ +#define RCSR_SC_3 0x30 /* Special Char 3 Detected */ +#define RCSR_SC_4 0x40 /* Special Char 4 Detected */ +#define RCSR_BREAK 0x08 /* Break has been detected */ +#define RCSR_PE 0x04 /* Parity Error */ +#define RCSR_FE 0x02 /* Frame Error */ +#define RCSR_OE 0x01 /* Overrun Error */ + + +/* Channel Command Register (R/W) (commands in groups can be OR-ed) */ + +#define CCR_HARDRESET 0x81 /* Reset the chip */ + +#define CCR_SOFTRESET 0x80 /* Soft Channel Reset */ + +#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */ +#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */ +#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */ + +#define CCR_SSCH1 0x21 /* Send Special Character 1 */ + +#define CCR_SSCH2 0x22 /* Send Special Character 2 */ + +#define CCR_SSCH3 0x23 /* Send Special Character 3 */ + +#define CCR_SSCH4 0x24 /* Send Special Character 4 */ + +#define CCR_TXEN 0x18 /* Enable Transmitter */ +#define CCR_RXEN 0x12 /* Enable Receiver */ + +#define CCR_TXDIS 0x14 /* Disable Transmitter */ +#define CCR_RXDIS 0x11 /* Disable Receiver */ + + +/* Interrupt Enable Register (R/W) */ + +#define IER_DSR 0x80 /* Enable interrupt on DSR change */ +#define IER_CD 0x40 /* Enable interrupt on CD change */ +#define IER_CTS 0x20 /* Enable interrupt on CTS change */ +#define IER_RXD 0x10 /* Enable interrupt on Receive Data */ +#define IER_RXSC 0x08 /* Enable interrupt on Receive Spec. Char */ +#define IER_TXRDY 0x04 /* Enable interrupt on TX FIFO empty */ +#define IER_TXEMPTY 0x02 /* Enable interrupt on TX completely empty */ +#define IER_RET 0x01 /* Enable interrupt on RX Exc. Timeout */ + + +/* Channel Option Register 1 (R/W) */ + +#define COR1_ODDP 0x80 /* Odd Parity */ +#define COR1_PARMODE 0x60 /* Parity Mode mask */ +#define COR1_NOPAR 0x00 /* No Parity */ +#define COR1_FORCEPAR 0x20 /* Force Parity */ +#define COR1_NORMPAR 0x40 /* Normal Parity */ +#define COR1_IGNORE 0x10 /* Ignore Parity on RX */ +#define COR1_STOPBITS 0x0c /* Number of Stop Bits */ +#define COR1_1SB 0x00 /* 1 Stop Bit */ +#define COR1_15SB 0x04 /* 1.5 Stop Bits */ +#define COR1_2SB 0x08 /* 2 Stop Bits */ +#define COR1_CHARLEN 0x03 /* Character Length */ +#define COR1_5BITS 0x00 /* 5 bits */ +#define COR1_6BITS 0x01 /* 6 bits */ +#define COR1_7BITS 0x02 /* 7 bits */ +#define COR1_8BITS 0x03 /* 8 bits */ + + +/* Channel Option Register 2 (R/W) */ + +#define COR2_IXM 0x80 /* Implied XON mode */ +#define COR2_TXIBE 0x40 /* Enable In-Band (XON/XOFF) Flow Control */ +#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */ +#define COR2_LLM 0x10 /* Local Loopback Mode */ +#define COR2_RLM 0x08 /* Remote Loopback Mode */ +#define COR2_RTSAO 0x04 /* RTS Automatic Output Enable */ +#define COR2_CTSAE 0x02 /* CTS Automatic Enable */ +#define COR2_DSRAE 0x01 /* DSR Automatic Enable */ + + +/* Channel Option Register 3 (R/W) */ + +#define COR3_XONCH 0x80 /* XON is a pair of characters (1 & 3) */ +#define COR3_XOFFCH 0x40 /* XOFF is a pair of characters (2 & 4) */ +#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */ +#define COR3_SCDE 0x10 /* Special Character Detection Enable */ +#define COR3_RXTH 0x0f /* RX FIFO Threshold value (1-8) */ + + +/* Channel Control Status Register (R/O) */ + +#define CCSR_RXEN 0x80 /* Receiver Enabled */ +#define CCSR_RXFLOFF 0x40 /* Receive Flow Off (XOFF was sent) */ +#define CCSR_RXFLON 0x20 /* Receive Flow On (XON was sent) */ +#define CCSR_TXEN 0x08 /* Transmitter Enabled */ +#define CCSR_TXFLOFF 0x04 /* Transmit Flow Off (got XOFF) */ +#define CCSR_TXFLON 0x02 /* Transmit Flow On (got XON) */ + + +/* Modem Change Option Register 1 (R/W) */ + +#define MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR */ +#define MCOR1_CDZD 0x40 /* Detect 0->1 transition of CD */ +#define MCOR1_CTSZD 0x20 /* Detect 0->1 transition of CTS */ +#define MCOR1_DTRTH 0x0f /* Auto DTR flow control Threshold (1-8) */ +#define MCOR1_NODTRFC 0x0 /* Automatic DTR flow control disabled */ + + +/* Modem Change Option Register 2 (R/W) */ + +#define MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR */ +#define MCOR2_CDOD 0x40 /* Detect 1->0 transition of CD */ +#define MCOR2_CTSOD 0x20 /* Detect 1->0 transition of CTS */ + +/* Modem Change Register (R/W) */ + +#define MCR_DSRCHG 0x80 /* DSR Changed */ +#define MCR_CDCHG 0x40 /* CD Changed */ +#define MCR_CTSCHG 0x20 /* CTS Changed */ + + +/* Modem Signal Value Register (R/W) */ + +#define MSVR_DSR 0x80 /* Current state of DSR input */ +#define MSVR_CD 0x40 /* Current state of CD input */ +#define MSVR_CTS 0x20 /* Current state of CTS input */ +#define MSVR_DTR 0x02 /* Current state of DTR output */ +#define MSVR_RTS 0x01 /* Current state of RTS output */ + + +/* Escape characters */ + +#define CD186x_C_ESC 0x00 /* Escape character */ +#define CD186x_C_SBRK 0x81 /* Start sending BREAK */ +#define CD186x_C_DELAY 0x82 /* Delay output */ +#define CD186x_C_EBRK 0x83 /* Stop sending BREAK */ + +#define SRSR_RREQint 0x10 /* This chip wants "rec" serviced */ +#define SRSR_TREQint 0x04 /* This chip wants "transmit" serviced */ +#define SRSR_MREQint 0x01 /* This chip wants "mdm change" serviced */ + + + +#define SRCR_PKGTYPE 0x80 +#define SRCR_REGACKEN 0x40 +#define SRCR_DAISYEN 0x20 +#define SRCR_GLOBPRI 0x10 +#define SRCR_UNFAIR 0x08 +#define SRCR_AUTOPRI 0x02 +#define SRCR_PRISEL 0x01 + + diff --git a/drivers/char/consolemap.c b/drivers/char/consolemap.c new file mode 100644 index 000000000000..406dea914635 --- /dev/null +++ b/drivers/char/consolemap.c @@ -0,0 +1,672 @@ +/* + * consolemap.c + * + * Mapping from internal code (such as Latin-1 or Unicode or IBM PC code) + * to font positions. + * + * aeb, 950210 + * + * Support for multiple unimaps by Jakub Jelinek , July 1998 + * + * Fix bug in inverse translation. Stanislav Voronyi , Dec 1998 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned short translations[][256] = { + /* 8-bit Latin-1 mapped to Unicode -- trivial mapping */ + { + 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, + 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f, + 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017, + 0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f, + 0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027, + 0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f, + 0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037, + 0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f, + 0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047, + 0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f, + 0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057, + 0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f, + 0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067, + 0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f, + 0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077, + 0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f, + 0x0080, 0x0081, 0x0082, 0x0083, 0x0084, 0x0085, 0x0086, 0x0087, + 0x0088, 0x0089, 0x008a, 0x008b, 0x008c, 0x008d, 0x008e, 0x008f, + 0x0090, 0x0091, 0x0092, 0x0093, 0x0094, 0x0095, 0x0096, 0x0097, + 0x0098, 0x0099, 0x009a, 0x009b, 0x009c, 0x009d, 0x009e, 0x009f, + 0x00a0, 0x00a1, 0x00a2, 0x00a3, 0x00a4, 0x00a5, 0x00a6, 0x00a7, + 0x00a8, 0x00a9, 0x00aa, 0x00ab, 0x00ac, 0x00ad, 0x00ae, 0x00af, + 0x00b0, 0x00b1, 0x00b2, 0x00b3, 0x00b4, 0x00b5, 0x00b6, 0x00b7, + 0x00b8, 0x00b9, 0x00ba, 0x00bb, 0x00bc, 0x00bd, 0x00be, 0x00bf, + 0x00c0, 0x00c1, 0x00c2, 0x00c3, 0x00c4, 0x00c5, 0x00c6, 0x00c7, + 0x00c8, 0x00c9, 0x00ca, 0x00cb, 0x00cc, 0x00cd, 0x00ce, 0x00cf, + 0x00d0, 0x00d1, 0x00d2, 0x00d3, 0x00d4, 0x00d5, 0x00d6, 0x00d7, + 0x00d8, 0x00d9, 0x00da, 0x00db, 0x00dc, 0x00dd, 0x00de, 0x00df, + 0x00e0, 0x00e1, 0x00e2, 0x00e3, 0x00e4, 0x00e5, 0x00e6, 0x00e7, + 0x00e8, 0x00e9, 0x00ea, 0x00eb, 0x00ec, 0x00ed, 0x00ee, 0x00ef, + 0x00f0, 0x00f1, 0x00f2, 0x00f3, 0x00f4, 0x00f5, 0x00f6, 0x00f7, + 0x00f8, 0x00f9, 0x00fa, 0x00fb, 0x00fc, 0x00fd, 0x00fe, 0x00ff + }, + /* VT100 graphics mapped to Unicode */ + { + 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, + 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f, + 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017, + 0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f, + 0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027, + 0x0028, 0x0029, 0x002a, 0x2192, 0x2190, 0x2191, 0x2193, 0x002f, + 0x2588, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037, + 0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f, + 0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047, + 0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f, + 0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057, + 0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x00a0, + 0x25c6, 0x2592, 0x2409, 0x240c, 0x240d, 0x240a, 0x00b0, 0x00b1, + 0x2591, 0x240b, 0x2518, 0x2510, 0x250c, 0x2514, 0x253c, 0x23ba, + 0x23bb, 0x2500, 0x23bc, 0x23bd, 0x251c, 0x2524, 0x2534, 0x252c, + 0x2502, 0x2264, 0x2265, 0x03c0, 0x2260, 0x00a3, 0x00b7, 0x007f, + 0x0080, 0x0081, 0x0082, 0x0083, 0x0084, 0x0085, 0x0086, 0x0087, + 0x0088, 0x0089, 0x008a, 0x008b, 0x008c, 0x008d, 0x008e, 0x008f, + 0x0090, 0x0091, 0x0092, 0x0093, 0x0094, 0x0095, 0x0096, 0x0097, + 0x0098, 0x0099, 0x009a, 0x009b, 0x009c, 0x009d, 0x009e, 0x009f, + 0x00a0, 0x00a1, 0x00a2, 0x00a3, 0x00a4, 0x00a5, 0x00a6, 0x00a7, + 0x00a8, 0x00a9, 0x00aa, 0x00ab, 0x00ac, 0x00ad, 0x00ae, 0x00af, + 0x00b0, 0x00b1, 0x00b2, 0x00b3, 0x00b4, 0x00b5, 0x00b6, 0x00b7, + 0x00b8, 0x00b9, 0x00ba, 0x00bb, 0x00bc, 0x00bd, 0x00be, 0x00bf, + 0x00c0, 0x00c1, 0x00c2, 0x00c3, 0x00c4, 0x00c5, 0x00c6, 0x00c7, + 0x00c8, 0x00c9, 0x00ca, 0x00cb, 0x00cc, 0x00cd, 0x00ce, 0x00cf, + 0x00d0, 0x00d1, 0x00d2, 0x00d3, 0x00d4, 0x00d5, 0x00d6, 0x00d7, + 0x00d8, 0x00d9, 0x00da, 0x00db, 0x00dc, 0x00dd, 0x00de, 0x00df, + 0x00e0, 0x00e1, 0x00e2, 0x00e3, 0x00e4, 0x00e5, 0x00e6, 0x00e7, + 0x00e8, 0x00e9, 0x00ea, 0x00eb, 0x00ec, 0x00ed, 0x00ee, 0x00ef, + 0x00f0, 0x00f1, 0x00f2, 0x00f3, 0x00f4, 0x00f5, 0x00f6, 0x00f7, + 0x00f8, 0x00f9, 0x00fa, 0x00fb, 0x00fc, 0x00fd, 0x00fe, 0x00ff + }, + /* IBM Codepage 437 mapped to Unicode */ + { + 0x0000, 0x263a, 0x263b, 0x2665, 0x2666, 0x2663, 0x2660, 0x2022, + 0x25d8, 0x25cb, 0x25d9, 0x2642, 0x2640, 0x266a, 0x266b, 0x263c, + 0x25b6, 0x25c0, 0x2195, 0x203c, 0x00b6, 0x00a7, 0x25ac, 0x21a8, + 0x2191, 0x2193, 0x2192, 0x2190, 0x221f, 0x2194, 0x25b2, 0x25bc, + 0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027, + 0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f, + 0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037, + 0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f, + 0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047, + 0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f, + 0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057, + 0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f, + 0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067, + 0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f, + 0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077, + 0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x2302, + 0x00c7, 0x00fc, 0x00e9, 0x00e2, 0x00e4, 0x00e0, 0x00e5, 0x00e7, + 0x00ea, 0x00eb, 0x00e8, 0x00ef, 0x00ee, 0x00ec, 0x00c4, 0x00c5, + 0x00c9, 0x00e6, 0x00c6, 0x00f4, 0x00f6, 0x00f2, 0x00fb, 0x00f9, + 0x00ff, 0x00d6, 0x00dc, 0x00a2, 0x00a3, 0x00a5, 0x20a7, 0x0192, + 0x00e1, 0x00ed, 0x00f3, 0x00fa, 0x00f1, 0x00d1, 0x00aa, 0x00ba, + 0x00bf, 0x2310, 0x00ac, 0x00bd, 0x00bc, 0x00a1, 0x00ab, 0x00bb, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255d, 0x255c, 0x255b, 0x2510, + 0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x255e, 0x255f, + 0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256b, + 0x256a, 0x2518, 0x250c, 0x2588, 0x2584, 0x258c, 0x2590, 0x2580, + 0x03b1, 0x00df, 0x0393, 0x03c0, 0x03a3, 0x03c3, 0x00b5, 0x03c4, + 0x03a6, 0x0398, 0x03a9, 0x03b4, 0x221e, 0x03c6, 0x03b5, 0x2229, + 0x2261, 0x00b1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00f7, 0x2248, + 0x00b0, 0x2219, 0x00b7, 0x221a, 0x207f, 0x00b2, 0x25a0, 0x00a0 + }, + /* User mapping -- default to codes for direct font mapping */ + { + 0xf000, 0xf001, 0xf002, 0xf003, 0xf004, 0xf005, 0xf006, 0xf007, + 0xf008, 0xf009, 0xf00a, 0xf00b, 0xf00c, 0xf00d, 0xf00e, 0xf00f, + 0xf010, 0xf011, 0xf012, 0xf013, 0xf014, 0xf015, 0xf016, 0xf017, + 0xf018, 0xf019, 0xf01a, 0xf01b, 0xf01c, 0xf01d, 0xf01e, 0xf01f, + 0xf020, 0xf021, 0xf022, 0xf023, 0xf024, 0xf025, 0xf026, 0xf027, + 0xf028, 0xf029, 0xf02a, 0xf02b, 0xf02c, 0xf02d, 0xf02e, 0xf02f, + 0xf030, 0xf031, 0xf032, 0xf033, 0xf034, 0xf035, 0xf036, 0xf037, + 0xf038, 0xf039, 0xf03a, 0xf03b, 0xf03c, 0xf03d, 0xf03e, 0xf03f, + 0xf040, 0xf041, 0xf042, 0xf043, 0xf044, 0xf045, 0xf046, 0xf047, + 0xf048, 0xf049, 0xf04a, 0xf04b, 0xf04c, 0xf04d, 0xf04e, 0xf04f, + 0xf050, 0xf051, 0xf052, 0xf053, 0xf054, 0xf055, 0xf056, 0xf057, + 0xf058, 0xf059, 0xf05a, 0xf05b, 0xf05c, 0xf05d, 0xf05e, 0xf05f, + 0xf060, 0xf061, 0xf062, 0xf063, 0xf064, 0xf065, 0xf066, 0xf067, + 0xf068, 0xf069, 0xf06a, 0xf06b, 0xf06c, 0xf06d, 0xf06e, 0xf06f, + 0xf070, 0xf071, 0xf072, 0xf073, 0xf074, 0xf075, 0xf076, 0xf077, + 0xf078, 0xf079, 0xf07a, 0xf07b, 0xf07c, 0xf07d, 0xf07e, 0xf07f, + 0xf080, 0xf081, 0xf082, 0xf083, 0xf084, 0xf085, 0xf086, 0xf087, + 0xf088, 0xf089, 0xf08a, 0xf08b, 0xf08c, 0xf08d, 0xf08e, 0xf08f, + 0xf090, 0xf091, 0xf092, 0xf093, 0xf094, 0xf095, 0xf096, 0xf097, + 0xf098, 0xf099, 0xf09a, 0xf09b, 0xf09c, 0xf09d, 0xf09e, 0xf09f, + 0xf0a0, 0xf0a1, 0xf0a2, 0xf0a3, 0xf0a4, 0xf0a5, 0xf0a6, 0xf0a7, + 0xf0a8, 0xf0a9, 0xf0aa, 0xf0ab, 0xf0ac, 0xf0ad, 0xf0ae, 0xf0af, + 0xf0b0, 0xf0b1, 0xf0b2, 0xf0b3, 0xf0b4, 0xf0b5, 0xf0b6, 0xf0b7, + 0xf0b8, 0xf0b9, 0xf0ba, 0xf0bb, 0xf0bc, 0xf0bd, 0xf0be, 0xf0bf, + 0xf0c0, 0xf0c1, 0xf0c2, 0xf0c3, 0xf0c4, 0xf0c5, 0xf0c6, 0xf0c7, + 0xf0c8, 0xf0c9, 0xf0ca, 0xf0cb, 0xf0cc, 0xf0cd, 0xf0ce, 0xf0cf, + 0xf0d0, 0xf0d1, 0xf0d2, 0xf0d3, 0xf0d4, 0xf0d5, 0xf0d6, 0xf0d7, + 0xf0d8, 0xf0d9, 0xf0da, 0xf0db, 0xf0dc, 0xf0dd, 0xf0de, 0xf0df, + 0xf0e0, 0xf0e1, 0xf0e2, 0xf0e3, 0xf0e4, 0xf0e5, 0xf0e6, 0xf0e7, + 0xf0e8, 0xf0e9, 0xf0ea, 0xf0eb, 0xf0ec, 0xf0ed, 0xf0ee, 0xf0ef, + 0xf0f0, 0xf0f1, 0xf0f2, 0xf0f3, 0xf0f4, 0xf0f5, 0xf0f6, 0xf0f7, + 0xf0f8, 0xf0f9, 0xf0fa, 0xf0fb, 0xf0fc, 0xf0fd, 0xf0fe, 0xf0ff + } +}; + +/* The standard kernel character-to-font mappings are not invertible + -- this is just a best effort. */ + +#define MAX_GLYPH 512 /* Max possible glyph value */ + +static int inv_translate[MAX_NR_CONSOLES]; + +struct uni_pagedir { + u16 **uni_pgdir[32]; + unsigned long refcount; + unsigned long sum; + unsigned char *inverse_translations[4]; + int readonly; +}; + +static struct uni_pagedir *dflt; + +static void set_inverse_transl(struct vc_data *conp, struct uni_pagedir *p, int i) +{ + int j, glyph; + unsigned short *t = translations[i]; + unsigned char *q; + + if (!p) return; + q = p->inverse_translations[i]; + + if (!q) { + q = p->inverse_translations[i] = (unsigned char *) + kmalloc(MAX_GLYPH, GFP_KERNEL); + if (!q) return; + } + memset(q, 0, MAX_GLYPH); + + for (j = 0; j < E_TABSZ; j++) { + glyph = conv_uni_to_pc(conp, t[j]); + if (glyph >= 0 && glyph < MAX_GLYPH && q[glyph] < 32) { + /* prefer '-' above SHY etc. */ + q[glyph] = j; + } + } +} + +unsigned short *set_translate(int m, struct vc_data *vc) +{ + inv_translate[vc->vc_num] = m; + return translations[m]; +} + +/* + * Inverse translation is impossible for several reasons: + * 1. The font<->character maps are not 1-1. + * 2. The text may have been written while a different translation map + * was active, or using Unicode. + * Still, it is now possible to a certain extent to cut and paste non-ASCII. + */ +unsigned char inverse_translate(struct vc_data *conp, int glyph) +{ + struct uni_pagedir *p; + if (glyph < 0 || glyph >= MAX_GLYPH) + return 0; + else if (!(p = (struct uni_pagedir *)*conp->vc_uni_pagedir_loc) || + !p->inverse_translations[inv_translate[conp->vc_num]]) + return glyph; + else + return p->inverse_translations[inv_translate[conp->vc_num]][glyph]; +} + +static void update_user_maps(void) +{ + int i; + struct uni_pagedir *p, *q = NULL; + + for (i = 0; i < MAX_NR_CONSOLES; i++) { + if (!vc_cons_allocated(i)) + continue; + p = (struct uni_pagedir *)*vc_cons[i].d->vc_uni_pagedir_loc; + if (p && p != q) { + set_inverse_transl(vc_cons[i].d, p, USER_MAP); + q = p; + } + } +} + +/* + * Load customizable translation table + * arg points to a 256 byte translation table. + * + * The "old" variants are for translation directly to font (using the + * 0xf000-0xf0ff "transparent" Unicodes) whereas the "new" variants set + * Unicodes explicitly. + */ +int con_set_trans_old(unsigned char __user * arg) +{ + int i; + unsigned short *p = translations[USER_MAP]; + + if (!access_ok(VERIFY_READ, arg, E_TABSZ)) + return -EFAULT; + + for (i=0; i current font conversion + * + * A font has at most 512 chars, usually 256. + * But one font position may represent several Unicode chars. + * A hashtable is somewhat of a pain to deal with, so use a + * "paged table" instead. Simulation has shown the memory cost of + * this 3-level paged table scheme to be comparable to a hash table. + */ + +extern u8 dfont_unicount[]; /* Defined in console_defmap.c */ +extern u16 dfont_unitable[]; + +static void con_release_unimap(struct uni_pagedir *p) +{ + u16 **p1; + int i, j; + + if (p == dflt) dflt = NULL; + for (i = 0; i < 32; i++) { + if ((p1 = p->uni_pgdir[i]) != NULL) { + for (j = 0; j < 32; j++) + if (p1[j]) + kfree(p1[j]); + kfree(p1); + } + p->uni_pgdir[i] = NULL; + } + for (i = 0; i < 4; i++) + if (p->inverse_translations[i]) { + kfree(p->inverse_translations[i]); + p->inverse_translations[i] = NULL; + } +} + +void con_free_unimap(struct vc_data *vc) +{ + struct uni_pagedir *p; + + p = (struct uni_pagedir *)*vc->vc_uni_pagedir_loc; + if (!p) + return; + *vc->vc_uni_pagedir_loc = 0; + if (--p->refcount) + return; + con_release_unimap(p); + kfree(p); +} + +static int con_unify_unimap(struct vc_data *conp, struct uni_pagedir *p) +{ + int i, j, k; + struct uni_pagedir *q; + + for (i = 0; i < MAX_NR_CONSOLES; i++) { + if (!vc_cons_allocated(i)) + continue; + q = (struct uni_pagedir *)*vc_cons[i].d->vc_uni_pagedir_loc; + if (!q || q == p || q->sum != p->sum) + continue; + for (j = 0; j < 32; j++) { + u16 **p1, **q1; + p1 = p->uni_pgdir[j]; q1 = q->uni_pgdir[j]; + if (!p1 && !q1) + continue; + if (!p1 || !q1) + break; + for (k = 0; k < 32; k++) { + if (!p1[k] && !q1[k]) + continue; + if (!p1[k] || !q1[k]) + break; + if (memcmp(p1[k], q1[k], 64*sizeof(u16))) + break; + } + if (k < 32) + break; + } + if (j == 32) { + q->refcount++; + *conp->vc_uni_pagedir_loc = (unsigned long)q; + con_release_unimap(p); + kfree(p); + return 1; + } + } + return 0; +} + +static int +con_insert_unipair(struct uni_pagedir *p, u_short unicode, u_short fontpos) +{ + int i, n; + u16 **p1, *p2; + + if (!(p1 = p->uni_pgdir[n = unicode >> 11])) { + p1 = p->uni_pgdir[n] = kmalloc(32*sizeof(u16 *), GFP_KERNEL); + if (!p1) return -ENOMEM; + for (i = 0; i < 32; i++) + p1[i] = NULL; + } + + if (!(p2 = p1[n = (unicode >> 6) & 0x1f])) { + p2 = p1[n] = kmalloc(64*sizeof(u16), GFP_KERNEL); + if (!p2) return -ENOMEM; + memset(p2, 0xff, 64*sizeof(u16)); /* No glyphs for the characters (yet) */ + } + + p2[unicode & 0x3f] = fontpos; + + p->sum += (fontpos << 20) + unicode; + + return 0; +} + +/* ui is a leftover from using a hashtable, but might be used again */ +int con_clear_unimap(struct vc_data *vc, struct unimapinit *ui) +{ + struct uni_pagedir *p, *q; + + p = (struct uni_pagedir *)*vc->vc_uni_pagedir_loc; + if (p && p->readonly) return -EIO; + if (!p || --p->refcount) { + q = (struct uni_pagedir *)kmalloc(sizeof(*p), GFP_KERNEL); + if (!q) { + if (p) p->refcount++; + return -ENOMEM; + } + memset(q, 0, sizeof(*q)); + q->refcount=1; + *vc->vc_uni_pagedir_loc = (unsigned long)q; + } else { + if (p == dflt) dflt = NULL; + p->refcount++; + p->sum = 0; + con_release_unimap(p); + } + return 0; +} + +int con_set_unimap(struct vc_data *vc, ushort ct, struct unipair __user *list) +{ + int err = 0, err1, i; + struct uni_pagedir *p, *q; + + p = (struct uni_pagedir *)*vc->vc_uni_pagedir_loc; + if (p->readonly) return -EIO; + + if (!ct) return 0; + + if (p->refcount > 1) { + int j, k; + u16 **p1, *p2, l; + + err1 = con_clear_unimap(vc, NULL); + if (err1) return err1; + + q = (struct uni_pagedir *)*vc->vc_uni_pagedir_loc; + for (i = 0, l = 0; i < 32; i++) + if ((p1 = p->uni_pgdir[i])) + for (j = 0; j < 32; j++) + if ((p2 = p1[j])) + for (k = 0; k < 64; k++, l++) + if (p2[k] != 0xffff) { + err1 = con_insert_unipair(q, l, p2[k]); + if (err1) { + p->refcount++; + *vc->vc_uni_pagedir_loc = (unsigned long)p; + con_release_unimap(q); + kfree(q); + return err1; + } + } + p = q; + } else if (p == dflt) + dflt = NULL; + + while (ct--) { + unsigned short unicode, fontpos; + __get_user(unicode, &list->unicode); + __get_user(fontpos, &list->fontpos); + if ((err1 = con_insert_unipair(p, unicode,fontpos)) != 0) + err = err1; + list++; + } + + if (con_unify_unimap(vc, p)) + return err; + + for (i = 0; i <= 3; i++) + set_inverse_transl(vc, p, i); /* Update all inverse translations */ + + return err; +} + +/* Loads the unimap for the hardware font, as defined in uni_hash.tbl. + The representation used was the most compact I could come up + with. This routine is executed at sys_setup time, and when the + PIO_FONTRESET ioctl is called. */ + +int con_set_default_unimap(struct vc_data *vc) +{ + int i, j, err = 0, err1; + u16 *q; + struct uni_pagedir *p; + + if (dflt) { + p = (struct uni_pagedir *)*vc->vc_uni_pagedir_loc; + if (p == dflt) + return 0; + dflt->refcount++; + *vc->vc_uni_pagedir_loc = (unsigned long)dflt; + if (p && --p->refcount) { + con_release_unimap(p); + kfree(p); + } + return 0; + } + + /* The default font is always 256 characters */ + + err = con_clear_unimap(vc, NULL); + if (err) return err; + + p = (struct uni_pagedir *)*vc->vc_uni_pagedir_loc; + q = dfont_unitable; + + for (i = 0; i < 256; i++) + for (j = dfont_unicount[i]; j; j--) { + err1 = con_insert_unipair(p, *(q++), i); + if (err1) + err = err1; + } + + if (con_unify_unimap(vc, p)) { + dflt = (struct uni_pagedir *)*vc->vc_uni_pagedir_loc; + return err; + } + + for (i = 0; i <= 3; i++) + set_inverse_transl(vc, p, i); /* Update all inverse translations */ + dflt = p; + return err; +} +EXPORT_SYMBOL(con_set_default_unimap); + +int con_copy_unimap(struct vc_data *dst_vc, struct vc_data *src_vc) +{ + struct uni_pagedir *q; + + if (!*src_vc->vc_uni_pagedir_loc) + return -EINVAL; + if (*dst_vc->vc_uni_pagedir_loc == *src_vc->vc_uni_pagedir_loc) + return 0; + con_free_unimap(dst_vc); + q = (struct uni_pagedir *)*src_vc->vc_uni_pagedir_loc; + q->refcount++; + *dst_vc->vc_uni_pagedir_loc = (long)q; + return 0; +} + +int con_get_unimap(struct vc_data *vc, ushort ct, ushort __user *uct, struct unipair __user *list) +{ + int i, j, k, ect; + u16 **p1, *p2; + struct uni_pagedir *p; + + ect = 0; + if (*vc->vc_uni_pagedir_loc) { + p = (struct uni_pagedir *)*vc->vc_uni_pagedir_loc; + for (i = 0; i < 32; i++) + if ((p1 = p->uni_pgdir[i])) + for (j = 0; j < 32; j++) + if ((p2 = *(p1++))) + for (k = 0; k < 64; k++) { + if (*p2 < MAX_GLYPH && ect++ < ct) { + __put_user((u_short)((i<<11)+(j<<6)+k), + &list->unicode); + __put_user((u_short) *p2, + &list->fontpos); + list++; + } + p2++; + } + } + __put_user(ect, uct); + return ((ect <= ct) ? 0 : -ENOMEM); +} + +void con_protect_unimap(struct vc_data *vc, int rdonly) +{ + struct uni_pagedir *p = (struct uni_pagedir *)*vc->vc_uni_pagedir_loc; + + if (p) + p->readonly = rdonly; +} + +int +conv_uni_to_pc(struct vc_data *conp, long ucs) +{ + int h; + u16 **p1, *p2; + struct uni_pagedir *p; + + /* Only 16-bit codes supported at this time */ + if (ucs > 0xffff) + ucs = 0xfffd; /* U+FFFD: REPLACEMENT CHARACTER */ + else if (ucs < 0x20 || ucs >= 0xfffe) + return -1; /* Not a printable character */ + else if (ucs == 0xfeff || (ucs >= 0x200a && ucs <= 0x200f)) + return -2; /* Zero-width space */ + /* + * UNI_DIRECT_BASE indicates the start of the region in the User Zone + * which always has a 1:1 mapping to the currently loaded font. The + * UNI_DIRECT_MASK indicates the bit span of the region. + */ + else if ((ucs & ~UNI_DIRECT_MASK) == UNI_DIRECT_BASE) + return ucs & UNI_DIRECT_MASK; + + if (!*conp->vc_uni_pagedir_loc) + return -3; + + p = (struct uni_pagedir *)*conp->vc_uni_pagedir_loc; + if ((p1 = p->uni_pgdir[ucs >> 11]) && + (p2 = p1[(ucs >> 6) & 0x1f]) && + (h = p2[ucs & 0x3f]) < MAX_GLYPH) + return h; + + return -4; /* not found */ +} + +/* + * This is called at sys_setup time, after memory and the console are + * initialized. It must be possible to call kmalloc(..., GFP_KERNEL) + * from this function, hence the call from sys_setup. + */ +void __init +console_map_init(void) +{ + int i; + + for (i = 0; i < MAX_NR_CONSOLES; i++) + if (vc_cons_allocated(i) && !*vc_cons[i].d->vc_uni_pagedir_loc) + con_set_default_unimap(vc_cons[i].d); +} + +EXPORT_SYMBOL(con_copy_unimap); diff --git a/drivers/char/cp437.uni b/drivers/char/cp437.uni new file mode 100644 index 000000000000..1f06889a96b9 --- /dev/null +++ b/drivers/char/cp437.uni @@ -0,0 +1,291 @@ +# +# Unicode table for IBM Codepage 437. Note that there are many more +# substitutions that could be conceived (for example, thick-line +# graphs probably should be replaced with double-line ones, accented +# Latin characters should replaced with their nonaccented versions, +# and some upper case Greek characters could be replaced by Latin), however, +# I have limited myself to the Unicodes used by the kernel ISO 8859-1, +# DEC VT, and IBM CP 437 tables. +# +# -------------------------------- +# +# Basic IBM dingbats, some of which will never have a purpose clear +# to mankind +# +0x00 U+0000 +0x01 U+263a +0x02 U+263b +0x03 U+2665 +0x04 U+2666 U+25c6 +0x05 U+2663 +0x06 U+2660 +0x07 U+2022 +0x08 U+25d8 +0x09 U+25cb +0x0a U+25d9 +0x0b U+2642 +0x0c U+2640 +0x0d U+266a +0x0e U+266b +0x0f U+263c +0x10 U+25b6 U+25ba +0x11 U+25c0 U+25c4 +0x12 U+2195 +0x13 U+203c +0x14 U+00b6 +0x15 U+00a7 +0x16 U+25ac +0x17 U+21a8 +0x18 U+2191 +0x19 U+2193 +0x1a U+2192 +0x1b U+2190 +0x1c U+221f +0x1d U+2194 +0x1e U+25b2 +0x1f U+25bc +# +# The ASCII range is identity-mapped, but some of the characters also +# have to act as substitutes, especially the upper-case characters. +# +0x20 U+0020 +0x21 U+0021 +0x22 U+0022 U+00a8 +0x23 U+0023 +0x24 U+0024 +0x25 U+0025 +0x26 U+0026 +0x27 U+0027 +0x28 U+0028 +0x29 U+0029 +0x2a U+002a +0x2b U+002b +0x2c U+002c U+00b8 +0x2d U+002d U+00ad +0x2e U+002e +0x2f U+002f +0x30 U+0030 +0x31 U+0031 +0x32 U+0032 +0x33 U+0033 +0x34 U+0034 +0x35 U+0035 +0x36 U+0036 +0x37 U+0037 +0x38 U+0038 +0x39 U+0039 +0x3a U+003a +0x3b U+003b +0x3c U+003c +0x3d U+003d +0x3e U+003e +0x3f U+003f +0x40 U+0040 +0x41 U+0041 U+00c0 U+00c1 U+00c2 U+00c3 +0x42 U+0042 +0x43 U+0043 U+00a9 +0x44 U+0044 +0x45 U+0045 U+00c8 U+00ca U+00cb +0x46 U+0046 +0x47 U+0047 +0x48 U+0048 +0x49 U+0049 U+00cc U+00cd U+00ce U+00cf +0x4a U+004a +0x4b U+004b U+212a +0x4c U+004c +0x4d U+004d +0x4e U+004e +0x4f U+004f U+00d2 U+00d3 U+00d4 U+00d5 +0x50 U+0050 +0x51 U+0051 +0x52 U+0052 U+00ae +0x53 U+0053 +0x54 U+0054 +0x55 U+0055 U+00d9 U+00da U+00db +0x56 U+0056 +0x57 U+0057 +0x58 U+0058 +0x59 U+0059 U+00dd +0x5a U+005a +0x5b U+005b +0x5c U+005c +0x5d U+005d +0x5e U+005e +0x5f U+005f U+23bd U+f804 +0x60 U+0060 +0x61 U+0061 U+00e3 +0x62 U+0062 +0x63 U+0063 +0x64 U+0064 +0x65 U+0065 +0x66 U+0066 +0x67 U+0067 +0x68 U+0068 +0x69 U+0069 +0x6a U+006a +0x6b U+006b +0x6c U+006c +0x6d U+006d +0x6e U+006e +0x6f U+006f U+00f5 +0x70 U+0070 +0x71 U+0071 +0x72 U+0072 +0x73 U+0073 +0x74 U+0074 +0x75 U+0075 +0x76 U+0076 +0x77 U+0077 +0x78 U+0078 U+00d7 +0x79 U+0079 U+00fd +0x7a U+007a +0x7b U+007b +0x7c U+007c U+00a5 +0x7d U+007d +0x7e U+007e +# +# Okay, what on Earth is this one supposed to be used for? +# +0x7f U+2302 +# +# Non-English characters, mostly lower case letters... +# +0x80 U+00c7 +0x81 U+00fc +0x82 U+00e9 +0x83 U+00e2 +0x84 U+00e4 +0x85 U+00e0 +0x86 U+00e5 +0x87 U+00e7 +0x88 U+00ea +0x89 U+00eb +0x8a U+00e8 +0x8b U+00ef +0x8c U+00ee +0x8d U+00ec +0x8e U+00c4 +0x8f U+00c5 U+212b +0x90 U+00c9 +0x91 U+00e6 +0x92 U+00c6 +0x93 U+00f4 +0x94 U+00f6 +0x95 U+00f2 +0x96 U+00fb +0x97 U+00f9 +0x98 U+00ff +0x99 U+00d6 +0x9a U+00dc +0x9b U+00a2 +0x9c U+00a3 +0x9d U+00a5 +0x9e U+20a7 +0x9f U+0192 +0xa0 U+00e1 +0xa1 U+00ed +0xa2 U+00f3 +0xa3 U+00fa +0xa4 U+00f1 +0xa5 U+00d1 +0xa6 U+00aa +0xa7 U+00ba +0xa8 U+00bf +0xa9 U+2310 +0xaa U+00ac +0xab U+00bd +0xac U+00bc +0xad U+00a1 +0xae U+00ab +0xaf U+00bb +# +# Block graphics +# +0xb0 U+2591 +0xb1 U+2592 +0xb2 U+2593 +0xb3 U+2502 +0xb4 U+2524 +0xb5 U+2561 +0xb6 U+2562 +0xb7 U+2556 +0xb8 U+2555 +0xb9 U+2563 +0xba U+2551 +0xbb U+2557 +0xbc U+255d +0xbd U+255c +0xbe U+255b +0xbf U+2510 +0xc0 U+2514 +0xc1 U+2534 +0xc2 U+252c +0xc3 U+251c +0xc4 U+2500 +0xc5 U+253c +0xc6 U+255e +0xc7 U+255f +0xc8 U+255a +0xc9 U+2554 +0xca U+2569 +0xcb U+2566 +0xcc U+2560 +0xcd U+2550 +0xce U+256c +0xcf U+2567 +0xd0 U+2568 +0xd1 U+2564 +0xd2 U+2565 +0xd3 U+2559 +0xd4 U+2558 +0xd5 U+2552 +0xd6 U+2553 +0xd7 U+256b +0xd8 U+256a +0xd9 U+2518 +0xda U+250c +0xdb U+2588 +0xdc U+2584 +0xdd U+258c +0xde U+2590 +0xdf U+2580 +# +# Greek letters and mathematical symbols +# +0xe0 U+03b1 +0xe1 U+03b2 U+00df +0xe2 U+0393 +0xe3 U+03c0 +0xe4 U+03a3 +0xe5 U+03c3 +0xe6 U+00b5 U+03bc +0xe7 U+03c4 +0xe8 U+03a6 U+00d8 +0xe9 U+0398 +0xea U+03a9 U+2126 +0xeb U+03b4 +0xec U+221e +0xed U+03c6 U+00f8 +0xee U+03b5 +0xef U+2229 +0xf0 U+2261 +0xf1 U+00b1 +0xf2 U+2265 +0xf3 U+2264 +0xf4 U+2320 +0xf5 U+2321 +0xf6 U+00f7 +0xf7 U+2248 +0xf8 U+00b0 +0xf9 U+2219 +0xfa U+00b7 +0xfb U+221a +0xfc U+207f +0xfd U+00b2 +# +# Square bullet, non-spacing blank +# Mapping U+fffd to the square bullet means it is the substitution +# character +# +0xfe U+25a0 U+fffd +0xff U+00a0 diff --git a/drivers/char/cyclades.c b/drivers/char/cyclades.c new file mode 100644 index 000000000000..6a5337bf0936 --- /dev/null +++ b/drivers/char/cyclades.c @@ -0,0 +1,5540 @@ +#undef BLOCKMOVE +#define Z_WAKE +#undef Z_EXT_CHARS_IN_BUFFER +static char rcsid[] = +"$Revision: 2.3.2.20 $$Date: 2004/02/25 18:14:16 $"; + +/* + * linux/drivers/char/cyclades.c + * + * This file contains the driver for the Cyclades async multiport + * serial boards. + * + * Initially written by Randolph Bentson . + * Modified and maintained by Marcio Saito . + * Currently maintained by Cyclades team . + * + * For Technical support and installation problems, please send e-mail + * to support@cyclades.com. + * + * Much of the design and some of the code came from serial.c + * which was copyright (C) 1991, 1992 Linus Torvalds. It was + * extensively rewritten by Theodore Ts'o, 8/16/92 -- 9/14/92, + * and then fixed as suggested by Michael K. Johnson 12/12/92. + * + * This version supports shared IRQ's (only for PCI boards). + * + * $Log: cyclades.c,v $ + * Prevent users from opening non-existing Z ports. + * + * Revision 2.3.2.8 2000/07/06 18:14:16 ivan + * Fixed the PCI detection function to work properly on Alpha systems. + * Implemented support for TIOCSERGETLSR ioctl. + * Implemented full support for non-standard baud rates. + * + * Revision 2.3.2.7 2000/06/01 18:26:34 ivan + * Request PLX I/O region, although driver doesn't use it, to avoid + * problems with other drivers accessing it. + * Removed count for on-board buffer characters in cy_chars_in_buffer + * (Cyclades-Z only). + * + * Revision 2.3.2.6 2000/05/05 13:56:05 ivan + * Driver now reports physical instead of virtual memory addresses. + * Masks were added to some Cyclades-Z read accesses. + * Implemented workaround for PLX9050 bug that would cause a system lockup + * in certain systems, depending on the MMIO addresses allocated to the + * board. + * Changed the Tx interrupt programming in the CD1400 chips to boost up + * performance (Cyclom-Y only). + * Code is now compliant with the new module interface (module_[init|exit]). + * Make use of the PCI helper functions to access PCI resources. + * Did some code "housekeeping". + * + * Revision 2.3.2.5 2000/01/19 14:35:33 ivan + * Fixed bug in cy_set_termios on CRTSCTS flag turnoff. + * + * Revision 2.3.2.4 2000/01/17 09:19:40 ivan + * Fixed SMP locking in Cyclom-Y interrupt handler. + * + * Revision 2.3.2.3 1999/12/28 12:11:39 ivan + * Added a new cyclades_card field called nports to allow the driver to + * know the exact number of ports found by the Z firmware after its load; + * RX buffer contention prevention logic on interrupt op mode revisited + * (Cyclades-Z only); + * Revisited printk's for Z debug; + * Driver now makes sure that the constant SERIAL_XMIT_SIZE is defined; + * + * Revision 2.3.2.2 1999/10/01 11:27:43 ivan + * Fixed bug in cyz_poll that would make all ports but port 0 + * unable to transmit/receive data (Cyclades-Z only); + * Implemented logic to prevent the RX buffer from being stuck with data + * due to a driver / firmware race condition in interrupt op mode + * (Cyclades-Z only); + * Fixed bug in block_til_ready logic that would lead to a system crash; + * Revisited cy_close spinlock usage; + * + * Revision 2.3.2.1 1999/09/28 11:01:22 ivan + * Revisited CONFIG_PCI conditional compilation for PCI board support; + * Implemented TIOCGICOUNT and TIOCMIWAIT ioctl support; + * _Major_ cleanup on the Cyclades-Z interrupt support code / logic; + * Removed CTS handling from the driver -- this is now completely handled + * by the firmware (Cyclades-Z only); + * Flush RX on-board buffers on a port open (Cyclades-Z only); + * Fixed handling of ASYNC_SPD_* TTY flags; + * Module unload now unmaps all memory area allocated by ioremap; + * + * Revision 2.3.1.1 1999/07/15 16:45:53 ivan + * Removed CY_PROC conditional compilation; + * Implemented SMP-awareness for the driver; + * Implemented a new ISA IRQ autoprobe that uses the irq_probe_[on|off] + * functions; + * The driver now accepts memory addresses (maddr=0xMMMMM) and IRQs + * (irq=NN) as parameters (only for ISA boards); + * Fixed bug in set_line_char that would prevent the Cyclades-Z + * ports from being configured at speeds above 115.2Kbps; + * Fixed bug in cy_set_termios that would prevent XON/XOFF flow control + * switching from working properly; + * The driver now only prints IRQ info for the Cyclades-Z if it's + * configured to work in interrupt mode; + * + * Revision 2.2.2.3 1999/06/28 11:13:29 ivan + * Added support for interrupt mode operation for the Z cards; + * Removed the driver inactivity control for the Z; + * Added a missing MOD_DEC_USE_COUNT in the cy_open function for when + * the Z firmware is not loaded yet; + * Replaced the "manual" Z Tx flush buffer by a call to a FW command of + * same functionality; + * Implemented workaround for IRQ setting loss on the PCI configuration + * registers after a PCI bridge EEPROM reload (affects PLX9060 only); + * + * Revision 2.2.2.2 1999/05/14 17:18:15 ivan + * /proc entry location changed to /proc/tty/driver/cyclades; + * Added support to shared IRQ's (only for PCI boards); + * Added support for Cobalt Qube2 systems; + * IRQ [de]allocation scheme revisited; + * BREAK implementation changed in order to make use of the 'break_ctl' + * TTY facility; + * Fixed typo in TTY structure field 'driver_name'; + * Included a PCI bridge reset and EEPROM reload in the board + * initialization code (for both Y and Z series). + * + * Revision 2.2.2.1 1999/04/08 16:17:43 ivan + * Fixed a bug in cy_wait_until_sent that was preventing the port to be + * closed properly after a SIGINT; + * Module usage counter scheme revisited; + * Added support to the upcoming Y PCI boards (i.e., support to additional + * PCI Device ID's). + * + * Revision 2.2.1.10 1999/01/20 16:14:29 ivan + * Removed all unnecessary page-alignement operations in ioremap calls + * (ioremap is currently safe for these operations). + * + * Revision 2.2.1.9 1998/12/30 18:18:30 ivan + * Changed access to PLX PCI bridge registers from I/O to MMIO, in + * order to make PLX9050-based boards work with certain motherboards. + * + * Revision 2.2.1.8 1998/11/13 12:46:20 ivan + * cy_close function now resets (correctly) the tty->closing flag; + * JIFFIES_DIFF macro fixed. + * + * Revision 2.2.1.7 1998/09/03 12:07:28 ivan + * Fixed bug in cy_close function, which was not informing HW of + * which port should have the reception disabled before doing so; + * fixed Cyclom-8YoP hardware detection bug. + * + * Revision 2.2.1.6 1998/08/20 17:15:39 ivan + * Fixed bug in cy_close function, which causes malfunction + * of one of the first 4 ports when a higher port is closed + * (Cyclom-Y only). + * + * Revision 2.2.1.5 1998/08/10 18:10:28 ivan + * Fixed Cyclom-4Yo hardware detection bug. + * + * Revision 2.2.1.4 1998/08/04 11:02:50 ivan + * /proc/cyclades implementation with great collaboration of + * Marc Lewis ; + * cyy_interrupt was changed to avoid occurrence of kernel oopses + * during PPP operation. + * + * Revision 2.2.1.3 1998/06/01 12:09:10 ivan + * General code review in order to comply with 2.1 kernel standards; + * data loss prevention for slow devices revisited (cy_wait_until_sent + * was created); + * removed conditional compilation for new/old PCI structure support + * (now the driver only supports the new PCI structure). + * + * Revision 2.2.1.1 1998/03/19 16:43:12 ivan + * added conditional compilation for new/old PCI structure support; + * removed kernel series (2.0.x / 2.1.x) conditional compilation. + * + * Revision 2.1.1.3 1998/03/16 18:01:12 ivan + * cleaned up the data loss fix; + * fixed XON/XOFF handling once more (Cyclades-Z); + * general review of the driver routines; + * introduction of a mechanism to prevent data loss with slow + * printers, by forcing a delay before closing the port. + * + * Revision 2.1.1.2 1998/02/17 16:50:00 ivan + * fixed detection/handling of new CD1400 in Ye boards; + * fixed XON/XOFF handling (Cyclades-Z); + * fixed data loss caused by a premature port close; + * introduction of a flag that holds the CD1400 version ID per port + * (used by the CYGETCD1400VER new ioctl). + * + * Revision 2.1.1.1 1997/12/03 17:31:19 ivan + * Code review for the module cleanup routine; + * fixed RTS and DTR status report for new CD1400's in get_modem_info; + * includes anonymous changes regarding signal_pending. + * + * Revision 2.1 1997/11/01 17:42:41 ivan + * Changes in the driver to support Alpha systems (except 8Zo V_1); + * BREAK fix for the Cyclades-Z boards; + * driver inactivity control by FW implemented; + * introduction of flag that allows driver to take advantage of + * a special CD1400 feature related to HW flow control; + * added support for the CD1400 rev. J (Cyclom-Y boards); + * introduction of ioctls to: + * - control the rtsdtr_inv flag (Cyclom-Y); + * - control the rflow flag (Cyclom-Y); + * - adjust the polling interval (Cyclades-Z); + * + * Revision 1.36.4.33 1997/06/27 19:00:00 ivan + * Fixes related to kernel version conditional + * compilation. + * + * Revision 1.36.4.32 1997/06/14 19:30:00 ivan + * Compatibility issues between kernels 2.0.x and + * 2.1.x (mainly related to clear_bit function). + * + * Revision 1.36.4.31 1997/06/03 15:30:00 ivan + * Changes to define the memory window according to the + * board type. + * + * Revision 1.36.4.30 1997/05/16 15:30:00 daniel + * Changes to support new cycladesZ boards. + * + * Revision 1.36.4.29 1997/05/12 11:30:00 daniel + * Merge of Bentson's and Daniel's version 1.36.4.28. + * Corrects bug in cy_detect_pci: check if there are more + * ports than the number of static structs allocated. + * Warning message during initialization if this driver is + * used with the new generation of cycladesZ boards. Those + * will be supported only in next release of the driver. + * Corrects bug in cy_detect_pci and cy_detect_isa that + * returned wrong number of VALID boards, when a cyclomY + * was found with no serial modules connected. + * Changes to use current (2.1.x) kernel subroutine names + * and created macros for compilation with 2.0.x kernel, + * instead of the other way around. + * + * Revision 1.36.4.28 1997/05/?? ??:00:00 bentson + * Change queue_task_irq_off to queue_task_irq. + * The inline function queue_task_irq_off (tqueue.h) + * was removed from latest releases of 2.1.x kernel. + * Use of macro __init to mark the initialization + * routines, so memory can be reused. + * Also incorporate implementation of critical region + * in function cleanup_module() created by anonymous + * linuxer. + * + * Revision 1.36.4.28 1997/04/25 16:00:00 daniel + * Change to support new firmware that solves DCD problem: + * application could fail to receive SIGHUP signal when DCD + * varying too fast. + * + * Revision 1.36.4.27 1997/03/26 10:30:00 daniel + * Changed for support linux versions 2.1.X. + * Backward compatible with linux versions 2.0.X. + * Corrected illegal use of filler field in + * CH_CTRL struct. + * Deleted some debug messages. + * + * Revision 1.36.4.26 1997/02/27 12:00:00 daniel + * Included check for NULL tty pointer in cyz_poll. + * + * Revision 1.36.4.25 1997/02/26 16:28:30 bentson + * Bill Foster at Blarg! Online services noticed that + * some of the switch elements of -Z modem control + * lacked a closing "break;" + * + * Revision 1.36.4.24 1997/02/24 11:00:00 daniel + * Changed low water threshold for buffer xmit_buf + * + * Revision 1.36.4.23 1996/12/02 21:50:16 bentson + * Marcio provided fix to modem status fetch for -Z + * + * Revision 1.36.4.22 1996/10/28 22:41:17 bentson + * improve mapping of -Z control page (thanks to Steve + * Price for help on this) + * + * Revision 1.36.4.21 1996/09/10 17:00:10 bentson + * shift from CPU-bound to memcopy in cyz_polling operation + * + * Revision 1.36.4.20 1996/09/09 18:30:32 Bentson + * Added support to set and report higher speeds. + * + * Revision 1.36.4.19c 1996/08/09 10:00:00 Marcio Saito + * Some fixes in the HW flow control for the BETA release. + * Don't try to register the IRQ. + * + * Revision 1.36.4.19 1996/08/08 16:23:18 Bentson + * make sure "cyc" appears in all kernel messages; all soft interrupts + * handled by same routine; recognize out-of-band reception; comment + * out some diagnostic messages; leave RTS/CTS flow control to hardware; + * fix race condition in -Z buffer management; only -Y needs to explictly + * flush chars; tidy up some startup messages; + * + * Revision 1.36.4.18 1996/07/25 18:57:31 bentson + * shift MOD_INC_USE_COUNT location to match + * serial.c; purge some diagnostic messages; + * + * Revision 1.36.4.17 1996/07/25 18:01:08 bentson + * enable modem status messages and fetch & process them; note + * time of last activity type for each port; set_line_char now + * supports more than line 0 and treats 0 baud correctly; + * get_modem_info senses rs_status; + * + * Revision 1.36.4.16 1996/07/20 08:43:15 bentson + * barely works--now's time to turn on + * more features 'til it breaks + * + * Revision 1.36.4.15 1996/07/19 22:30:06 bentson + * check more -Z board status; shorten boot message + * + * Revision 1.36.4.14 1996/07/19 22:20:37 bentson + * fix reference to ch_ctrl in startup; verify return + * values from cyz_issue_cmd and cyz_update_channel; + * more stuff to get modem control correct; + * + * Revision 1.36.4.13 1996/07/11 19:53:33 bentson + * more -Z stuff folded in; re-order changes to put -Z stuff + * after -Y stuff (to make changes clearer) + * + * Revision 1.36.4.12 1996/07/11 15:40:55 bentson + * Add code to poll Cyclades-Z. Add code to get & set RS-232 control. + * Add code to send break. Clear firmware ID word at startup (so + * that other code won't talk to inactive board). + * + * Revision 1.36.4.11 1996/07/09 05:28:29 bentson + * add code for -Z in set_line_char + * + * Revision 1.36.4.10 1996/07/08 19:28:37 bentson + * fold more -Z stuff (or in some cases, error messages) + * into driver; add text to "don't know what to do" messages. + * + * Revision 1.36.4.9 1996/07/08 18:38:38 bentson + * moved compile-time flags near top of file; cosmetic changes + * to narrow text (to allow 2-up printing); changed many declarations + * to "static" to limit external symbols; shuffled code order to + * coalesce -Y and -Z specific code, also to put internal functions + * in order of tty_driver structure; added code to recognize -Z + * ports (and for moment, do nothing or report error); add cy_startup + * to parse boot command line for extra base addresses for ISA probes; + * + * Revision 1.36.4.8 1996/06/25 17:40:19 bentson + * reorder some code, fix types of some vars (int vs. long), + * add cy_setup to support user declared ISA addresses + * + * Revision 1.36.4.7 1996/06/21 23:06:18 bentson + * dump ioctl based firmware load (it's now a user level + * program); ensure uninitialzed ports cannot be used + * + * Revision 1.36.4.6 1996/06/20 23:17:19 bentson + * rename vars and restructure some code + * + * Revision 1.36.4.5 1996/06/14 15:09:44 bentson + * get right status back after boot load + * + * Revision 1.36.4.4 1996/06/13 19:51:44 bentson + * successfully loads firmware + * + * Revision 1.36.4.3 1996/06/13 06:08:33 bentson + * add more of the code for the boot/load ioctls + * + * Revision 1.36.4.2 1996/06/11 21:00:51 bentson + * start to add Z functionality--starting with ioctl + * for loading firmware + * + * Revision 1.36.4.1 1996/06/10 18:03:02 bentson + * added code to recognize Z/PCI card at initialization; report + * presence, but card is not initialized (because firmware needs + * to be loaded) + * + * Revision 1.36.3.8 1996/06/07 16:29:00 bentson + * starting minor number at zero; added missing verify_area + * as noted by Heiko Eissfeldt + * + * Revision 1.36.3.7 1996/04/19 21:06:18 bentson + * remove unneeded boot message & fix CLOCAL hardware flow + * control (Miquel van Smoorenburg ); + * remove unused diagnostic statements; minor 0 is first; + * + * Revision 1.36.3.6 1996/03/13 13:21:17 marcio + * The kernel function vremap (available only in later 1.3.xx kernels) + * allows the access to memory addresses above the RAM. This revision + * of the driver supports PCI boards below 1Mb (device id 0x100) and + * above 1Mb (device id 0x101). + * + * Revision 1.36.3.5 1996/03/07 15:20:17 bentson + * Some global changes to interrupt handling spilled into + * this driver--mostly unused arguments in system function + * calls. Also added change by Marcio Saito which should + * reduce lost interrupts at startup by fast processors. + * + * Revision 1.36.3.4 1995/11/13 20:45:10 bentson + * Changes by Corey Minyard distributed + * in 1.3.41 kernel to remove a possible race condition, extend + * some error messages, and let the driver run as a loadable module + * Change by Alan Wendt to remove a + * possible race condition. + * Change by Marcio Saito to fix PCI addressing. + * + * Revision 1.36.3.3 1995/11/13 19:44:48 bentson + * Changes by Linus Torvalds in 1.3.33 kernel distribution + * required due to reordering of driver initialization. + * Drivers are now initialized *after* memory management. + * + * Revision 1.36.3.2 1995/09/08 22:07:14 bentson + * remove printk from ISR; fix typo + * + * Revision 1.36.3.1 1995/09/01 12:00:42 marcio + * Minor fixes in the PCI board support. PCI function calls in + * conditional compilation (CONFIG_PCI). Thanks to Jim Duncan + * . "bad serial count" message removed. + * + * Revision 1.36.3 1995/08/22 09:19:42 marcio + * Cyclom-Y/PCI support added. Changes in the cy_init routine and + * board initialization. Changes in the boot messages. The driver + * supports up to 4 boards and 64 ports by default. + * + * Revision 1.36.1.4 1995/03/29 06:14:14 bentson + * disambiguate between Cyclom-16Y and Cyclom-32Ye; + * + * Revision 1.36.1.3 1995/03/23 22:15:35 bentson + * add missing break in modem control block in ioctl switch statement + * (discovered by Michael Edward Chastain ); + * + * Revision 1.36.1.2 1995/03/22 19:16:22 bentson + * make sure CTS flow control is set as soon as possible (thanks + * to note from David Lambert ); + * + * Revision 1.36.1.1 1995/03/13 15:44:43 bentson + * initialize defaults for receive threshold and stale data timeout; + * cosmetic changes; + * + * Revision 1.36 1995/03/10 23:33:53 bentson + * added support of chips 4-7 in 32 port Cyclom-Ye; + * fix cy_interrupt pointer dereference problem + * (Joe Portman ); + * give better error response if open is attempted on non-existent port + * (Zachariah Vaum ); + * correct command timeout (Kenneth Lerman ); + * conditional compilation for -16Y on systems with fast, noisy bus; + * comment out diagnostic print function; + * cleaned up table of base addresses; + * set receiver time-out period register to correct value, + * set receive threshold to better default values, + * set chip timer to more accurate 200 Hz ticking, + * add code to monitor and modify receive parameters + * (Rik Faith Nick Simicich + * ); + * + * Revision 1.35 1994/12/16 13:54:18 steffen + * additional patch by Marcio Saito for board detection + * Accidently left out in 1.34 + * + * Revision 1.34 1994/12/10 12:37:12 steffen + * This is the corrected version as suggested by Marcio Saito + * + * Revision 1.33 1994/12/01 22:41:18 bentson + * add hooks to support more high speeds directly; add tytso + * patch regarding CLOCAL wakeups + * + * Revision 1.32 1994/11/23 19:50:04 bentson + * allow direct kernel control of higher signalling rates; + * look for cards at additional locations + * + * Revision 1.31 1994/11/16 04:33:28 bentson + * ANOTHER fix from Corey Minyard, minyard@wf-rch.cirr.com-- + * a problem in chars_in_buffer has been resolved by some + * small changes; this should yield smoother output + * + * Revision 1.30 1994/11/16 04:28:05 bentson + * Fix from Corey Minyard, Internet: minyard@metronet.com, + * UUCP: minyard@wf-rch.cirr.com, WORK: minyardbnr.ca, to + * cy_hangup that appears to clear up much (all?) of the + * DTR glitches; also he's added/cleaned-up diagnostic messages + * + * Revision 1.29 1994/11/16 04:16:07 bentson + * add change proposed by Ralph Sims, ralphs@halcyon.com, to + * operate higher speeds in same way as other serial ports; + * add more serial ports (for up to two 16-port muxes). + * + * Revision 1.28 1994/11/04 00:13:16 root + * turn off diagnostic messages + * + * Revision 1.27 1994/11/03 23:46:37 root + * bunch of changes to bring driver into greater conformance + * with the serial.c driver (looking for missed fixes) + * + * Revision 1.26 1994/11/03 22:40:36 root + * automatic interrupt probing fixed. + * + * Revision 1.25 1994/11/03 20:17:02 root + * start to implement auto-irq + * + * Revision 1.24 1994/11/03 18:01:55 root + * still working on modem signals--trying not to drop DTR + * during the getty/login processes + * + * Revision 1.23 1994/11/03 17:51:36 root + * extend baud rate support; set receive threshold as function + * of baud rate; fix some problems with RTS/CTS; + * + * Revision 1.22 1994/11/02 18:05:35 root + * changed arguments to udelay to type long to get + * delays to be of correct duration + * + * Revision 1.21 1994/11/02 17:37:30 root + * employ udelay (after calibrating loops_per_second earlier + * in init/main.c) instead of using home-grown delay routines + * + * Revision 1.20 1994/11/02 03:11:38 root + * cy_chars_in_buffer forces a return value of 0 to let + * login work (don't know why it does); some functions + * that were returning EFAULT, now executes the code; + * more work on deciding when to disable xmit interrupts; + * + * Revision 1.19 1994/11/01 20:10:14 root + * define routine to start transmission interrupts (by enabling + * transmit interrupts); directly enable/disable modem interrupts; + * + * Revision 1.18 1994/11/01 18:40:45 bentson + * Don't always enable transmit interrupts in startup; interrupt on + * TxMpty instead of TxRdy to help characters get out before shutdown; + * restructure xmit interrupt to check for chars first and quit if + * none are ready to go; modem status (MXVRx) is upright, _not_ inverted + * (to my view); + * + * Revision 1.17 1994/10/30 04:39:45 bentson + * rename serial_driver and callout_driver to cy_serial_driver and + * cy_callout_driver to avoid linkage interference; initialize + * info->type to PORT_CIRRUS; ruggedize paranoia test; elide ->port + * from cyclades_port structure; add paranoia check to cy_close; + * + * Revision 1.16 1994/10/30 01:14:33 bentson + * change major numbers; add some _early_ return statements; + * + * Revision 1.15 1994/10/29 06:43:15 bentson + * final tidying up for clean compile; enable some error reporting + * + * Revision 1.14 1994/10/28 20:30:22 Bentson + * lots of changes to drag the driver towards the new tty_io + * structures and operation. not expected to work, but may + * compile cleanly. + * + * Revision 1.13 1994/07/21 23:08:57 Bentson + * add some diagnostic cruft; support 24 lines (for testing + * both -8Y and -16Y cards; be more thorough in servicing all + * chips during interrupt; add "volatile" a few places to + * circumvent compiler optimizations; fix base & offset + * computations in block_til_ready (was causing chip 0 to + * stop operation) + * + * Revision 1.12 1994/07/19 16:42:11 Bentson + * add some hackery for kernel version 1.1.8; expand + * error messages; refine timing for delay loops and + * declare loop params volatile + * + * Revision 1.11 1994/06/11 21:53:10 bentson + * get use of save_car right in transmit interrupt service + * + * Revision 1.10.1.1 1994/06/11 21:31:18 bentson + * add some diagnostic printing; try to fix save_car stuff + * + * Revision 1.10 1994/06/11 20:36:08 bentson + * clean up compiler warnings + * + * Revision 1.9 1994/06/11 19:42:46 bentson + * added a bunch of code to support modem signalling + * + * Revision 1.8 1994/06/11 17:57:07 bentson + * recognize break & parity error + * + * Revision 1.7 1994/06/05 05:51:34 bentson + * Reorder baud table to be monotonic; add cli to CP; discard + * incoming characters and status if the line isn't open; start to + * fold code into cy_throttle; start to port get_serial_info, + * set_serial_info, get_modem_info, set_modem_info, and send_break + * from serial.c; expand cy_ioctl; relocate and expand config_setup; + * get flow control characters from tty struct; invalidate ports w/o + * hardware; + * + * Revision 1.6 1994/05/31 18:42:21 bentson + * add a loop-breaker in the interrupt service routine; + * note when port is initialized so that it can be shut + * down under the right conditions; receive works without + * any obvious errors + * + * Revision 1.5 1994/05/30 00:55:02 bentson + * transmit works without obvious errors + * + * Revision 1.4 1994/05/27 18:46:27 bentson + * incorporated more code from lib_y.c; can now print short + * strings under interrupt control to port zero; seems to + * select ports/channels/lines correctly + * + * Revision 1.3 1994/05/25 22:12:44 bentson + * shifting from multi-port on a card to proper multiplexor + * data structures; added skeletons of most routines + * + * Revision 1.2 1994/05/19 13:21:43 bentson + * start to crib from other sources + * + */ + +/* If you need to install more boards than NR_CARDS, change the constant + in the definition below. No other change is necessary to support up to + eight boards. Beyond that you'll have to extend cy_isa_addresses. */ + +#define NR_CARDS 4 + +/* + If the total number of ports is larger than NR_PORTS, change this + constant in the definition below. No other change is necessary to + support more boards/ports. */ + +#define NR_PORTS 256 + +#define ZE_V1_NPORTS 64 +#define ZO_V1 0 +#define ZO_V2 1 +#define ZE_V1 2 + +#define SERIAL_PARANOIA_CHECK +#undef CY_DEBUG_OPEN +#undef CY_DEBUG_THROTTLE +#undef CY_DEBUG_OTHER +#undef CY_DEBUG_IO +#undef CY_DEBUG_COUNT +#undef CY_DEBUG_DTR +#undef CY_DEBUG_WAIT_UNTIL_SENT +#undef CY_DEBUG_INTERRUPTS +#undef CY_16Y_HACK +#undef CY_ENABLE_MONITORING +#undef CY_PCI_DEBUG + +#if 0 +#define PAUSE __asm__("nop"); +#else +#define PAUSE ; +#endif + +/* + * Include section + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define CY_LOCK(info,flags) \ + do { \ + spin_lock_irqsave(&cy_card[info->card].card_lock, flags); \ + } while (0) + +#define CY_UNLOCK(info,flags) \ + do { \ + spin_unlock_irqrestore(&cy_card[info->card].card_lock, flags); \ + } while (0) + +#include +#include +#include + +#include +#include + +static void cy_throttle (struct tty_struct *tty); +static void cy_send_xchar (struct tty_struct *tty, char ch); + +#define IS_CYC_Z(card) ((card).num_chips == -1) + +#define Z_FPGA_CHECK(card) \ + ((cy_readl(&((struct RUNTIME_9060 __iomem *) \ + ((card).ctl_addr))->init_ctrl) & (1<<17)) != 0) + +#define ISZLOADED(card) (((ZO_V1==cy_readl(&((struct RUNTIME_9060 __iomem *) \ + ((card).ctl_addr))->mail_box_0)) || \ + Z_FPGA_CHECK(card)) && \ + (ZFIRM_ID==cy_readl(&((struct FIRM_ID __iomem *) \ + ((card).base_addr+ID_ADDRESS))->signature))) + +#ifndef SERIAL_XMIT_SIZE +#define SERIAL_XMIT_SIZE (min(PAGE_SIZE, 4096)) +#endif +#define WAKEUP_CHARS 256 + +#define STD_COM_FLAGS (0) + +#define JIFFIES_DIFF(n, j) ((j) - (n)) + +static struct tty_driver *cy_serial_driver; + +#ifdef CONFIG_ISA +/* This is the address lookup table. The driver will probe for + Cyclom-Y/ISA boards at all addresses in here. If you want the + driver to probe addresses at a different address, add it to + this table. If the driver is probing some other board and + causing problems, remove the offending address from this table. + The cy_setup function extracts additional addresses from the + boot options line. The form is "cyclades=address,address..." +*/ + +static unsigned int cy_isa_addresses[] = { + 0xD0000, + 0xD2000, + 0xD4000, + 0xD6000, + 0xD8000, + 0xDA000, + 0xDC000, + 0xDE000, + 0,0,0,0,0,0,0,0 +}; +#define NR_ISA_ADDRS (sizeof(cy_isa_addresses)/sizeof(unsigned char*)) + +#ifdef MODULE +static long maddr[NR_CARDS] = { 0, }; +static int irq[NR_CARDS] = { 0, }; + +module_param_array(maddr, long, NULL, 0); +module_param_array(irq, int, NULL, 0); +#endif + +#endif /* CONFIG_ISA */ + +/* This is the per-card data structure containing address, irq, number of + channels, etc. This driver supports a maximum of NR_CARDS cards. +*/ +static struct cyclades_card cy_card[NR_CARDS]; + +/* This is the per-channel data structure containing pointers, flags + and variables for the port. This driver supports a maximum of NR_PORTS. +*/ +static struct cyclades_port cy_port[NR_PORTS]; + +static int cy_next_channel; /* next minor available */ + +/* + * tmp_buf is used as a temporary buffer by serial_write. We need to + * lock it in case the copy_from_user blocks while swapping in a page, + * and some other program tries to do a serial write at the same time. + * Since the lock will only come under contention when the system is + * swapping and available memory is low, it makes sense to share one + * buffer across all the serial ports, since it significantly saves + * memory if large numbers of serial ports are open. This buffer is + * allocated when the first cy_open occurs. + */ +static unsigned char *tmp_buf; + +/* + * This is used to look up the divisor speeds and the timeouts + * We're normally limited to 15 distinct baud rates. The extra + * are accessed via settings in info->flags. + * 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, + * 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, + * HI VHI + * 20 + */ +static int baud_table[] = { + 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, + 1800, 2400, 4800, 9600, 19200, 38400, 57600, 76800,115200,150000, + 230400, 0}; + +static char baud_co_25[] = { /* 25 MHz clock option table */ + /* value => 00 01 02 03 04 */ + /* divide by 8 32 128 512 2048 */ + 0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, + 0x02, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + +static char baud_bpr_25[] = { /* 25 MHz baud rate period table */ + 0x00, 0xf5, 0xa3, 0x6f, 0x5c, 0x51, 0xf5, 0xa3, 0x51, 0xa3, + 0x6d, 0x51, 0xa3, 0x51, 0xa3, 0x51, 0x36, 0x29, 0x1b, 0x15}; + +static char baud_co_60[] = { /* 60 MHz clock option table (CD1400 J) */ + /* value => 00 01 02 03 04 */ + /* divide by 8 32 128 512 2048 */ + 0x00, 0x00, 0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x03, 0x03, + 0x03, 0x02, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}; + +static char baud_bpr_60[] = { /* 60 MHz baud rate period table (CD1400 J) */ + 0x00, 0x82, 0x21, 0xff, 0xdb, 0xc3, 0x92, 0x62, 0xc3, 0x62, + 0x41, 0xc3, 0x62, 0xc3, 0x62, 0xc3, 0x82, 0x62, 0x41, 0x32, + 0x21}; + +static char baud_cor3[] = { /* receive threshold */ + 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, + 0x0a, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x08, 0x08, 0x07, + 0x07}; + +/* + * The Cyclades driver implements HW flow control as any serial driver. + * The cyclades_port structure member rflow and the vector rflow_thr + * allows us to take advantage of a special feature in the CD1400 to avoid + * data loss even when the system interrupt latency is too high. These flags + * are to be used only with very special applications. Setting these flags + * requires the use of a special cable (DTR and RTS reversed). In the new + * CD1400-based boards (rev. 6.00 or later), there is no need for special + * cables. + */ + +static char rflow_thr[] = { /* rflow threshold */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, + 0x0a}; + +/* The Cyclom-Ye has placed the sequential chips in non-sequential + * address order. This look-up table overcomes that problem. + */ +static int cy_chip_offset [] = + { 0x0000, + 0x0400, + 0x0800, + 0x0C00, + 0x0200, + 0x0600, + 0x0A00, + 0x0E00 + }; + +/* PCI related definitions */ + +static unsigned short cy_pci_nboard; +static unsigned short cy_isa_nboard; +static unsigned short cy_nboard; +#ifdef CONFIG_PCI +static unsigned short cy_pci_dev_id[] = { + PCI_DEVICE_ID_CYCLOM_Y_Lo, /* PCI < 1Mb */ + PCI_DEVICE_ID_CYCLOM_Y_Hi, /* PCI > 1Mb */ + PCI_DEVICE_ID_CYCLOM_4Y_Lo, /* 4Y PCI < 1Mb */ + PCI_DEVICE_ID_CYCLOM_4Y_Hi, /* 4Y PCI > 1Mb */ + PCI_DEVICE_ID_CYCLOM_8Y_Lo, /* 8Y PCI < 1Mb */ + PCI_DEVICE_ID_CYCLOM_8Y_Hi, /* 8Y PCI > 1Mb */ + PCI_DEVICE_ID_CYCLOM_Z_Lo, /* Z PCI < 1Mb */ + PCI_DEVICE_ID_CYCLOM_Z_Hi, /* Z PCI > 1Mb */ + 0 /* end of table */ + }; +#endif + +static void cy_start(struct tty_struct *); +static void set_line_char(struct cyclades_port *); +static int cyz_issue_cmd(struct cyclades_card *, uclong, ucchar, uclong); +#ifdef CONFIG_ISA +static unsigned detect_isa_irq(void __iomem *); +#endif /* CONFIG_ISA */ + +static int cyclades_get_proc_info(char *, char **, off_t , int , int *, void *); + +#ifndef CONFIG_CYZ_INTR +static void cyz_poll(unsigned long); + +/* The Cyclades-Z polling cycle is defined by this variable */ +static long cyz_polling_cycle = CZ_DEF_POLL; + +static int cyz_timeron = 0; +static struct timer_list cyz_timerlist = TIMER_INITIALIZER(cyz_poll, 0, 0); + +#else /* CONFIG_CYZ_INTR */ +static void cyz_rx_restart(unsigned long); +static struct timer_list cyz_rx_full_timer[NR_PORTS]; +#endif /* CONFIG_CYZ_INTR */ + +static inline int +serial_paranoia_check(struct cyclades_port *info, + char *name, const char *routine) +{ +#ifdef SERIAL_PARANOIA_CHECK + static const char *badmagic = + "cyc Warning: bad magic number for serial struct (%s) in %s\n"; + static const char *badinfo = + "cyc Warning: null cyclades_port for (%s) in %s\n"; + static const char *badrange = + "cyc Warning: cyclades_port out of range for (%s) in %s\n"; + + if (!info) { + printk(badinfo, name, routine); + return 1; + } + + if( (long)info < (long)(&cy_port[0]) + || (long)(&cy_port[NR_PORTS]) < (long)info ){ + printk(badrange, name, routine); + return 1; + } + + if (info->magic != CYCLADES_MAGIC) { + printk(badmagic, name, routine); + return 1; + } +#endif + return 0; +} /* serial_paranoia_check */ + +/* + * This routine is used by the interrupt handler to schedule + * processing in the software interrupt portion of the driver + * (also known as the "bottom half"). This can be called any + * number of times for any channel without harm. + */ +static inline void +cy_sched_event(struct cyclades_port *info, int event) +{ + info->event |= 1 << event; /* remember what kind of event and who */ + schedule_work(&info->tqueue); +} /* cy_sched_event */ + + +/* + * This routine is used to handle the "bottom half" processing for the + * serial driver, known also the "software interrupt" processing. + * This processing is done at the kernel interrupt level, after the + * cy#/_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This + * is where time-consuming activities which can not be done in the + * interrupt driver proper are done; the interrupt driver schedules + * them using cy_sched_event(), and they get done here. + * + * This is done through one level of indirection--the task queue. + * When a hardware interrupt service routine wants service by the + * driver's bottom half, it enqueues the appropriate tq_struct (one + * per port) to the keventd work queue and sets a request flag + * that the work queue be processed. + * + * Although this may seem unwieldy, it gives the system a way to + * pass an argument (in this case the pointer to the cyclades_port + * structure) to the bottom half of the driver. Previous kernels + * had to poll every port to see if that port needed servicing. + */ +static void +do_softint(void *private_) +{ + struct cyclades_port *info = (struct cyclades_port *) private_; + struct tty_struct *tty; + + tty = info->tty; + if (!tty) + return; + + if (test_and_clear_bit(Cy_EVENT_HANGUP, &info->event)) { + tty_hangup(info->tty); + wake_up_interruptible(&info->open_wait); + info->flags &= ~ASYNC_NORMAL_ACTIVE; + } + if (test_and_clear_bit(Cy_EVENT_OPEN_WAKEUP, &info->event)) { + wake_up_interruptible(&info->open_wait); + } +#ifdef CONFIG_CYZ_INTR + if (test_and_clear_bit(Cy_EVENT_Z_RX_FULL, &info->event)) { + if (cyz_rx_full_timer[info->line].function == NULL) { + cyz_rx_full_timer[info->line].expires = jiffies + 1; + cyz_rx_full_timer[info->line].function = cyz_rx_restart; + cyz_rx_full_timer[info->line].data = (unsigned long)info; + add_timer(&cyz_rx_full_timer[info->line]); + } + } +#endif + if (test_and_clear_bit(Cy_EVENT_DELTA_WAKEUP, &info->event)) { + wake_up_interruptible(&info->delta_msr_wait); + } + if (test_and_clear_bit(Cy_EVENT_WRITE_WAKEUP, &info->event)) { + tty_wakeup(tty); + wake_up_interruptible(&tty->write_wait); + } +#ifdef Z_WAKE + if (test_and_clear_bit(Cy_EVENT_SHUTDOWN_WAKEUP, &info->event)) { + wake_up_interruptible(&info->shutdown_wait); + } +#endif +} /* do_softint */ + + +/***********************************************************/ +/********* Start of block of Cyclom-Y specific code ********/ + +/* This routine waits up to 1000 micro-seconds for the previous + command to the Cirrus chip to complete and then issues the + new command. An error is returned if the previous command + didn't finish within the time limit. + + This function is only called from inside spinlock-protected code. + */ +static int +cyy_issue_cmd(void __iomem *base_addr, u_char cmd, int index) +{ + volatile int i; + + /* Check to see that the previous command has completed */ + for(i = 0 ; i < 100 ; i++){ + if (cy_readb(base_addr+(CyCCR< 0)? irq : 0; +} +#endif /* CONFIG_ISA */ + +/* The real interrupt service routine is called + whenever the card wants its hand held--chars + received, out buffer empty, modem change, etc. + */ +static irqreturn_t +cyy_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + struct tty_struct *tty; + int status; + struct cyclades_card *cinfo; + struct cyclades_port *info; + void __iomem *base_addr, *card_base_addr; + int chip; + int save_xir, channel, save_car; + char data; + volatile int char_count; + int outch; + int i,j,index; + int too_many; + int had_work; + int mdm_change; + int mdm_status; + + if((cinfo = (struct cyclades_card *)dev_id) == 0){ +#ifdef CY_DEBUG_INTERRUPTS + printk("cyy_interrupt: spurious interrupt %d\n\r", irq); +#endif + return IRQ_NONE; /* spurious interrupt */ + } + + card_base_addr = cinfo->base_addr; + index = cinfo->bus_index; + + + /* This loop checks all chips in the card. Make a note whenever + _any_ chip had some work to do, as this is considered an + indication that there will be more to do. Only when no chip + has any work does this outermost loop exit. + */ + do{ + had_work = 0; + for ( chip = 0 ; chip < cinfo->num_chips ; chip ++) { + base_addr = cinfo->base_addr + (cy_chip_offset[chip]<card_lock); + save_xir = (u_char) cy_readb(base_addr+(CyRIR<first_line; + info = &cy_port[i]; + info->last_active = jiffies; + save_car = cy_readb(base_addr+(CyCAR<tty == 0){ + j = (cy_readb(base_addr+(CyRIVR<tty; + j = (cy_readb(base_addr+(CyRIVR<icount.brk++; + else if(data & CyFRAME) + info->icount.frame++; + else if(data & CyPARITY) + info->icount.parity++; + else if(data & CyOVERRUN) + info->icount.overrun++; + + if(data & info->ignore_status_mask){ + info->icount.rx++; + continue; + } + if (tty->flip.count < TTY_FLIPBUF_SIZE){ + tty->flip.count++; + if (data & info->read_status_mask){ + if(data & CyBREAK){ + *tty->flip.flag_buf_ptr++ = + TTY_BREAK; + *tty->flip.char_buf_ptr++ = + cy_readb(base_addr+(CyRDSR<icount.rx++; + if (info->flags & ASYNC_SAK){ + do_SAK(tty); + } + }else if(data & CyFRAME){ + *tty->flip.flag_buf_ptr++ = + TTY_FRAME; + *tty->flip.char_buf_ptr++ = + cy_readb(base_addr+(CyRDSR<icount.rx++; + info->idle_stats.frame_errs++; + }else if(data & CyPARITY){ + *tty->flip.flag_buf_ptr++ = + TTY_PARITY; + *tty->flip.char_buf_ptr++ = + cy_readb(base_addr+(CyRDSR<icount.rx++; + info->idle_stats.parity_errs++; + }else if(data & CyOVERRUN){ + *tty->flip.flag_buf_ptr++ = + TTY_OVERRUN; + *tty->flip.char_buf_ptr++ = 0; + info->icount.rx++; + /* If the flip buffer itself is + overflowing, we still lose + the next incoming character. + */ + if(tty->flip.count + < TTY_FLIPBUF_SIZE){ + tty->flip.count++; + *tty->flip.flag_buf_ptr++ = + TTY_NORMAL; + *tty->flip.char_buf_ptr++ = + cy_readb(base_addr+(CyRDSR<icount.rx++; + } + info->idle_stats.overruns++; + /* These two conditions may imply */ + /* a normal read should be done. */ + /* }else if(data & CyTIMEOUT){ */ + /* }else if(data & CySPECHAR){ */ + }else{ + *tty->flip.flag_buf_ptr++ = 0; + *tty->flip.char_buf_ptr++ = 0; + info->icount.rx++; + } + }else{ + *tty->flip.flag_buf_ptr++ = 0; + *tty->flip.char_buf_ptr++ = 0; + info->icount.rx++; + } + }else{ + /* there was a software buffer + overrun and nothing could be + done about it!!! */ + info->icount.buf_overrun++; + info->idle_stats.overruns++; + } + } else { /* normal character reception */ + /* load # chars available from the chip */ + char_count = cy_readb(base_addr+(CyRDCR<mon.int_count; + info->mon.char_count += char_count; + if (char_count > info->mon.char_max) + info->mon.char_max = char_count; + info->mon.char_last = char_count; +#endif + while(char_count--){ + if (tty->flip.count >= TTY_FLIPBUF_SIZE){ + break; + } + tty->flip.count++; + data = cy_readb(base_addr+(CyRDSR<flip.flag_buf_ptr++ = TTY_NORMAL; + *tty->flip.char_buf_ptr++ = data; + info->idle_stats.recv_bytes++; + info->icount.rx++; +#ifdef CY_16Y_HACK + udelay(10L); +#endif + } + info->idle_stats.recv_idle = jiffies; + } + schedule_delayed_work(&tty->flip.work, 1); + } + /* end of service */ + cy_writeb(base_addr+(CyRIR<card_lock); + } + + + if (status & CySRTransmit) { /* transmission interrupt */ + /* Since we only get here when the transmit buffer + is empty, we know we can always stuff a dozen + characters. */ +#ifdef CY_DEBUG_INTERRUPTS + printk("cyy_interrupt: xmit intr, chip %d\n\r", chip); +#endif + + /* determine the channel & change to that context */ + spin_lock(&cinfo->card_lock); + save_xir = (u_char) cy_readb(base_addr+(CyTIR<first_line; + save_car = cy_readb(base_addr+(CyCAR<last_active = jiffies; + if(info->tty == 0){ + cy_writeb(base_addr+(CySRER<xmit_fifo_size; + + if(info->x_char) { /* send special char */ + outch = info->x_char; + cy_writeb(base_addr+(CyTDR<icount.tx++; + info->x_char = 0; + } + + if (info->breakon || info->breakoff) { + if (info->breakon) { + cy_writeb(base_addr + (CyTDR<breakon = 0; + char_count -= 2; + } + if (info->breakoff) { + cy_writeb(base_addr + (CyTDR<breakoff = 0; + char_count -= 2; + } + } + + while (char_count-- > 0){ + if (!info->xmit_cnt){ + if (cy_readb(base_addr+(CySRER<xmit_buf == 0){ + cy_writeb(base_addr+(CySRER<tty->stopped || info->tty->hw_stopped){ + cy_writeb(base_addr+(CySRER<xmit_buf[info->xmit_tail]; + if( outch ){ + info->xmit_cnt--; + info->xmit_tail = (info->xmit_tail + 1) + & (SERIAL_XMIT_SIZE - 1); + cy_writeb(base_addr+(CyTDR<icount.tx++; + }else{ + if(char_count > 1){ + info->xmit_cnt--; + info->xmit_tail = (info->xmit_tail + 1) + & (SERIAL_XMIT_SIZE - 1); + cy_writeb(base_addr+(CyTDR<icount.tx++; + char_count--; + }else{ + } + } + } + + txdone: + if (info->xmit_cnt < WAKEUP_CHARS) { + cy_sched_event(info, Cy_EVENT_WRITE_WAKEUP); + } + txend: + /* end of service */ + cy_writeb(base_addr+(CyTIR<card_lock); + } + + if (status & CySRModem) { /* modem interrupt */ + + /* determine the channel & change to that context */ + spin_lock(&cinfo->card_lock); + save_xir = (u_char) cy_readb(base_addr+(CyMIR<first_line]; + info->last_active = jiffies; + save_car = cy_readb(base_addr+(CyCAR<tty == 0){/* no place for data, ignore it*/ + ; + }else{ + if (mdm_change & CyANY_DELTA) { + /* For statistics only */ + if (mdm_change & CyDCD) info->icount.dcd++; + if (mdm_change & CyCTS) info->icount.cts++; + if (mdm_change & CyDSR) info->icount.dsr++; + if (mdm_change & CyRI) info->icount.rng++; + + cy_sched_event(info, Cy_EVENT_DELTA_WAKEUP); + } + + if((mdm_change & CyDCD) + && (info->flags & ASYNC_CHECK_CD)){ + if(mdm_status & CyDCD){ + cy_sched_event(info, + Cy_EVENT_OPEN_WAKEUP); + }else{ + cy_sched_event(info, + Cy_EVENT_HANGUP); + } + } + if((mdm_change & CyCTS) + && (info->flags & ASYNC_CTS_FLOW)){ + if(info->tty->hw_stopped){ + if(mdm_status & CyCTS){ + /* cy_start isn't used + because... !!! */ + info->tty->hw_stopped = 0; + cy_writeb(base_addr+(CySRER<tty->hw_stopped = 1; + cy_writeb(base_addr+(CySRER<card_lock); + } + } /* end while status != 0 */ + } /* end loop for chips... */ + } while(had_work); + + /* clear interrupts */ + spin_lock(&cinfo->card_lock); + cy_writeb(card_base_addr + (Cy_ClrIntr<card_lock); + return IRQ_HANDLED; +} /* cyy_interrupt */ + +/***********************************************************/ +/********* End of block of Cyclom-Y specific code **********/ +/******** Start of block of Cyclades-Z specific code *********/ +/***********************************************************/ + +static int +cyz_fetch_msg( struct cyclades_card *cinfo, + uclong *channel, ucchar *cmd, uclong *param) +{ + struct FIRM_ID __iomem *firm_id; + struct ZFW_CTRL __iomem *zfw_ctrl; + struct BOARD_CTRL __iomem *board_ctrl; + unsigned long loc_doorbell; + + firm_id = cinfo->base_addr + ID_ADDRESS; + if (!ISZLOADED(*cinfo)){ + return (-1); + } + zfw_ctrl = cinfo->base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); + board_ctrl = &zfw_ctrl->board_ctrl; + + loc_doorbell = cy_readl(&((struct RUNTIME_9060 __iomem *) + (cinfo->ctl_addr))->loc_doorbell); + if (loc_doorbell){ + *cmd = (char)(0xff & loc_doorbell); + *channel = cy_readl(&board_ctrl->fwcmd_channel); + *param = (uclong)cy_readl(&board_ctrl->fwcmd_param); + cy_writel(&((struct RUNTIME_9060 __iomem *)(cinfo->ctl_addr))->loc_doorbell, + 0xffffffff); + return 1; + } + return 0; +} /* cyz_fetch_msg */ + +static int +cyz_issue_cmd( struct cyclades_card *cinfo, + uclong channel, ucchar cmd, uclong param) +{ + struct FIRM_ID __iomem *firm_id; + struct ZFW_CTRL __iomem *zfw_ctrl; + struct BOARD_CTRL __iomem *board_ctrl; + unsigned long __iomem *pci_doorbell; + int index; + + firm_id = cinfo->base_addr + ID_ADDRESS; + if (!ISZLOADED(*cinfo)){ + return (-1); + } + zfw_ctrl = cinfo->base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); + board_ctrl = &zfw_ctrl->board_ctrl; + + index = 0; + pci_doorbell = &((struct RUNTIME_9060 __iomem *) (cinfo->ctl_addr))->pci_doorbell; + while( (cy_readl(pci_doorbell) & 0xff) != 0){ + if (index++ == 1000){ + return((int)(cy_readl(pci_doorbell) & 0xff)); + } + udelay(50L); + } + cy_writel(&board_ctrl->hcmd_channel, channel); + cy_writel(&board_ctrl->hcmd_param , param); + cy_writel(pci_doorbell, (long)cmd); + + return(0); +} /* cyz_issue_cmd */ + +static void +cyz_handle_rx(struct cyclades_port *info, + volatile struct CH_CTRL __iomem *ch_ctrl, + volatile struct BUF_CTRL __iomem *buf_ctrl) +{ + struct cyclades_card *cinfo = &cy_card[info->card]; + struct tty_struct *tty = info->tty; + volatile int char_count; +#ifdef BLOCKMOVE + int small_count; +#else + char data; +#endif + volatile uclong rx_put, rx_get, new_rx_get, rx_bufsize, rx_bufaddr; + + rx_get = new_rx_get = cy_readl(&buf_ctrl->rx_get); + rx_put = cy_readl(&buf_ctrl->rx_put); + rx_bufsize = cy_readl(&buf_ctrl->rx_bufsize); + rx_bufaddr = cy_readl(&buf_ctrl->rx_bufaddr); + if (rx_put >= rx_get) + char_count = rx_put - rx_get; + else + char_count = rx_put - rx_get + rx_bufsize; + + if ( char_count ) { + info->last_active = jiffies; + info->jiffies[1] = jiffies; + +#ifdef CY_ENABLE_MONITORING + info->mon.int_count++; + info->mon.char_count += char_count; + if (char_count > info->mon.char_max) + info->mon.char_max = char_count; + info->mon.char_last = char_count; +#endif + if(tty == 0){ + /* flush received characters */ + new_rx_get = (new_rx_get + char_count) & (rx_bufsize - 1); + info->rflush_count++; + }else{ +#ifdef BLOCKMOVE + /* we'd like to use memcpy(t, f, n) and memset(s, c, count) + for performance, but because of buffer boundaries, there + may be several steps to the operation */ + while(0 < (small_count = + min_t(unsigned int, (rx_bufsize - new_rx_get), + min_t(unsigned int, (TTY_FLIPBUF_SIZE - tty->flip.count), char_count)) + )) { + memcpy_fromio(tty->flip.char_buf_ptr, + (char *)(cinfo->base_addr + + rx_bufaddr + new_rx_get), + small_count); + + tty->flip.char_buf_ptr += small_count; + memset(tty->flip.flag_buf_ptr, TTY_NORMAL, small_count); + tty->flip.flag_buf_ptr += small_count; + new_rx_get = (new_rx_get + small_count) & (rx_bufsize - 1); + char_count -= small_count; + info->icount.rx += small_count; + info->idle_stats.recv_bytes += small_count; + tty->flip.count += small_count; + } +#else + while(char_count--){ + if (tty->flip.count >= N_TTY_BUF_SIZE - tty->read_cnt) + break; + + if (tty->flip.count >= TTY_FLIPBUF_SIZE) + break; + + data = cy_readb(cinfo->base_addr + rx_bufaddr + new_rx_get); + new_rx_get = (new_rx_get + 1) & (rx_bufsize - 1); + tty->flip.count++; + *tty->flip.flag_buf_ptr++ = TTY_NORMAL; + *tty->flip.char_buf_ptr++ = data; + info->idle_stats.recv_bytes++; + info->icount.rx++; + } +#endif +#ifdef CONFIG_CYZ_INTR + /* Recalculate the number of chars in the RX buffer and issue + a cmd in case it's higher than the RX high water mark */ + rx_put = cy_readl(&buf_ctrl->rx_put); + if (rx_put >= rx_get) + char_count = rx_put - rx_get; + else + char_count = rx_put - rx_get + rx_bufsize; + if(char_count >= cy_readl(&buf_ctrl->rx_threshold)) { + cy_sched_event(info, Cy_EVENT_Z_RX_FULL); + } +#endif + info->idle_stats.recv_idle = jiffies; + schedule_delayed_work(&tty->flip.work, 1); + } + /* Update rx_get */ + cy_writel(&buf_ctrl->rx_get, new_rx_get); + } +} + +static void +cyz_handle_tx(struct cyclades_port *info, + volatile struct CH_CTRL __iomem *ch_ctrl, + volatile struct BUF_CTRL __iomem *buf_ctrl) +{ + struct cyclades_card *cinfo = &cy_card[info->card]; + struct tty_struct *tty = info->tty; + char data; + volatile int char_count; +#ifdef BLOCKMOVE + int small_count; +#endif + volatile uclong tx_put, tx_get, tx_bufsize, tx_bufaddr; + + if (info->xmit_cnt <= 0) /* Nothing to transmit */ + return; + + tx_get = cy_readl(&buf_ctrl->tx_get); + tx_put = cy_readl(&buf_ctrl->tx_put); + tx_bufsize = cy_readl(&buf_ctrl->tx_bufsize); + tx_bufaddr = cy_readl(&buf_ctrl->tx_bufaddr); + if (tx_put >= tx_get) + char_count = tx_get - tx_put - 1 + tx_bufsize; + else + char_count = tx_get - tx_put - 1; + + if ( char_count ) { + + if( tty == 0 ){ + goto ztxdone; + } + + if(info->x_char) { /* send special char */ + data = info->x_char; + + cy_writeb((cinfo->base_addr + tx_bufaddr + tx_put), data); + tx_put = (tx_put + 1) & (tx_bufsize - 1); + info->x_char = 0; + char_count--; + info->icount.tx++; + info->last_active = jiffies; + info->jiffies[2] = jiffies; + } +#ifdef BLOCKMOVE + while(0 < (small_count = + min_t(unsigned int, (tx_bufsize - tx_put), + min_t(unsigned int, (SERIAL_XMIT_SIZE - info->xmit_tail), + min_t(unsigned int, info->xmit_cnt, char_count))))) { + + memcpy_toio((char *)(cinfo->base_addr + tx_bufaddr + tx_put), + &info->xmit_buf[info->xmit_tail], + small_count); + + tx_put = (tx_put + small_count) & (tx_bufsize - 1); + char_count -= small_count; + info->icount.tx += small_count; + info->xmit_cnt -= small_count; + info->xmit_tail = + (info->xmit_tail + small_count) & (SERIAL_XMIT_SIZE - 1); + info->last_active = jiffies; + info->jiffies[2] = jiffies; + } +#else + while (info->xmit_cnt && char_count){ + data = info->xmit_buf[info->xmit_tail]; + info->xmit_cnt--; + info->xmit_tail = (info->xmit_tail + 1) & (SERIAL_XMIT_SIZE - 1); + + cy_writeb(cinfo->base_addr + tx_bufaddr + tx_put, data); + tx_put = (tx_put + 1) & (tx_bufsize - 1); + char_count--; + info->icount.tx++; + info->last_active = jiffies; + info->jiffies[2] = jiffies; + } +#endif + ztxdone: + if (info->xmit_cnt < WAKEUP_CHARS) { + cy_sched_event(info, Cy_EVENT_WRITE_WAKEUP); + } + /* Update tx_put */ + cy_writel(&buf_ctrl->tx_put, tx_put); + } +} + +static void +cyz_handle_cmd(struct cyclades_card *cinfo) +{ + struct tty_struct *tty; + struct cyclades_port *info; + static volatile struct FIRM_ID __iomem *firm_id; + static volatile struct ZFW_CTRL __iomem *zfw_ctrl; + static volatile struct BOARD_CTRL __iomem *board_ctrl; + static volatile struct CH_CTRL __iomem *ch_ctrl; + static volatile struct BUF_CTRL __iomem *buf_ctrl; + uclong channel; + ucchar cmd; + uclong param; + uclong hw_ver, fw_ver; + int special_count; + int delta_count; + + firm_id = cinfo->base_addr + ID_ADDRESS; + zfw_ctrl = cinfo->base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); + board_ctrl = &zfw_ctrl->board_ctrl; + fw_ver = cy_readl(&board_ctrl->fw_version); + hw_ver = cy_readl(&((struct RUNTIME_9060 __iomem *)(cinfo->ctl_addr))->mail_box_0); + + + while(cyz_fetch_msg(cinfo, &channel, &cmd, ¶m) == 1) { + special_count = 0; + delta_count = 0; + info = &cy_port[channel + cinfo->first_line]; + if((tty = info->tty) == 0) { + continue; + } + ch_ctrl = &(zfw_ctrl->ch_ctrl[channel]); + buf_ctrl = &(zfw_ctrl->buf_ctrl[channel]); + + switch(cmd) { + case C_CM_PR_ERROR: + tty->flip.count++; + *tty->flip.flag_buf_ptr++ = TTY_PARITY; + *tty->flip.char_buf_ptr++ = 0; + info->icount.rx++; + special_count++; + break; + case C_CM_FR_ERROR: + tty->flip.count++; + *tty->flip.flag_buf_ptr++ = TTY_FRAME; + *tty->flip.char_buf_ptr++ = 0; + info->icount.rx++; + special_count++; + break; + case C_CM_RXBRK: + tty->flip.count++; + *tty->flip.flag_buf_ptr++ = TTY_BREAK; + *tty->flip.char_buf_ptr++ = 0; + info->icount.rx++; + special_count++; + break; + case C_CM_MDCD: + info->icount.dcd++; + delta_count++; + if (info->flags & ASYNC_CHECK_CD){ + if ((fw_ver > 241 ? + ((u_long)param) : + cy_readl(&ch_ctrl->rs_status)) & C_RS_DCD) { + cy_sched_event(info, Cy_EVENT_OPEN_WAKEUP); + }else{ + cy_sched_event(info, Cy_EVENT_HANGUP); + } + } + break; + case C_CM_MCTS: + info->icount.cts++; + delta_count++; + break; + case C_CM_MRI: + info->icount.rng++; + delta_count++; + break; + case C_CM_MDSR: + info->icount.dsr++; + delta_count++; + break; +#ifdef Z_WAKE + case C_CM_IOCTLW: + cy_sched_event(info, Cy_EVENT_SHUTDOWN_WAKEUP); + break; +#endif +#ifdef CONFIG_CYZ_INTR + case C_CM_RXHIWM: + case C_CM_RXNNDT: + case C_CM_INTBACK2: + /* Reception Interrupt */ +#ifdef CY_DEBUG_INTERRUPTS + printk("cyz_interrupt: rcvd intr, card %d, port %ld\n\r", + info->card, channel); +#endif + cyz_handle_rx(info, ch_ctrl, buf_ctrl); + break; + case C_CM_TXBEMPTY: + case C_CM_TXLOWWM: + case C_CM_INTBACK: + /* Transmission Interrupt */ +#ifdef CY_DEBUG_INTERRUPTS + printk("cyz_interrupt: xmit intr, card %d, port %ld\n\r", + info->card, channel); +#endif + cyz_handle_tx(info, ch_ctrl, buf_ctrl); + break; +#endif /* CONFIG_CYZ_INTR */ + case C_CM_FATAL: + /* should do something with this !!! */ + break; + default: + break; + } + if(delta_count) + cy_sched_event(info, Cy_EVENT_DELTA_WAKEUP); + if(special_count) + schedule_delayed_work(&tty->flip.work, 1); + } +} + +#ifdef CONFIG_CYZ_INTR +static irqreturn_t +cyz_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + struct cyclades_card *cinfo; + + if((cinfo = (struct cyclades_card *)dev_id) == 0){ +#ifdef CY_DEBUG_INTERRUPTS + printk("cyz_interrupt: spurious interrupt %d\n\r", irq); +#endif + return IRQ_NONE; /* spurious interrupt */ + } + + if (!ISZLOADED(*cinfo)) { +#ifdef CY_DEBUG_INTERRUPTS + printk("cyz_interrupt: board not yet loaded (IRQ%d).\n\r", irq); +#endif + return IRQ_NONE; + } + + /* Handle the interrupts */ + cyz_handle_cmd(cinfo); + + return IRQ_HANDLED; +} /* cyz_interrupt */ + +static void +cyz_rx_restart(unsigned long arg) +{ + struct cyclades_port *info = (struct cyclades_port *)arg; + int retval; + int card = info->card; + uclong channel = (info->line) - (cy_card[card].first_line); + unsigned long flags; + + CY_LOCK(info, flags); + retval = cyz_issue_cmd(&cy_card[card], channel, C_CM_INTBACK2, 0L); + if (retval != 0){ + printk("cyc:cyz_rx_restart retval on ttyC%d was %x\n", + info->line, retval); + } + cyz_rx_full_timer[info->line].function = NULL; + CY_UNLOCK(info, flags); +} + +#else /* CONFIG_CYZ_INTR */ + +static void +cyz_poll(unsigned long arg) +{ + struct cyclades_card *cinfo; + struct cyclades_port *info; + struct tty_struct *tty; + static volatile struct FIRM_ID *firm_id; + static volatile struct ZFW_CTRL *zfw_ctrl; + static volatile struct BOARD_CTRL *board_ctrl; + static volatile struct CH_CTRL *ch_ctrl; + static volatile struct BUF_CTRL *buf_ctrl; + int card, port; + + cyz_timerlist.expires = jiffies + (HZ); + for (card = 0 ; card < NR_CARDS ; card++){ + cinfo = &cy_card[card]; + + if (!IS_CYC_Z(*cinfo)) continue; + if (!ISZLOADED(*cinfo)) continue; + + firm_id = cinfo->base_addr + ID_ADDRESS; + zfw_ctrl = cinfo->base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); + board_ctrl = &(zfw_ctrl->board_ctrl); + + /* Skip first polling cycle to avoid racing conditions with the FW */ + if (!cinfo->intr_enabled) { + cinfo->nports = (int) cy_readl(&board_ctrl->n_channel); + cinfo->intr_enabled = 1; + continue; + } + + cyz_handle_cmd(cinfo); + + for (port = 0 ; port < cinfo->nports ; port++) { + info = &cy_port[ port + cinfo->first_line ]; + tty = info->tty; + ch_ctrl = &(zfw_ctrl->ch_ctrl[port]); + buf_ctrl = &(zfw_ctrl->buf_ctrl[port]); + + if (!info->throttle) + cyz_handle_rx(info, ch_ctrl, buf_ctrl); + cyz_handle_tx(info, ch_ctrl, buf_ctrl); + } + /* poll every 'cyz_polling_cycle' period */ + cyz_timerlist.expires = jiffies + cyz_polling_cycle; + } + add_timer(&cyz_timerlist); + + return; +} /* cyz_poll */ + +#endif /* CONFIG_CYZ_INTR */ + +/********** End of block of Cyclades-Z specific code *********/ +/***********************************************************/ + + +/* This is called whenever a port becomes active; + interrupts are enabled and DTR & RTS are turned on. + */ +static int +startup(struct cyclades_port * info) +{ + unsigned long flags; + int retval = 0; + void __iomem *base_addr; + int card,chip,channel,index; + unsigned long page; + + card = info->card; + channel = (info->line) - (cy_card[card].first_line); + + page = get_zeroed_page(GFP_KERNEL); + if (!page) + return -ENOMEM; + + CY_LOCK(info, flags); + + if (info->flags & ASYNC_INITIALIZED){ + free_page(page); + goto errout; + } + + if (!info->type){ + if (info->tty){ + set_bit(TTY_IO_ERROR, &info->tty->flags); + } + free_page(page); + goto errout; + } + + if (info->xmit_buf) + free_page(page); + else + info->xmit_buf = (unsigned char *) page; + + CY_UNLOCK(info, flags); + + set_line_char(info); + + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<default_timeout + ? info->default_timeout : 0x02)); /* 10ms rx timeout */ + + cyy_issue_cmd(base_addr,CyCHAN_CTL|CyENB_RCVR|CyENB_XMTR,index); + + cy_writeb(base_addr+(CyCAR<flags |= ASYNC_INITIALIZED; + + if (info->tty){ + clear_bit(TTY_IO_ERROR, &info->tty->flags); + } + info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; + info->breakon = info->breakoff = 0; + memset((char *)&info->idle_stats, 0, sizeof(info->idle_stats)); + info->idle_stats.in_use = + info->idle_stats.recv_idle = + info->idle_stats.xmit_idle = jiffies; + + CY_UNLOCK(info, flags); + + } else { + struct FIRM_ID __iomem *firm_id; + struct ZFW_CTRL __iomem *zfw_ctrl; + struct BOARD_CTRL __iomem *board_ctrl; + struct CH_CTRL __iomem *ch_ctrl; + int retval; + + base_addr = cy_card[card].base_addr; + + firm_id = base_addr + ID_ADDRESS; + if (!ISZLOADED(cy_card[card])){ + return -ENODEV; + } + + zfw_ctrl = cy_card[card].base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); + board_ctrl = &zfw_ctrl->board_ctrl; + ch_ctrl = zfw_ctrl->ch_ctrl; + +#ifdef CY_DEBUG_OPEN + printk("cyc startup Z card %d, channel %d, base_addr %lx\n", + card, channel, (long)base_addr);/**/ +#endif + + CY_LOCK(info, flags); + + cy_writel(&ch_ctrl[channel].op_mode, C_CH_ENABLE); +#ifdef Z_WAKE +#ifdef CONFIG_CYZ_INTR + cy_writel(&ch_ctrl[channel].intr_enable, + C_IN_TXBEMPTY|C_IN_TXLOWWM|C_IN_RXHIWM|C_IN_RXNNDT| + C_IN_IOCTLW| + C_IN_MDCD); +#else + cy_writel(&ch_ctrl[channel].intr_enable, + C_IN_IOCTLW| + C_IN_MDCD); +#endif /* CONFIG_CYZ_INTR */ +#else +#ifdef CONFIG_CYZ_INTR + cy_writel(&ch_ctrl[channel].intr_enable, + C_IN_TXBEMPTY|C_IN_TXLOWWM|C_IN_RXHIWM|C_IN_RXNNDT| + C_IN_MDCD); +#else + cy_writel(&ch_ctrl[channel].intr_enable, + C_IN_MDCD); +#endif /* CONFIG_CYZ_INTR */ +#endif /* Z_WAKE */ + + retval = cyz_issue_cmd(&cy_card[card], channel, C_CM_IOCTL, 0L); + if (retval != 0){ + printk("cyc:startup(1) retval on ttyC%d was %x\n", + info->line, retval); + } + + /* Flush RX buffers before raising DTR and RTS */ + retval = cyz_issue_cmd(&cy_card[card], channel, C_CM_FLUSH_RX, 0L); + if (retval != 0){ + printk("cyc:startup(2) retval on ttyC%d was %x\n", + info->line, retval); + } + + /* set timeout !!! */ + /* set RTS and DTR !!! */ + cy_writel(&ch_ctrl[channel].rs_control, + cy_readl(&ch_ctrl[channel].rs_control) | C_RS_RTS | C_RS_DTR) ; + retval = cyz_issue_cmd(&cy_card[info->card], + channel, C_CM_IOCTLM, 0L); + if (retval != 0){ + printk("cyc:startup(3) retval on ttyC%d was %x\n", + info->line, retval); + } +#ifdef CY_DEBUG_DTR + printk("cyc:startup raising Z DTR\n"); +#endif + + /* enable send, recv, modem !!! */ + + info->flags |= ASYNC_INITIALIZED; + if (info->tty){ + clear_bit(TTY_IO_ERROR, &info->tty->flags); + } + info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; + info->breakon = info->breakoff = 0; + memset((char *)&info->idle_stats, 0, sizeof(info->idle_stats)); + info->idle_stats.in_use = + info->idle_stats.recv_idle = + info->idle_stats.xmit_idle = jiffies; + + CY_UNLOCK(info, flags); + } + +#ifdef CY_DEBUG_OPEN + printk(" cyc startup done\n"); +#endif + return 0; + +errout: + CY_UNLOCK(info, flags); + return retval; +} /* startup */ + + +static void +start_xmit( struct cyclades_port *info ) +{ + unsigned long flags; + void __iomem *base_addr; + int card,chip,channel,index; + + card = info->card; + channel = (info->line) - (cy_card[card].first_line); + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<line, retval); + } + CY_UNLOCK(info, flags); +#else /* CONFIG_CYZ_INTR */ + /* Don't have to do anything at this time */ +#endif /* CONFIG_CYZ_INTR */ + } +} /* start_xmit */ + +/* + * This routine shuts down a serial port; interrupts are disabled, + * and DTR is dropped if the hangup on close termio flag is on. + */ +static void +shutdown(struct cyclades_port * info) +{ + unsigned long flags; + void __iomem *base_addr; + int card,chip,channel,index; + + if (!(info->flags & ASYNC_INITIALIZED)){ + return; + } + + card = info->card; + channel = info->line - cy_card[card].first_line; + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<delta_msr_wait); + + if (info->xmit_buf){ + unsigned char * temp; + temp = info->xmit_buf; + info->xmit_buf = NULL; + free_page((unsigned long) temp); + } + cy_writeb(base_addr+(CyCAR<tty || (info->tty->termios->c_cflag & HUPCL)) { + cy_writeb(base_addr+(CyMSVR1<tty){ + set_bit(TTY_IO_ERROR, &info->tty->flags); + } + info->flags &= ~ASYNC_INITIALIZED; + CY_UNLOCK(info, flags); + } else { + struct FIRM_ID __iomem *firm_id; + struct ZFW_CTRL __iomem *zfw_ctrl; + struct BOARD_CTRL __iomem *board_ctrl; + struct CH_CTRL __iomem *ch_ctrl; + int retval; + + base_addr = cy_card[card].base_addr; +#ifdef CY_DEBUG_OPEN + printk("cyc shutdown Z card %d, channel %d, base_addr %lx\n", + card, channel, (long)base_addr); +#endif + + firm_id = base_addr + ID_ADDRESS; + if (!ISZLOADED(cy_card[card])) { + return; + } + + zfw_ctrl = cy_card[card].base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); + board_ctrl = &zfw_ctrl->board_ctrl; + ch_ctrl = zfw_ctrl->ch_ctrl; + + CY_LOCK(info, flags); + + if (info->xmit_buf){ + unsigned char * temp; + temp = info->xmit_buf; + info->xmit_buf = NULL; + free_page((unsigned long) temp); + } + + if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) { + cy_writel(&ch_ctrl[channel].rs_control, + (uclong)(cy_readl(&ch_ctrl[channel].rs_control) & + ~(C_RS_RTS | C_RS_DTR))); + retval = cyz_issue_cmd(&cy_card[info->card], + channel, C_CM_IOCTLM, 0L); + if (retval != 0){ + printk("cyc:shutdown retval on ttyC%d was %x\n", + info->line, retval); + } +#ifdef CY_DEBUG_DTR + printk("cyc:shutdown dropping Z DTR\n"); +#endif + } + + if (info->tty){ + set_bit(TTY_IO_ERROR, &info->tty->flags); + } + info->flags &= ~ASYNC_INITIALIZED; + + CY_UNLOCK(info, flags); + } + +#ifdef CY_DEBUG_OPEN + printk(" cyc shutdown done\n"); +#endif + return; +} /* shutdown */ + + +/* + * ------------------------------------------------------------ + * cy_open() and friends + * ------------------------------------------------------------ + */ + +static int +block_til_ready(struct tty_struct *tty, struct file * filp, + struct cyclades_port *info) +{ + DECLARE_WAITQUEUE(wait, current); + struct cyclades_card *cinfo; + unsigned long flags; + int chip, channel,index; + int retval; + void __iomem *base_addr; + + cinfo = &cy_card[info->card]; + channel = info->line - cinfo->first_line; + + /* + * If the device is in the middle of being closed, then block + * until it's done, and then try again. + */ + if (tty_hung_up_p(filp) || (info->flags & ASYNC_CLOSING)) { + if (info->flags & ASYNC_CLOSING) { + interruptible_sleep_on(&info->close_wait); + } + return ((info->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS); + } + + /* + * If non-blocking mode is set, then make the check up front + * and then exit. + */ + if ((filp->f_flags & O_NONBLOCK) || + (tty->flags & (1 << TTY_IO_ERROR))) { + info->flags |= ASYNC_NORMAL_ACTIVE; + return 0; + } + + /* + * Block waiting for the carrier detect and the line to become + * free (i.e., not in use by the callout). While we are in + * this loop, info->count is dropped by one, so that + * cy_close() knows when to free things. We restore it upon + * exit, either normal or abnormal. + */ + retval = 0; + add_wait_queue(&info->open_wait, &wait); +#ifdef CY_DEBUG_OPEN + printk("cyc block_til_ready before block: ttyC%d, count = %d\n", + info->line, info->count);/**/ +#endif + CY_LOCK(info, flags); + if (!tty_hung_up_p(filp)) + info->count--; + CY_UNLOCK(info, flags); +#ifdef CY_DEBUG_COUNT + printk("cyc block_til_ready: (%d): decrementing count to %d\n", + current->pid, info->count); +#endif + info->blocked_open++; + + if (!IS_CYC_Z(*cinfo)) { + chip = channel>>2; + channel &= 0x03; + index = cinfo->bus_index; + base_addr = cinfo->base_addr + (cy_chip_offset[chip]<termios->c_cflag & CBAUD)){ + cy_writeb(base_addr+(CyCAR<flags & ASYNC_INITIALIZED) ){ + retval = ((info->flags & ASYNC_HUP_NOTIFY) ? + -EAGAIN : -ERESTARTSYS); + break; + } + + CY_LOCK(info, flags); + cy_writeb(base_addr+(CyCAR<flags & ASYNC_CLOSING) + && (C_CLOCAL(tty) + || (cy_readb(base_addr+(CyMSVR1<line, info->count);/**/ +#endif + schedule(); + } + } else { + struct FIRM_ID __iomem *firm_id; + struct ZFW_CTRL __iomem *zfw_ctrl; + struct BOARD_CTRL __iomem *board_ctrl; + struct CH_CTRL __iomem *ch_ctrl; + int retval; + + base_addr = cinfo->base_addr; + firm_id = base_addr + ID_ADDRESS; + if (!ISZLOADED(*cinfo)){ + current->state = TASK_RUNNING; + remove_wait_queue(&info->open_wait, &wait); + return -EINVAL; + } + + zfw_ctrl = base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); + board_ctrl = &zfw_ctrl->board_ctrl; + ch_ctrl = zfw_ctrl->ch_ctrl; + + while (1) { + if ((tty->termios->c_cflag & CBAUD)){ + cy_writel(&ch_ctrl[channel].rs_control, + cy_readl(&ch_ctrl[channel].rs_control) | + (C_RS_RTS | C_RS_DTR)); + retval = cyz_issue_cmd(&cy_card[info->card], + channel, C_CM_IOCTLM, 0L); + if (retval != 0){ + printk("cyc:block_til_ready retval on ttyC%d was %x\n", + info->line, retval); + } +#ifdef CY_DEBUG_DTR + printk("cyc:block_til_ready raising Z DTR\n"); +#endif + } + + set_current_state(TASK_INTERRUPTIBLE); + if (tty_hung_up_p(filp) + || !(info->flags & ASYNC_INITIALIZED) ){ + retval = ((info->flags & ASYNC_HUP_NOTIFY) ? + -EAGAIN : -ERESTARTSYS); + break; + } + if (!(info->flags & ASYNC_CLOSING) + && (C_CLOCAL(tty) + || (cy_readl(&ch_ctrl[channel].rs_status) & C_RS_DCD))) { + break; + } + if (signal_pending(current)) { + retval = -ERESTARTSYS; + break; + } +#ifdef CY_DEBUG_OPEN + printk("cyc block_til_ready blocking: ttyC%d, count = %d\n", + info->line, info->count);/**/ +#endif + schedule(); + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&info->open_wait, &wait); + if (!tty_hung_up_p(filp)){ + info->count++; +#ifdef CY_DEBUG_COUNT + printk("cyc:block_til_ready (%d): incrementing count to %d\n", + current->pid, info->count); +#endif + } + info->blocked_open--; +#ifdef CY_DEBUG_OPEN + printk("cyc:block_til_ready after blocking: ttyC%d, count = %d\n", + info->line, info->count);/**/ +#endif + if (retval) + return retval; + info->flags |= ASYNC_NORMAL_ACTIVE; + return 0; +} /* block_til_ready */ + + +/* + * This routine is called whenever a serial port is opened. It + * performs the serial-specific initialization for the tty structure. + */ +static int +cy_open(struct tty_struct *tty, struct file * filp) +{ + struct cyclades_port *info; + int retval, line; + unsigned long page; + + line = tty->index; + if ((line < 0) || (NR_PORTS <= line)){ + return -ENODEV; + } + info = &cy_port[line]; + if (info->line < 0){ + return -ENODEV; + } + + /* If the card's firmware hasn't been loaded, + treat it as absent from the system. This + will make the user pay attention. + */ + if (IS_CYC_Z(cy_card[info->card])) { + struct cyclades_card *cinfo = &cy_card[info->card]; + struct FIRM_ID __iomem *firm_id = cinfo->base_addr + ID_ADDRESS; + + if (!ISZLOADED(*cinfo)) { + if (((ZE_V1 ==cy_readl(&((struct RUNTIME_9060 __iomem *) + (cinfo->ctl_addr))->mail_box_0)) && + Z_FPGA_CHECK (*cinfo)) && + (ZFIRM_HLT == cy_readl (&firm_id->signature))) + { + printk ("cyc:Cyclades-Z Error: you need an external power supply for this number of ports.\n\rFirmware halted.\r\n"); + } else { + printk("cyc:Cyclades-Z firmware not yet loaded\n"); + } + return -ENODEV; + } +#ifdef CONFIG_CYZ_INTR + else { + /* In case this Z board is operating in interrupt mode, its + interrupts should be enabled as soon as the first open happens + to one of its ports. */ + if (!cinfo->intr_enabled) { + struct ZFW_CTRL __iomem *zfw_ctrl; + struct BOARD_CTRL __iomem *board_ctrl; + + zfw_ctrl = cinfo->base_addr + (cy_readl (&firm_id->zfwctrl_addr) & 0xfffff); + + board_ctrl = &zfw_ctrl->board_ctrl; + + /* Enable interrupts on the PLX chip */ + cy_writew(cinfo->ctl_addr+0x68, + cy_readw(cinfo->ctl_addr+0x68)|0x0900); + /* Enable interrupts on the FW */ + retval = cyz_issue_cmd(cinfo, + 0, C_CM_IRQ_ENBL, 0L); + if (retval != 0){ + printk("cyc:IRQ enable retval was %x\n", retval); + } + cinfo->nports = (int) cy_readl (&board_ctrl->n_channel); + cinfo->intr_enabled = 1; + } + } +#endif /* CONFIG_CYZ_INTR */ + /* Make sure this Z port really exists in hardware */ + if (info->line > (cinfo->first_line + cinfo->nports - 1)) + return -ENODEV; + } +#ifdef CY_DEBUG_OTHER + printk("cyc:cy_open ttyC%d\n", info->line); /* */ +#endif + tty->driver_data = info; + info->tty = tty; + if (serial_paranoia_check(info, tty->name, "cy_open")){ + return -ENODEV; + } +#ifdef CY_DEBUG_OPEN + printk("cyc:cy_open ttyC%d, count = %d\n", + info->line, info->count);/**/ +#endif + info->count++; +#ifdef CY_DEBUG_COUNT + printk("cyc:cy_open (%d): incrementing count to %d\n", + current->pid, info->count); +#endif + if (!tmp_buf) { + page = get_zeroed_page(GFP_KERNEL); + if (!page) + return -ENOMEM; + if (tmp_buf) + free_page(page); + else + tmp_buf = (unsigned char *) page; + } + + /* + * If the port is the middle of closing, bail out now + */ + if (tty_hung_up_p(filp) || (info->flags & ASYNC_CLOSING)) { + if (info->flags & ASYNC_CLOSING) + interruptible_sleep_on(&info->close_wait); + return ((info->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS); + } + + /* + * Start up serial port + */ + retval = startup(info); + if (retval){ + return retval; + } + + retval = block_til_ready(tty, filp, info); + if (retval) { +#ifdef CY_DEBUG_OPEN + printk("cyc:cy_open returning after block_til_ready with %d\n", + retval); +#endif + return retval; + } + + info->throttle = 0; + +#ifdef CY_DEBUG_OPEN + printk(" cyc:cy_open done\n");/**/ +#endif + + return 0; +} /* cy_open */ + + +/* + * cy_wait_until_sent() --- wait until the transmitter is empty + */ +static void +cy_wait_until_sent(struct tty_struct *tty, int timeout) +{ + struct cyclades_port * info = (struct cyclades_port *)tty->driver_data; + void __iomem *base_addr; + int card,chip,channel,index; + unsigned long orig_jiffies; + int char_time; + + if (serial_paranoia_check(info, tty->name, "cy_wait_until_sent")) + return; + + if (info->xmit_fifo_size == 0) + return; /* Just in case.... */ + + + orig_jiffies = jiffies; + /* + * Set the check interval to be 1/5 of the estimated time to + * send a single character, and make it at least 1. The check + * interval should also be less than the timeout. + * + * Note: we have to use pretty tight timings here to satisfy + * the NIST-PCTS. + */ + char_time = (info->timeout - HZ/50) / info->xmit_fifo_size; + char_time = char_time / 5; + if (char_time <= 0) + char_time = 1; + if (timeout < 0) + timeout = 0; + if (timeout) + char_time = min(char_time, timeout); + /* + * If the transmitter hasn't cleared in twice the approximate + * amount of time to send the entire FIFO, it probably won't + * ever clear. This assumes the UART isn't doing flow + * control, which is currently the case. Hence, if it ever + * takes longer than info->timeout, this is probably due to a + * UART bug of some kind. So, we clamp the timeout parameter at + * 2*info->timeout. + */ + if (!timeout || timeout > 2*info->timeout) + timeout = 2*info->timeout; +#ifdef CY_DEBUG_WAIT_UNTIL_SENT + printk("In cy_wait_until_sent(%d) check=%lu...", timeout, char_time); + printk("jiff=%lu...", jiffies); +#endif + card = info->card; + channel = (info->line) - (cy_card[card].first_line); + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<driver_data; + unsigned long flags; + +#ifdef CY_DEBUG_OTHER + printk("cyc:cy_close ttyC%d\n", info->line); +#endif + + if (!info || serial_paranoia_check(info, tty->name, "cy_close")){ + return; + } + + CY_LOCK(info, flags); + /* If the TTY is being hung up, nothing to do */ + if (tty_hung_up_p(filp)) { + CY_UNLOCK(info, flags); + return; + } + +#ifdef CY_DEBUG_OPEN + printk("cyc:cy_close ttyC%d, count = %d\n", info->line, info->count); +#endif + if ((tty->count == 1) && (info->count != 1)) { + /* + * Uh, oh. tty->count is 1, which means that the tty + * structure will be freed. Info->count should always + * be one in these conditions. If it's greater than + * one, we've got real problems, since it means the + * serial port won't be shutdown. + */ + printk("cyc:cy_close: bad serial port count; tty->count is 1, " + "info->count is %d\n", info->count); + info->count = 1; + } +#ifdef CY_DEBUG_COUNT + printk("cyc:cy_close at (%d): decrementing count to %d\n", + current->pid, info->count - 1); +#endif + if (--info->count < 0) { +#ifdef CY_DEBUG_COUNT + printk("cyc:cyc_close setting count to 0\n"); +#endif + info->count = 0; + } + if (info->count) { + CY_UNLOCK(info, flags); + return; + } + info->flags |= ASYNC_CLOSING; + + /* + * Now we wait for the transmit buffer to clear; and we notify + * the line discipline to only process XON/XOFF characters. + */ + tty->closing = 1; + CY_UNLOCK(info, flags); + if (info->closing_wait != CY_CLOSING_WAIT_NONE) { + tty_wait_until_sent(tty, info->closing_wait); + } + CY_LOCK(info, flags); + + if (!IS_CYC_Z(cy_card[info->card])) { + int channel = info->line - cy_card[info->card].first_line; + int index = cy_card[info->card].bus_index; + void __iomem *base_addr = cy_card[info->card].base_addr + (cy_chip_offset[channel>>2] << index); + /* Stop accepting input */ + channel &= 0x03; + cy_writeb(base_addr+(CyCAR<flags & ASYNC_INITIALIZED) { + /* Waiting for on-board buffers to be empty before closing + the port */ + CY_UNLOCK(info, flags); + cy_wait_until_sent(tty, info->timeout); + CY_LOCK(info, flags); + } + } else { +#ifdef Z_WAKE + /* Waiting for on-board buffers to be empty before closing the port */ + void __iomem *base_addr = cy_card[info->card].base_addr; + struct FIRM_ID __iomem *firm_id = base_addr + ID_ADDRESS; + struct ZFW_CTRL __iomem *zfw_ctrl = base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); + struct CH_CTRL __iomem *ch_ctrl = zfw_ctrl->ch_ctrl; + int channel = info->line - cy_card[info->card].first_line; + int retval; + + if (cy_readl(&ch_ctrl[channel].flow_status) != C_FS_TXIDLE) { + retval = cyz_issue_cmd(&cy_card[info->card], channel, + C_CM_IOCTLW, 0L); + if (retval != 0){ + printk("cyc:cy_close retval on ttyC%d was %x\n", + info->line, retval); + } + CY_UNLOCK(info, flags); + interruptible_sleep_on(&info->shutdown_wait); + CY_LOCK(info, flags); + } +#endif + } + + CY_UNLOCK(info, flags); + shutdown(info); + if (tty->driver->flush_buffer) + tty->driver->flush_buffer(tty); + tty_ldisc_flush(tty); + CY_LOCK(info, flags); + + tty->closing = 0; + info->event = 0; + info->tty = NULL; + if (info->blocked_open) { + CY_UNLOCK(info, flags); + if (info->close_delay) { + msleep_interruptible(jiffies_to_msecs(info->close_delay)); + } + wake_up_interruptible(&info->open_wait); + CY_LOCK(info, flags); + } + info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING); + wake_up_interruptible(&info->close_wait); + +#ifdef CY_DEBUG_OTHER + printk(" cyc:cy_close done\n"); +#endif + + CY_UNLOCK(info, flags); + return; +} /* cy_close */ + + +/* This routine gets called when tty_write has put something into + * the write_queue. The characters may come from user space or + * kernel space. + * + * This routine will return the number of characters actually + * accepted for writing. + * + * If the port is not already transmitting stuff, start it off by + * enabling interrupts. The interrupt service routine will then + * ensure that the characters are sent. + * If the port is already active, there is no need to kick it. + * + */ +static int +cy_write(struct tty_struct * tty, const unsigned char *buf, int count) +{ + struct cyclades_port *info = (struct cyclades_port *)tty->driver_data; + unsigned long flags; + int c, ret = 0; + +#ifdef CY_DEBUG_IO + printk("cyc:cy_write ttyC%d\n", info->line); /* */ +#endif + + if (serial_paranoia_check(info, tty->name, "cy_write")){ + return 0; + } + + if (!tty || !info->xmit_buf || !tmp_buf){ + return 0; + } + + CY_LOCK(info, flags); + while (1) { + c = min(count, min((int)(SERIAL_XMIT_SIZE - info->xmit_cnt - 1), + (int)(SERIAL_XMIT_SIZE - info->xmit_head))); + + if (c <= 0) + break; + + memcpy(info->xmit_buf + info->xmit_head, buf, c); + info->xmit_head = (info->xmit_head + c) & (SERIAL_XMIT_SIZE-1); + info->xmit_cnt += c; + buf += c; + count -= c; + ret += c; + } + CY_UNLOCK(info, flags); + + info->idle_stats.xmit_bytes += ret; + info->idle_stats.xmit_idle = jiffies; + + if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) { + start_xmit(info); + } + return ret; +} /* cy_write */ + + +/* + * This routine is called by the kernel to write a single + * character to the tty device. If the kernel uses this routine, + * it must call the flush_chars() routine (if defined) when it is + * done stuffing characters into the driver. If there is no room + * in the queue, the character is ignored. + */ +static void +cy_put_char(struct tty_struct *tty, unsigned char ch) +{ + struct cyclades_port *info = (struct cyclades_port *)tty->driver_data; + unsigned long flags; + +#ifdef CY_DEBUG_IO + printk("cyc:cy_put_char ttyC%d\n", info->line); +#endif + + if (serial_paranoia_check(info, tty->name, "cy_put_char")) + return; + + if (!tty || !info->xmit_buf) + return; + + CY_LOCK(info, flags); + if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1) { + CY_UNLOCK(info, flags); + return; + } + + info->xmit_buf[info->xmit_head++] = ch; + info->xmit_head &= SERIAL_XMIT_SIZE - 1; + info->xmit_cnt++; + info->idle_stats.xmit_bytes++; + info->idle_stats.xmit_idle = jiffies; + CY_UNLOCK(info, flags); +} /* cy_put_char */ + + +/* + * This routine is called by the kernel after it has written a + * series of characters to the tty device using put_char(). + */ +static void +cy_flush_chars(struct tty_struct *tty) +{ + struct cyclades_port *info = (struct cyclades_port *)tty->driver_data; + +#ifdef CY_DEBUG_IO + printk("cyc:cy_flush_chars ttyC%d\n", info->line); /* */ +#endif + + if (serial_paranoia_check(info, tty->name, "cy_flush_chars")) + return; + + if (info->xmit_cnt <= 0 || tty->stopped + || tty->hw_stopped || !info->xmit_buf) + return; + + start_xmit(info); +} /* cy_flush_chars */ + + +/* + * This routine returns the numbers of characters the tty driver + * will accept for queuing to be written. This number is subject + * to change as output buffers get emptied, or if the output flow + * control is activated. + */ +static int +cy_write_room(struct tty_struct *tty) +{ + struct cyclades_port *info = (struct cyclades_port *)tty->driver_data; + int ret; + +#ifdef CY_DEBUG_IO + printk("cyc:cy_write_room ttyC%d\n", info->line); /* */ +#endif + + if (serial_paranoia_check(info, tty->name, "cy_write_room")) + return 0; + ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; + if (ret < 0) + ret = 0; + return ret; +} /* cy_write_room */ + + +static int +cy_chars_in_buffer(struct tty_struct *tty) +{ + struct cyclades_port *info = (struct cyclades_port *)tty->driver_data; + int card, channel; + + if (serial_paranoia_check(info, tty->name, "cy_chars_in_buffer")) + return 0; + + card = info->card; + channel = (info->line) - (cy_card[card].first_line); + +#ifdef Z_EXT_CHARS_IN_BUFFER + if (!IS_CYC_Z(cy_card[card])) { +#endif /* Z_EXT_CHARS_IN_BUFFER */ +#ifdef CY_DEBUG_IO + printk("cyc:cy_chars_in_buffer ttyC%d %d\n", + info->line, info->xmit_cnt); /* */ +#endif + return info->xmit_cnt; +#ifdef Z_EXT_CHARS_IN_BUFFER + } else { + static volatile struct FIRM_ID *firm_id; + static volatile struct ZFW_CTRL *zfw_ctrl; + static volatile struct CH_CTRL *ch_ctrl; + static volatile struct BUF_CTRL *buf_ctrl; + int char_count; + volatile uclong tx_put, tx_get, tx_bufsize; + + firm_id = cy_card[card].base_addr + ID_ADDRESS; + zfw_ctrl = cy_card[card].base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); + ch_ctrl = &(zfw_ctrl->ch_ctrl[channel]); + buf_ctrl = &(zfw_ctrl->buf_ctrl[channel]); + + tx_get = cy_readl(&buf_ctrl->tx_get); + tx_put = cy_readl(&buf_ctrl->tx_put); + tx_bufsize = cy_readl(&buf_ctrl->tx_bufsize); + if (tx_put >= tx_get) + char_count = tx_put - tx_get; + else + char_count = tx_put - tx_get + tx_bufsize; +#ifdef CY_DEBUG_IO + printk("cyc:cy_chars_in_buffer ttyC%d %d\n", + info->line, info->xmit_cnt + char_count); /* */ +#endif + return (info->xmit_cnt + char_count); + } +#endif /* Z_EXT_CHARS_IN_BUFFER */ +} /* cy_chars_in_buffer */ + + +/* + * ------------------------------------------------------------ + * cy_ioctl() and friends + * ------------------------------------------------------------ + */ + +static void +cyy_baud_calc(struct cyclades_port *info, uclong baud) +{ + int co, co_val, bpr; + uclong cy_clock = ((info->chip_rev >= CD1400_REV_J) ? 60000000 : 25000000); + + if (baud == 0) { + info->tbpr = info->tco = info->rbpr = info->rco = 0; + return; + } + + /* determine which prescaler to use */ + for (co = 4, co_val = 2048; co; co--, co_val >>= 2) { + if (cy_clock / co_val / baud > 63) + break; + } + + bpr = (cy_clock / co_val * 2 / baud + 1) / 2; + if (bpr > 255) + bpr = 255; + + info->tbpr = info->rbpr = bpr; + info->tco = info->rco = co; +} + +/* + * This routine finds or computes the various line characteristics. + * It used to be called config_setup + */ +static void +set_line_char(struct cyclades_port * info) +{ + unsigned long flags; + void __iomem *base_addr; + int card,chip,channel,index; + unsigned cflag, iflag; + unsigned short chip_number; + int baud, baud_rate = 0; + int i; + + + if (!info->tty || !info->tty->termios){ + return; + } + if (info->line == -1){ + return; + } + cflag = info->tty->termios->c_cflag; + iflag = info->tty->termios->c_iflag; + + /* + * Set up the tty->alt_speed kludge + */ + if (info->tty) { + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI) + info->tty->alt_speed = 57600; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI) + info->tty->alt_speed = 115200; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI) + info->tty->alt_speed = 230400; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP) + info->tty->alt_speed = 460800; + } + + card = info->card; + channel = (info->line) - (cy_card[card].first_line); + chip_number = channel / 4; + + if (!IS_CYC_Z(cy_card[card])) { + + index = cy_card[card].bus_index; + + /* baud rate */ + baud = tty_get_baud_rate(info->tty); + if ((baud == 38400) && + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) { + if (info->custom_divisor) + baud_rate = info->baud / info->custom_divisor; + else + baud_rate = info->baud; + } else if (baud > CD1400_MAX_SPEED) { + baud = CD1400_MAX_SPEED; + } + /* find the baud index */ + for (i = 0; i < 20; i++) { + if (baud == baud_table[i]) { + break; + } + } + if (i == 20) { + i = 19; /* CD1400_MAX_SPEED */ + } + + if ((baud == 38400) && + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) { + cyy_baud_calc(info, baud_rate); + } else { + if(info->chip_rev >= CD1400_REV_J) { + /* It is a CD1400 rev. J or later */ + info->tbpr = baud_bpr_60[i]; /* Tx BPR */ + info->tco = baud_co_60[i]; /* Tx CO */ + info->rbpr = baud_bpr_60[i]; /* Rx BPR */ + info->rco = baud_co_60[i]; /* Rx CO */ + } else { + info->tbpr = baud_bpr_25[i]; /* Tx BPR */ + info->tco = baud_co_25[i]; /* Tx CO */ + info->rbpr = baud_bpr_25[i]; /* Rx BPR */ + info->rco = baud_co_25[i]; /* Rx CO */ + } + } + if (baud_table[i] == 134) { + /* get it right for 134.5 baud */ + info->timeout = (info->xmit_fifo_size*HZ*30/269) + 2; + } else if ((baud == 38400) && + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) { + info->timeout = (info->xmit_fifo_size*HZ*15/baud_rate) + 2; + } else if (baud_table[i]) { + info->timeout = (info->xmit_fifo_size*HZ*15/baud_table[i]) + 2; + /* this needs to be propagated into the card info */ + } else { + info->timeout = 0; + } + /* By tradition (is it a standard?) a baud rate of zero + implies the line should be/has been closed. A bit + later in this routine such a test is performed. */ + + /* byte size and parity */ + info->cor5 = 0; + info->cor4 = 0; + info->cor3 = (info->default_threshold + ? info->default_threshold + : baud_cor3[i]); /* receive threshold */ + info->cor2 = CyETC; + switch(cflag & CSIZE){ + case CS5: + info->cor1 = Cy_5_BITS; + break; + case CS6: + info->cor1 = Cy_6_BITS; + break; + case CS7: + info->cor1 = Cy_7_BITS; + break; + case CS8: + info->cor1 = Cy_8_BITS; + break; + } + if(cflag & CSTOPB){ + info->cor1 |= Cy_2_STOP; + } + if (cflag & PARENB){ + if (cflag & PARODD){ + info->cor1 |= CyPARITY_O; + }else{ + info->cor1 |= CyPARITY_E; + } + }else{ + info->cor1 |= CyPARITY_NONE; + } + + /* CTS flow control flag */ + if (cflag & CRTSCTS){ + info->flags |= ASYNC_CTS_FLOW; + info->cor2 |= CyCtsAE; + }else{ + info->flags &= ~ASYNC_CTS_FLOW; + info->cor2 &= ~CyCtsAE; + } + if (cflag & CLOCAL) + info->flags &= ~ASYNC_CHECK_CD; + else + info->flags |= ASYNC_CHECK_CD; + + /*********************************************** + The hardware option, CyRtsAO, presents RTS when + the chip has characters to send. Since most modems + use RTS as reverse (inbound) flow control, this + option is not used. If inbound flow control is + necessary, DTR can be programmed to provide the + appropriate signals for use with a non-standard + cable. Contact Marcio Saito for details. + ***********************************************/ + + chip = channel>>2; + channel &= 0x03; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<tco); + cy_writeb(base_addr+(CyTBPR<tbpr); + cy_writeb(base_addr+(CyRCOR<rco); + cy_writeb(base_addr+(CyRBPR<rbpr); + + /* set line characteristics according configuration */ + + cy_writeb(base_addr+(CySCHR1<tty)); + cy_writeb(base_addr+(CySCHR2<tty)); + cy_writeb(base_addr+(CyCOR1<cor1); + cy_writeb(base_addr+(CyCOR2<cor2); + cy_writeb(base_addr+(CyCOR3<cor3); + cy_writeb(base_addr+(CyCOR4<cor4); + cy_writeb(base_addr+(CyCOR5<cor5); + + cyy_issue_cmd(base_addr, + CyCOR_CHANGE|CyCOR1ch|CyCOR2ch|CyCOR3ch,index); + + cy_writeb(base_addr+(CyCAR<default_timeout + ? info->default_timeout + : 0x02)); /* 10ms rx timeout */ + + if (C_CLOCAL(info->tty)) { + /* without modem intr */ + cy_writeb(base_addr+(CySRER<0 modem transitions */ + if ((cflag & CRTSCTS) && info->rflow) { + cy_writeb(base_addr+(CyMCOR1<1 modem transitions */ + cy_writeb(base_addr+(CyMCOR2<0 modem transitions */ + if ((cflag & CRTSCTS) && info->rflow) { + cy_writeb(base_addr+(CyMCOR1<1 modem transitions */ + cy_writeb(base_addr+(CyMCOR2<rtsdtr_inv) { + cy_writeb(base_addr+(CyMSVR1<rtsdtr_inv) { + cy_writeb(base_addr+(CyMSVR1<tty){ + clear_bit(TTY_IO_ERROR, &info->tty->flags); + } + CY_UNLOCK(info, flags); + + } else { + struct FIRM_ID __iomem *firm_id; + struct ZFW_CTRL __iomem *zfw_ctrl; + struct BOARD_CTRL __iomem *board_ctrl; + struct CH_CTRL __iomem *ch_ctrl; + struct BUF_CTRL __iomem *buf_ctrl; + uclong sw_flow; + int retval; + + firm_id = cy_card[card].base_addr + ID_ADDRESS; + if (!ISZLOADED(cy_card[card])) { + return; + } + + zfw_ctrl = cy_card[card].base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); + board_ctrl = &zfw_ctrl->board_ctrl; + ch_ctrl = &(zfw_ctrl->ch_ctrl[channel]); + buf_ctrl = &zfw_ctrl->buf_ctrl[channel]; + + /* baud rate */ + baud = tty_get_baud_rate(info->tty); + if ((baud == 38400) && + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) { + if (info->custom_divisor) + baud_rate = info->baud / info->custom_divisor; + else + baud_rate = info->baud; + } else if (baud > CYZ_MAX_SPEED) { + baud = CYZ_MAX_SPEED; + } + cy_writel(&ch_ctrl->comm_baud , baud); + + if (baud == 134) { + /* get it right for 134.5 baud */ + info->timeout = (info->xmit_fifo_size*HZ*30/269) + 2; + } else if ((baud == 38400) && + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) { + info->timeout = (info->xmit_fifo_size*HZ*15/baud_rate) + 2; + } else if (baud) { + info->timeout = (info->xmit_fifo_size*HZ*15/baud) + 2; + /* this needs to be propagated into the card info */ + } else { + info->timeout = 0; + } + + /* byte size and parity */ + switch(cflag & CSIZE){ + case CS5: cy_writel(&ch_ctrl->comm_data_l , C_DL_CS5); break; + case CS6: cy_writel(&ch_ctrl->comm_data_l , C_DL_CS6); break; + case CS7: cy_writel(&ch_ctrl->comm_data_l , C_DL_CS7); break; + case CS8: cy_writel(&ch_ctrl->comm_data_l , C_DL_CS8); break; + } + if(cflag & CSTOPB){ + cy_writel(&ch_ctrl->comm_data_l, + cy_readl(&ch_ctrl->comm_data_l) | C_DL_2STOP); + }else{ + cy_writel(&ch_ctrl->comm_data_l, + cy_readl(&ch_ctrl->comm_data_l) | C_DL_1STOP); + } + if (cflag & PARENB){ + if (cflag & PARODD){ + cy_writel(&ch_ctrl->comm_parity , C_PR_ODD); + }else{ + cy_writel(&ch_ctrl->comm_parity , C_PR_EVEN); + } + }else{ + cy_writel(&ch_ctrl->comm_parity , C_PR_NONE); + } + + /* CTS flow control flag */ + if (cflag & CRTSCTS){ + cy_writel(&ch_ctrl->hw_flow, + cy_readl(&ch_ctrl->hw_flow) | C_RS_CTS | C_RS_RTS); + }else{ + cy_writel(&ch_ctrl->hw_flow, + cy_readl(&ch_ctrl->hw_flow) & ~(C_RS_CTS | C_RS_RTS)); + } + /* As the HW flow control is done in firmware, the driver doesn't + need to care about it */ + info->flags &= ~ASYNC_CTS_FLOW; + + /* XON/XOFF/XANY flow control flags */ + sw_flow = 0; + if (iflag & IXON){ + sw_flow |= C_FL_OXX; + if (iflag & IXANY) + sw_flow |= C_FL_OIXANY; + } + cy_writel(&ch_ctrl->sw_flow, sw_flow); + + retval = cyz_issue_cmd(&cy_card[card], channel, C_CM_IOCTL, 0L); + if (retval != 0){ + printk("cyc:set_line_char retval on ttyC%d was %x\n", + info->line, retval); + } + + /* CD sensitivity */ + if (cflag & CLOCAL){ + info->flags &= ~ASYNC_CHECK_CD; + }else{ + info->flags |= ASYNC_CHECK_CD; + } + + if(baud == 0){ /* baud rate is zero, turn off line */ + cy_writel(&ch_ctrl->rs_control, + cy_readl(&ch_ctrl->rs_control) & ~C_RS_DTR); +#ifdef CY_DEBUG_DTR + printk("cyc:set_line_char dropping Z DTR\n"); +#endif + }else{ + cy_writel(&ch_ctrl->rs_control, + cy_readl(&ch_ctrl->rs_control) | C_RS_DTR); +#ifdef CY_DEBUG_DTR + printk("cyc:set_line_char raising Z DTR\n"); +#endif + } + + retval = cyz_issue_cmd( &cy_card[card], channel, C_CM_IOCTLM, 0L); + if (retval != 0){ + printk("cyc:set_line_char(2) retval on ttyC%d was %x\n", + info->line, retval); + } + + if (info->tty){ + clear_bit(TTY_IO_ERROR, &info->tty->flags); + } + } +} /* set_line_char */ + + +static int +get_serial_info(struct cyclades_port * info, + struct serial_struct __user * retinfo) +{ + struct serial_struct tmp; + struct cyclades_card *cinfo = &cy_card[info->card]; + + if (!retinfo) + return -EFAULT; + memset(&tmp, 0, sizeof(tmp)); + tmp.type = info->type; + tmp.line = info->line; + tmp.port = info->card * 0x100 + info->line - cinfo->first_line; + tmp.irq = cinfo->irq; + tmp.flags = info->flags; + tmp.close_delay = info->close_delay; + tmp.baud_base = info->baud; + tmp.custom_divisor = info->custom_divisor; + tmp.hub6 = 0; /*!!!*/ + return copy_to_user(retinfo,&tmp,sizeof(*retinfo))?-EFAULT:0; +} /* get_serial_info */ + + +static int +set_serial_info(struct cyclades_port * info, + struct serial_struct __user * new_info) +{ + struct serial_struct new_serial; + struct cyclades_port old_info; + + if (copy_from_user(&new_serial,new_info,sizeof(new_serial))) + return -EFAULT; + old_info = *info; + + if (!capable(CAP_SYS_ADMIN)) { + if ((new_serial.close_delay != info->close_delay) || + (new_serial.baud_base != info->baud) || + ((new_serial.flags & ASYNC_FLAGS & ~ASYNC_USR_MASK) != + (info->flags & ASYNC_FLAGS & ~ASYNC_USR_MASK))) + return -EPERM; + info->flags = ((info->flags & ~ASYNC_USR_MASK) | + (new_serial.flags & ASYNC_USR_MASK)); + info->baud = new_serial.baud_base; + info->custom_divisor = new_serial.custom_divisor; + goto check_and_exit; + } + + + /* + * OK, past this point, all the error checking has been done. + * At this point, we start making changes..... + */ + + info->baud = new_serial.baud_base; + info->custom_divisor = new_serial.custom_divisor; + info->flags = ((info->flags & ~ASYNC_FLAGS) | + (new_serial.flags & ASYNC_FLAGS)); + info->close_delay = new_serial.close_delay * HZ/100; + info->closing_wait = new_serial.closing_wait * HZ/100; + +check_and_exit: + if (info->flags & ASYNC_INITIALIZED){ + set_line_char(info); + return 0; + }else{ + return startup(info); + } +} /* set_serial_info */ + +/* + * get_lsr_info - get line status register info + * + * Purpose: Let user call ioctl() to get info when the UART physically + * is emptied. On bus types like RS485, the transmitter must + * release the bus after transmitting. This must be done when + * the transmit shift register is empty, not be done when the + * transmit holding register is empty. This functionality + * allows an RS485 driver to be written in user space. + */ +static int get_lsr_info(struct cyclades_port *info, unsigned int __user *value) +{ + int card, chip, channel, index; + unsigned char status; + unsigned int result; + unsigned long flags; + void __iomem *base_addr; + + card = info->card; + channel = (info->line) - (cy_card[card].first_line); + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<driver_data; + int card,chip,channel,index; + void __iomem *base_addr; + unsigned long flags; + unsigned char status; + unsigned long lstatus; + unsigned int result; + struct FIRM_ID __iomem *firm_id; + struct ZFW_CTRL __iomem *zfw_ctrl; + struct BOARD_CTRL __iomem *board_ctrl; + struct CH_CTRL __iomem *ch_ctrl; + + if (serial_paranoia_check(info, tty->name, __FUNCTION__)) + return -ENODEV; + + card = info->card; + channel = (info->line) - (cy_card[card].first_line); + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<rtsdtr_inv) { + result = ((status & CyRTS) ? TIOCM_DTR : 0) + | ((status & CyDTR) ? TIOCM_RTS : 0); + } else { + result = ((status & CyRTS) ? TIOCM_RTS : 0) + | ((status & CyDTR) ? TIOCM_DTR : 0); + } + result |= ((status & CyDCD) ? TIOCM_CAR : 0) + | ((status & CyRI) ? TIOCM_RNG : 0) + | ((status & CyDSR) ? TIOCM_DSR : 0) + | ((status & CyCTS) ? TIOCM_CTS : 0); + } else { + base_addr = cy_card[card].base_addr; + + if (cy_card[card].num_chips != -1){ + return -EINVAL; + } + + firm_id = cy_card[card].base_addr + ID_ADDRESS; + if (ISZLOADED(cy_card[card])) { + zfw_ctrl = cy_card[card].base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); + board_ctrl = &zfw_ctrl->board_ctrl; + ch_ctrl = zfw_ctrl->ch_ctrl; + lstatus = cy_readl(&ch_ctrl[channel].rs_status); + result = ((lstatus & C_RS_RTS) ? TIOCM_RTS : 0) + | ((lstatus & C_RS_DTR) ? TIOCM_DTR : 0) + | ((lstatus & C_RS_DCD) ? TIOCM_CAR : 0) + | ((lstatus & C_RS_RI) ? TIOCM_RNG : 0) + | ((lstatus & C_RS_DSR) ? TIOCM_DSR : 0) + | ((lstatus & C_RS_CTS) ? TIOCM_CTS : 0); + }else{ + result = 0; + return -ENODEV; + } + + } + return result; +} /* cy_tiomget */ + + +static int +cy_tiocmset(struct tty_struct *tty, struct file *file, + unsigned int set, unsigned int clear) +{ + struct cyclades_port * info = (struct cyclades_port *)tty->driver_data; + int card,chip,channel,index; + void __iomem *base_addr; + unsigned long flags; + struct FIRM_ID __iomem *firm_id; + struct ZFW_CTRL __iomem *zfw_ctrl; + struct BOARD_CTRL __iomem *board_ctrl; + struct CH_CTRL __iomem *ch_ctrl; + int retval; + + if (serial_paranoia_check(info, tty->name, __FUNCTION__)) + return -ENODEV; + + card = info->card; + channel = (info->line) - (cy_card[card].first_line); + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<rtsdtr_inv) { + cy_writeb(base_addr+(CyMSVR2<rtsdtr_inv) { + cy_writeb(base_addr+(CyMSVR2<rtsdtr_inv) { + cy_writeb(base_addr+(CyMSVR1<rtsdtr_inv) { + cy_writeb(base_addr+(CyMSVR1<zfwctrl_addr) & 0xfffff); + board_ctrl = &zfw_ctrl->board_ctrl; + ch_ctrl = zfw_ctrl->ch_ctrl; + + if (set & TIOCM_RTS){ + CY_LOCK(info, flags); + cy_writel(&ch_ctrl[channel].rs_control, + cy_readl(&ch_ctrl[channel].rs_control) | C_RS_RTS); + CY_UNLOCK(info, flags); + } + if (clear & TIOCM_RTS) { + CY_LOCK(info, flags); + cy_writel(&ch_ctrl[channel].rs_control, + cy_readl(&ch_ctrl[channel].rs_control) & ~C_RS_RTS); + CY_UNLOCK(info, flags); + } + if (set & TIOCM_DTR){ + CY_LOCK(info, flags); + cy_writel(&ch_ctrl[channel].rs_control, + cy_readl(&ch_ctrl[channel].rs_control) | C_RS_DTR); +#ifdef CY_DEBUG_DTR + printk("cyc:set_modem_info raising Z DTR\n"); +#endif + CY_UNLOCK(info, flags); + } + if (clear & TIOCM_DTR) { + CY_LOCK(info, flags); + cy_writel(&ch_ctrl[channel].rs_control, + cy_readl(&ch_ctrl[channel].rs_control) & ~C_RS_DTR); +#ifdef CY_DEBUG_DTR + printk("cyc:set_modem_info clearing Z DTR\n"); +#endif + CY_UNLOCK(info, flags); + } + }else{ + return -ENODEV; + } + CY_LOCK(info, flags); + retval = cyz_issue_cmd(&cy_card[info->card], + channel, C_CM_IOCTLM,0L); + if (retval != 0){ + printk("cyc:set_modem_info retval on ttyC%d was %x\n", + info->line, retval); + } + CY_UNLOCK(info, flags); + } + return 0; +} /* cy_tiocmset */ + +/* + * cy_break() --- routine which turns the break handling on or off + */ +static void +cy_break(struct tty_struct *tty, int break_state) +{ + struct cyclades_port * info = (struct cyclades_port *)tty->driver_data; + unsigned long flags; + + if (serial_paranoia_check(info, tty->name, "cy_break")) + return; + + CY_LOCK(info, flags); + if (!IS_CYC_Z(cy_card[info->card])) { + /* Let the transmit ISR take care of this (since it + requires stuffing characters into the output stream). + */ + if (break_state == -1) { + if (!info->breakon) { + info->breakon = 1; + if (!info->xmit_cnt) { + CY_UNLOCK(info, flags); + start_xmit(info); + CY_LOCK(info, flags); + } + } + } else { + if (!info->breakoff) { + info->breakoff = 1; + if (!info->xmit_cnt) { + CY_UNLOCK(info, flags); + start_xmit(info); + CY_LOCK(info, flags); + } + } + } + } else { + int retval; + + if (break_state == -1) { + retval = cyz_issue_cmd(&cy_card[info->card], + (info->line) - (cy_card[info->card].first_line), + C_CM_SET_BREAK, 0L); + if (retval != 0) { + printk("cyc:cy_break (set) retval on ttyC%d was %x\n", + info->line, retval); + } + } else { + retval = cyz_issue_cmd(&cy_card[info->card], + (info->line) - (cy_card[info->card].first_line), + C_CM_CLR_BREAK, 0L); + if (retval != 0) { + printk("cyc:cy_break (clr) retval on ttyC%d was %x\n", + info->line, retval); + } + } + } + CY_UNLOCK(info, flags); +} /* cy_break */ + +static int +get_mon_info(struct cyclades_port * info, struct cyclades_monitor __user * mon) +{ + + if(copy_to_user(mon, &info->mon, sizeof(struct cyclades_monitor))) + return -EFAULT; + info->mon.int_count = 0; + info->mon.char_count = 0; + info->mon.char_max = 0; + info->mon.char_last = 0; + return 0; +}/* get_mon_info */ + + +static int +set_threshold(struct cyclades_port * info, unsigned long value) +{ + void __iomem *base_addr; + int card,channel,chip,index; + unsigned long flags; + + card = info->card; + channel = info->line - cy_card[card].first_line; + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<cor3 &= ~CyREC_FIFO; + info->cor3 |= value & CyREC_FIFO; + + CY_LOCK(info, flags); + cy_writeb(base_addr+(CyCOR3<cor3); + cyy_issue_cmd(base_addr,CyCOR_CHANGE|CyCOR3ch,index); + CY_UNLOCK(info, flags); + } else { + // Nothing to do! + } + return 0; +}/* set_threshold */ + + +static int +get_threshold(struct cyclades_port * info, unsigned long __user *value) +{ + void __iomem *base_addr; + int card,channel,chip,index; + unsigned long tmp; + + card = info->card; + channel = info->line - cy_card[card].first_line; + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<default_threshold = value & 0x0f; + return 0; +}/* set_default_threshold */ + + +static int +get_default_threshold(struct cyclades_port * info, unsigned long __user *value) +{ + return put_user(info->default_threshold,value); +}/* get_default_threshold */ + + +static int +set_timeout(struct cyclades_port * info, unsigned long value) +{ + void __iomem *base_addr; + int card,channel,chip,index; + unsigned long flags; + + card = info->card; + channel = info->line - cy_card[card].first_line; + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<card; + channel = info->line - cy_card[card].first_line; + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<default_timeout = value & 0xff; + return 0; +}/* set_default_timeout */ + + +static int +get_default_timeout(struct cyclades_port * info, unsigned long __user *value) +{ + return put_user(info->default_timeout,value); +}/* get_default_timeout */ + +/* + * This routine allows the tty driver to implement device- + * specific ioctl's. If the ioctl number passed in cmd is + * not recognized by the driver, it should return ENOIOCTLCMD. + */ +static int +cy_ioctl(struct tty_struct *tty, struct file * file, + unsigned int cmd, unsigned long arg) +{ + struct cyclades_port * info = (struct cyclades_port *)tty->driver_data; + struct cyclades_icount cprev, cnow; /* kernel counter temps */ + struct serial_icounter_struct __user *p_cuser; /* user space */ + int ret_val = 0; + unsigned long flags; + void __user *argp = (void __user *)arg; + + if (serial_paranoia_check(info, tty->name, "cy_ioctl")) + return -ENODEV; + +#ifdef CY_DEBUG_OTHER + printk("cyc:cy_ioctl ttyC%d, cmd = %x arg = %lx\n", + info->line, cmd, arg); /* */ +#endif + + switch (cmd) { + case CYGETMON: + ret_val = get_mon_info(info, argp); + break; + case CYGETTHRESH: + ret_val = get_threshold(info, argp); + break; + case CYSETTHRESH: + ret_val = set_threshold(info, arg); + break; + case CYGETDEFTHRESH: + ret_val = get_default_threshold(info, argp); + break; + case CYSETDEFTHRESH: + ret_val = set_default_threshold(info, arg); + break; + case CYGETTIMEOUT: + ret_val = get_timeout(info, argp); + break; + case CYSETTIMEOUT: + ret_val = set_timeout(info, arg); + break; + case CYGETDEFTIMEOUT: + ret_val = get_default_timeout(info, argp); + break; + case CYSETDEFTIMEOUT: + ret_val = set_default_timeout(info, arg); + break; + case CYSETRFLOW: + info->rflow = (int)arg; + ret_val = 0; + break; + case CYGETRFLOW: + ret_val = info->rflow; + break; + case CYSETRTSDTR_INV: + info->rtsdtr_inv = (int)arg; + ret_val = 0; + break; + case CYGETRTSDTR_INV: + ret_val = info->rtsdtr_inv; + break; + case CYGETCARDINFO: + if (copy_to_user(argp, &cy_card[info->card], + sizeof (struct cyclades_card))) { + ret_val = -EFAULT; + break; + } + ret_val = 0; + break; + case CYGETCD1400VER: + ret_val = info->chip_rev; + break; +#ifndef CONFIG_CYZ_INTR + case CYZSETPOLLCYCLE: + cyz_polling_cycle = (arg * HZ) / 1000; + ret_val = 0; + break; + case CYZGETPOLLCYCLE: + ret_val = (cyz_polling_cycle * 1000) / HZ; + break; +#endif /* CONFIG_CYZ_INTR */ + case CYSETWAIT: + info->closing_wait = (unsigned short)arg * HZ/100; + ret_val = 0; + break; + case CYGETWAIT: + ret_val = info->closing_wait / (HZ/100); + break; + case TIOCGSERIAL: + ret_val = get_serial_info(info, argp); + break; + case TIOCSSERIAL: + ret_val = set_serial_info(info, argp); + break; + case TIOCSERGETLSR: /* Get line status register */ + ret_val = get_lsr_info(info, argp); + break; + /* + * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change + * - mask passed in arg for lines of interest + * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) + * Caller should use TIOCGICOUNT to see which one it was + */ + case TIOCMIWAIT: + CY_LOCK(info, flags); + /* note the counters on entry */ + cprev = info->icount; + CY_UNLOCK(info, flags); + while (1) { + interruptible_sleep_on(&info->delta_msr_wait); + /* see if a signal did it */ + if (signal_pending(current)) { + return -ERESTARTSYS; + } + + CY_LOCK(info, flags); + cnow = info->icount; /* atomic copy */ + CY_UNLOCK(info, flags); + + if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && + cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { + return -EIO; /* no change => error */ + } + if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) || + ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) || + ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) || + ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)) ) { + return 0; + } + cprev = cnow; + } + /* NOTREACHED */ + + /* + * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) + * Return: write counters to the user passed counter struct + * NB: both 1->0 and 0->1 transitions are counted except for + * RI where only 0->1 is counted. + */ + case TIOCGICOUNT: + CY_LOCK(info, flags); + cnow = info->icount; + CY_UNLOCK(info, flags); + p_cuser = argp; + ret_val = put_user(cnow.cts, &p_cuser->cts); + if (ret_val) return ret_val; + ret_val = put_user(cnow.dsr, &p_cuser->dsr); + if (ret_val) return ret_val; + ret_val = put_user(cnow.rng, &p_cuser->rng); + if (ret_val) return ret_val; + ret_val = put_user(cnow.dcd, &p_cuser->dcd); + if (ret_val) return ret_val; + ret_val = put_user(cnow.rx, &p_cuser->rx); + if (ret_val) return ret_val; + ret_val = put_user(cnow.tx, &p_cuser->tx); + if (ret_val) return ret_val; + ret_val = put_user(cnow.frame, &p_cuser->frame); + if (ret_val) return ret_val; + ret_val = put_user(cnow.overrun, &p_cuser->overrun); + if (ret_val) return ret_val; + ret_val = put_user(cnow.parity, &p_cuser->parity); + if (ret_val) return ret_val; + ret_val = put_user(cnow.brk, &p_cuser->brk); + if (ret_val) return ret_val; + ret_val = put_user(cnow.buf_overrun, &p_cuser->buf_overrun); + if (ret_val) return ret_val; + ret_val = 0; + break; + default: + ret_val = -ENOIOCTLCMD; + } + +#ifdef CY_DEBUG_OTHER + printk(" cyc:cy_ioctl done\n"); +#endif + + return ret_val; +} /* cy_ioctl */ + + +/* + * This routine allows the tty driver to be notified when + * device's termios settings have changed. Note that a + * well-designed tty driver should be prepared to accept the case + * where old == NULL, and try to do something rational. + */ +static void +cy_set_termios(struct tty_struct *tty, struct termios * old_termios) +{ + struct cyclades_port *info = (struct cyclades_port *)tty->driver_data; + +#ifdef CY_DEBUG_OTHER + printk("cyc:cy_set_termios ttyC%d\n", info->line); +#endif + + if ((tty->termios->c_cflag == old_termios->c_cflag) && + ((tty->termios->c_iflag & (IXON|IXANY)) == + (old_termios->c_iflag & (IXON|IXANY)))) + return; + set_line_char(info); + + if ((old_termios->c_cflag & CRTSCTS) && + !(tty->termios->c_cflag & CRTSCTS)) { + tty->hw_stopped = 0; + cy_start(tty); + } +#if 0 + /* + * No need to wake up processes in open wait, since they + * sample the CLOCAL flag once, and don't recheck it. + * XXX It's not clear whether the current behavior is correct + * or not. Hence, this may change..... + */ + if (!(old_termios->c_cflag & CLOCAL) && + (tty->termios->c_cflag & CLOCAL)) + wake_up_interruptible(&info->open_wait); +#endif + + return; +} /* cy_set_termios */ + +/* This function is used to send a high-priority XON/XOFF character to + the device. +*/ +static void +cy_send_xchar (struct tty_struct *tty, char ch) +{ + struct cyclades_port *info = (struct cyclades_port *) tty->driver_data; + int card, channel; + + if (serial_paranoia_check (info, tty->name, "cy_send_xchar")) + return; + + info->x_char = ch; + + if (ch) + cy_start (tty); + + card = info->card; + channel = info->line - cy_card[card].first_line; + + if (IS_CYC_Z (cy_card[card])) { + if (ch == STOP_CHAR (tty)) + cyz_issue_cmd (&cy_card[card], channel, C_CM_SENDXOFF, 0L); + else if (ch == START_CHAR (tty)) + cyz_issue_cmd (&cy_card[card], channel, C_CM_SENDXON, 0L); + } +} + +/* This routine is called by the upper-layer tty layer to signal + that incoming characters should be throttled because the input + buffers are close to full. + */ +static void +cy_throttle(struct tty_struct * tty) +{ + struct cyclades_port *info = (struct cyclades_port *)tty->driver_data; + unsigned long flags; + void __iomem *base_addr; + int card,chip,channel,index; + +#ifdef CY_DEBUG_THROTTLE + char buf[64]; + + printk("cyc:throttle %s: %d....ttyC%d\n", + tty_name(tty, buf), + tty->ldisc.chars_in_buffer(tty), info->line); +#endif + + if (serial_paranoia_check(info, tty->name, "cy_throttle")){ + return; + } + + card = info->card; + + if (I_IXOFF(tty)) { + if (!IS_CYC_Z (cy_card[card])) + cy_send_xchar (tty, STOP_CHAR (tty)); + else + info->throttle = 1; + } + + if (tty->termios->c_cflag & CRTSCTS) { + channel = info->line - cy_card[card].first_line; + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<rtsdtr_inv) { + cy_writeb(base_addr+(CyMSVR2<throttle = 1; + } + } + + return; +} /* cy_throttle */ + + +/* + * This routine notifies the tty driver that it should signal + * that characters can now be sent to the tty without fear of + * overrunning the input buffers of the line disciplines. + */ +static void +cy_unthrottle(struct tty_struct * tty) +{ + struct cyclades_port *info = (struct cyclades_port *)tty->driver_data; + unsigned long flags; + void __iomem *base_addr; + int card,chip,channel,index; + +#ifdef CY_DEBUG_THROTTLE + char buf[64]; + + printk("cyc:unthrottle %s: %d....ttyC%d\n", + tty_name(tty, buf), + tty->ldisc.chars_in_buffer(tty), info->line); +#endif + + if (serial_paranoia_check(info, tty->name, "cy_unthrottle")){ + return; + } + + if (I_IXOFF(tty)) { + if (info->x_char) + info->x_char = 0; + else + cy_send_xchar (tty, START_CHAR (tty)); + } + + if (tty->termios->c_cflag & CRTSCTS) { + card = info->card; + channel = info->line - cy_card[card].first_line; + if (!IS_CYC_Z(cy_card[card])) { + chip = channel>>2; + channel &= 0x03; + index = cy_card[card].bus_index; + base_addr = cy_card[card].base_addr + (cy_chip_offset[chip]<rtsdtr_inv) { + cy_writeb(base_addr+(CyMSVR2<throttle = 0; + } + } + + return; +} /* cy_unthrottle */ + + +/* cy_start and cy_stop provide software output flow control as a + function of XON/XOFF, software CTS, and other such stuff. +*/ +static void +cy_stop(struct tty_struct *tty) +{ + struct cyclades_card *cinfo; + struct cyclades_port *info = (struct cyclades_port *)tty->driver_data; + void __iomem *base_addr; + int chip,channel,index; + unsigned long flags; + +#ifdef CY_DEBUG_OTHER + printk("cyc:cy_stop ttyC%d\n", info->line); /* */ +#endif + + if (serial_paranoia_check(info, tty->name, "cy_stop")) + return; + + cinfo = &cy_card[info->card]; + channel = info->line - cinfo->first_line; + if (!IS_CYC_Z(*cinfo)) { + index = cinfo->bus_index; + chip = channel>>2; + channel &= 0x03; + base_addr = cy_card[info->card].base_addr + (cy_chip_offset[chip]<driver_data; + void __iomem *base_addr; + int chip,channel,index; + unsigned long flags; + +#ifdef CY_DEBUG_OTHER + printk("cyc:cy_start ttyC%d\n", info->line); /* */ +#endif + + if (serial_paranoia_check(info, tty->name, "cy_start")) + return; + + cinfo = &cy_card[info->card]; + channel = info->line - cinfo->first_line; + index = cinfo->bus_index; + if (!IS_CYC_Z(*cinfo)) { + chip = channel>>2; + channel &= 0x03; + base_addr = cy_card[info->card].base_addr + (cy_chip_offset[chip]<driver_data; + int card, channel, retval; + unsigned long flags; + +#ifdef CY_DEBUG_IO + printk("cyc:cy_flush_buffer ttyC%d\n", info->line); /* */ +#endif + + if (serial_paranoia_check(info, tty->name, "cy_flush_buffer")) + return; + + card = info->card; + channel = (info->line) - (cy_card[card].first_line); + + CY_LOCK(info, flags); + info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; + CY_UNLOCK(info, flags); + + if (IS_CYC_Z(cy_card[card])) { /* If it is a Z card, flush the on-board + buffers as well */ + CY_LOCK(info, flags); + retval = cyz_issue_cmd(&cy_card[card], channel, C_CM_FLUSH_TX, 0L); + if (retval != 0) { + printk("cyc: flush_buffer retval on ttyC%d was %x\n", + info->line, retval); + } + CY_UNLOCK(info, flags); + } + tty_wakeup(tty); + wake_up_interruptible(&tty->write_wait); +} /* cy_flush_buffer */ + + +/* + * cy_hangup() --- called by tty_hangup() when a hangup is signaled. + */ +static void +cy_hangup(struct tty_struct *tty) +{ + struct cyclades_port * info = (struct cyclades_port *)tty->driver_data; + +#ifdef CY_DEBUG_OTHER + printk("cyc:cy_hangup ttyC%d\n", info->line); /* */ +#endif + + if (serial_paranoia_check(info, tty->name, "cy_hangup")) + return; + + cy_flush_buffer(tty); + shutdown(info); + info->event = 0; + info->count = 0; +#ifdef CY_DEBUG_COUNT + printk("cyc:cy_hangup (%d): setting count to 0\n", current->pid); +#endif + info->tty = NULL; + info->flags &= ~ASYNC_NORMAL_ACTIVE; + wake_up_interruptible(&info->open_wait); +} /* cy_hangup */ + + +/* + * --------------------------------------------------------------------- + * cy_init() and friends + * + * cy_init() is called at boot-time to initialize the serial driver. + * --------------------------------------------------------------------- + */ + +/* initialize chips on Cyclom-Y card -- return number of valid + chips (which is number of ports/4) */ +static unsigned short __init +cyy_init_card(void __iomem *true_base_addr,int index) +{ + unsigned int chip_number; + void __iomem *base_addr; + + cy_writeb(true_base_addr+(Cy_HwReset<= CD1400_REV_J){ + /* It is a CD1400 rev. J or later */ + /* Impossible to reach 5ms with this chip. + Changed to 2ms instead (f = 500 Hz). */ + cy_writeb(base_addr+(CyPPR< NR_PORTS) { + printk("Cyclom-Y/ISA found at 0x%lx ", + (unsigned long) cy_isa_address); + printk("but no more channels are available.\n"); + printk("Change NR_PORTS in cyclades.c and recompile kernel.\n"); + return(nboard); + } + /* fill the next cy_card structure available */ + for (j = 0 ; j < NR_CARDS ; j++) { + if (cy_card[j].base_addr == 0) break; + } + if (j == NR_CARDS) { /* no more cy_cards available */ + printk("Cyclom-Y/ISA found at 0x%lx ", + (unsigned long) cy_isa_address); + printk("but no more cards can be used .\n"); + printk("Change NR_CARDS in cyclades.c and recompile kernel.\n"); + return(nboard); + } + + /* allocate IRQ */ + if(request_irq(cy_isa_irq, cyy_interrupt, + SA_INTERRUPT, "Cyclom-Y", &cy_card[j])) + { + printk("Cyclom-Y/ISA found at 0x%lx ", + (unsigned long) cy_isa_address); + printk("but could not allocate IRQ#%d.\n", + cy_isa_irq); + return(nboard); + } + + /* set cy_card */ + cy_card[j].base_addr = cy_isa_address; + cy_card[j].ctl_addr = NULL; + cy_card[j].irq = (int) cy_isa_irq; + cy_card[j].bus_index = 0; + cy_card[j].first_line = cy_next_channel; + cy_card[j].num_chips = cy_isa_nchan/4; + nboard++; + + /* print message */ + printk("Cyclom-Y/ISA #%d: 0x%lx-0x%lx, IRQ%d, ", + j+1, (unsigned long) cy_isa_address, + (unsigned long)(cy_isa_address + (CyISA_Ywin - 1)), + cy_isa_irq); + printk("%d channels starting from port %d.\n", + cy_isa_nchan, cy_next_channel); + cy_next_channel += cy_isa_nchan; + } + return(nboard); +#else + return(0); +#endif /* CONFIG_ISA */ +} /* cy_detect_isa */ + +static void +plx_init(void __iomem *addr, uclong initctl) +{ + /* Reset PLX */ + cy_writel(addr + initctl, cy_readl(addr + initctl) | 0x40000000); + udelay(100L); + cy_writel(addr + initctl, cy_readl(addr + initctl) & ~0x40000000); + + /* Reload Config. Registers from EEPROM */ + cy_writel(addr + initctl, cy_readl(addr + initctl) | 0x20000000); + udelay(100L); + cy_writel(addr + initctl, cy_readl(addr + initctl) & ~0x20000000); +} + +/* + * --------------------------------------------------------------------- + * cy_detect_pci() - Test PCI bus presence and Cyclom-Ye/PCI. + * sets global variables and return the number of PCI boards found. + * --------------------------------------------------------------------- + */ +static int __init +cy_detect_pci(void) +{ +#ifdef CONFIG_PCI + + struct pci_dev *pdev = NULL; + unsigned char cyy_rev_id; + unsigned char cy_pci_irq = 0; + uclong cy_pci_phys0, cy_pci_phys2; + void __iomem *cy_pci_addr0, *cy_pci_addr2; + unsigned short i,j,cy_pci_nchan, plx_ver; + unsigned short device_id,dev_index = 0; + uclong mailbox; + uclong ZeIndex = 0; + void __iomem *Ze_addr0[NR_CARDS], *Ze_addr2[NR_CARDS]; + uclong Ze_phys0[NR_CARDS], Ze_phys2[NR_CARDS]; + unsigned char Ze_irq[NR_CARDS]; + struct pci_dev *Ze_pdev[NR_CARDS]; + + for (i = 0; i < NR_CARDS; i++) { + /* look for a Cyclades card by vendor and device id */ + while((device_id = cy_pci_dev_id[dev_index]) != 0) { + if((pdev = pci_get_device(PCI_VENDOR_ID_CYCLADES, + device_id, pdev)) == NULL) { + dev_index++; /* try next device id */ + } else { + break; /* found a board */ + } + } + + if (device_id == 0) + break; + + if (pci_enable_device(pdev)) + continue; + + /* read PCI configuration area */ + cy_pci_irq = pdev->irq; + cy_pci_phys0 = pci_resource_start(pdev, 0); + cy_pci_phys2 = pci_resource_start(pdev, 2); + pci_read_config_byte(pdev, PCI_REVISION_ID, &cyy_rev_id); + + device_id &= ~PCI_DEVICE_ID_MASK; + + if ((device_id == PCI_DEVICE_ID_CYCLOM_Y_Lo) + || (device_id == PCI_DEVICE_ID_CYCLOM_Y_Hi)){ +#ifdef CY_PCI_DEBUG + printk("Cyclom-Y/PCI (bus=0x0%x, pci_id=0x%x, ", + pdev->bus->number, pdev->devfn); + printk("rev_id=%d) IRQ%d\n", + cyy_rev_id, (int)cy_pci_irq); + printk("Cyclom-Y/PCI:found winaddr=0x%lx ctladdr=0x%lx\n", + (ulong)cy_pci_phys2, (ulong)cy_pci_phys0); +#endif + + if (pci_resource_flags(pdev, 2) & IORESOURCE_IO) { + printk(" Warning: PCI I/O bit incorrectly set. " + "Ignoring it...\n"); + pdev->resource[2].flags &= ~IORESOURCE_IO; + } + + /* Although we don't use this I/O region, we should + request it from the kernel anyway, to avoid problems + with other drivers accessing it. */ + if (pci_request_regions(pdev, "Cyclom-Y") != 0) { + printk(KERN_ERR "cyclades: failed to reserve PCI resources\n"); + continue; + } + +#if defined(__alpha__) + if (device_id == PCI_DEVICE_ID_CYCLOM_Y_Lo) { /* below 1M? */ + printk("Cyclom-Y/PCI (bus=0x0%x, pci_id=0x%x, ", + pdev->bus->number, pdev->devfn); + printk("rev_id=%d) IRQ%d\n", + cyy_rev_id, (int)cy_pci_irq); + printk("Cyclom-Y/PCI:found winaddr=0x%lx ctladdr=0x%lx\n", + (ulong)cy_pci_phys2, (ulong)cy_pci_phys0); + printk("Cyclom-Y/PCI not supported for low addresses in " + "Alpha systems.\n"); + i--; + continue; + } +#endif + cy_pci_addr0 = ioremap(cy_pci_phys0, CyPCI_Yctl); + cy_pci_addr2 = ioremap(cy_pci_phys2, CyPCI_Ywin); + +#ifdef CY_PCI_DEBUG + printk("Cyclom-Y/PCI: relocate winaddr=0x%lx ctladdr=0x%lx\n", + (u_long)cy_pci_addr2, (u_long)cy_pci_addr0); +#endif + cy_pci_nchan = (unsigned short)(CyPORTS_PER_CHIP * + cyy_init_card(cy_pci_addr2, 1)); + if(cy_pci_nchan == 0) { + printk("Cyclom-Y PCI host card with "); + printk("no Serial-Modules at 0x%lx.\n", + (ulong) cy_pci_phys2); + i--; + continue; + } + if((cy_next_channel+cy_pci_nchan) > NR_PORTS) { + printk("Cyclom-Y/PCI found at 0x%lx ", + (ulong) cy_pci_phys2); + printk("but no channels are available.\n"); + printk("Change NR_PORTS in cyclades.c and recompile kernel.\n"); + return(i); + } + /* fill the next cy_card structure available */ + for (j = 0 ; j < NR_CARDS ; j++) { + if (cy_card[j].base_addr == 0) break; + } + if (j == NR_CARDS) { /* no more cy_cards available */ + printk("Cyclom-Y/PCI found at 0x%lx ", + (ulong) cy_pci_phys2); + printk("but no more cards can be used.\n"); + printk("Change NR_CARDS in cyclades.c and recompile kernel.\n"); + return(i); + } + + /* allocate IRQ */ + if(request_irq(cy_pci_irq, cyy_interrupt, + SA_SHIRQ, "Cyclom-Y", &cy_card[j])) + { + printk("Cyclom-Y/PCI found at 0x%lx ", + (ulong) cy_pci_phys2); + printk("but could not allocate IRQ%d.\n", + cy_pci_irq); + return(i); + } + + /* set cy_card */ + cy_card[j].base_phys = (ulong)cy_pci_phys2; + cy_card[j].ctl_phys = (ulong)cy_pci_phys0; + cy_card[j].base_addr = cy_pci_addr2; + cy_card[j].ctl_addr = cy_pci_addr0; + cy_card[j].irq = (int) cy_pci_irq; + cy_card[j].bus_index = 1; + cy_card[j].first_line = cy_next_channel; + cy_card[j].num_chips = cy_pci_nchan/4; + cy_card[j].pdev = pdev; + + /* enable interrupts in the PCI interface */ + plx_ver = cy_readb(cy_pci_addr2 + CyPLX_VER) & 0x0f; + switch (plx_ver) { + case PLX_9050: + + cy_writeb(cy_pci_addr0+0x4c, 0x43); + break; + + case PLX_9060: + case PLX_9080: + default: /* Old boards, use PLX_9060 */ + + plx_init(cy_pci_addr0, 0x6c); + /* For some yet unknown reason, once the PLX9060 reloads + the EEPROM, the IRQ is lost and, thus, we have to + re-write it to the PCI config. registers. + This will remain here until we find a permanent fix. */ + pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, cy_pci_irq); + + cy_writew(cy_pci_addr0+0x68, + cy_readw(cy_pci_addr0+0x68)|0x0900); + break; + } + + /* print message */ + printk("Cyclom-Y/PCI #%d: 0x%lx-0x%lx, IRQ%d, ", + j+1, + (ulong)cy_pci_phys2, + (ulong)(cy_pci_phys2 + CyPCI_Ywin - 1), + (int)cy_pci_irq); + printk("%d channels starting from port %d.\n", + cy_pci_nchan, cy_next_channel); + + cy_next_channel += cy_pci_nchan; + }else if (device_id == PCI_DEVICE_ID_CYCLOM_Z_Lo){ + /* print message */ + printk("Cyclades-Z/PCI (bus=0x0%x, pci_id=0x%x, ", + pdev->bus->number, pdev->devfn); + printk("rev_id=%d) IRQ%d\n", + cyy_rev_id, (int)cy_pci_irq); + printk("Cyclades-Z/PCI: found winaddr=0x%lx ctladdr=0x%lx\n", + (ulong)cy_pci_phys2, (ulong)cy_pci_phys0); + printk("Cyclades-Z/PCI not supported for low addresses\n"); + break; + }else if (device_id == PCI_DEVICE_ID_CYCLOM_Z_Hi){ +#ifdef CY_PCI_DEBUG + printk("Cyclades-Z/PCI (bus=0x0%x, pci_id=0x%x, ", + pdev->bus->number, pdev->devfn); + printk("rev_id=%d) IRQ%d\n", + cyy_rev_id, (int)cy_pci_irq); + printk("Cyclades-Z/PCI: found winaddr=0x%lx ctladdr=0x%lx\n", + (ulong)cy_pci_phys2, (ulong)cy_pci_phys0); +#endif + cy_pci_addr0 = ioremap(cy_pci_phys0, CyPCI_Zctl); + + /* Disable interrupts on the PLX before resetting it */ + cy_writew(cy_pci_addr0+0x68, + cy_readw(cy_pci_addr0+0x68) & ~0x0900); + + plx_init(cy_pci_addr0, 0x6c); + /* For some yet unknown reason, once the PLX9060 reloads + the EEPROM, the IRQ is lost and, thus, we have to + re-write it to the PCI config. registers. + This will remain here until we find a permanent fix. */ + pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, cy_pci_irq); + + mailbox = (uclong)cy_readl(&((struct RUNTIME_9060 __iomem *) + cy_pci_addr0)->mail_box_0); + + if (pci_resource_flags(pdev, 2) & IORESOURCE_IO) { + printk(" Warning: PCI I/O bit incorrectly set. " + "Ignoring it...\n"); + pdev->resource[2].flags &= ~IORESOURCE_IO; + } + + /* Although we don't use this I/O region, we should + request it from the kernel anyway, to avoid problems + with other drivers accessing it. */ + if (pci_request_regions(pdev, "Cyclades-Z") != 0) { + printk(KERN_ERR "cyclades: failed to reserve PCI resources\n"); + continue; + } + + if (mailbox == ZE_V1) { + cy_pci_addr2 = ioremap(cy_pci_phys2, CyPCI_Ze_win); + if (ZeIndex == NR_CARDS) { + printk("Cyclades-Ze/PCI found at 0x%lx ", + (ulong)cy_pci_phys2); + printk("but no more cards can be used.\n"); + printk("Change NR_CARDS in cyclades.c and recompile kernel.\n"); + } else { + Ze_phys0[ZeIndex] = cy_pci_phys0; + Ze_phys2[ZeIndex] = cy_pci_phys2; + Ze_addr0[ZeIndex] = cy_pci_addr0; + Ze_addr2[ZeIndex] = cy_pci_addr2; + Ze_irq[ZeIndex] = cy_pci_irq; + Ze_pdev[ZeIndex] = pdev; + ZeIndex++; + } + i--; + continue; + } else { + cy_pci_addr2 = ioremap(cy_pci_phys2, CyPCI_Zwin); + } + +#ifdef CY_PCI_DEBUG + printk("Cyclades-Z/PCI: relocate winaddr=0x%lx ctladdr=0x%lx\n", + (ulong)cy_pci_addr2, (ulong)cy_pci_addr0); + if (mailbox == ZO_V1) { + cy_writel(&((struct RUNTIME_9060 *) + (cy_pci_addr0))->loc_addr_base, WIN_CREG); + PAUSE + printk("Cyclades-8Zo/PCI: FPGA id %lx, ver %lx\n", + (ulong)(0xff & cy_readl(&((struct CUSTOM_REG *) + (cy_pci_addr2))->fpga_id)), + (ulong)(0xff & cy_readl(&((struct CUSTOM_REG *) + (cy_pci_addr2))->fpga_version))); + cy_writel(&((struct RUNTIME_9060 *) + (cy_pci_addr0))->loc_addr_base, WIN_RAM); + } else { + printk("Cyclades-Z/PCI: New Cyclades-Z board. FPGA not loaded\n"); + } +#endif + /* The following clears the firmware id word. This ensures + that the driver will not attempt to talk to the board + until it has been properly initialized. + */ + PAUSE + if ((mailbox == ZO_V1) || (mailbox == ZO_V2)) + cy_writel(cy_pci_addr2 + ID_ADDRESS, 0L); + + /* This must be a Cyclades-8Zo/PCI. The extendable + version will have a different device_id and will + be allocated its maximum number of ports. */ + cy_pci_nchan = 8; + + if((cy_next_channel+cy_pci_nchan) > NR_PORTS) { + printk("Cyclades-8Zo/PCI found at 0x%lx ", + (ulong)cy_pci_phys2); + printk("but no channels are available.\n"); + printk("Change NR_PORTS in cyclades.c and recompile kernel.\n"); + return(i); + } + + /* fill the next cy_card structure available */ + for (j = 0 ; j < NR_CARDS ; j++) { + if (cy_card[j].base_addr == 0) break; + } + if (j == NR_CARDS) { /* no more cy_cards available */ + printk("Cyclades-8Zo/PCI found at 0x%lx ", + (ulong)cy_pci_phys2); + printk("but no more cards can be used.\n"); + printk("Change NR_CARDS in cyclades.c and recompile kernel.\n"); + return(i); + } + +#ifdef CONFIG_CYZ_INTR + /* allocate IRQ only if board has an IRQ */ + if( (cy_pci_irq != 0) && (cy_pci_irq != 255) ) { + if(request_irq(cy_pci_irq, cyz_interrupt, + SA_SHIRQ, "Cyclades-Z", &cy_card[j])) + { + printk("Cyclom-8Zo/PCI found at 0x%lx ", + (ulong) cy_pci_phys2); + printk("but could not allocate IRQ%d.\n", + cy_pci_irq); + return(i); + } + } +#endif /* CONFIG_CYZ_INTR */ + + + /* set cy_card */ + cy_card[j].base_phys = cy_pci_phys2; + cy_card[j].ctl_phys = cy_pci_phys0; + cy_card[j].base_addr = cy_pci_addr2; + cy_card[j].ctl_addr = cy_pci_addr0; + cy_card[j].irq = (int) cy_pci_irq; + cy_card[j].bus_index = 1; + cy_card[j].first_line = cy_next_channel; + cy_card[j].num_chips = -1; + cy_card[j].pdev = pdev; + + /* print message */ +#ifdef CONFIG_CYZ_INTR + /* don't report IRQ if board is no IRQ */ + if( (cy_pci_irq != 0) && (cy_pci_irq != 255) ) + printk("Cyclades-8Zo/PCI #%d: 0x%lx-0x%lx, IRQ%d, ", + j+1,(ulong)cy_pci_phys2, + (ulong)(cy_pci_phys2 + CyPCI_Zwin - 1), + (int)cy_pci_irq); + else +#endif /* CONFIG_CYZ_INTR */ + printk("Cyclades-8Zo/PCI #%d: 0x%lx-0x%lx, ", + j+1,(ulong)cy_pci_phys2, + (ulong)(cy_pci_phys2 + CyPCI_Zwin - 1)); + + printk("%d channels starting from port %d.\n", + cy_pci_nchan,cy_next_channel); + cy_next_channel += cy_pci_nchan; + } + } + + for (; ZeIndex != 0 && i < NR_CARDS; i++) { + cy_pci_phys0 = Ze_phys0[0]; + cy_pci_phys2 = Ze_phys2[0]; + cy_pci_addr0 = Ze_addr0[0]; + cy_pci_addr2 = Ze_addr2[0]; + cy_pci_irq = Ze_irq[0]; + pdev = Ze_pdev[0]; + for (j = 0 ; j < ZeIndex-1 ; j++) { + Ze_phys0[j] = Ze_phys0[j+1]; + Ze_phys2[j] = Ze_phys2[j+1]; + Ze_addr0[j] = Ze_addr0[j+1]; + Ze_addr2[j] = Ze_addr2[j+1]; + Ze_irq[j] = Ze_irq[j+1]; + Ze_pdev[j] = Ze_pdev[j+1]; + } + ZeIndex--; + mailbox = (uclong)cy_readl(&((struct RUNTIME_9060 __iomem *) + cy_pci_addr0)->mail_box_0); +#ifdef CY_PCI_DEBUG + printk("Cyclades-Z/PCI: relocate winaddr=0x%lx ctladdr=0x%lx\n", + (ulong)cy_pci_addr2, (ulong)cy_pci_addr0); + printk("Cyclades-Z/PCI: New Cyclades-Z board. FPGA not loaded\n"); +#endif + PAUSE + /* This must be the new Cyclades-Ze/PCI. */ + cy_pci_nchan = ZE_V1_NPORTS; + + if((cy_next_channel+cy_pci_nchan) > NR_PORTS) { + printk("Cyclades-Ze/PCI found at 0x%lx ", + (ulong)cy_pci_phys2); + printk("but no channels are available.\n"); + printk("Change NR_PORTS in cyclades.c and recompile kernel.\n"); + return(i); + } + + /* fill the next cy_card structure available */ + for (j = 0 ; j < NR_CARDS ; j++) { + if (cy_card[j].base_addr == 0) break; + } + if (j == NR_CARDS) { /* no more cy_cards available */ + printk("Cyclades-Ze/PCI found at 0x%lx ", + (ulong)cy_pci_phys2); + printk("but no more cards can be used.\n"); + printk("Change NR_CARDS in cyclades.c and recompile kernel.\n"); + return(i); + } + +#ifdef CONFIG_CYZ_INTR + /* allocate IRQ only if board has an IRQ */ + if( (cy_pci_irq != 0) && (cy_pci_irq != 255) ) { + if(request_irq(cy_pci_irq, cyz_interrupt, + SA_SHIRQ, "Cyclades-Z", &cy_card[j])) + { + printk("Cyclom-Ze/PCI found at 0x%lx ", + (ulong) cy_pci_phys2); + printk("but could not allocate IRQ%d.\n", + cy_pci_irq); + return(i); + } + } +#endif /* CONFIG_CYZ_INTR */ + + /* set cy_card */ + cy_card[j].base_phys = cy_pci_phys2; + cy_card[j].ctl_phys = cy_pci_phys0; + cy_card[j].base_addr = cy_pci_addr2; + cy_card[j].ctl_addr = cy_pci_addr0; + cy_card[j].irq = (int) cy_pci_irq; + cy_card[j].bus_index = 1; + cy_card[j].first_line = cy_next_channel; + cy_card[j].num_chips = -1; + cy_card[j].pdev = pdev; + + /* print message */ +#ifdef CONFIG_CYZ_INTR + /* don't report IRQ if board is no IRQ */ + if( (cy_pci_irq != 0) && (cy_pci_irq != 255) ) + printk("Cyclades-Ze/PCI #%d: 0x%lx-0x%lx, IRQ%d, ", + j+1,(ulong)cy_pci_phys2, + (ulong)(cy_pci_phys2 + CyPCI_Ze_win - 1), + (int)cy_pci_irq); + else +#endif /* CONFIG_CYZ_INTR */ + printk("Cyclades-Ze/PCI #%d: 0x%lx-0x%lx, ", + j+1,(ulong)cy_pci_phys2, + (ulong)(cy_pci_phys2 + CyPCI_Ze_win - 1)); + + printk("%d channels starting from port %d.\n", + cy_pci_nchan,cy_next_channel); + cy_next_channel += cy_pci_nchan; + } + if (ZeIndex != 0) { + printk("Cyclades-Ze/PCI found at 0x%x ", + (unsigned int) Ze_phys2[0]); + printk("but no more cards can be used.\n"); + printk("Change NR_CARDS in cyclades.c and recompile kernel.\n"); + } + return(i); +#else + return(0); +#endif /* ifdef CONFIG_PCI */ +} /* cy_detect_pci */ + + +/* + * This routine prints out the appropriate serial driver version number + * and identifies which options were configured into this driver. + */ +static inline void +show_version(void) +{ + char *rcsvers, *rcsdate, *tmp; + rcsvers = strchr(rcsid, ' '); rcsvers++; + tmp = strchr(rcsvers, ' '); *tmp++ = '\0'; + rcsdate = strchr(tmp, ' '); rcsdate++; + tmp = strrchr(rcsdate, ' '); *tmp = '\0'; + printk("Cyclades driver %s %s\n", + rcsvers, rcsdate); + printk(" built %s %s\n", + __DATE__, __TIME__); +} /* show_version */ + +static int +cyclades_get_proc_info(char *buf, char **start, off_t offset, int length, + int *eof, void *data) +{ + struct cyclades_port *info; + int i; + int len=0; + off_t begin=0; + off_t pos=0; + int size; + __u32 cur_jifs = jiffies; + + size = sprintf(buf, "Dev TimeOpen BytesOut IdleOut BytesIn IdleIn Overruns Ldisc\n"); + + pos += size; + len += size; + + /* Output one line for each known port */ + for (i = 0; i < NR_PORTS && cy_port[i].line >= 0; i++) { + info = &cy_port[i]; + + if (info->count) + size = sprintf(buf+len, + "%3d %8lu %10lu %8lu %10lu %8lu %9lu %6ld\n", + info->line, + JIFFIES_DIFF(info->idle_stats.in_use, cur_jifs) / HZ, + info->idle_stats.xmit_bytes, + JIFFIES_DIFF(info->idle_stats.xmit_idle, cur_jifs) / HZ, + info->idle_stats.recv_bytes, + JIFFIES_DIFF(info->idle_stats.recv_idle, cur_jifs) / HZ, + info->idle_stats.overruns, + (long) info->tty->ldisc.num); + else + size = sprintf(buf+len, + "%3d %8lu %10lu %8lu %10lu %8lu %9lu %6ld\n", + info->line, 0L, 0L, 0L, 0L, 0L, 0L, 0L); + len += size; + pos = begin + len; + + if (pos < offset) { + len = 0; + begin = pos; + } + if (pos > offset + length) + goto done; + } + *eof = 1; +done: + *start = buf + (offset - begin); /* Start of wanted data */ + len -= (offset - begin); /* Start slop */ + if (len > length) + len = length; /* Ending slop */ + if (len < 0) + len = 0; + return len; +} + +/* The serial driver boot-time initialization code! + Hardware I/O ports are mapped to character special devices on a + first found, first allocated manner. That is, this code searches + for Cyclom cards in the system. As each is found, it is probed + to discover how many chips (and thus how many ports) are present. + These ports are mapped to the tty ports 32 and upward in monotonic + fashion. If an 8-port card is replaced with a 16-port card, the + port mapping on a following card will shift. + + This approach is different from what is used in the other serial + device driver because the Cyclom is more properly a multiplexer, + not just an aggregation of serial ports on one card. + + If there are more cards with more ports than have been + statically allocated above, a warning is printed and the + extra ports are ignored. + */ + +static struct tty_operations cy_ops = { + .open = cy_open, + .close = cy_close, + .write = cy_write, + .put_char = cy_put_char, + .flush_chars = cy_flush_chars, + .write_room = cy_write_room, + .chars_in_buffer = cy_chars_in_buffer, + .flush_buffer = cy_flush_buffer, + .ioctl = cy_ioctl, + .throttle = cy_throttle, + .unthrottle = cy_unthrottle, + .set_termios = cy_set_termios, + .stop = cy_stop, + .start = cy_start, + .hangup = cy_hangup, + .break_ctl = cy_break, + .wait_until_sent = cy_wait_until_sent, + .read_proc = cyclades_get_proc_info, + .tiocmget = cy_tiocmget, + .tiocmset = cy_tiocmset, +}; + +static int __init +cy_init(void) +{ + struct cyclades_port *info; + struct cyclades_card *cinfo; + int number_z_boards = 0; + int board,port,i,index; + unsigned long mailbox; + unsigned short chip_number; + int nports; + + cy_serial_driver = alloc_tty_driver(NR_PORTS); + if (!cy_serial_driver) + return -ENOMEM; + show_version(); + + /* Initialize the tty_driver structure */ + + cy_serial_driver->owner = THIS_MODULE; + cy_serial_driver->driver_name = "cyclades"; + cy_serial_driver->name = "ttyC"; + cy_serial_driver->devfs_name = "tts/C"; + cy_serial_driver->major = CYCLADES_MAJOR; + cy_serial_driver->minor_start = 0; + cy_serial_driver->type = TTY_DRIVER_TYPE_SERIAL; + cy_serial_driver->subtype = SERIAL_TYPE_NORMAL; + cy_serial_driver->init_termios = tty_std_termios; + cy_serial_driver->init_termios.c_cflag = + B9600 | CS8 | CREAD | HUPCL | CLOCAL; + cy_serial_driver->flags = TTY_DRIVER_REAL_RAW; + tty_set_operations(cy_serial_driver, &cy_ops); + + if (tty_register_driver(cy_serial_driver)) + panic("Couldn't register Cyclades serial driver\n"); + + for (i = 0; i < NR_CARDS; i++) { + /* base_addr=0 indicates board not found */ + cy_card[i].base_addr = NULL; + } + + /* the code below is responsible to find the boards. Each different + type of board has its own detection routine. If a board is found, + the next cy_card structure available is set by the detection + routine. These functions are responsible for checking the + availability of cy_card and cy_port data structures and updating + the cy_next_channel. */ + + /* look for isa boards */ + cy_isa_nboard = cy_detect_isa(); + + /* look for pci boards */ + cy_pci_nboard = cy_detect_pci(); + + cy_nboard = cy_isa_nboard + cy_pci_nboard; + + /* invalidate remaining cy_card structures */ + for (i = 0 ; i < NR_CARDS ; i++) { + if (cy_card[i].base_addr == 0) { + cy_card[i].first_line = -1; + cy_card[i].ctl_addr = NULL; + cy_card[i].irq = 0; + cy_card[i].bus_index = 0; + cy_card[i].first_line = 0; + cy_card[i].num_chips = 0; + } + } + /* invalidate remaining cy_port structures */ + for (i = cy_next_channel ; i < NR_PORTS ; i++) { + cy_port[i].line = -1; + cy_port[i].magic = -1; + } + + /* initialize per-port data structures for each valid board found */ + for (board = 0 ; board < cy_nboard ; board++) { + cinfo = &cy_card[board]; + if (cinfo->num_chips == -1) { /* Cyclades-Z */ + number_z_boards++; + mailbox = cy_readl(&((struct RUNTIME_9060 __iomem *) + cy_card[board].ctl_addr)->mail_box_0); + nports = (mailbox == ZE_V1) ? ZE_V1_NPORTS : 8; + cinfo->intr_enabled = 0; + cinfo->nports = 0; /* Will be correctly set later, after + Z FW is loaded */ + spin_lock_init(&cinfo->card_lock); + for (port = cinfo->first_line ; + port < cinfo->first_line + nports; + port++) + { + info = &cy_port[port]; + info->magic = CYCLADES_MAGIC; + info->type = PORT_STARTECH; + info->card = board; + info->line = port; + info->chip_rev = 0; + info->flags = STD_COM_FLAGS; + info->tty = NULL; + if (mailbox == ZO_V1) + info->xmit_fifo_size = CYZ_FIFO_SIZE; + else + info->xmit_fifo_size = 4 * CYZ_FIFO_SIZE; + info->cor1 = 0; + info->cor2 = 0; + info->cor3 = 0; + info->cor4 = 0; + info->cor5 = 0; + info->tbpr = 0; + info->tco = 0; + info->rbpr = 0; + info->rco = 0; + info->custom_divisor = 0; + info->close_delay = 5*HZ/10; + info->closing_wait = CLOSING_WAIT_DELAY; + info->icount.cts = info->icount.dsr = + info->icount.rng = info->icount.dcd = 0; + info->icount.rx = info->icount.tx = 0; + info->icount.frame = info->icount.parity = 0; + info->icount.overrun = info->icount.brk = 0; + info->x_char = 0; + info->event = 0; + info->count = 0; + info->blocked_open = 0; + info->default_threshold = 0; + info->default_timeout = 0; + INIT_WORK(&info->tqueue, do_softint, info); + init_waitqueue_head(&info->open_wait); + init_waitqueue_head(&info->close_wait); + init_waitqueue_head(&info->shutdown_wait); + init_waitqueue_head(&info->delta_msr_wait); + /* info->session */ + /* info->pgrp */ + info->read_status_mask = 0; + /* info->timeout */ + /* Bentson's vars */ + info->jiffies[0] = 0; + info->jiffies[1] = 0; + info->jiffies[2] = 0; + info->rflush_count = 0; +#ifdef CONFIG_CYZ_INTR + init_timer(&cyz_rx_full_timer[port]); + cyz_rx_full_timer[port].function = NULL; +#endif + } + continue; + }else{ /* Cyclom-Y of some kind*/ + index = cinfo->bus_index; + spin_lock_init(&cinfo->card_lock); + cinfo->nports = CyPORTS_PER_CHIP * cinfo->num_chips; + for (port = cinfo->first_line ; + port < cinfo->first_line + cinfo->nports ; + port++) + { + info = &cy_port[port]; + info->magic = CYCLADES_MAGIC; + info->type = PORT_CIRRUS; + info->card = board; + info->line = port; + info->flags = STD_COM_FLAGS; + info->tty = NULL; + info->xmit_fifo_size = CyMAX_CHAR_FIFO; + info->cor1 = CyPARITY_NONE|Cy_1_STOP|Cy_8_BITS; + info->cor2 = CyETC; + info->cor3 = 0x08; /* _very_ small rcv threshold */ + info->cor4 = 0; + info->cor5 = 0; + info->custom_divisor = 0; + info->close_delay = 5*HZ/10; + info->closing_wait = CLOSING_WAIT_DELAY; + info->icount.cts = info->icount.dsr = + info->icount.rng = info->icount.dcd = 0; + info->icount.rx = info->icount.tx = 0; + info->icount.frame = info->icount.parity = 0; + info->icount.overrun = info->icount.brk = 0; + chip_number = (port - cinfo->first_line) / 4; + if ((info->chip_rev = + cy_readb(cinfo->base_addr + + (cy_chip_offset[chip_number]<= CD1400_REV_J) { + /* It is a CD1400 rev. J or later */ + info->tbpr = baud_bpr_60[13]; /* Tx BPR */ + info->tco = baud_co_60[13]; /* Tx CO */ + info->rbpr = baud_bpr_60[13]; /* Rx BPR */ + info->rco = baud_co_60[13]; /* Rx CO */ + info->rflow = 0; + info->rtsdtr_inv = 1; + } else { + info->tbpr = baud_bpr_25[13]; /* Tx BPR */ + info->tco = baud_co_25[13]; /* Tx CO */ + info->rbpr = baud_bpr_25[13]; /* Rx BPR */ + info->rco = baud_co_25[13]; /* Rx CO */ + info->rflow = 0; + info->rtsdtr_inv = 0; + } + info->x_char = 0; + info->event = 0; + info->count = 0; + info->blocked_open = 0; + info->default_threshold = 0; + info->default_timeout = 0; + INIT_WORK(&info->tqueue, do_softint, info); + init_waitqueue_head(&info->open_wait); + init_waitqueue_head(&info->close_wait); + init_waitqueue_head(&info->shutdown_wait); + init_waitqueue_head(&info->delta_msr_wait); + /* info->session */ + /* info->pgrp */ + info->read_status_mask = + CyTIMEOUT| CySPECHAR| CyBREAK + | CyPARITY| CyFRAME| CyOVERRUN; + /* info->timeout */ + } + } + } + +#ifndef CONFIG_CYZ_INTR + if (number_z_boards && !cyz_timeron){ + cyz_timeron++; + cyz_timerlist.expires = jiffies + 1; + add_timer(&cyz_timerlist); +#ifdef CY_PCI_DEBUG + printk("Cyclades-Z polling initialized\n"); +#endif + } +#endif /* CONFIG_CYZ_INTR */ + + return 0; + +} /* cy_init */ + +static void __exit +cy_cleanup_module(void) +{ + int i, e1; + +#ifndef CONFIG_CYZ_INTR + if (cyz_timeron){ + cyz_timeron = 0; + del_timer(&cyz_timerlist); + } +#endif /* CONFIG_CYZ_INTR */ + + if ((e1 = tty_unregister_driver(cy_serial_driver))) + printk("cyc: failed to unregister Cyclades serial driver(%d)\n", + e1); + + put_tty_driver(cy_serial_driver); + + for (i = 0; i < NR_CARDS; i++) { + if (cy_card[i].base_addr) { + iounmap(cy_card[i].base_addr); + if (cy_card[i].ctl_addr) + iounmap(cy_card[i].ctl_addr); + if (cy_card[i].irq +#ifndef CONFIG_CYZ_INTR + && cy_card[i].num_chips != -1 /* not a Z card */ +#endif /* CONFIG_CYZ_INTR */ + ) + free_irq(cy_card[i].irq, &cy_card[i]); +#ifdef CONFIG_PCI + if (cy_card[i].pdev) + pci_release_regions(cy_card[i].pdev); +#endif + } + } + if (tmp_buf) { + free_page((unsigned long) tmp_buf); + tmp_buf = NULL; + } +} /* cy_cleanup_module */ + +module_init(cy_init); +module_exit(cy_cleanup_module); + +MODULE_LICENSE("GPL"); diff --git a/drivers/char/decserial.c b/drivers/char/decserial.c new file mode 100644 index 000000000000..aa1440934e95 --- /dev/null +++ b/drivers/char/decserial.c @@ -0,0 +1,100 @@ +/* + * sercons.c + * choose the right serial device at boot time + * + * triemer 6-SEP-1998 + * sercons.c is designed to allow the three different kinds + * of serial devices under the decstation world to co-exist + * in the same kernel. The idea here is to abstract + * the pieces of the drivers that are common to this file + * so that they do not clash at compile time and runtime. + * + * HK 16-SEP-1998 v0.002 + * removed the PROM console as this is not a real serial + * device. Added support for PROM console in drivers/char/tty_io.c + * instead. Although it may work to enable more than one + * console device I strongly recommend to use only one. + */ + +#include +#include +#include + +#ifdef CONFIG_ZS +extern int zs_init(void); +#endif + +#ifdef CONFIG_DZ +extern int dz_init(void); +#endif + +#ifdef CONFIG_SERIAL_CONSOLE + +#ifdef CONFIG_ZS +extern void zs_serial_console_init(void); +#endif + +#ifdef CONFIG_DZ +extern void dz_serial_console_init(void); +#endif + +#endif + +/* rs_init - starts up the serial interface - + handle normal case of starting up the serial interface */ + +#ifdef CONFIG_SERIAL + +int __init rs_init(void) +{ + +#if defined(CONFIG_ZS) && defined(CONFIG_DZ) + if (IOASIC) + return zs_init(); + else + return dz_init(); +#else + +#ifdef CONFIG_ZS + return zs_init(); +#endif + +#ifdef CONFIG_DZ + return dz_init(); +#endif + +#endif +} + +__initcall(rs_init); + +#endif + +#ifdef CONFIG_SERIAL_CONSOLE + +/* serial_console_init handles the special case of starting + * up the console on the serial port + */ +static int __init decserial_console_init(void) +{ +#if defined(CONFIG_ZS) && defined(CONFIG_DZ) + if (IOASIC) + zs_serial_console_init(); + else + dz_serial_console_init(); +#else + +#ifdef CONFIG_ZS + zs_serial_console_init(); +#endif + +#ifdef CONFIG_DZ + dz_serial_console_init(); +#endif + +#endif + return 0; +} +console_initcall(decserial_console_init); + +#endif diff --git a/drivers/char/defkeymap.c_shipped b/drivers/char/defkeymap.c_shipped new file mode 100644 index 000000000000..453a2f1ffa15 --- /dev/null +++ b/drivers/char/defkeymap.c_shipped @@ -0,0 +1,262 @@ +/* Do not edit this file! It was automatically generated by */ +/* loadkeys --mktable defkeymap.map > defkeymap.c */ + +#include +#include +#include + +u_short plain_map[NR_KEYS] = { + 0xf200, 0xf01b, 0xf031, 0xf032, 0xf033, 0xf034, 0xf035, 0xf036, + 0xf037, 0xf038, 0xf039, 0xf030, 0xf02d, 0xf03d, 0xf07f, 0xf009, + 0xfb71, 0xfb77, 0xfb65, 0xfb72, 0xfb74, 0xfb79, 0xfb75, 0xfb69, + 0xfb6f, 0xfb70, 0xf05b, 0xf05d, 0xf201, 0xf702, 0xfb61, 0xfb73, + 0xfb64, 0xfb66, 0xfb67, 0xfb68, 0xfb6a, 0xfb6b, 0xfb6c, 0xf03b, + 0xf027, 0xf060, 0xf700, 0xf05c, 0xfb7a, 0xfb78, 0xfb63, 0xfb76, + 0xfb62, 0xfb6e, 0xfb6d, 0xf02c, 0xf02e, 0xf02f, 0xf700, 0xf30c, + 0xf703, 0xf020, 0xf207, 0xf100, 0xf101, 0xf102, 0xf103, 0xf104, + 0xf105, 0xf106, 0xf107, 0xf108, 0xf109, 0xf208, 0xf209, 0xf307, + 0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301, + 0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf03c, 0xf10a, + 0xf10b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, + 0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603, + 0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116, + 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d, + 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, +}; + +u_short shift_map[NR_KEYS] = { + 0xf200, 0xf01b, 0xf021, 0xf040, 0xf023, 0xf024, 0xf025, 0xf05e, + 0xf026, 0xf02a, 0xf028, 0xf029, 0xf05f, 0xf02b, 0xf07f, 0xf009, + 0xfb51, 0xfb57, 0xfb45, 0xfb52, 0xfb54, 0xfb59, 0xfb55, 0xfb49, + 0xfb4f, 0xfb50, 0xf07b, 0xf07d, 0xf201, 0xf702, 0xfb41, 0xfb53, + 0xfb44, 0xfb46, 0xfb47, 0xfb48, 0xfb4a, 0xfb4b, 0xfb4c, 0xf03a, + 0xf022, 0xf07e, 0xf700, 0xf07c, 0xfb5a, 0xfb58, 0xfb43, 0xfb56, + 0xfb42, 0xfb4e, 0xfb4d, 0xf03c, 0xf03e, 0xf03f, 0xf700, 0xf30c, + 0xf703, 0xf020, 0xf207, 0xf10a, 0xf10b, 0xf10c, 0xf10d, 0xf10e, + 0xf10f, 0xf110, 0xf111, 0xf112, 0xf113, 0xf213, 0xf203, 0xf307, + 0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301, + 0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf03e, 0xf10a, + 0xf10b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, + 0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603, + 0xf20b, 0xf601, 0xf602, 0xf117, 0xf600, 0xf20a, 0xf115, 0xf116, + 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d, + 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, +}; + +u_short altgr_map[NR_KEYS] = { + 0xf200, 0xf200, 0xf200, 0xf040, 0xf200, 0xf024, 0xf200, 0xf200, + 0xf07b, 0xf05b, 0xf05d, 0xf07d, 0xf05c, 0xf200, 0xf200, 0xf200, + 0xfb71, 0xfb77, 0xf918, 0xfb72, 0xfb74, 0xfb79, 0xfb75, 0xfb69, + 0xfb6f, 0xfb70, 0xf200, 0xf07e, 0xf201, 0xf702, 0xf914, 0xfb73, + 0xf917, 0xf919, 0xfb67, 0xfb68, 0xfb6a, 0xfb6b, 0xfb6c, 0xf200, + 0xf200, 0xf200, 0xf700, 0xf200, 0xfb7a, 0xfb78, 0xf916, 0xfb76, + 0xf915, 0xfb6e, 0xfb6d, 0xf200, 0xf200, 0xf200, 0xf700, 0xf30c, + 0xf703, 0xf200, 0xf207, 0xf50c, 0xf50d, 0xf50e, 0xf50f, 0xf510, + 0xf511, 0xf512, 0xf513, 0xf514, 0xf515, 0xf208, 0xf202, 0xf911, + 0xf912, 0xf913, 0xf30b, 0xf90e, 0xf90f, 0xf910, 0xf30a, 0xf90b, + 0xf90c, 0xf90d, 0xf90a, 0xf310, 0xf206, 0xf200, 0xf07c, 0xf516, + 0xf517, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, + 0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603, + 0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116, + 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d, + 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, +}; + +u_short ctrl_map[NR_KEYS] = { + 0xf200, 0xf200, 0xf200, 0xf000, 0xf01b, 0xf01c, 0xf01d, 0xf01e, + 0xf01f, 0xf07f, 0xf200, 0xf200, 0xf01f, 0xf200, 0xf008, 0xf200, + 0xf011, 0xf017, 0xf005, 0xf012, 0xf014, 0xf019, 0xf015, 0xf009, + 0xf00f, 0xf010, 0xf01b, 0xf01d, 0xf201, 0xf702, 0xf001, 0xf013, + 0xf004, 0xf006, 0xf007, 0xf008, 0xf00a, 0xf00b, 0xf00c, 0xf200, + 0xf007, 0xf000, 0xf700, 0xf01c, 0xf01a, 0xf018, 0xf003, 0xf016, + 0xf002, 0xf00e, 0xf00d, 0xf200, 0xf20e, 0xf07f, 0xf700, 0xf30c, + 0xf703, 0xf000, 0xf207, 0xf100, 0xf101, 0xf102, 0xf103, 0xf104, + 0xf105, 0xf106, 0xf107, 0xf108, 0xf109, 0xf208, 0xf204, 0xf307, + 0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301, + 0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf200, 0xf10a, + 0xf10b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, + 0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603, + 0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116, + 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d, + 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, +}; + +u_short shift_ctrl_map[NR_KEYS] = { + 0xf200, 0xf200, 0xf200, 0xf000, 0xf200, 0xf200, 0xf200, 0xf200, + 0xf200, 0xf200, 0xf200, 0xf200, 0xf01f, 0xf200, 0xf200, 0xf200, + 0xf011, 0xf017, 0xf005, 0xf012, 0xf014, 0xf019, 0xf015, 0xf009, + 0xf00f, 0xf010, 0xf200, 0xf200, 0xf201, 0xf702, 0xf001, 0xf013, + 0xf004, 0xf006, 0xf007, 0xf008, 0xf00a, 0xf00b, 0xf00c, 0xf200, + 0xf200, 0xf200, 0xf700, 0xf200, 0xf01a, 0xf018, 0xf003, 0xf016, + 0xf002, 0xf00e, 0xf00d, 0xf200, 0xf200, 0xf200, 0xf700, 0xf30c, + 0xf703, 0xf200, 0xf207, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, + 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf208, 0xf200, 0xf307, + 0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301, + 0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf200, 0xf200, + 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, + 0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603, + 0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116, + 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d, + 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, +}; + +u_short alt_map[NR_KEYS] = { + 0xf200, 0xf81b, 0xf831, 0xf832, 0xf833, 0xf834, 0xf835, 0xf836, + 0xf837, 0xf838, 0xf839, 0xf830, 0xf82d, 0xf83d, 0xf87f, 0xf809, + 0xf871, 0xf877, 0xf865, 0xf872, 0xf874, 0xf879, 0xf875, 0xf869, + 0xf86f, 0xf870, 0xf85b, 0xf85d, 0xf80d, 0xf702, 0xf861, 0xf873, + 0xf864, 0xf866, 0xf867, 0xf868, 0xf86a, 0xf86b, 0xf86c, 0xf83b, + 0xf827, 0xf860, 0xf700, 0xf85c, 0xf87a, 0xf878, 0xf863, 0xf876, + 0xf862, 0xf86e, 0xf86d, 0xf82c, 0xf82e, 0xf82f, 0xf700, 0xf30c, + 0xf703, 0xf820, 0xf207, 0xf500, 0xf501, 0xf502, 0xf503, 0xf504, + 0xf505, 0xf506, 0xf507, 0xf508, 0xf509, 0xf208, 0xf209, 0xf907, + 0xf908, 0xf909, 0xf30b, 0xf904, 0xf905, 0xf906, 0xf30a, 0xf901, + 0xf902, 0xf903, 0xf900, 0xf310, 0xf206, 0xf200, 0xf83c, 0xf50a, + 0xf50b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, + 0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603, + 0xf118, 0xf210, 0xf211, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116, + 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d, + 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, +}; + +u_short ctrl_alt_map[NR_KEYS] = { + 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, + 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, + 0xf811, 0xf817, 0xf805, 0xf812, 0xf814, 0xf819, 0xf815, 0xf809, + 0xf80f, 0xf810, 0xf200, 0xf200, 0xf201, 0xf702, 0xf801, 0xf813, + 0xf804, 0xf806, 0xf807, 0xf808, 0xf80a, 0xf80b, 0xf80c, 0xf200, + 0xf200, 0xf200, 0xf700, 0xf200, 0xf81a, 0xf818, 0xf803, 0xf816, + 0xf802, 0xf80e, 0xf80d, 0xf200, 0xf200, 0xf200, 0xf700, 0xf30c, + 0xf703, 0xf200, 0xf207, 0xf500, 0xf501, 0xf502, 0xf503, 0xf504, + 0xf505, 0xf506, 0xf507, 0xf508, 0xf509, 0xf208, 0xf200, 0xf307, + 0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301, + 0xf302, 0xf303, 0xf300, 0xf20c, 0xf206, 0xf200, 0xf200, 0xf50a, + 0xf50b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, + 0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603, + 0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf20c, + 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d, + 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, +}; + +ushort *key_maps[MAX_NR_KEYMAPS] = { + plain_map, shift_map, altgr_map, NULL, + ctrl_map, shift_ctrl_map, NULL, NULL, + alt_map, NULL, NULL, NULL, + ctrl_alt_map, NULL +}; + +unsigned int keymap_count = 7; + +/* + * Philosophy: most people do not define more strings, but they who do + * often want quite a lot of string space. So, we statically allocate + * the default and allocate dynamically in chunks of 512 bytes. + */ + +char func_buf[] = { + '\033', '[', '[', 'A', 0, + '\033', '[', '[', 'B', 0, + '\033', '[', '[', 'C', 0, + '\033', '[', '[', 'D', 0, + '\033', '[', '[', 'E', 0, + '\033', '[', '1', '7', '~', 0, + '\033', '[', '1', '8', '~', 0, + '\033', '[', '1', '9', '~', 0, + '\033', '[', '2', '0', '~', 0, + '\033', '[', '2', '1', '~', 0, + '\033', '[', '2', '3', '~', 0, + '\033', '[', '2', '4', '~', 0, + '\033', '[', '2', '5', '~', 0, + '\033', '[', '2', '6', '~', 0, + '\033', '[', '2', '8', '~', 0, + '\033', '[', '2', '9', '~', 0, + '\033', '[', '3', '1', '~', 0, + '\033', '[', '3', '2', '~', 0, + '\033', '[', '3', '3', '~', 0, + '\033', '[', '3', '4', '~', 0, + '\033', '[', '1', '~', 0, + '\033', '[', '2', '~', 0, + '\033', '[', '3', '~', 0, + '\033', '[', '4', '~', 0, + '\033', '[', '5', '~', 0, + '\033', '[', '6', '~', 0, + '\033', '[', 'M', 0, + '\033', '[', 'P', 0, +}; + +char *funcbufptr = func_buf; +int funcbufsize = sizeof(func_buf); +int funcbufleft = 0; /* space left */ + +char *func_table[MAX_NR_FUNC] = { + func_buf + 0, + func_buf + 5, + func_buf + 10, + func_buf + 15, + func_buf + 20, + func_buf + 25, + func_buf + 31, + func_buf + 37, + func_buf + 43, + func_buf + 49, + func_buf + 55, + func_buf + 61, + func_buf + 67, + func_buf + 73, + func_buf + 79, + func_buf + 85, + func_buf + 91, + func_buf + 97, + func_buf + 103, + func_buf + 109, + func_buf + 115, + func_buf + 120, + func_buf + 125, + func_buf + 130, + func_buf + 135, + func_buf + 140, + func_buf + 145, + NULL, + NULL, + func_buf + 149, + NULL, +}; + +struct kbdiacr accent_table[MAX_DIACR] = { + {'`', 'A', '\300'}, {'`', 'a', '\340'}, + {'\'', 'A', '\301'}, {'\'', 'a', '\341'}, + {'^', 'A', '\302'}, {'^', 'a', '\342'}, + {'~', 'A', '\303'}, {'~', 'a', '\343'}, + {'"', 'A', '\304'}, {'"', 'a', '\344'}, + {'O', 'A', '\305'}, {'o', 'a', '\345'}, + {'0', 'A', '\305'}, {'0', 'a', '\345'}, + {'A', 'A', '\305'}, {'a', 'a', '\345'}, + {'A', 'E', '\306'}, {'a', 'e', '\346'}, + {',', 'C', '\307'}, {',', 'c', '\347'}, + {'`', 'E', '\310'}, {'`', 'e', '\350'}, + {'\'', 'E', '\311'}, {'\'', 'e', '\351'}, + {'^', 'E', '\312'}, {'^', 'e', '\352'}, + {'"', 'E', '\313'}, {'"', 'e', '\353'}, + {'`', 'I', '\314'}, {'`', 'i', '\354'}, + {'\'', 'I', '\315'}, {'\'', 'i', '\355'}, + {'^', 'I', '\316'}, {'^', 'i', '\356'}, + {'"', 'I', '\317'}, {'"', 'i', '\357'}, + {'-', 'D', '\320'}, {'-', 'd', '\360'}, + {'~', 'N', '\321'}, {'~', 'n', '\361'}, + {'`', 'O', '\322'}, {'`', 'o', '\362'}, + {'\'', 'O', '\323'}, {'\'', 'o', '\363'}, + {'^', 'O', '\324'}, {'^', 'o', '\364'}, + {'~', 'O', '\325'}, {'~', 'o', '\365'}, + {'"', 'O', '\326'}, {'"', 'o', '\366'}, + {'/', 'O', '\330'}, {'/', 'o', '\370'}, + {'`', 'U', '\331'}, {'`', 'u', '\371'}, + {'\'', 'U', '\332'}, {'\'', 'u', '\372'}, + {'^', 'U', '\333'}, {'^', 'u', '\373'}, + {'"', 'U', '\334'}, {'"', 'u', '\374'}, + {'\'', 'Y', '\335'}, {'\'', 'y', '\375'}, + {'T', 'H', '\336'}, {'t', 'h', '\376'}, + {'s', 's', '\337'}, {'"', 'y', '\377'}, + {'s', 'z', '\337'}, {'i', 'j', '\377'}, +}; + +unsigned int accent_table_size = 68; diff --git a/drivers/char/defkeymap.map b/drivers/char/defkeymap.map new file mode 100644 index 000000000000..50b30cace261 --- /dev/null +++ b/drivers/char/defkeymap.map @@ -0,0 +1,357 @@ +# Default kernel keymap. This uses 7 modifier combinations. +keymaps 0-2,4-5,8,12 +# Change the above line into +# keymaps 0-2,4-6,8,12 +# in case you want the entries +# altgr control keycode 83 = Boot +# altgr control keycode 111 = Boot +# below. +# +# In fact AltGr is used very little, and one more keymap can +# be saved by mapping AltGr to Alt (and adapting a few entries): +# keycode 100 = Alt +# +keycode 1 = Escape Escape + alt keycode 1 = Meta_Escape +keycode 2 = one exclam + alt keycode 2 = Meta_one +keycode 3 = two at at + control keycode 3 = nul + shift control keycode 3 = nul + alt keycode 3 = Meta_two +keycode 4 = three numbersign + control keycode 4 = Escape + alt keycode 4 = Meta_three +keycode 5 = four dollar dollar + control keycode 5 = Control_backslash + alt keycode 5 = Meta_four +keycode 6 = five percent + control keycode 6 = Control_bracketright + alt keycode 6 = Meta_five +keycode 7 = six asciicircum + control keycode 7 = Control_asciicircum + alt keycode 7 = Meta_six +keycode 8 = seven ampersand braceleft + control keycode 8 = Control_underscore + alt keycode 8 = Meta_seven +keycode 9 = eight asterisk bracketleft + control keycode 9 = Delete + alt keycode 9 = Meta_eight +keycode 10 = nine parenleft bracketright + alt keycode 10 = Meta_nine +keycode 11 = zero parenright braceright + alt keycode 11 = Meta_zero +keycode 12 = minus underscore backslash + control keycode 12 = Control_underscore + shift control keycode 12 = Control_underscore + alt keycode 12 = Meta_minus +keycode 13 = equal plus + alt keycode 13 = Meta_equal +keycode 14 = Delete Delete + control keycode 14 = BackSpace + alt keycode 14 = Meta_Delete +keycode 15 = Tab Tab + alt keycode 15 = Meta_Tab +keycode 16 = q +keycode 17 = w +keycode 18 = e + altgr keycode 18 = Hex_E +keycode 19 = r +keycode 20 = t +keycode 21 = y +keycode 22 = u +keycode 23 = i +keycode 24 = o +keycode 25 = p +keycode 26 = bracketleft braceleft + control keycode 26 = Escape + alt keycode 26 = Meta_bracketleft +keycode 27 = bracketright braceright asciitilde + control keycode 27 = Control_bracketright + alt keycode 27 = Meta_bracketright +keycode 28 = Return + alt keycode 28 = Meta_Control_m +keycode 29 = Control +keycode 30 = a + altgr keycode 30 = Hex_A +keycode 31 = s +keycode 32 = d + altgr keycode 32 = Hex_D +keycode 33 = f + altgr keycode 33 = Hex_F +keycode 34 = g +keycode 35 = h +keycode 36 = j +keycode 37 = k +keycode 38 = l +keycode 39 = semicolon colon + alt keycode 39 = Meta_semicolon +keycode 40 = apostrophe quotedbl + control keycode 40 = Control_g + alt keycode 40 = Meta_apostrophe +keycode 41 = grave asciitilde + control keycode 41 = nul + alt keycode 41 = Meta_grave +keycode 42 = Shift +keycode 43 = backslash bar + control keycode 43 = Control_backslash + alt keycode 43 = Meta_backslash +keycode 44 = z +keycode 45 = x +keycode 46 = c + altgr keycode 46 = Hex_C +keycode 47 = v +keycode 48 = b + altgr keycode 48 = Hex_B +keycode 49 = n +keycode 50 = m +keycode 51 = comma less + alt keycode 51 = Meta_comma +keycode 52 = period greater + control keycode 52 = Compose + alt keycode 52 = Meta_period +keycode 53 = slash question + control keycode 53 = Delete + alt keycode 53 = Meta_slash +keycode 54 = Shift +keycode 55 = KP_Multiply +keycode 56 = Alt +keycode 57 = space space + control keycode 57 = nul + alt keycode 57 = Meta_space +keycode 58 = Caps_Lock +keycode 59 = F1 F11 Console_13 + control keycode 59 = F1 + alt keycode 59 = Console_1 + control alt keycode 59 = Console_1 +keycode 60 = F2 F12 Console_14 + control keycode 60 = F2 + alt keycode 60 = Console_2 + control alt keycode 60 = Console_2 +keycode 61 = F3 F13 Console_15 + control keycode 61 = F3 + alt keycode 61 = Console_3 + control alt keycode 61 = Console_3 +keycode 62 = F4 F14 Console_16 + control keycode 62 = F4 + alt keycode 62 = Console_4 + control alt keycode 62 = Console_4 +keycode 63 = F5 F15 Console_17 + control keycode 63 = F5 + alt keycode 63 = Console_5 + control alt keycode 63 = Console_5 +keycode 64 = F6 F16 Console_18 + control keycode 64 = F6 + alt keycode 64 = Console_6 + control alt keycode 64 = Console_6 +keycode 65 = F7 F17 Console_19 + control keycode 65 = F7 + alt keycode 65 = Console_7 + control alt keycode 65 = Console_7 +keycode 66 = F8 F18 Console_20 + control keycode 66 = F8 + alt keycode 66 = Console_8 + control alt keycode 66 = Console_8 +keycode 67 = F9 F19 Console_21 + control keycode 67 = F9 + alt keycode 67 = Console_9 + control alt keycode 67 = Console_9 +keycode 68 = F10 F20 Console_22 + control keycode 68 = F10 + alt keycode 68 = Console_10 + control alt keycode 68 = Console_10 +keycode 69 = Num_Lock + shift keycode 69 = Bare_Num_Lock +keycode 70 = Scroll_Lock Show_Memory Show_Registers + control keycode 70 = Show_State + alt keycode 70 = Scroll_Lock +keycode 71 = KP_7 + alt keycode 71 = Ascii_7 + altgr keycode 71 = Hex_7 +keycode 72 = KP_8 + alt keycode 72 = Ascii_8 + altgr keycode 72 = Hex_8 +keycode 73 = KP_9 + alt keycode 73 = Ascii_9 + altgr keycode 73 = Hex_9 +keycode 74 = KP_Subtract +keycode 75 = KP_4 + alt keycode 75 = Ascii_4 + altgr keycode 75 = Hex_4 +keycode 76 = KP_5 + alt keycode 76 = Ascii_5 + altgr keycode 76 = Hex_5 +keycode 77 = KP_6 + alt keycode 77 = Ascii_6 + altgr keycode 77 = Hex_6 +keycode 78 = KP_Add +keycode 79 = KP_1 + alt keycode 79 = Ascii_1 + altgr keycode 79 = Hex_1 +keycode 80 = KP_2 + alt keycode 80 = Ascii_2 + altgr keycode 80 = Hex_2 +keycode 81 = KP_3 + alt keycode 81 = Ascii_3 + altgr keycode 81 = Hex_3 +keycode 82 = KP_0 + alt keycode 82 = Ascii_0 + altgr keycode 82 = Hex_0 +keycode 83 = KP_Period +# altgr control keycode 83 = Boot + control alt keycode 83 = Boot +keycode 84 = Last_Console +keycode 85 = +keycode 86 = less greater bar + alt keycode 86 = Meta_less +keycode 87 = F11 F11 Console_23 + control keycode 87 = F11 + alt keycode 87 = Console_11 + control alt keycode 87 = Console_11 +keycode 88 = F12 F12 Console_24 + control keycode 88 = F12 + alt keycode 88 = Console_12 + control alt keycode 88 = Console_12 +keycode 89 = +keycode 90 = +keycode 91 = +keycode 92 = +keycode 93 = +keycode 94 = +keycode 95 = +keycode 96 = KP_Enter +keycode 97 = Control +keycode 98 = KP_Divide +keycode 99 = Control_backslash + control keycode 99 = Control_backslash + alt keycode 99 = Control_backslash +keycode 100 = AltGr +keycode 101 = Break +keycode 102 = Find +keycode 103 = Up +keycode 104 = Prior + shift keycode 104 = Scroll_Backward +keycode 105 = Left + alt keycode 105 = Decr_Console +keycode 106 = Right + alt keycode 106 = Incr_Console +keycode 107 = Select +keycode 108 = Down +keycode 109 = Next + shift keycode 109 = Scroll_Forward +keycode 110 = Insert +keycode 111 = Remove +# altgr control keycode 111 = Boot + control alt keycode 111 = Boot +keycode 112 = Macro +keycode 113 = F13 +keycode 114 = F14 +keycode 115 = Help +keycode 116 = Do +keycode 117 = F17 +keycode 118 = KP_MinPlus +keycode 119 = Pause +keycode 120 = +keycode 121 = +keycode 122 = +keycode 123 = +keycode 124 = +keycode 125 = +keycode 126 = +keycode 127 = +string F1 = "\033[[A" +string F2 = "\033[[B" +string F3 = "\033[[C" +string F4 = "\033[[D" +string F5 = "\033[[E" +string F6 = "\033[17~" +string F7 = "\033[18~" +string F8 = "\033[19~" +string F9 = "\033[20~" +string F10 = "\033[21~" +string F11 = "\033[23~" +string F12 = "\033[24~" +string F13 = "\033[25~" +string F14 = "\033[26~" +string F15 = "\033[28~" +string F16 = "\033[29~" +string F17 = "\033[31~" +string F18 = "\033[32~" +string F19 = "\033[33~" +string F20 = "\033[34~" +string Find = "\033[1~" +string Insert = "\033[2~" +string Remove = "\033[3~" +string Select = "\033[4~" +string Prior = "\033[5~" +string Next = "\033[6~" +string Macro = "\033[M" +string Pause = "\033[P" +compose '`' 'A' to 'À' +compose '`' 'a' to 'à' +compose '\'' 'A' to 'Á' +compose '\'' 'a' to 'á' +compose '^' 'A' to 'Â' +compose '^' 'a' to 'â' +compose '~' 'A' to 'Ã' +compose '~' 'a' to 'ã' +compose '"' 'A' to 'Ä' +compose '"' 'a' to 'ä' +compose 'O' 'A' to 'Å' +compose 'o' 'a' to 'å' +compose '0' 'A' to 'Å' +compose '0' 'a' to 'å' +compose 'A' 'A' to 'Å' +compose 'a' 'a' to 'å' +compose 'A' 'E' to 'Æ' +compose 'a' 'e' to 'æ' +compose ',' 'C' to 'Ç' +compose ',' 'c' to 'ç' +compose '`' 'E' to 'È' +compose '`' 'e' to 'è' +compose '\'' 'E' to 'É' +compose '\'' 'e' to 'é' +compose '^' 'E' to 'Ê' +compose '^' 'e' to 'ê' +compose '"' 'E' to 'Ë' +compose '"' 'e' to 'ë' +compose '`' 'I' to 'Ì' +compose '`' 'i' to 'ì' +compose '\'' 'I' to 'Í' +compose '\'' 'i' to 'í' +compose '^' 'I' to 'Î' +compose '^' 'i' to 'î' +compose '"' 'I' to 'Ï' +compose '"' 'i' to 'ï' +compose '-' 'D' to 'Ð' +compose '-' 'd' to 'ð' +compose '~' 'N' to 'Ñ' +compose '~' 'n' to 'ñ' +compose '`' 'O' to 'Ò' +compose '`' 'o' to 'ò' +compose '\'' 'O' to 'Ó' +compose '\'' 'o' to 'ó' +compose '^' 'O' to 'Ô' +compose '^' 'o' to 'ô' +compose '~' 'O' to 'Õ' +compose '~' 'o' to 'õ' +compose '"' 'O' to 'Ö' +compose '"' 'o' to 'ö' +compose '/' 'O' to 'Ø' +compose '/' 'o' to 'ø' +compose '`' 'U' to 'Ù' +compose '`' 'u' to 'ù' +compose '\'' 'U' to 'Ú' +compose '\'' 'u' to 'ú' +compose '^' 'U' to 'Û' +compose '^' 'u' to 'û' +compose '"' 'U' to 'Ü' +compose '"' 'u' to 'ü' +compose '\'' 'Y' to 'Ý' +compose '\'' 'y' to 'ý' +compose 'T' 'H' to 'Þ' +compose 't' 'h' to 'þ' +compose 's' 's' to 'ß' +compose '"' 'y' to 'ÿ' +compose 's' 'z' to 'ß' +compose 'i' 'j' to 'ÿ' diff --git a/drivers/char/digi.h b/drivers/char/digi.h new file mode 100644 index 000000000000..19df0e879b1b --- /dev/null +++ b/drivers/char/digi.h @@ -0,0 +1,71 @@ +/* Definitions for DigiBoard ditty(1) command. */ + +#if !defined(TIOCMODG) +#define TIOCMODG (('d'<<8) | 250) /* get modem ctrl state */ +#define TIOCMODS (('d'<<8) | 251) /* set modem ctrl state */ +#endif + +#if !defined(TIOCMSET) +#define TIOCMSET (('d'<<8) | 252) /* set modem ctrl state */ +#define TIOCMGET (('d'<<8) | 253) /* set modem ctrl state */ +#endif + +#if !defined(TIOCMBIC) +#define TIOCMBIC (('d'<<8) | 254) /* set modem ctrl state */ +#define TIOCMBIS (('d'<<8) | 255) /* set modem ctrl state */ +#endif + +#if !defined(TIOCSDTR) +#define TIOCSDTR (('e'<<8) | 0) /* set DTR */ +#define TIOCCDTR (('e'<<8) | 1) /* clear DTR */ +#endif + +/************************************************************************ + * Ioctl command arguments for DIGI parameters. + ************************************************************************/ +#define DIGI_GETA (('e'<<8) | 94) /* Read params */ + +#define DIGI_SETA (('e'<<8) | 95) /* Set params */ +#define DIGI_SETAW (('e'<<8) | 96) /* Drain & set params */ +#define DIGI_SETAF (('e'<<8) | 97) /* Drain, flush & set params */ + +#define DIGI_GETFLOW (('e'<<8) | 99) /* Get startc/stopc flow */ + /* control characters */ +#define DIGI_SETFLOW (('e'<<8) | 100) /* Set startc/stopc flow */ + /* control characters */ +#define DIGI_GETAFLOW (('e'<<8) | 101) /* Get Aux. startc/stopc */ + /* flow control chars */ +#define DIGI_SETAFLOW (('e'<<8) | 102) /* Set Aux. startc/stopc */ + /* flow control chars */ + +struct digiflow_struct { + unsigned char startc; /* flow cntl start char */ + unsigned char stopc; /* flow cntl stop char */ +}; + +typedef struct digiflow_struct digiflow_t; + + +/************************************************************************ + * Values for digi_flags + ************************************************************************/ +#define DIGI_IXON 0x0001 /* Handle IXON in the FEP */ +#define DIGI_FAST 0x0002 /* Fast baud rates */ +#define RTSPACE 0x0004 /* RTS input flow control */ +#define CTSPACE 0x0008 /* CTS output flow control */ +#define DSRPACE 0x0010 /* DSR output flow control */ +#define DCDPACE 0x0020 /* DCD output flow control */ +#define DTRPACE 0x0040 /* DTR input flow control */ +#define DIGI_FORCEDCD 0x0100 /* Force carrier */ +#define DIGI_ALTPIN 0x0200 /* Alternate RJ-45 pin config */ +#define DIGI_AIXON 0x0400 /* Aux flow control in fep */ + + +/************************************************************************ + * Structure used with ioctl commands for DIGI parameters. + ************************************************************************/ +struct digi_struct { + unsigned short digi_flags; /* Flags (see above) */ +}; + +typedef struct digi_struct digi_t; diff --git a/drivers/char/digi1.h b/drivers/char/digi1.h new file mode 100644 index 000000000000..184378d23f8c --- /dev/null +++ b/drivers/char/digi1.h @@ -0,0 +1,100 @@ +/* Definitions for DigiBoard ditty(1) command. */ + +#if !defined(TIOCMODG) +#define TIOCMODG ('d'<<8) | 250 /* get modem ctrl state */ +#define TIOCMODS ('d'<<8) | 251 /* set modem ctrl state */ +#endif + +#if !defined(TIOCMSET) +#define TIOCMSET ('d'<<8) | 252 /* set modem ctrl state */ +#define TIOCMGET ('d'<<8) | 253 /* set modem ctrl state */ +#endif + +#if !defined(TIOCMBIC) +#define TIOCMBIC ('d'<<8) | 254 /* set modem ctrl state */ +#define TIOCMBIS ('d'<<8) | 255 /* set modem ctrl state */ +#endif + +#if !defined(TIOCSDTR) +#define TIOCSDTR ('e'<<8) | 0 /* set DTR */ +#define TIOCCDTR ('e'<<8) | 1 /* clear DTR */ +#endif + +/************************************************************************ + * Ioctl command arguments for DIGI parameters. + ************************************************************************/ +#define DIGI_GETA ('e'<<8) | 94 /* Read params */ + +#define DIGI_SETA ('e'<<8) | 95 /* Set params */ +#define DIGI_SETAW ('e'<<8) | 96 /* Drain & set params */ +#define DIGI_SETAF ('e'<<8) | 97 /* Drain, flush & set params */ + +#define DIGI_GETFLOW ('e'<<8) | 99 /* Get startc/stopc flow */ + /* control characters */ +#define DIGI_SETFLOW ('e'<<8) | 100 /* Set startc/stopc flow */ + /* control characters */ +#define DIGI_GETAFLOW ('e'<<8) | 101 /* Get Aux. startc/stopc */ + /* flow control chars */ +#define DIGI_SETAFLOW ('e'<<8) | 102 /* Set Aux. startc/stopc */ + /* flow control chars */ + +#define DIGI_GETINFO ('e'<<8) | 103 /* Fill in digi_info */ +#define DIGI_POLLER ('e'<<8) | 104 /* Turn on/off poller */ +#define DIGI_INIT ('e'<<8) | 105 /* Allow things to run. */ + +struct digiflow_struct +{ + unsigned char startc; /* flow cntl start char */ + unsigned char stopc; /* flow cntl stop char */ +}; + +typedef struct digiflow_struct digiflow_t; + + +/************************************************************************ + * Values for digi_flags + ************************************************************************/ +#define DIGI_IXON 0x0001 /* Handle IXON in the FEP */ +#define DIGI_FAST 0x0002 /* Fast baud rates */ +#define RTSPACE 0x0004 /* RTS input flow control */ +#define CTSPACE 0x0008 /* CTS output flow control */ +#define DSRPACE 0x0010 /* DSR output flow control */ +#define DCDPACE 0x0020 /* DCD output flow control */ +#define DTRPACE 0x0040 /* DTR input flow control */ +#define DIGI_FORCEDCD 0x0100 /* Force carrier */ +#define DIGI_ALTPIN 0x0200 /* Alternate RJ-45 pin config */ +#define DIGI_AIXON 0x0400 /* Aux flow control in fep */ + + +/************************************************************************ + * Values for digiDload + ************************************************************************/ +#define NORMAL 0 +#define PCI_CTL 1 + +#define SIZE8 0 +#define SIZE16 1 +#define SIZE32 2 + +/************************************************************************ + * Structure used with ioctl commands for DIGI parameters. + ************************************************************************/ +struct digi_struct +{ + unsigned short digi_flags; /* Flags (see above) */ +}; + +typedef struct digi_struct digi_t; + +struct digi_info +{ + unsigned long board; /* Which board is this ? */ + unsigned char status; /* Alive or dead */ + unsigned char type; /* see epca.h */ + unsigned char subtype; /* For future XEM, XR, etc ... */ + unsigned short numports; /* Number of ports configured */ + unsigned char *port; /* I/O Address */ + unsigned char *membase; /* DPR Address */ + unsigned char *version; /* For future ... */ + unsigned short windowData; /* For future ... */ +} ; diff --git a/drivers/char/digiFep1.h b/drivers/char/digiFep1.h new file mode 100644 index 000000000000..c47d7fcb8400 --- /dev/null +++ b/drivers/char/digiFep1.h @@ -0,0 +1,136 @@ + +#define CSTART 0x400L +#define CMAX 0x800L +#define ISTART 0x800L +#define IMAX 0xC00L +#define CIN 0xD10L +#define GLOBAL 0xD10L +#define EIN 0xD18L +#define FEPSTAT 0xD20L +#define CHANSTRUCT 0x1000L +#define RXTXBUF 0x4000L + + +struct global_data +{ + volatile ushort cin; + volatile ushort cout; + volatile ushort cstart; + volatile ushort cmax; + volatile ushort ein; + volatile ushort eout; + volatile ushort istart; + volatile ushort imax; +}; + + +struct board_chan +{ + int filler1; + int filler2; + volatile ushort tseg; + volatile ushort tin; + volatile ushort tout; + volatile ushort tmax; + + volatile ushort rseg; + volatile ushort rin; + volatile ushort rout; + volatile ushort rmax; + + volatile ushort tlow; + volatile ushort rlow; + volatile ushort rhigh; + volatile ushort incr; + + volatile ushort etime; + volatile ushort edelay; + volatile unchar *dev; + + volatile ushort iflag; + volatile ushort oflag; + volatile ushort cflag; + volatile ushort gmask; + + volatile ushort col; + volatile ushort delay; + volatile ushort imask; + volatile ushort tflush; + + int filler3; + int filler4; + int filler5; + int filler6; + + volatile unchar num; + volatile unchar ract; + volatile unchar bstat; + volatile unchar tbusy; + volatile unchar iempty; + volatile unchar ilow; + volatile unchar idata; + volatile unchar eflag; + + volatile unchar tflag; + volatile unchar rflag; + volatile unchar xmask; + volatile unchar xval; + volatile unchar mstat; + volatile unchar mchange; + volatile unchar mint; + volatile unchar lstat; + + volatile unchar mtran; + volatile unchar orun; + volatile unchar startca; + volatile unchar stopca; + volatile unchar startc; + volatile unchar stopc; + volatile unchar vnext; + volatile unchar hflow; + + volatile unchar fillc; + volatile unchar ochar; + volatile unchar omask; + + unchar filler7; + unchar filler8[28]; +}; + + +#define SRXLWATER 0xE0 +#define SRXHWATER 0xE1 +#define STOUT 0xE2 +#define PAUSETX 0xE3 +#define RESUMETX 0xE4 +#define SAUXONOFFC 0xE6 +#define SENDBREAK 0xE8 +#define SETMODEM 0xE9 +#define SETIFLAGS 0xEA +#define SONOFFC 0xEB +#define STXLWATER 0xEC +#define PAUSERX 0xEE +#define RESUMERX 0xEF +#define SETBUFFER 0xF2 +#define SETCOOKED 0xF3 +#define SETHFLOW 0xF4 +#define SETCTRLFLAGS 0xF5 +#define SETVNEXT 0xF6 + + + +#define BREAK_IND 0x01 +#define LOWTX_IND 0x02 +#define EMPTYTX_IND 0x04 +#define DATA_IND 0x08 +#define MODEMCHG_IND 0x20 + +#define FEP_HUPCL 0002000 +#if 0 +#define RTS 0x02 +#define CD 0x08 +#define DSR 0x10 +#define CTS 0x20 +#define RI 0x40 +#define DTR 0x80 +#endif diff --git a/drivers/char/digiPCI.h b/drivers/char/digiPCI.h new file mode 100644 index 000000000000..6ca7819e5069 --- /dev/null +++ b/drivers/char/digiPCI.h @@ -0,0 +1,42 @@ +/************************************************************************* + * Defines and structure definitions for PCI BIOS Interface + *************************************************************************/ +#define PCIMAX 32 /* maximum number of PCI boards */ + + +#define PCI_VENDOR_DIGI 0x114F +#define PCI_DEVICE_EPC 0x0002 +#define PCI_DEVICE_RIGHTSWITCH 0x0003 /* For testing */ +#define PCI_DEVICE_XEM 0x0004 +#define PCI_DEVICE_XR 0x0005 +#define PCI_DEVICE_CX 0x0006 +#define PCI_DEVICE_XRJ 0x0009 /* Jupiter boards with */ +#define PCI_DEVICE_EPCJ 0x000a /* PLX 9060 chip for PCI */ + + +/* + * On the PCI boards, there is no IO space allocated + * The I/O registers will be in the first 3 bytes of the + * upper 2MB of the 4MB memory space. The board memory + * will be mapped into the low 2MB of the 4MB memory space + */ + +/* Potential location of PCI Bios from E0000 to FFFFF*/ +#define PCI_BIOS_SIZE 0x00020000 + +/* Size of Memory and I/O for PCI (4MB) */ +#define PCI_RAM_SIZE 0x00400000 + +/* Size of Memory (2MB) */ +#define PCI_MEM_SIZE 0x00200000 + +/* Offset of I/0 in Memory (2MB) */ +#define PCI_IO_OFFSET 0x00200000 + +#define MEMOUTB(basemem, pnum, setmemval) *(caddr_t)((basemem) + ( PCI_IO_OFFSET | pnum << 4 | pnum )) = (setmemval) +#define MEMINB(basemem, pnum) *(caddr_t)((basemem) + (PCI_IO_OFFSET | pnum << 4 | pnum )) /* for PCI I/O */ + + + + + diff --git a/drivers/char/drm/Kconfig b/drivers/char/drm/Kconfig new file mode 100644 index 000000000000..d9a029934678 --- /dev/null +++ b/drivers/char/drm/Kconfig @@ -0,0 +1,98 @@ +# +# Drm device configuration +# +# This driver provides support for the +# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. +# +config DRM + tristate "Direct Rendering Manager (XFree86 4.1.0 and higher DRI support)" + depends on AGP || AGP=n + help + Kernel-level support for the Direct Rendering Infrastructure (DRI) + introduced in XFree86 4.0. If you say Y here, you need to select + the module that's right for your graphics card from the list below. + These modules provide support for synchronization, security, and + DMA transfers. Please see for more + details. You should also select and configure AGP + (/dev/agpgart) support. + +config DRM_TDFX + tristate "3dfx Banshee/Voodoo3+" + depends on DRM && PCI + help + Choose this option if you have a 3dfx Banshee or Voodoo3 (or later), + graphics card. If M is selected, the module will be called tdfx. + +config DRM_GAMMA + tristate "3dlabs GMX 2000" + depends on DRM && BROKEN + help + This is the old gamma driver, please tell me if it might actually + work. + +config DRM_R128 + tristate "ATI Rage 128" + depends on DRM && PCI + help + Choose this option if you have an ATI Rage 128 graphics card. If M + is selected, the module will be called r128. AGP support for + this card is strongly suggested (unless you have a PCI version). + +config DRM_RADEON + tristate "ATI Radeon" + depends on DRM && PCI + help + Choose this option if you have an ATI Radeon graphics card. There + are both PCI and AGP versions. You don't need to choose this to + run the Radeon in plain VGA mode. There is a product page at + . + If M is selected, the module will be called radeon. + +config DRM_I810 + tristate "Intel I810" + depends on DRM && AGP && AGP_INTEL + help + Choose this option if you have an Intel I810 graphics card. If M is + selected, the module will be called i810. AGP support is required + for this driver to work. + +choice + prompt "Intel 830M, 845G, 852GM, 855GM, 865G" + depends on DRM && AGP && AGP_INTEL + optional + +config DRM_I830 + tristate "i830 driver" + help + Choose this option if you have a system that has Intel 830M, 845G, + 852GM, 855GM or 865G integrated graphics. If M is selected, the + module will be called i830. AGP support is required for this driver + to work. This driver will eventually be replaced by the i915 one. + +config DRM_I915 + tristate "i915 driver" + help + Choose this option if you have a system that has Intel 830M, 845G, + 852GM, 855GM 865G or 915G integrated graphics. If M is selected, the + module will be called i915. AGP support is required for this driver + to work. This driver will eventually replace the I830 driver, when + later release of X start to use the new DDX and DRI. + +endchoice + +config DRM_MGA + tristate "Matrox g200/g400" + depends on DRM && AGP + help + Choose this option if you have a Matrox G200, G400 or G450 graphics + card. If M is selected, the module will be called mga. AGP + support is required for this driver to work. + +config DRM_SIS + tristate "SiS video cards" + depends on DRM && AGP + help + Choose this option if you have a SiS 630 or compatible video + chipset. If M is selected the module will be called sis. AGP + support is required for this driver to work. + diff --git a/drivers/char/drm/Makefile b/drivers/char/drm/Makefile new file mode 100644 index 000000000000..23ab26321e9a --- /dev/null +++ b/drivers/char/drm/Makefile @@ -0,0 +1,33 @@ +# +# Makefile for the drm device driver. This driver provides support for the +# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. + +drm-objs := drm_auth.o drm_bufs.o drm_context.o drm_dma.o drm_drawable.o \ + drm_drv.o drm_fops.o drm_init.o drm_ioctl.o drm_irq.o \ + drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \ + drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \ + drm_sysfs.o + +gamma-objs := gamma_drv.o gamma_dma.o +tdfx-objs := tdfx_drv.o +r128-objs := r128_drv.o r128_cce.o r128_state.o r128_irq.o +mga-objs := mga_drv.o mga_dma.o mga_state.o mga_warp.o mga_irq.o +i810-objs := i810_drv.o i810_dma.o +i830-objs := i830_drv.o i830_dma.o i830_irq.o +i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o +radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o +ffb-objs := ffb_drv.o ffb_context.o +sis-objs := sis_drv.o sis_ds.o sis_mm.o + +obj-$(CONFIG_DRM) += drm.o +obj-$(CONFIG_DRM_GAMMA) += gamma.o +obj-$(CONFIG_DRM_TDFX) += tdfx.o +obj-$(CONFIG_DRM_R128) += r128.o +obj-$(CONFIG_DRM_RADEON)+= radeon.o +obj-$(CONFIG_DRM_MGA) += mga.o +obj-$(CONFIG_DRM_I810) += i810.o +obj-$(CONFIG_DRM_I830) += i830.o +obj-$(CONFIG_DRM_I915) += i915.o +obj-$(CONFIG_DRM_FFB) += ffb.o +obj-$(CONFIG_DRM_SIS) += sis.o + diff --git a/drivers/char/drm/README.drm b/drivers/char/drm/README.drm new file mode 100644 index 000000000000..6441e01e587c --- /dev/null +++ b/drivers/char/drm/README.drm @@ -0,0 +1,46 @@ +************************************************************ +* For the very latest on DRI development, please see: * +* http://dri.sourceforge.net/ * +************************************************************ + +The Direct Rendering Manager (drm) is a device-independent kernel-level +device driver that provides support for the XFree86 Direct Rendering +Infrastructure (DRI). + +The DRM supports the Direct Rendering Infrastructure (DRI) in four major +ways: + + 1. The DRM provides synchronized access to the graphics hardware via + the use of an optimized two-tiered lock. + + 2. The DRM enforces the DRI security policy for access to the graphics + hardware by only allowing authenticated X11 clients access to + restricted regions of memory. + + 3. The DRM provides a generic DMA engine, complete with multiple + queues and the ability to detect the need for an OpenGL context + switch. + + 4. The DRM is extensible via the use of small device-specific modules + that rely extensively on the API exported by the DRM module. + + +Documentation on the DRI is available from: + http://precisioninsight.com/piinsights.html + +For specific information about kernel-level support, see: + + The Direct Rendering Manager, Kernel Support for the Direct Rendering + Infrastructure + http://precisioninsight.com/dr/drm.html + + Hardware Locking for the Direct Rendering Infrastructure + http://precisioninsight.com/dr/locking.html + + A Security Analysis of the Direct Rendering Infrastructure + http://precisioninsight.com/dr/security.html + +************************************************************ +* For the very latest on DRI development, please see: * +* http://dri.sourceforge.net/ * +************************************************************ diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c new file mode 100644 index 000000000000..fdca1876ecd5 --- /dev/null +++ b/drivers/char/drm/ati_pcigart.c @@ -0,0 +1,208 @@ +/** + * \file ati_pcigart.h + * ATI PCI GART support + * + * \author Gareth Hughes + */ + +/* + * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com + * + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" + +#if PAGE_SIZE == 65536 +# define ATI_PCIGART_TABLE_ORDER 0 +# define ATI_PCIGART_TABLE_PAGES (1 << 0) +#elif PAGE_SIZE == 16384 +# define ATI_PCIGART_TABLE_ORDER 1 +# define ATI_PCIGART_TABLE_PAGES (1 << 1) +#elif PAGE_SIZE == 8192 +# define ATI_PCIGART_TABLE_ORDER 2 +# define ATI_PCIGART_TABLE_PAGES (1 << 2) +#elif PAGE_SIZE == 4096 +# define ATI_PCIGART_TABLE_ORDER 3 +# define ATI_PCIGART_TABLE_PAGES (1 << 3) +#else +# error - PAGE_SIZE not 64K, 16K, 8K or 4K +#endif + +# define ATI_MAX_PCIGART_PAGES 8192 /**< 32 MB aperture, 4K pages */ +# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ + +unsigned long drm_ati_alloc_pcigart_table( void ) +{ + unsigned long address; + struct page *page; + int i; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + address = __get_free_pages( GFP_KERNEL, ATI_PCIGART_TABLE_ORDER ); + if ( address == 0UL ) { + return 0; + } + + page = virt_to_page( address ); + + for ( i = 0 ; i < ATI_PCIGART_TABLE_PAGES ; i++, page++ ) { + get_page(page); + SetPageReserved( page ); + } + + DRM_DEBUG( "%s: returning 0x%08lx\n", __FUNCTION__, address ); + return address; +} + +static void drm_ati_free_pcigart_table( unsigned long address ) +{ + struct page *page; + int i; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + page = virt_to_page( address ); + + for ( i = 0 ; i < ATI_PCIGART_TABLE_PAGES ; i++, page++ ) { + __put_page(page); + ClearPageReserved( page ); + } + + free_pages( address, ATI_PCIGART_TABLE_ORDER ); +} + +int drm_ati_pcigart_cleanup( drm_device_t *dev, + unsigned long addr, + dma_addr_t bus_addr) +{ + drm_sg_mem_t *entry = dev->sg; + unsigned long pages; + int i; + + /* we need to support large memory configurations */ + if ( !entry ) { + DRM_ERROR( "no scatter/gather memory!\n" ); + return 0; + } + + if ( bus_addr ) { + pci_unmap_single(dev->pdev, bus_addr, + ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, + PCI_DMA_TODEVICE); + + pages = ( entry->pages <= ATI_MAX_PCIGART_PAGES ) + ? entry->pages : ATI_MAX_PCIGART_PAGES; + + for ( i = 0 ; i < pages ; i++ ) { + if ( !entry->busaddr[i] ) break; + pci_unmap_single(dev->pdev, entry->busaddr[i], + PAGE_SIZE, PCI_DMA_TODEVICE); + } + } + + if ( addr ) { + drm_ati_free_pcigart_table( addr ); + } + + return 1; +} +EXPORT_SYMBOL(drm_ati_pcigart_cleanup); + +int drm_ati_pcigart_init( drm_device_t *dev, + unsigned long *addr, + dma_addr_t *bus_addr) +{ + drm_sg_mem_t *entry = dev->sg; + unsigned long address = 0; + unsigned long pages; + u32 *pci_gart, page_base, bus_address = 0; + int i, j, ret = 0; + + if ( !entry ) { + DRM_ERROR( "no scatter/gather memory!\n" ); + goto done; + } + + address = drm_ati_alloc_pcigart_table(); + if ( !address ) { + DRM_ERROR( "cannot allocate PCI GART page!\n" ); + goto done; + } + + if ( !dev->pdev ) { + DRM_ERROR( "PCI device unknown!\n" ); + goto done; + } + + bus_address = pci_map_single(dev->pdev, (void *)address, + ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, + PCI_DMA_TODEVICE); + if (bus_address == 0) { + DRM_ERROR( "unable to map PCIGART pages!\n" ); + drm_ati_free_pcigart_table( address ); + address = 0; + goto done; + } + + pci_gart = (u32 *)address; + + pages = ( entry->pages <= ATI_MAX_PCIGART_PAGES ) + ? entry->pages : ATI_MAX_PCIGART_PAGES; + + memset( pci_gart, 0, ATI_MAX_PCIGART_PAGES * sizeof(u32) ); + + for ( i = 0 ; i < pages ; i++ ) { + /* we need to support large memory configurations */ + entry->busaddr[i] = pci_map_single(dev->pdev, + page_address( entry->pagelist[i] ), + PAGE_SIZE, + PCI_DMA_TODEVICE); + if (entry->busaddr[i] == 0) { + DRM_ERROR( "unable to map PCIGART pages!\n" ); + drm_ati_pcigart_cleanup( dev, address, bus_address ); + address = 0; + bus_address = 0; + goto done; + } + page_base = (u32) entry->busaddr[i]; + + for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { + *pci_gart++ = cpu_to_le32( page_base ); + page_base += ATI_PCIGART_PAGE_SIZE; + } + } + + ret = 1; + +#if defined(__i386__) || defined(__x86_64__) + wbinvd(); +#else + mb(); +#endif + +done: + *addr = address; + *bus_addr = bus_address; + return ret; +} +EXPORT_SYMBOL(drm_ati_pcigart_init); diff --git a/drivers/char/drm/drm.h b/drivers/char/drm/drm.h new file mode 100644 index 000000000000..587305282ea8 --- /dev/null +++ b/drivers/char/drm/drm.h @@ -0,0 +1,675 @@ +/** + * \file drm.h + * Header for the Direct Rendering Manager + * + * \author Rickard E. (Rik) Faith + * + * \par Acknowledgments: + * Dec 1999, Richard Henderson , move to generic \c cmpxchg. + */ + +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _DRM_H_ +#define _DRM_H_ + +#if defined(__linux__) +#include +#include /* For _IO* macros */ +#define DRM_IOCTL_NR(n) _IOC_NR(n) +#define DRM_IOC_VOID _IOC_NONE +#define DRM_IOC_READ _IOC_READ +#define DRM_IOC_WRITE _IOC_WRITE +#define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE +#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) +#elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) +#if defined(__FreeBSD__) && defined(IN_MODULE) +/* Prevent name collision when including sys/ioccom.h */ +#undef ioctl +#include +#define ioctl(a,b,c) xf86ioctl(a,b,c) +#else +#include +#endif /* __FreeBSD__ && xf86ioctl */ +#define DRM_IOCTL_NR(n) ((n) & 0xff) +#define DRM_IOC_VOID IOC_VOID +#define DRM_IOC_READ IOC_OUT +#define DRM_IOC_WRITE IOC_IN +#define DRM_IOC_READWRITE IOC_INOUT +#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) +#endif + +#define XFREE86_VERSION(major,minor,patch,snap) \ + ((major << 16) | (minor << 8) | patch) + +#ifndef CONFIG_XFREE86_VERSION +#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0) +#endif + +#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) +#define DRM_PROC_DEVICES "/proc/devices" +#define DRM_PROC_MISC "/proc/misc" +#define DRM_PROC_DRM "/proc/drm" +#define DRM_DEV_DRM "/dev/drm" +#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) +#define DRM_DEV_UID 0 +#define DRM_DEV_GID 0 +#endif + +#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0) +#define DRM_MAJOR 226 +#define DRM_MAX_MINOR 15 +#endif +#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ +#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ +#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ +#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ + +#define _DRM_LOCK_HELD 0x80000000 /**< Hardware lock is held */ +#define _DRM_LOCK_CONT 0x40000000 /**< Hardware lock is contended */ +#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) +#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) +#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) + + +typedef unsigned long drm_handle_t; +typedef unsigned int drm_context_t; +typedef unsigned int drm_drawable_t; +typedef unsigned int drm_magic_t; + + +/** + * Cliprect. + * + * \warning: If you change this structure, make sure you change + * XF86DRIClipRectRec in the server as well + * + * \note KW: Actually it's illegal to change either for + * backwards-compatibility reasons. + */ +typedef struct drm_clip_rect { + unsigned short x1; + unsigned short y1; + unsigned short x2; + unsigned short y2; +} drm_clip_rect_t; + + +/** + * Texture region, + */ +typedef struct drm_tex_region { + unsigned char next; + unsigned char prev; + unsigned char in_use; + unsigned char padding; + unsigned int age; +} drm_tex_region_t; + +/** + * Hardware lock. + * + * The lock structure is a simple cache-line aligned integer. To avoid + * processor bus contention on a multiprocessor system, there should not be any + * other data stored in the same cache line. + */ +typedef struct drm_hw_lock { + __volatile__ unsigned int lock; /**< lock variable */ + char padding[60]; /**< Pad to cache line */ +} drm_hw_lock_t; + + +/** + * DRM_IOCTL_VERSION ioctl argument type. + * + * \sa drmGetVersion(). + */ +typedef struct drm_version { + int version_major; /**< Major version */ + int version_minor; /**< Minor version */ + int version_patchlevel;/**< Patch level */ + size_t name_len; /**< Length of name buffer */ + char __user *name; /**< Name of driver */ + size_t date_len; /**< Length of date buffer */ + char __user *date; /**< User-space buffer to hold date */ + size_t desc_len; /**< Length of desc buffer */ + char __user *desc; /**< User-space buffer to hold desc */ +} drm_version_t; + + +/** + * DRM_IOCTL_GET_UNIQUE ioctl argument type. + * + * \sa drmGetBusid() and drmSetBusId(). + */ +typedef struct drm_unique { + size_t unique_len; /**< Length of unique */ + char __user *unique; /**< Unique name for driver instantiation */ +} drm_unique_t; + + +typedef struct drm_list { + int count; /**< Length of user-space structures */ + drm_version_t __user *version; +} drm_list_t; + + +typedef struct drm_block { + int unused; +} drm_block_t; + + +/** + * DRM_IOCTL_CONTROL ioctl argument type. + * + * \sa drmCtlInstHandler() and drmCtlUninstHandler(). + */ +typedef struct drm_control { + enum { + DRM_ADD_COMMAND, + DRM_RM_COMMAND, + DRM_INST_HANDLER, + DRM_UNINST_HANDLER + } func; + int irq; +} drm_control_t; + + +/** + * Type of memory to map. + */ +typedef enum drm_map_type { + _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ + _DRM_REGISTERS = 1, /**< no caching, no core dump */ + _DRM_SHM = 2, /**< shared, cached */ + _DRM_AGP = 3, /**< AGP/GART */ + _DRM_SCATTER_GATHER = 4 /**< Scatter/gather memory for PCI DMA */ +} drm_map_type_t; + + +/** + * Memory mapping flags. + */ +typedef enum drm_map_flags { + _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ + _DRM_READ_ONLY = 0x02, + _DRM_LOCKED = 0x04, /**< shared, cached, locked */ + _DRM_KERNEL = 0x08, /**< kernel requires access */ + _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ + _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ + _DRM_REMOVABLE = 0x40 /**< Removable mapping */ +} drm_map_flags_t; + + +typedef struct drm_ctx_priv_map { + unsigned int ctx_id; /**< Context requesting private mapping */ + void *handle; /**< Handle of map */ +} drm_ctx_priv_map_t; + + +/** + * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls + * argument type. + * + * \sa drmAddMap(). + */ +typedef struct drm_map { + unsigned long offset; /**< Requested physical address (0 for SAREA)*/ + unsigned long size; /**< Requested physical size (bytes) */ + drm_map_type_t type; /**< Type of memory to map */ + drm_map_flags_t flags; /**< Flags */ + void *handle; /**< User-space: "Handle" to pass to mmap() */ + /**< Kernel-space: kernel-virtual address */ + int mtrr; /**< MTRR slot used */ + /* Private data */ +} drm_map_t; + + +/** + * DRM_IOCTL_GET_CLIENT ioctl argument type. + */ +typedef struct drm_client { + int idx; /**< Which client desired? */ + int auth; /**< Is client authenticated? */ + unsigned long pid; /**< Process ID */ + unsigned long uid; /**< User ID */ + unsigned long magic; /**< Magic */ + unsigned long iocs; /**< Ioctl count */ +} drm_client_t; + + +typedef enum { + _DRM_STAT_LOCK, + _DRM_STAT_OPENS, + _DRM_STAT_CLOSES, + _DRM_STAT_IOCTLS, + _DRM_STAT_LOCKS, + _DRM_STAT_UNLOCKS, + _DRM_STAT_VALUE, /**< Generic value */ + _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ + _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ + + _DRM_STAT_IRQ, /**< IRQ */ + _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ + _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ + _DRM_STAT_DMA, /**< DMA */ + _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ + _DRM_STAT_MISSED /**< Missed DMA opportunity */ + + /* Add to the *END* of the list */ +} drm_stat_type_t; + + +/** + * DRM_IOCTL_GET_STATS ioctl argument type. + */ +typedef struct drm_stats { + unsigned long count; + struct { + unsigned long value; + drm_stat_type_t type; + } data[15]; +} drm_stats_t; + + +/** + * Hardware locking flags. + */ +typedef enum drm_lock_flags { + _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ + _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ + _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ + _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ + /* These *HALT* flags aren't supported yet + -- they will be used to support the + full-screen DGA-like mode. */ + _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ + _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ +} drm_lock_flags_t; + + +/** + * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. + * + * \sa drmGetLock() and drmUnlock(). + */ +typedef struct drm_lock { + int context; + drm_lock_flags_t flags; +} drm_lock_t; + + +/** + * DMA flags + * + * \warning + * These values \e must match xf86drm.h. + * + * \sa drm_dma. + */ +typedef enum drm_dma_flags { + /* Flags for DMA buffer dispatch */ + _DRM_DMA_BLOCK = 0x01, /**< + * Block until buffer dispatched. + * + * \note The buffer may not yet have + * been processed by the hardware -- + * getting a hardware lock with the + * hardware quiescent will ensure + * that the buffer has been + * processed. + */ + _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ + _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ + + /* Flags for DMA buffer request */ + _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ + _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ + _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ +} drm_dma_flags_t; + + +/** + * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. + * + * \sa drmAddBufs(). + */ +typedef struct drm_buf_desc { + int count; /**< Number of buffers of this size */ + int size; /**< Size in bytes */ + int low_mark; /**< Low water mark */ + int high_mark; /**< High water mark */ + enum { + _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ + _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ + _DRM_SG_BUFFER = 0x04 /**< Scatter/gather memory buffer */ + } flags; + unsigned long agp_start; /**< + * Start address of where the AGP buffers are + * in the AGP aperture + */ +} drm_buf_desc_t; + + +/** + * DRM_IOCTL_INFO_BUFS ioctl argument type. + */ +typedef struct drm_buf_info { + int count; /**< Entries in list */ + drm_buf_desc_t __user *list; +} drm_buf_info_t; + + +/** + * DRM_IOCTL_FREE_BUFS ioctl argument type. + */ +typedef struct drm_buf_free { + int count; + int __user *list; +} drm_buf_free_t; + + +/** + * Buffer information + * + * \sa drm_buf_map. + */ +typedef struct drm_buf_pub { + int idx; /**< Index into the master buffer list */ + int total; /**< Buffer size */ + int used; /**< Amount of buffer in use (for DMA) */ + void __user *address; /**< Address of buffer */ +} drm_buf_pub_t; + + +/** + * DRM_IOCTL_MAP_BUFS ioctl argument type. + */ +typedef struct drm_buf_map { + int count; /**< Length of the buffer list */ + void __user *virtual; /**< Mmap'd area in user-virtual */ + drm_buf_pub_t __user *list; /**< Buffer information */ +} drm_buf_map_t; + + +/** + * DRM_IOCTL_DMA ioctl argument type. + * + * Indices here refer to the offset into the buffer list in drm_buf_get. + * + * \sa drmDMA(). + */ +typedef struct drm_dma { + int context; /**< Context handle */ + int send_count; /**< Number of buffers to send */ + int __user *send_indices; /**< List of handles to buffers */ + int __user *send_sizes; /**< Lengths of data to send */ + drm_dma_flags_t flags; /**< Flags */ + int request_count; /**< Number of buffers requested */ + int request_size; /**< Desired size for buffers */ + int __user *request_indices; /**< Buffer information */ + int __user *request_sizes; + int granted_count; /**< Number of buffers granted */ +} drm_dma_t; + + +typedef enum { + _DRM_CONTEXT_PRESERVED = 0x01, + _DRM_CONTEXT_2DONLY = 0x02 +} drm_ctx_flags_t; + + +/** + * DRM_IOCTL_ADD_CTX ioctl argument type. + * + * \sa drmCreateContext() and drmDestroyContext(). + */ +typedef struct drm_ctx { + drm_context_t handle; + drm_ctx_flags_t flags; +} drm_ctx_t; + + +/** + * DRM_IOCTL_RES_CTX ioctl argument type. + */ +typedef struct drm_ctx_res { + int count; + drm_ctx_t __user *contexts; +} drm_ctx_res_t; + + +/** + * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. + */ +typedef struct drm_draw { + drm_drawable_t handle; +} drm_draw_t; + + +/** + * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. + */ +typedef struct drm_auth { + drm_magic_t magic; +} drm_auth_t; + + +/** + * DRM_IOCTL_IRQ_BUSID ioctl argument type. + * + * \sa drmGetInterruptFromBusID(). + */ +typedef struct drm_irq_busid { + int irq; /**< IRQ number */ + int busnum; /**< bus number */ + int devnum; /**< device number */ + int funcnum; /**< function number */ +} drm_irq_busid_t; + + +typedef enum { + _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ + _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ + _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ +} drm_vblank_seq_type_t; + + +#define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL + + +struct drm_wait_vblank_request { + drm_vblank_seq_type_t type; + unsigned int sequence; + unsigned long signal; +}; + + +struct drm_wait_vblank_reply { + drm_vblank_seq_type_t type; + unsigned int sequence; + long tval_sec; + long tval_usec; +}; + + +/** + * DRM_IOCTL_WAIT_VBLANK ioctl argument type. + * + * \sa drmWaitVBlank(). + */ +typedef union drm_wait_vblank { + struct drm_wait_vblank_request request; + struct drm_wait_vblank_reply reply; +} drm_wait_vblank_t; + + +/** + * DRM_IOCTL_AGP_ENABLE ioctl argument type. + * + * \sa drmAgpEnable(). + */ +typedef struct drm_agp_mode { + unsigned long mode; /**< AGP mode */ +} drm_agp_mode_t; + + +/** + * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. + * + * \sa drmAgpAlloc() and drmAgpFree(). + */ +typedef struct drm_agp_buffer { + unsigned long size; /**< In bytes -- will round to page boundary */ + unsigned long handle; /**< Used for binding / unbinding */ + unsigned long type; /**< Type of memory to allocate */ + unsigned long physical; /**< Physical used by i810 */ +} drm_agp_buffer_t; + + +/** + * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. + * + * \sa drmAgpBind() and drmAgpUnbind(). + */ +typedef struct drm_agp_binding { + unsigned long handle; /**< From drm_agp_buffer */ + unsigned long offset; /**< In bytes -- will round to page boundary */ +} drm_agp_binding_t; + + +/** + * DRM_IOCTL_AGP_INFO ioctl argument type. + * + * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), + * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), + * drmAgpVendorId() and drmAgpDeviceId(). + */ +typedef struct drm_agp_info { + int agp_version_major; + int agp_version_minor; + unsigned long mode; + unsigned long aperture_base; /* physical address */ + unsigned long aperture_size; /* bytes */ + unsigned long memory_allowed; /* bytes */ + unsigned long memory_used; + + /* PCI information */ + unsigned short id_vendor; + unsigned short id_device; +} drm_agp_info_t; + + +/** + * DRM_IOCTL_SG_ALLOC ioctl argument type. + */ +typedef struct drm_scatter_gather { + unsigned long size; /**< In bytes -- will round to page boundary */ + unsigned long handle; /**< Used for mapping / unmapping */ +} drm_scatter_gather_t; + +/** + * DRM_IOCTL_SET_VERSION ioctl argument type. + */ +typedef struct drm_set_version { + int drm_di_major; + int drm_di_minor; + int drm_dd_major; + int drm_dd_minor; +} drm_set_version_t; + + +#define DRM_IOCTL_BASE 'd' +#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) +#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) +#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) +#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) + +#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t) +#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t) +#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t) +#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t) +#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t) +#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t) +#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t) +#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t) + +#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t) +#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t) +#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t) +#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t) +#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t) +#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t) +#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t) +#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t) +#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t) +#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t) +#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t) + +#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t) + +#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t) +#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t) + +#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t) +#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t) +#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t) +#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t) +#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t) +#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t) +#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t) +#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t) +#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t) +#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t) +#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t) +#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t) +#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t) + +#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) +#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) +#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t) +#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t) +#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t) +#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t) +#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t) +#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t) + +#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t) +#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t) + +#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t) + +/** + * Device specific ioctls should only be in their respective headers + * The device specific ioctl range is from 0x40 to 0x79. + * + * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and + * drmCommandReadWrite(). + */ +#define DRM_COMMAND_BASE 0x40 + +#endif diff --git a/drivers/char/drm/drmP.h b/drivers/char/drm/drmP.h new file mode 100644 index 000000000000..21f4c54e1a8d --- /dev/null +++ b/drivers/char/drm/drmP.h @@ -0,0 +1,1073 @@ +/** + * \file drmP.h + * Private header for Direct Rendering Manager + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DRM_P_H_ +#define _DRM_P_H_ + +/* If you want the memory alloc debug functionality, change define below */ +/* #define DEBUG_MEMORY */ + +#ifdef __KERNEL__ +#ifdef __alpha__ +/* add include of current.h so that "current" is defined + * before static inline funcs in wait.h. Doing this so we + * can build the DRM (part of PI DRI). 4/21/2000 S + B */ +#include +#endif /* __alpha__ */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* For (un)lock_kernel */ +#include +#include +#if defined(__alpha__) || defined(__powerpc__) +#include /* For pte_wrprotect */ +#endif +#include +#include +#include +#ifdef CONFIG_MTRR +#include +#endif +#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) +#include +#include +#endif +#include +#include +#include +#include "drm.h" + +#define __OS_HAS_AGP (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE))) +#define __OS_HAS_MTRR (defined(CONFIG_MTRR)) + +#include "drm_os_linux.h" + +/***********************************************************************/ +/** \name DRM template customization defaults */ +/*@{*/ + +/* driver capabilities and requirements mask */ +#define DRIVER_USE_AGP 0x1 +#define DRIVER_REQUIRE_AGP 0x2 +#define DRIVER_USE_MTRR 0x4 +#define DRIVER_PCI_DMA 0x8 +#define DRIVER_SG 0x10 +#define DRIVER_HAVE_DMA 0x20 +#define DRIVER_HAVE_IRQ 0x40 +#define DRIVER_IRQ_SHARED 0x80 +#define DRIVER_IRQ_VBL 0x100 +#define DRIVER_DMA_QUEUE 0x200 + +/***********************************************************************/ +/** \name Begin the DRM... */ +/*@{*/ + +#define DRM_DEBUG_CODE 2 /**< Include debugging code if > 1, then + also include looping detection. */ + +#define DRM_HASH_SIZE 16 /**< Size of key hash table. Must be power of 2. */ +#define DRM_KERNEL_CONTEXT 0 /**< Change drm_resctx if changed */ +#define DRM_RESERVED_CONTEXTS 1 /**< Change drm_resctx if changed */ +#define DRM_LOOPING_LIMIT 5000000 +#define DRM_BSZ 1024 /**< Buffer size for /dev/drm? output */ +#define DRM_TIME_SLICE (HZ/20) /**< Time slice for GLXContexts */ +#define DRM_LOCK_SLICE 1 /**< Time slice for lock, in jiffies */ + +#define DRM_FLAG_DEBUG 0x01 + +#define DRM_MEM_DMA 0 +#define DRM_MEM_SAREA 1 +#define DRM_MEM_DRIVER 2 +#define DRM_MEM_MAGIC 3 +#define DRM_MEM_IOCTLS 4 +#define DRM_MEM_MAPS 5 +#define DRM_MEM_VMAS 6 +#define DRM_MEM_BUFS 7 +#define DRM_MEM_SEGS 8 +#define DRM_MEM_PAGES 9 +#define DRM_MEM_FILES 10 +#define DRM_MEM_QUEUES 11 +#define DRM_MEM_CMDS 12 +#define DRM_MEM_MAPPINGS 13 +#define DRM_MEM_BUFLISTS 14 +#define DRM_MEM_AGPLISTS 15 +#define DRM_MEM_TOTALAGP 16 +#define DRM_MEM_BOUNDAGP 17 +#define DRM_MEM_CTXBITMAP 18 +#define DRM_MEM_STUB 19 +#define DRM_MEM_SGLISTS 20 +#define DRM_MEM_CTXLIST 21 + +#define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8) + +/*@}*/ + + +/***********************************************************************/ +/** \name Backward compatibility section */ +/*@{*/ + +#ifndef MODULE_LICENSE +#define MODULE_LICENSE(x) +#endif + +#ifndef preempt_disable +#define preempt_disable() +#define preempt_enable() +#endif + +#ifndef pte_offset_map +#define pte_offset_map pte_offset +#define pte_unmap(pte) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19) +static inline struct page * vmalloc_to_page(void * vmalloc_addr) +{ + unsigned long addr = (unsigned long) vmalloc_addr; + struct page *page = NULL; + pgd_t *pgd = pgd_offset_k(addr); + pmd_t *pmd; + pte_t *ptep, pte; + + if (!pgd_none(*pgd)) { + pmd = pmd_offset(pgd, addr); + if (!pmd_none(*pmd)) { + preempt_disable(); + ptep = pte_offset_map(pmd, addr); + pte = *ptep; + if (pte_present(pte)) + page = pte_page(pte); + pte_unmap(ptep); + preempt_enable(); + } + } + return page; +} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#define DRM_RPR_ARG(vma) +#else +#define DRM_RPR_ARG(vma) vma, +#endif + +#define VM_OFFSET(vma) ((vma)->vm_pgoff << PAGE_SHIFT) + +/*@}*/ + + +/***********************************************************************/ +/** \name Macros to make printk easier */ +/*@{*/ + +/** + * Error output. + * + * \param fmt printf() like format string. + * \param arg arguments + */ +#define DRM_ERROR(fmt, arg...) \ + printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* " fmt , __FUNCTION__ , ##arg) + +/** + * Memory error output. + * + * \param area memory area where the error occurred. + * \param fmt printf() like format string. + * \param arg arguments + */ +#define DRM_MEM_ERROR(area, fmt, arg...) \ + printk(KERN_ERR "[" DRM_NAME ":%s:%s] *ERROR* " fmt , __FUNCTION__, \ + drm_mem_stats[area].name , ##arg) + +#define DRM_INFO(fmt, arg...) printk(KERN_INFO "[" DRM_NAME "] " fmt , ##arg) + +/** + * Debug output. + * + * \param fmt printf() like format string. + * \param arg arguments + */ +#if DRM_DEBUG_CODE +#define DRM_DEBUG(fmt, arg...) \ + do { \ + if ( drm_debug ) \ + printk(KERN_DEBUG \ + "[" DRM_NAME ":%s] " fmt , \ + __FUNCTION__ , ##arg); \ + } while (0) +#else +#define DRM_DEBUG(fmt, arg...) do { } while (0) +#endif + +#define DRM_PROC_LIMIT (PAGE_SIZE-80) + +#define DRM_PROC_PRINT(fmt, arg...) \ + len += sprintf(&buf[len], fmt , ##arg); \ + if (len > DRM_PROC_LIMIT) { *eof = 1; return len - offset; } + +#define DRM_PROC_PRINT_RET(ret, fmt, arg...) \ + len += sprintf(&buf[len], fmt , ##arg); \ + if (len > DRM_PROC_LIMIT) { ret; *eof = 1; return len - offset; } + +/*@}*/ + + +/***********************************************************************/ +/** \name Internal types and structures */ +/*@{*/ + +#define DRM_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) +#define DRM_MIN(a,b) ((a)<(b)?(a):(b)) +#define DRM_MAX(a,b) ((a)>(b)?(a):(b)) + +#define DRM_LEFTCOUNT(x) (((x)->rp + (x)->count - (x)->wp) % ((x)->count + 1)) +#define DRM_BUFCOUNT(x) ((x)->count - DRM_LEFTCOUNT(x)) +#define DRM_WAITCOUNT(dev,idx) DRM_BUFCOUNT(&dev->queuelist[idx]->waitlist) + +#define DRM_IF_VERSION(maj, min) (maj << 16 | min) +/** + * Get the private SAREA mapping. + * + * \param _dev DRM device. + * \param _ctx context number. + * \param _map output mapping. + */ +#define DRM_GET_PRIV_SAREA(_dev, _ctx, _map) do { \ + (_map) = (_dev)->context_sareas[_ctx]; \ +} while(0) + +/** + * Test that the hardware lock is held by the caller, returning otherwise. + * + * \param dev DRM device. + * \param filp file pointer of the caller. + */ +#define LOCK_TEST_WITH_RETURN( dev, filp ) \ +do { \ + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \ + dev->lock.filp != filp ) { \ + DRM_ERROR( "%s called without lock held\n", \ + __FUNCTION__ ); \ + return -EINVAL; \ + } \ +} while (0) + +/** + * Copy and IOCTL return string to user space + */ +#define DRM_COPY( name, value ) \ + len = strlen( value ); \ + if ( len > name##_len ) len = name##_len; \ + name##_len = strlen( value ); \ + if ( len && name ) { \ + if ( copy_to_user( name, value, len ) ) \ + return -EFAULT; \ + } + +/** + * Ioctl function type. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg argument. + */ +typedef int drm_ioctl_t( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); + +typedef struct drm_ioctl_desc { + drm_ioctl_t *func; + int auth_needed; + int root_only; +} drm_ioctl_desc_t; + +typedef struct drm_devstate { + pid_t owner; /**< X server pid holding x_lock */ +} drm_devstate_t; + +typedef struct drm_magic_entry { + drm_magic_t magic; + struct drm_file *priv; + struct drm_magic_entry *next; +} drm_magic_entry_t; + +typedef struct drm_magic_head { + struct drm_magic_entry *head; + struct drm_magic_entry *tail; +} drm_magic_head_t; + +typedef struct drm_vma_entry { + struct vm_area_struct *vma; + struct drm_vma_entry *next; + pid_t pid; +} drm_vma_entry_t; + +/** + * DMA buffer. + */ +typedef struct drm_buf { + int idx; /**< Index into master buflist */ + int total; /**< Buffer size */ + int order; /**< log-base-2(total) */ + int used; /**< Amount of buffer in use (for DMA) */ + unsigned long offset; /**< Byte offset (used internally) */ + void *address; /**< Address of buffer */ + unsigned long bus_address; /**< Bus address of buffer */ + struct drm_buf *next; /**< Kernel-only: used for free list */ + __volatile__ int waiting; /**< On kernel DMA queue */ + __volatile__ int pending; /**< On hardware DMA queue */ + wait_queue_head_t dma_wait; /**< Processes waiting */ + struct file *filp; /**< Pointer to holding file descr */ + int context; /**< Kernel queue for this buffer */ + int while_locked;/**< Dispatch this buffer while locked */ + enum { + DRM_LIST_NONE = 0, + DRM_LIST_FREE = 1, + DRM_LIST_WAIT = 2, + DRM_LIST_PEND = 3, + DRM_LIST_PRIO = 4, + DRM_LIST_RECLAIM = 5 + } list; /**< Which list we're on */ + + int dev_priv_size; /**< Size of buffer private storage */ + void *dev_private; /**< Per-buffer private storage */ +} drm_buf_t; + + +/** bufs is one longer than it has to be */ +typedef struct drm_waitlist { + int count; /**< Number of possible buffers */ + drm_buf_t **bufs; /**< List of pointers to buffers */ + drm_buf_t **rp; /**< Read pointer */ + drm_buf_t **wp; /**< Write pointer */ + drm_buf_t **end; /**< End pointer */ + spinlock_t read_lock; + spinlock_t write_lock; +} drm_waitlist_t; + +typedef struct drm_freelist { + int initialized; /**< Freelist in use */ + atomic_t count; /**< Number of free buffers */ + drm_buf_t *next; /**< End pointer */ + + wait_queue_head_t waiting; /**< Processes waiting on free bufs */ + int low_mark; /**< Low water mark */ + int high_mark; /**< High water mark */ + atomic_t wfh; /**< If waiting for high mark */ + spinlock_t lock; +} drm_freelist_t; + +/** + * Buffer entry. There is one of this for each buffer size order. + */ +typedef struct drm_buf_entry { + int buf_size; /**< size */ + int buf_count; /**< number of buffers */ + drm_buf_t *buflist; /**< buffer list */ + int seg_count; + int page_order; + unsigned long *seglist; + + drm_freelist_t freelist; +} drm_buf_entry_t; + +/** File private data */ +typedef struct drm_file { + int authenticated; + int minor; + pid_t pid; + uid_t uid; + drm_magic_t magic; + unsigned long ioctl_count; + struct drm_file *next; + struct drm_file *prev; + struct drm_head *head; + int remove_auth_on_close; + unsigned long lock_count; + void *driver_priv; +} drm_file_t; + +/** Wait queue */ +typedef struct drm_queue { + atomic_t use_count; /**< Outstanding uses (+1) */ + atomic_t finalization; /**< Finalization in progress */ + atomic_t block_count; /**< Count of processes waiting */ + atomic_t block_read; /**< Queue blocked for reads */ + wait_queue_head_t read_queue; /**< Processes waiting on block_read */ + atomic_t block_write; /**< Queue blocked for writes */ + wait_queue_head_t write_queue; /**< Processes waiting on block_write */ +#if 1 + atomic_t total_queued; /**< Total queued statistic */ + atomic_t total_flushed;/**< Total flushes statistic */ + atomic_t total_locks; /**< Total locks statistics */ +#endif + drm_ctx_flags_t flags; /**< Context preserving and 2D-only */ + drm_waitlist_t waitlist; /**< Pending buffers */ + wait_queue_head_t flush_queue; /**< Processes waiting until flush */ +} drm_queue_t; + +/** + * Lock data. + */ +typedef struct drm_lock_data { + drm_hw_lock_t *hw_lock; /**< Hardware lock */ + struct file *filp; /**< File descr of lock holder (0=kernel) */ + wait_queue_head_t lock_queue; /**< Queue of blocked processes */ + unsigned long lock_time; /**< Time of last lock in jiffies */ +} drm_lock_data_t; + +/** + * DMA data. + */ +typedef struct drm_device_dma { + + drm_buf_entry_t bufs[DRM_MAX_ORDER+1]; /**< buffers, grouped by their size order */ + int buf_count; /**< total number of buffers */ + drm_buf_t **buflist; /**< Vector of pointers into drm_device_dma::bufs */ + int seg_count; + int page_count; /**< number of pages */ + unsigned long *pagelist; /**< page list */ + unsigned long byte_count; + enum { + _DRM_DMA_USE_AGP = 0x01, + _DRM_DMA_USE_SG = 0x02 + } flags; + +} drm_device_dma_t; + +/** + * AGP memory entry. Stored as a doubly linked list. + */ +typedef struct drm_agp_mem { + unsigned long handle; /**< handle */ + DRM_AGP_MEM *memory; + unsigned long bound; /**< address */ + int pages; + struct drm_agp_mem *prev; /**< previous entry */ + struct drm_agp_mem *next; /**< next entry */ +} drm_agp_mem_t; + +/** + * AGP data. + * + * \sa drm_agp_init() and drm_device::agp. + */ +typedef struct drm_agp_head { + DRM_AGP_KERN agp_info; /**< AGP device information */ + drm_agp_mem_t *memory; /**< memory entries */ + unsigned long mode; /**< AGP mode */ + struct agp_bridge_data *bridge; + int enabled; /**< whether the AGP bus as been enabled */ + int acquired; /**< whether the AGP device has been acquired */ + unsigned long base; + int agp_mtrr; + int cant_use_aperture; + unsigned long page_mask; +} drm_agp_head_t; + +/** + * Scatter-gather memory. + */ +typedef struct drm_sg_mem { + unsigned long handle; + void *virtual; + int pages; + struct page **pagelist; + dma_addr_t *busaddr; +} drm_sg_mem_t; + +typedef struct drm_sigdata { + int context; + drm_hw_lock_t *lock; +} drm_sigdata_t; + +/** + * Mappings list + */ +typedef struct drm_map_list { + struct list_head head; /**< list head */ + drm_map_t *map; /**< mapping */ +} drm_map_list_t; + +typedef drm_map_t drm_local_map_t; + +/** + * Context handle list + */ +typedef struct drm_ctx_list { + struct list_head head; /**< list head */ + drm_context_t handle; /**< context handle */ + drm_file_t *tag; /**< associated fd private data */ +} drm_ctx_list_t; + + +typedef struct drm_vbl_sig { + struct list_head head; + unsigned int sequence; + struct siginfo info; + struct task_struct *task; +} drm_vbl_sig_t; + + +/** + * DRM driver structure. This structure represent the common code for + * a family of cards. There will one drm_device for each card present + * in this family + */ +struct drm_device; + +struct drm_driver { + int (*preinit)(struct drm_device *, unsigned long flags); + void (*prerelease)(struct drm_device *, struct file *filp); + void (*pretakedown)(struct drm_device *); + int (*postcleanup)(struct drm_device *); + int (*presetup)(struct drm_device *); + int (*postsetup)(struct drm_device *); + int (*dma_ioctl)( DRM_IOCTL_ARGS ); + int (*open_helper)(struct drm_device *, drm_file_t *); + void (*free_filp_priv)(struct drm_device *, drm_file_t *); + void (*release)(struct drm_device *, struct file *filp); + void (*dma_ready)(struct drm_device *); + int (*dma_quiescent)(struct drm_device *); + int (*context_ctor)(struct drm_device *dev, int context); + int (*context_dtor)(struct drm_device *dev, int context); + int (*kernel_context_switch)(struct drm_device *dev, int old, int new); + void (*kernel_context_switch_unlock)(struct drm_device *dev, drm_lock_t *lock); + int (*vblank_wait)(struct drm_device *dev, unsigned int *sequence); + /* these have to be filled in */ + int (*postinit)(struct drm_device *, unsigned long flags); + irqreturn_t (*irq_handler)( DRM_IRQ_ARGS ); + void (*irq_preinstall)(struct drm_device *dev); + void (*irq_postinstall)(struct drm_device *dev); + void (*irq_uninstall)(struct drm_device *dev); + void (*reclaim_buffers)(struct drm_device *dev, struct file *filp); + unsigned long (*get_map_ofs)(drm_map_t *map); + unsigned long (*get_reg_ofs)(struct drm_device *dev); + void (*set_version)(struct drm_device *dev, drm_set_version_t *sv); + int (*version)(drm_version_t *version); + u32 driver_features; + int dev_priv_size; + drm_ioctl_desc_t *ioctls; + int num_ioctls; + struct file_operations fops; + struct pci_driver pci_driver; +}; + +/** + * DRM head structure. This structure represent a video head on a card + * that may contain multiple heads. Embed one per head of these in the + * private drm_device structure. + */ +typedef struct drm_head { + int minor; /**< Minor device number */ + struct drm_device *dev; + struct proc_dir_entry *dev_root; /**< proc directory entry */ + dev_t device; /**< Device number for mknod */ + struct class_device *dev_class; +} drm_head_t; + +/** + * DRM device structure. This structure represent a complete card that + * may contain multiple heads. + */ +typedef struct drm_device { + char *unique; /**< Unique identifier: e.g., busid */ + int unique_len; /**< Length of unique field */ + char *devname; /**< For /proc/interrupts */ + int if_version; /**< Highest interface version set */ + + int blocked; /**< Blocked due to VC switch? */ + + /** \name Locks */ + /*@{*/ + spinlock_t count_lock; /**< For inuse, drm_device::open_count, drm_device::buf_use */ + struct semaphore struct_sem; /**< For others */ + /*@}*/ + + /** \name Usage Counters */ + /*@{*/ + int open_count; /**< Outstanding files open */ + atomic_t ioctl_count; /**< Outstanding IOCTLs pending */ + atomic_t vma_count; /**< Outstanding vma areas open */ + int buf_use; /**< Buffers in use -- cannot alloc */ + atomic_t buf_alloc; /**< Buffer allocation in progress */ + /*@}*/ + + /** \name Performance counters */ + /*@{*/ + unsigned long counters; + drm_stat_type_t types[15]; + atomic_t counts[15]; + /*@}*/ + + /** \name Authentication */ + /*@{*/ + drm_file_t *file_first; /**< file list head */ + drm_file_t *file_last; /**< file list tail */ + drm_magic_head_t magiclist[DRM_HASH_SIZE]; /**< magic hash table */ + /*@}*/ + + /** \name Memory management */ + /*@{*/ + drm_map_list_t *maplist; /**< Linked list of regions */ + int map_count; /**< Number of mappable regions */ + + /** \name Context handle management */ + /*@{*/ + drm_ctx_list_t *ctxlist; /**< Linked list of context handles */ + int ctx_count; /**< Number of context handles */ + struct semaphore ctxlist_sem; /**< For ctxlist */ + + drm_map_t **context_sareas; /**< per-context SAREA's */ + int max_context; + + drm_vma_entry_t *vmalist; /**< List of vmas (for debugging) */ + drm_lock_data_t lock; /**< Information on hardware lock */ + /*@}*/ + + /** \name DMA queues (contexts) */ + /*@{*/ + int queue_count; /**< Number of active DMA queues */ + int queue_reserved; /**< Number of reserved DMA queues */ + int queue_slots; /**< Actual length of queuelist */ + drm_queue_t **queuelist; /**< Vector of pointers to DMA queues */ + drm_device_dma_t *dma; /**< Optional pointer for DMA support */ + /*@}*/ + + /** \name Context support */ + /*@{*/ + int irq; /**< Interrupt used by board */ + int irq_enabled; /**< True if irq handler is enabled */ + __volatile__ long context_flag; /**< Context swapping flag */ + __volatile__ long interrupt_flag; /**< Interruption handler flag */ + __volatile__ long dma_flag; /**< DMA dispatch flag */ + struct timer_list timer; /**< Timer for delaying ctx switch */ + wait_queue_head_t context_wait; /**< Processes waiting on ctx switch */ + int last_checked; /**< Last context checked for DMA */ + int last_context; /**< Last current context */ + unsigned long last_switch; /**< jiffies at last context switch */ + /*@}*/ + + struct work_struct work; + /** \name VBLANK IRQ support */ + /*@{*/ + + wait_queue_head_t vbl_queue; /**< VBLANK wait queue */ + atomic_t vbl_received; + spinlock_t vbl_lock; + drm_vbl_sig_t vbl_sigs; /**< signal list to send on VBLANK */ + unsigned int vbl_pending; + + /*@}*/ + cycles_t ctx_start; + cycles_t lck_start; + + char buf[DRM_BSZ]; /**< Output buffer */ + char *buf_rp; /**< Read pointer */ + char *buf_wp; /**< Write pointer */ + char *buf_end; /**< End pointer */ + struct fasync_struct *buf_async;/**< Processes waiting for SIGIO */ + wait_queue_head_t buf_readers; /**< Processes waiting to read */ + wait_queue_head_t buf_writers; /**< Processes waiting to ctx switch */ + + drm_agp_head_t *agp; /**< AGP data */ + + struct pci_dev *pdev; /**< PCI device structure */ + int pci_domain; /**< PCI bus domain number */ + int pci_bus; /**< PCI bus number */ + int pci_slot; /**< PCI slot number */ + int pci_func; /**< PCI function number */ +#ifdef __alpha__ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) + struct pci_controler *hose; +#else + struct pci_controller *hose; +#endif +#endif + drm_sg_mem_t *sg; /**< Scatter gather memory */ + unsigned long *ctx_bitmap; /**< context bitmap */ + void *dev_private; /**< device private data */ + drm_sigdata_t sigdata; /**< For block_all_signals */ + sigset_t sigmask; + + struct drm_driver *driver; + drm_local_map_t *agp_buffer_map; + drm_head_t primary; /**< primary screen head */ +} drm_device_t; + +static __inline__ int drm_core_check_feature(struct drm_device *dev, int feature) +{ + return ((dev->driver->driver_features & feature) ? 1 : 0); +} + +#if __OS_HAS_AGP +static inline int drm_core_has_AGP(struct drm_device *dev) +{ + return drm_core_check_feature(dev, DRIVER_USE_AGP); +} +#else +#define drm_core_has_AGP(dev) (0) +#endif + +#if __OS_HAS_MTRR +static inline int drm_core_has_MTRR(struct drm_device *dev) +{ + return drm_core_check_feature(dev, DRIVER_USE_MTRR); +} +#else +#define drm_core_has_MTRR(dev) (0) +#endif + +/******************************************************************/ +/** \name Internal function definitions */ +/*@{*/ + + /* Misc. support (drm_init.h) */ +extern int drm_flags; +extern void drm_parse_options( char *s ); +extern int drm_cpu_valid( void ); + + /* Driver support (drm_drv.h) */ +extern int drm_init(struct drm_driver *driver); +extern void drm_exit(struct drm_driver *driver); +extern int drm_version(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_takedown(drm_device_t * dev); + + /* Device support (drm_fops.h) */ +extern int drm_open(struct inode *inode, struct file *filp); +extern int drm_stub_open(struct inode *inode, struct file *filp); +extern int drm_open_helper(struct inode *inode, struct file *filp, + drm_device_t *dev); +extern int drm_flush(struct file *filp); +extern int drm_fasync(int fd, struct file *filp, int on); +extern int drm_release(struct inode *inode, struct file *filp); + + /* Mapping support (drm_vm.h) */ +extern void drm_vm_open(struct vm_area_struct *vma); +extern void drm_vm_close(struct vm_area_struct *vma); +extern void drm_vm_shm_close(struct vm_area_struct *vma); +extern int drm_mmap_dma(struct file *filp, + struct vm_area_struct *vma); +extern int drm_mmap(struct file *filp, struct vm_area_struct *vma); +extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait); +extern ssize_t drm_read(struct file *filp, char __user *buf, size_t count, loff_t *off); + + /* Memory management support (drm_memory.h) */ +#include "drm_memory.h" +extern void drm_mem_init(void); +extern int drm_mem_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +extern void *drm_calloc(size_t nmemb, size_t size, int area); +extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, + int area); +extern unsigned long drm_alloc_pages(int order, int area); +extern void drm_free_pages(unsigned long address, int order, + int area); +extern void *drm_ioremap(unsigned long offset, unsigned long size, drm_device_t *dev); +extern void *drm_ioremap_nocache(unsigned long offset, unsigned long size, + drm_device_t *dev); +extern void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *dev); + +extern DRM_AGP_MEM *drm_alloc_agp(struct agp_bridge_data *bridge, int pages, u32 type); +extern int drm_free_agp(DRM_AGP_MEM *handle, int pages); +extern int drm_bind_agp(DRM_AGP_MEM *handle, unsigned int start); +extern int drm_unbind_agp(DRM_AGP_MEM *handle); + + /* Misc. IOCTL support (drm_ioctl.h) */ +extern int drm_irq_by_busid(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getunique(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_setunique(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getmap(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getclient(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getstats(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_setversion(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* Context IOCTL support (drm_context.h) */ +extern int drm_resctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_addctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_modctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_getctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_switchctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_newctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_rmctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); + +extern int drm_context_switch(drm_device_t *dev, int old, int new); +extern int drm_context_switch_complete(drm_device_t *dev, int new); + +extern int drm_ctxbitmap_init( drm_device_t *dev ); +extern void drm_ctxbitmap_cleanup( drm_device_t *dev ); +extern void drm_ctxbitmap_free( drm_device_t *dev, int ctx_handle ); + +extern int drm_setsareactx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_getsareactx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); + + /* Drawable IOCTL support (drm_drawable.h) */ +extern int drm_adddraw(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_rmdraw(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + + /* Authentication IOCTL support (drm_auth.h) */ +extern int drm_add_magic(drm_device_t *dev, drm_file_t *priv, + drm_magic_t magic); +extern int drm_remove_magic(drm_device_t *dev, drm_magic_t magic); +extern int drm_getmagic(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_authmagic(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* Placeholder for ioctls past */ +extern int drm_noop(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* Locking IOCTL support (drm_lock.h) */ +extern int drm_lock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_unlock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_lock_take(__volatile__ unsigned int *lock, + unsigned int context); +extern int drm_lock_transfer(drm_device_t *dev, + __volatile__ unsigned int *lock, + unsigned int context); +extern int drm_lock_free(drm_device_t *dev, + __volatile__ unsigned int *lock, + unsigned int context); +extern int drm_notifier(void *priv); + + /* Buffer management support (drm_bufs.h) */ +extern int drm_order( unsigned long size ); +extern int drm_addmap( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_rmmap( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_addbufs( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_infobufs( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_markbufs( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_freebufs( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_mapbufs( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); + + /* DMA support (drm_dma.h) */ +extern int drm_dma_setup(drm_device_t *dev); +extern void drm_dma_takedown(drm_device_t *dev); +extern void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf); +extern void drm_core_reclaim_buffers(drm_device_t *dev, struct file *filp); + + /* IRQ support (drm_irq.h) */ +extern int drm_control( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int drm_irq_install( drm_device_t *dev ); +extern int drm_irq_uninstall( drm_device_t *dev ); +extern irqreturn_t drm_irq_handler( DRM_IRQ_ARGS ); +extern void drm_driver_irq_preinstall( drm_device_t *dev ); +extern void drm_driver_irq_postinstall( drm_device_t *dev ); +extern void drm_driver_irq_uninstall( drm_device_t *dev ); + +extern int drm_wait_vblank(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_vblank_wait(drm_device_t *dev, unsigned int *vbl_seq); +extern void drm_vbl_send_signals( drm_device_t *dev ); + + /* AGP/GART support (drm_agpsupport.h) */ +extern drm_agp_head_t *drm_agp_init(drm_device_t *dev); +extern int drm_agp_acquire(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern void drm_agp_do_release(drm_device_t *dev); +extern int drm_agp_release(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_enable(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_info(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_alloc(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_free(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_unbind(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_bind(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size_t pages, u32 type); +extern int drm_agp_free_memory(DRM_AGP_MEM *handle); +extern int drm_agp_bind_memory(DRM_AGP_MEM *handle, off_t start); +extern int drm_agp_unbind_memory(DRM_AGP_MEM *handle); + + /* Stub support (drm_stub.h) */ +extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent, + struct drm_driver *driver); +extern int drm_put_dev(drm_device_t * dev); +extern int drm_get_head(drm_device_t * dev, drm_head_t *head); +extern int drm_put_head(drm_head_t * head); +extern unsigned int drm_debug; +extern unsigned int drm_cards_limit; +extern drm_head_t **drm_heads; +extern struct drm_sysfs_class *drm_class; +extern struct proc_dir_entry *drm_proc_root; + + /* Proc support (drm_proc.h) */ +extern int drm_proc_init(drm_device_t *dev, + int minor, + struct proc_dir_entry *root, + struct proc_dir_entry **dev_root); +extern int drm_proc_cleanup(int minor, + struct proc_dir_entry *root, + struct proc_dir_entry *dev_root); + + /* Scatter Gather Support (drm_scatter.h) */ +extern void drm_sg_cleanup(drm_sg_mem_t *entry); +extern int drm_sg_alloc(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_sg_free(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* ATI PCIGART support (ati_pcigart.h) */ +extern int drm_ati_pcigart_init(drm_device_t *dev, + unsigned long *addr, + dma_addr_t *bus_addr); +extern int drm_ati_pcigart_cleanup(drm_device_t *dev, + unsigned long addr, + dma_addr_t bus_addr); + +extern void *drm_pci_alloc(drm_device_t * dev, size_t size, + size_t align, dma_addr_t maxaddr, + dma_addr_t * busaddr); + +extern void drm_pci_free(drm_device_t * dev, size_t size, + void *vaddr, dma_addr_t busaddr); + + /* sysfs support (drm_sysfs.c) */ +struct drm_sysfs_class; +extern struct drm_sysfs_class *drm_sysfs_create(struct module *owner, + char *name); +extern void drm_sysfs_destroy(struct drm_sysfs_class *cs); +extern struct class_device *drm_sysfs_device_add(struct drm_sysfs_class *cs, + dev_t dev, + struct device *device, + const char *fmt, ...); +extern void drm_sysfs_device_remove(dev_t dev); + + +/* Inline replacements for DRM_IOREMAP macros */ +static __inline__ void drm_core_ioremap(struct drm_map *map, struct drm_device *dev) +{ + map->handle = drm_ioremap( map->offset, map->size, dev ); +} + +static __inline__ void drm_core_ioremap_nocache(struct drm_map *map, struct drm_device *dev) +{ + map->handle = drm_ioremap_nocache(map->offset, map->size, dev); +} + +static __inline__ void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev) +{ + if ( map->handle && map->size ) + drm_ioremapfree( map->handle, map->size, dev ); +} + +static __inline__ struct drm_map *drm_core_findmap(struct drm_device *dev, unsigned long offset) +{ + struct list_head *_list; + list_for_each( _list, &dev->maplist->head ) { + drm_map_list_t *_entry = list_entry( _list, drm_map_list_t, head ); + if ( _entry->map && + _entry->map->offset == offset ) { + return _entry->map; + } + } + return NULL; +} + +static __inline__ void drm_core_dropmap(struct drm_map *map) +{ +} + +#ifndef DEBUG_MEMORY +/** Wrapper around kmalloc() */ +static __inline__ void *drm_alloc(size_t size, int area) +{ + return kmalloc(size, GFP_KERNEL); +} + +/** Wrapper around kfree() */ +static __inline__ void drm_free(void *pt, size_t size, int area) +{ + kfree(pt); +} +#else +extern void *drm_alloc(size_t size, int area); +extern void drm_free(void *pt, size_t size, int area); +#endif + +/*@}*/ + +extern unsigned long drm_core_get_map_ofs(drm_map_t *map); +extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev); + +#endif /* __KERNEL__ */ +#endif diff --git a/drivers/char/drm/drm_agpsupport.c b/drivers/char/drm/drm_agpsupport.c new file mode 100644 index 000000000000..8d94c0b5fa44 --- /dev/null +++ b/drivers/char/drm/drm_agpsupport.c @@ -0,0 +1,448 @@ +/** + * \file drm_agpsupport.h + * DRM support for AGP/GART backend + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" +#include + +#if __OS_HAS_AGP + +/** + * AGP information ioctl. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a (output) drm_agp_info structure. + * \return zero on success or a negative number on failure. + * + * Verifies the AGP device has been initialized and acquired and fills in the + * drm_agp_info structure with the information in drm_agp_head::agp_info. + */ +int drm_agp_info(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + DRM_AGP_KERN *kern; + drm_agp_info_t info; + + if (!dev->agp || !dev->agp->acquired) + return -EINVAL; + + kern = &dev->agp->agp_info; + info.agp_version_major = kern->version.major; + info.agp_version_minor = kern->version.minor; + info.mode = kern->mode; + info.aperture_base = kern->aper_base; + info.aperture_size = kern->aper_size * 1024 * 1024; + info.memory_allowed = kern->max_memory << PAGE_SHIFT; + info.memory_used = kern->current_memory << PAGE_SHIFT; + info.id_vendor = kern->device->vendor; + info.id_device = kern->device->device; + + if (copy_to_user((drm_agp_info_t __user *)arg, &info, sizeof(info))) + return -EFAULT; + return 0; +} + +/** + * Acquire the AGP device (ioctl). + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument. + * \return zero on success or a negative number on failure. + * + * Verifies the AGP device hasn't been acquired before and calls + * agp_acquire(). + */ +int drm_agp_acquire(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + + if (!dev->agp) + return -ENODEV; + if (dev->agp->acquired) + return -EBUSY; + if (!(dev->agp->bridge = agp_backend_acquire(dev->pdev))) + return -ENODEV; + dev->agp->acquired = 1; + return 0; +} + +/** + * Release the AGP device (ioctl). + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument. + * \return zero on success or a negative number on failure. + * + * Verifies the AGP device has been acquired and calls agp_backend_release(). + */ +int drm_agp_release(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + + if (!dev->agp || !dev->agp->acquired) + return -EINVAL; + agp_backend_release(dev->agp->bridge); + dev->agp->acquired = 0; + return 0; + +} + +/** + * Release the AGP device. + * + * Calls agp_backend_release(). + */ +void drm_agp_do_release(drm_device_t *dev) +{ + agp_backend_release(dev->agp->bridge); +} + +/** + * Enable the AGP bus. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_agp_mode structure. + * \return zero on success or a negative number on failure. + * + * Verifies the AGP device has been acquired but not enabled, and calls + * agp_enable(). + */ +int drm_agp_enable(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_agp_mode_t mode; + + if (!dev->agp || !dev->agp->acquired) + return -EINVAL; + + if (copy_from_user(&mode, (drm_agp_mode_t __user *)arg, sizeof(mode))) + return -EFAULT; + + dev->agp->mode = mode.mode; + agp_enable(dev->agp->bridge, mode.mode); + dev->agp->base = dev->agp->agp_info.aper_base; + dev->agp->enabled = 1; + return 0; +} + +/** + * Allocate AGP memory. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_agp_buffer structure. + * \return zero on success or a negative number on failure. + * + * Verifies the AGP device is present and has been acquired, allocates the + * memory via alloc_agp() and creates a drm_agp_mem entry for it. + */ +int drm_agp_alloc(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_agp_buffer_t request; + drm_agp_mem_t *entry; + DRM_AGP_MEM *memory; + unsigned long pages; + u32 type; + drm_agp_buffer_t __user *argp = (void __user *)arg; + + if (!dev->agp || !dev->agp->acquired) + return -EINVAL; + if (copy_from_user(&request, argp, sizeof(request))) + return -EFAULT; + if (!(entry = drm_alloc(sizeof(*entry), DRM_MEM_AGPLISTS))) + return -ENOMEM; + + memset(entry, 0, sizeof(*entry)); + + pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE; + type = (u32) request.type; + + if (!(memory = drm_alloc_agp(dev->agp->bridge, pages, type))) { + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); + return -ENOMEM; + } + + entry->handle = (unsigned long)memory->key + 1; + entry->memory = memory; + entry->bound = 0; + entry->pages = pages; + entry->prev = NULL; + entry->next = dev->agp->memory; + if (dev->agp->memory) + dev->agp->memory->prev = entry; + dev->agp->memory = entry; + + request.handle = entry->handle; + request.physical = memory->physical; + + if (copy_to_user(argp, &request, sizeof(request))) { + dev->agp->memory = entry->next; + dev->agp->memory->prev = NULL; + drm_free_agp(memory, pages); + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); + return -EFAULT; + } + return 0; +} + +/** + * Search for the AGP memory entry associated with a handle. + * + * \param dev DRM device structure. + * \param handle AGP memory handle. + * \return pointer to the drm_agp_mem structure associated with \p handle. + * + * Walks through drm_agp_head::memory until finding a matching handle. + */ +static drm_agp_mem_t *drm_agp_lookup_entry(drm_device_t *dev, + unsigned long handle) +{ + drm_agp_mem_t *entry; + + for (entry = dev->agp->memory; entry; entry = entry->next) { + if (entry->handle == handle) + return entry; + } + return NULL; +} + +/** + * Unbind AGP memory from the GATT (ioctl). + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_agp_binding structure. + * \return zero on success or a negative number on failure. + * + * Verifies the AGP device is present and acquired, looks-up the AGP memory + * entry and passes it to the unbind_agp() function. + */ +int drm_agp_unbind(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_agp_binding_t request; + drm_agp_mem_t *entry; + int ret; + + if (!dev->agp || !dev->agp->acquired) + return -EINVAL; + if (copy_from_user(&request, (drm_agp_binding_t __user *)arg, sizeof(request))) + return -EFAULT; + if (!(entry = drm_agp_lookup_entry(dev, request.handle))) + return -EINVAL; + if (!entry->bound) + return -EINVAL; + ret = drm_unbind_agp(entry->memory); + if (ret == 0) + entry->bound = 0; + return ret; +} + +/** + * Bind AGP memory into the GATT (ioctl) + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_agp_binding structure. + * \return zero on success or a negative number on failure. + * + * Verifies the AGP device is present and has been acquired and that no memory + * is currently bound into the GATT. Looks-up the AGP memory entry and passes + * it to bind_agp() function. + */ +int drm_agp_bind(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_agp_binding_t request; + drm_agp_mem_t *entry; + int retcode; + int page; + + if (!dev->agp || !dev->agp->acquired) + return -EINVAL; + if (copy_from_user(&request, (drm_agp_binding_t __user *)arg, sizeof(request))) + return -EFAULT; + if (!(entry = drm_agp_lookup_entry(dev, request.handle))) + return -EINVAL; + if (entry->bound) + return -EINVAL; + page = (request.offset + PAGE_SIZE - 1) / PAGE_SIZE; + if ((retcode = drm_bind_agp(entry->memory, page))) + return retcode; + entry->bound = dev->agp->base + (page << PAGE_SHIFT); + DRM_DEBUG("base = 0x%lx entry->bound = 0x%lx\n", + dev->agp->base, entry->bound); + return 0; +} + +/** + * Free AGP memory (ioctl). + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_agp_buffer structure. + * \return zero on success or a negative number on failure. + * + * Verifies the AGP device is present and has been acquired and looks up the + * AGP memory entry. If the memory it's currently bound, unbind it via + * unbind_agp(). Frees it via free_agp() as well as the entry itself + * and unlinks from the doubly linked list it's inserted in. + */ +int drm_agp_free(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_agp_buffer_t request; + drm_agp_mem_t *entry; + + if (!dev->agp || !dev->agp->acquired) + return -EINVAL; + if (copy_from_user(&request, (drm_agp_buffer_t __user *)arg, sizeof(request))) + return -EFAULT; + if (!(entry = drm_agp_lookup_entry(dev, request.handle))) + return -EINVAL; + if (entry->bound) + drm_unbind_agp(entry->memory); + + if (entry->prev) + entry->prev->next = entry->next; + else + dev->agp->memory = entry->next; + + if (entry->next) + entry->next->prev = entry->prev; + + drm_free_agp(entry->memory, entry->pages); + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); + return 0; +} + +/** + * Initialize the AGP resources. + * + * \return pointer to a drm_agp_head structure. + * + */ +drm_agp_head_t *drm_agp_init(drm_device_t *dev) +{ + drm_agp_head_t *head = NULL; + + if (!(head = drm_alloc(sizeof(*head), DRM_MEM_AGPLISTS))) + return NULL; + memset((void *)head, 0, sizeof(*head)); + head->bridge = agp_find_bridge(dev->pdev); + if (!head->bridge) { + if (!(head->bridge = agp_backend_acquire(dev->pdev))) { + drm_free(head, sizeof(*head), DRM_MEM_AGPLISTS); + return NULL; + } + agp_copy_info(head->bridge, &head->agp_info); + agp_backend_release(head->bridge); + } else { + agp_copy_info(head->bridge, &head->agp_info); + } + if (head->agp_info.chipset == NOT_SUPPORTED) { + drm_free(head, sizeof(*head), DRM_MEM_AGPLISTS); + return NULL; + } + head->memory = NULL; +#if LINUX_VERSION_CODE <= 0x020408 + head->cant_use_aperture = 0; + head->page_mask = ~(0xfff); +#else + head->cant_use_aperture = head->agp_info.cant_use_aperture; + head->page_mask = head->agp_info.page_mask; +#endif + + return head; +} + +/** Calls agp_allocate_memory() */ +DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size_t pages, u32 type) +{ + return agp_allocate_memory(bridge, pages, type); +} + +/** Calls agp_free_memory() */ +int drm_agp_free_memory(DRM_AGP_MEM *handle) +{ + if (!handle) + return 0; + agp_free_memory(handle); + return 1; +} + +/** Calls agp_bind_memory() */ +int drm_agp_bind_memory(DRM_AGP_MEM *handle, off_t start) +{ + if (!handle) + return -EINVAL; + return agp_bind_memory(handle, start); +} + +/** Calls agp_unbind_memory() */ +int drm_agp_unbind_memory(DRM_AGP_MEM *handle) +{ + if (!handle) + return -EINVAL; + return agp_unbind_memory(handle); +} + +#endif /* __OS_HAS_AGP */ diff --git a/drivers/char/drm/drm_auth.c b/drivers/char/drm/drm_auth.c new file mode 100644 index 000000000000..b428761c4e91 --- /dev/null +++ b/drivers/char/drm/drm_auth.c @@ -0,0 +1,230 @@ +/** + * \file drm_auth.h + * IOCTLs for authentication + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Tue Feb 2 08:37:54 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" + +/** + * Generate a hash key from a magic. + * + * \param magic magic. + * \return hash key. + * + * The key is the modulus of the hash table size, #DRM_HASH_SIZE, which must be + * a power of 2. + */ +static int drm_hash_magic(drm_magic_t magic) +{ + return magic & (DRM_HASH_SIZE-1); +} + +/** + * Find the file with the given magic number. + * + * \param dev DRM device. + * \param magic magic number. + * + * Searches in drm_device::magiclist within all files with the same hash key + * the one with matching magic number, while holding the drm_device::struct_sem + * lock. + */ +static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic) +{ + drm_file_t *retval = NULL; + drm_magic_entry_t *pt; + int hash = drm_hash_magic(magic); + + down(&dev->struct_sem); + for (pt = dev->magiclist[hash].head; pt; pt = pt->next) { + if (pt->magic == magic) { + retval = pt->priv; + break; + } + } + up(&dev->struct_sem); + return retval; +} + +/** + * Adds a magic number. + * + * \param dev DRM device. + * \param priv file private data. + * \param magic magic number. + * + * Creates a drm_magic_entry structure and appends to the linked list + * associated the magic number hash key in drm_device::magiclist, while holding + * the drm_device::struct_sem lock. + */ +int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic) +{ + int hash; + drm_magic_entry_t *entry; + + DRM_DEBUG("%d\n", magic); + + hash = drm_hash_magic(magic); + entry = drm_alloc(sizeof(*entry), DRM_MEM_MAGIC); + if (!entry) return -ENOMEM; + memset(entry, 0, sizeof(*entry)); + entry->magic = magic; + entry->priv = priv; + entry->next = NULL; + + down(&dev->struct_sem); + if (dev->magiclist[hash].tail) { + dev->magiclist[hash].tail->next = entry; + dev->magiclist[hash].tail = entry; + } else { + dev->magiclist[hash].head = entry; + dev->magiclist[hash].tail = entry; + } + up(&dev->struct_sem); + + return 0; +} + +/** + * Remove a magic number. + * + * \param dev DRM device. + * \param magic magic number. + * + * Searches and unlinks the entry in drm_device::magiclist with the magic + * number hash key, while holding the drm_device::struct_sem lock. + */ +int drm_remove_magic(drm_device_t *dev, drm_magic_t magic) +{ + drm_magic_entry_t *prev = NULL; + drm_magic_entry_t *pt; + int hash; + + + DRM_DEBUG("%d\n", magic); + hash = drm_hash_magic(magic); + + down(&dev->struct_sem); + for (pt = dev->magiclist[hash].head; pt; prev = pt, pt = pt->next) { + if (pt->magic == magic) { + if (dev->magiclist[hash].head == pt) { + dev->magiclist[hash].head = pt->next; + } + if (dev->magiclist[hash].tail == pt) { + dev->magiclist[hash].tail = prev; + } + if (prev) { + prev->next = pt->next; + } + up(&dev->struct_sem); + return 0; + } + } + up(&dev->struct_sem); + + drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); + + return -EINVAL; +} + +/** + * Get a unique magic number (ioctl). + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a resulting drm_auth structure. + * \return zero on success, or a negative number on failure. + * + * If there is a magic number in drm_file::magic then use it, otherwise + * searches an unique non-zero magic number and add it associating it with \p + * filp. + */ +int drm_getmagic(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + static drm_magic_t sequence = 0; + static DEFINE_SPINLOCK(lock); + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_auth_t auth; + + /* Find unique magic */ + if (priv->magic) { + auth.magic = priv->magic; + } else { + do { + spin_lock(&lock); + if (!sequence) ++sequence; /* reserve 0 */ + auth.magic = sequence++; + spin_unlock(&lock); + } while (drm_find_file(dev, auth.magic)); + priv->magic = auth.magic; + drm_add_magic(dev, priv, auth.magic); + } + + DRM_DEBUG("%u\n", auth.magic); + if (copy_to_user((drm_auth_t __user *)arg, &auth, sizeof(auth))) + return -EFAULT; + return 0; +} + +/** + * Authenticate with a magic. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_auth structure. + * \return zero if authentication successed, or a negative number otherwise. + * + * Checks if \p filp is associated with the magic number passed in \arg. + */ +int drm_authmagic(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_auth_t auth; + drm_file_t *file; + + if (copy_from_user(&auth, (drm_auth_t __user *)arg, sizeof(auth))) + return -EFAULT; + DRM_DEBUG("%u\n", auth.magic); + if ((file = drm_find_file(dev, auth.magic))) { + file->authenticated = 1; + drm_remove_magic(dev, auth.magic); + return 0; + } + return -EINVAL; +} diff --git a/drivers/char/drm/drm_bufs.c b/drivers/char/drm/drm_bufs.c new file mode 100644 index 000000000000..4113bcba67fe --- /dev/null +++ b/drivers/char/drm/drm_bufs.c @@ -0,0 +1,1270 @@ +/** + * \file drm_bufs.h + * Generic buffer template + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Thu Nov 23 03:10:50 2000 by gareth@valinux.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "drmP.h" + +/** + * Compute size order. Returns the exponent of the smaller power of two which + * is greater or equal to given number. + * + * \param size size. + * \return order. + * + * \todo Can be made faster. + */ +int drm_order( unsigned long size ) +{ + int order; + unsigned long tmp; + + for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) + ; + + if (size & (size - 1)) + ++order; + + return order; +} +EXPORT_SYMBOL(drm_order); + +/** + * Ioctl to specify a range of memory that is available for mapping by a non-root process. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_map structure. + * \return zero on success or a negative value on error. + * + * Adjusts the memory offset to its absolute value according to the mapping + * type. Adds the map to the map list drm_device::maplist. Adds MTRR's where + * applicable and if supported by the kernel. + */ +int drm_addmap( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_map_t *map; + drm_map_t __user *argp = (void __user *)arg; + drm_map_list_t *list; + + if ( !(filp->f_mode & 3) ) return -EACCES; /* Require read/write */ + + map = drm_alloc( sizeof(*map), DRM_MEM_MAPS ); + if ( !map ) + return -ENOMEM; + + if ( copy_from_user( map, argp, sizeof(*map) ) ) { + drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + return -EFAULT; + } + + /* Only allow shared memory to be removable since we only keep enough + * book keeping information about shared memory to allow for removal + * when processes fork. + */ + if ( (map->flags & _DRM_REMOVABLE) && map->type != _DRM_SHM ) { + drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + return -EINVAL; + } + DRM_DEBUG( "offset = 0x%08lx, size = 0x%08lx, type = %d\n", + map->offset, map->size, map->type ); + if ( (map->offset & (~PAGE_MASK)) || (map->size & (~PAGE_MASK)) ) { + drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + return -EINVAL; + } + map->mtrr = -1; + map->handle = NULL; + + switch ( map->type ) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: +#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) + if ( map->offset + map->size < map->offset || + map->offset < virt_to_phys(high_memory) ) { + drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + return -EINVAL; + } +#endif +#ifdef __alpha__ + map->offset += dev->hose->mem_space->start; +#endif + if (drm_core_has_MTRR(dev)) { + if ( map->type == _DRM_FRAME_BUFFER || + (map->flags & _DRM_WRITE_COMBINING) ) { + map->mtrr = mtrr_add( map->offset, map->size, + MTRR_TYPE_WRCOMB, 1 ); + } + } + if (map->type == _DRM_REGISTERS) + map->handle = drm_ioremap( map->offset, map->size, + dev ); + break; + + case _DRM_SHM: + map->handle = vmalloc_32(map->size); + DRM_DEBUG( "%lu %d %p\n", + map->size, drm_order( map->size ), map->handle ); + if ( !map->handle ) { + drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + return -ENOMEM; + } + map->offset = (unsigned long)map->handle; + if ( map->flags & _DRM_CONTAINS_LOCK ) { + /* Prevent a 2nd X Server from creating a 2nd lock */ + if (dev->lock.hw_lock != NULL) { + vfree( map->handle ); + drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + return -EBUSY; + } + dev->sigdata.lock = + dev->lock.hw_lock = map->handle; /* Pointer to lock */ + } + break; + case _DRM_AGP: + if (drm_core_has_AGP(dev)) { +#ifdef __alpha__ + map->offset += dev->hose->mem_space->start; +#endif + map->offset += dev->agp->base; + map->mtrr = dev->agp->agp_mtrr; /* for getmap */ + } + break; + case _DRM_SCATTER_GATHER: + if (!dev->sg) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + return -EINVAL; + } + map->offset += dev->sg->handle; + break; + + default: + drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + return -EINVAL; + } + + list = drm_alloc(sizeof(*list), DRM_MEM_MAPS); + if(!list) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + return -EINVAL; + } + memset(list, 0, sizeof(*list)); + list->map = map; + + down(&dev->struct_sem); + list_add(&list->head, &dev->maplist->head); + up(&dev->struct_sem); + + if ( copy_to_user( argp, map, sizeof(*map) ) ) + return -EFAULT; + if ( map->type != _DRM_SHM ) { + if ( copy_to_user( &argp->handle, + &map->offset, + sizeof(map->offset) ) ) + return -EFAULT; + } + return 0; +} + + +/** + * Remove a map private from list and deallocate resources if the mapping + * isn't in use. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_map_t structure. + * \return zero on success or a negative value on error. + * + * Searches the map on drm_device::maplist, removes it from the list, see if + * its being used, and free any associate resource (such as MTRR's) if it's not + * being on use. + * + * \sa addmap(). + */ +int drm_rmmap(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + struct list_head *list; + drm_map_list_t *r_list = NULL; + drm_vma_entry_t *pt, *prev; + drm_map_t *map; + drm_map_t request; + int found_maps = 0; + + if (copy_from_user(&request, (drm_map_t __user *)arg, + sizeof(request))) { + return -EFAULT; + } + + down(&dev->struct_sem); + list = &dev->maplist->head; + list_for_each(list, &dev->maplist->head) { + r_list = list_entry(list, drm_map_list_t, head); + + if(r_list->map && + r_list->map->handle == request.handle && + r_list->map->flags & _DRM_REMOVABLE) break; + } + + /* List has wrapped around to the head pointer, or its empty we didn't + * find anything. + */ + if(list == (&dev->maplist->head)) { + up(&dev->struct_sem); + return -EINVAL; + } + map = r_list->map; + list_del(list); + drm_free(list, sizeof(*list), DRM_MEM_MAPS); + + for (pt = dev->vmalist, prev = NULL; pt; prev = pt, pt = pt->next) { + if (pt->vma->vm_private_data == map) found_maps++; + } + + if(!found_maps) { + switch (map->type) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: + if (drm_core_has_MTRR(dev)) { + if (map->mtrr >= 0) { + int retcode; + retcode = mtrr_del(map->mtrr, + map->offset, + map->size); + DRM_DEBUG("mtrr_del = %d\n", retcode); + } + } + drm_ioremapfree(map->handle, map->size, dev); + break; + case _DRM_SHM: + vfree(map->handle); + break; + case _DRM_AGP: + case _DRM_SCATTER_GATHER: + break; + } + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + } + up(&dev->struct_sem); + return 0; +} + +/** + * Cleanup after an error on one of the addbufs() functions. + * + * \param entry buffer entry where the error occurred. + * + * Frees any pages and buffers associated with the given entry. + */ +static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry) +{ + int i; + + if (entry->seg_count) { + for (i = 0; i < entry->seg_count; i++) { + if (entry->seglist[i]) { + drm_free_pages(entry->seglist[i], + entry->page_order, + DRM_MEM_DMA); + } + } + drm_free(entry->seglist, + entry->seg_count * + sizeof(*entry->seglist), + DRM_MEM_SEGS); + + entry->seg_count = 0; + } + + if (entry->buf_count) { + for (i = 0; i < entry->buf_count; i++) { + if (entry->buflist[i].dev_private) { + drm_free(entry->buflist[i].dev_private, + entry->buflist[i].dev_priv_size, + DRM_MEM_BUFS); + } + } + drm_free(entry->buflist, + entry->buf_count * + sizeof(*entry->buflist), + DRM_MEM_BUFS); + + entry->buf_count = 0; + } +} + +#if __OS_HAS_AGP +/** + * Add AGP buffers for DMA transfers (ioctl). + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_buf_desc_t request. + * \return zero on success or a negative number on failure. + * + * After some sanity checks creates a drm_buf structure for each buffer and + * reallocates the buffer list of the same size order to accommodate the new + * buffers. + */ +int drm_addbufs_agp( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t request; + drm_buf_entry_t *entry; + drm_buf_t *buf; + unsigned long offset; + unsigned long agp_offset; + int count; + int order; + int size; + int alignment; + int page_order; + int total; + int byte_count; + int i; + drm_buf_t **temp_buflist; + drm_buf_desc_t __user *argp = (void __user *)arg; + + if ( !dma ) return -EINVAL; + + if ( copy_from_user( &request, argp, + sizeof(request) ) ) + return -EFAULT; + + count = request.count; + order = drm_order( request.size ); + size = 1 << order; + + alignment = (request.flags & _DRM_PAGE_ALIGN) + ? PAGE_ALIGN(size) : size; + page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; + total = PAGE_SIZE << page_order; + + byte_count = 0; + agp_offset = dev->agp->base + request.agp_start; + + DRM_DEBUG( "count: %d\n", count ); + DRM_DEBUG( "order: %d\n", order ); + DRM_DEBUG( "size: %d\n", size ); + DRM_DEBUG( "agp_offset: %lu\n", agp_offset ); + DRM_DEBUG( "alignment: %d\n", alignment ); + DRM_DEBUG( "page_order: %d\n", page_order ); + DRM_DEBUG( "total: %d\n", total ); + + if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; + if ( dev->queue_count ) return -EBUSY; /* Not while in use */ + + spin_lock( &dev->count_lock ); + if ( dev->buf_use ) { + spin_unlock( &dev->count_lock ); + return -EBUSY; + } + atomic_inc( &dev->buf_alloc ); + spin_unlock( &dev->count_lock ); + + down( &dev->struct_sem ); + entry = &dma->bufs[order]; + if ( entry->buf_count ) { + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; /* May only call once for each order */ + } + + if (count < 0 || count > 4096) { + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -EINVAL; + } + + entry->buflist = drm_alloc( count * sizeof(*entry->buflist), + DRM_MEM_BUFS ); + if ( !entry->buflist ) { + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; + } + memset( entry->buflist, 0, count * sizeof(*entry->buflist) ); + + entry->buf_size = size; + entry->page_order = page_order; + + offset = 0; + + while ( entry->buf_count < count ) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; + + buf->offset = (dma->byte_count + offset); + buf->bus_address = agp_offset + offset; + buf->address = (void *)(agp_offset + offset); + buf->next = NULL; + buf->waiting = 0; + buf->pending = 0; + init_waitqueue_head( &buf->dma_wait ); + buf->filp = NULL; + + buf->dev_priv_size = dev->driver->dev_priv_size; + buf->dev_private = drm_alloc( buf->dev_priv_size, + DRM_MEM_BUFS ); + if(!buf->dev_private) { + /* Set count correctly so we free the proper amount. */ + entry->buf_count = count; + drm_cleanup_buf_error(dev,entry); + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; + } + memset( buf->dev_private, 0, buf->dev_priv_size ); + + DRM_DEBUG( "buffer %d @ %p\n", + entry->buf_count, buf->address ); + + offset += alignment; + entry->buf_count++; + byte_count += PAGE_SIZE << page_order; + } + + DRM_DEBUG( "byte_count: %d\n", byte_count ); + + temp_buflist = drm_realloc( dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), + DRM_MEM_BUFS ); + if(!temp_buflist) { + /* Free the entry because it isn't valid */ + drm_cleanup_buf_error(dev,entry); + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; + } + dma->buflist = temp_buflist; + + for ( i = 0 ; i < entry->buf_count ; i++ ) { + dma->buflist[i + dma->buf_count] = &entry->buflist[i]; + } + + dma->buf_count += entry->buf_count; + dma->byte_count += byte_count; + + DRM_DEBUG( "dma->buf_count : %d\n", dma->buf_count ); + DRM_DEBUG( "entry->buf_count : %d\n", entry->buf_count ); + + up( &dev->struct_sem ); + + request.count = entry->buf_count; + request.size = size; + + if ( copy_to_user( argp, &request, sizeof(request) ) ) + return -EFAULT; + + dma->flags = _DRM_DMA_USE_AGP; + + atomic_dec( &dev->buf_alloc ); + return 0; +} +#endif /* __OS_HAS_AGP */ + +int drm_addbufs_pci( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t request; + int count; + int order; + int size; + int total; + int page_order; + drm_buf_entry_t *entry; + unsigned long page; + drm_buf_t *buf; + int alignment; + unsigned long offset; + int i; + int byte_count; + int page_count; + unsigned long *temp_pagelist; + drm_buf_t **temp_buflist; + drm_buf_desc_t __user *argp = (void __user *)arg; + + if (!drm_core_check_feature(dev, DRIVER_PCI_DMA)) return -EINVAL; + if ( !dma ) return -EINVAL; + + if ( copy_from_user( &request, argp, sizeof(request) ) ) + return -EFAULT; + + count = request.count; + order = drm_order( request.size ); + size = 1 << order; + + DRM_DEBUG( "count=%d, size=%d (%d), order=%d, queue_count=%d\n", + request.count, request.size, size, + order, dev->queue_count ); + + if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; + if ( dev->queue_count ) return -EBUSY; /* Not while in use */ + + alignment = (request.flags & _DRM_PAGE_ALIGN) + ? PAGE_ALIGN(size) : size; + page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; + total = PAGE_SIZE << page_order; + + spin_lock( &dev->count_lock ); + if ( dev->buf_use ) { + spin_unlock( &dev->count_lock ); + return -EBUSY; + } + atomic_inc( &dev->buf_alloc ); + spin_unlock( &dev->count_lock ); + + down( &dev->struct_sem ); + entry = &dma->bufs[order]; + if ( entry->buf_count ) { + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; /* May only call once for each order */ + } + + if (count < 0 || count > 4096) { + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -EINVAL; + } + + entry->buflist = drm_alloc( count * sizeof(*entry->buflist), + DRM_MEM_BUFS ); + if ( !entry->buflist ) { + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; + } + memset( entry->buflist, 0, count * sizeof(*entry->buflist) ); + + entry->seglist = drm_alloc( count * sizeof(*entry->seglist), + DRM_MEM_SEGS ); + if ( !entry->seglist ) { + drm_free( entry->buflist, + count * sizeof(*entry->buflist), + DRM_MEM_BUFS ); + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; + } + memset( entry->seglist, 0, count * sizeof(*entry->seglist) ); + + /* Keep the original pagelist until we know all the allocations + * have succeeded + */ + temp_pagelist = drm_alloc( (dma->page_count + (count << page_order)) + * sizeof(*dma->pagelist), + DRM_MEM_PAGES ); + if (!temp_pagelist) { + drm_free( entry->buflist, + count * sizeof(*entry->buflist), + DRM_MEM_BUFS ); + drm_free( entry->seglist, + count * sizeof(*entry->seglist), + DRM_MEM_SEGS ); + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; + } + memcpy(temp_pagelist, + dma->pagelist, + dma->page_count * sizeof(*dma->pagelist)); + DRM_DEBUG( "pagelist: %d entries\n", + dma->page_count + (count << page_order) ); + + entry->buf_size = size; + entry->page_order = page_order; + byte_count = 0; + page_count = 0; + + while ( entry->buf_count < count ) { + page = drm_alloc_pages( page_order, DRM_MEM_DMA ); + if ( !page ) { + /* Set count correctly so we free the proper amount. */ + entry->buf_count = count; + entry->seg_count = count; + drm_cleanup_buf_error(dev, entry); + drm_free( temp_pagelist, + (dma->page_count + (count << page_order)) + * sizeof(*dma->pagelist), + DRM_MEM_PAGES ); + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; + } + entry->seglist[entry->seg_count++] = page; + for ( i = 0 ; i < (1 << page_order) ; i++ ) { + DRM_DEBUG( "page %d @ 0x%08lx\n", + dma->page_count + page_count, + page + PAGE_SIZE * i ); + temp_pagelist[dma->page_count + page_count++] + = page + PAGE_SIZE * i; + } + for ( offset = 0 ; + offset + size <= total && entry->buf_count < count ; + offset += alignment, ++entry->buf_count ) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; + buf->offset = (dma->byte_count + byte_count + offset); + buf->address = (void *)(page + offset); + buf->next = NULL; + buf->waiting = 0; + buf->pending = 0; + init_waitqueue_head( &buf->dma_wait ); + buf->filp = NULL; + + buf->dev_priv_size = dev->driver->dev_priv_size; + buf->dev_private = drm_alloc( buf->dev_priv_size, + DRM_MEM_BUFS ); + if(!buf->dev_private) { + /* Set count correctly so we free the proper amount. */ + entry->buf_count = count; + entry->seg_count = count; + drm_cleanup_buf_error(dev,entry); + drm_free( temp_pagelist, + (dma->page_count + (count << page_order)) + * sizeof(*dma->pagelist), + DRM_MEM_PAGES ); + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; + } + memset( buf->dev_private, 0, buf->dev_priv_size ); + + DRM_DEBUG( "buffer %d @ %p\n", + entry->buf_count, buf->address ); + } + byte_count += PAGE_SIZE << page_order; + } + + temp_buflist = drm_realloc( dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), + DRM_MEM_BUFS ); + if (!temp_buflist) { + /* Free the entry because it isn't valid */ + drm_cleanup_buf_error(dev,entry); + drm_free( temp_pagelist, + (dma->page_count + (count << page_order)) + * sizeof(*dma->pagelist), + DRM_MEM_PAGES ); + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; + } + dma->buflist = temp_buflist; + + for ( i = 0 ; i < entry->buf_count ; i++ ) { + dma->buflist[i + dma->buf_count] = &entry->buflist[i]; + } + + /* No allocations failed, so now we can replace the orginal pagelist + * with the new one. + */ + if (dma->page_count) { + drm_free(dma->pagelist, + dma->page_count * sizeof(*dma->pagelist), + DRM_MEM_PAGES); + } + dma->pagelist = temp_pagelist; + + dma->buf_count += entry->buf_count; + dma->seg_count += entry->seg_count; + dma->page_count += entry->seg_count << page_order; + dma->byte_count += PAGE_SIZE * (entry->seg_count << page_order); + + up( &dev->struct_sem ); + + request.count = entry->buf_count; + request.size = size; + + if ( copy_to_user( argp, &request, sizeof(request) ) ) + return -EFAULT; + + atomic_dec( &dev->buf_alloc ); + return 0; + +} + +int drm_addbufs_sg( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t __user *argp = (void __user *)arg; + drm_buf_desc_t request; + drm_buf_entry_t *entry; + drm_buf_t *buf; + unsigned long offset; + unsigned long agp_offset; + int count; + int order; + int size; + int alignment; + int page_order; + int total; + int byte_count; + int i; + drm_buf_t **temp_buflist; + + if (!drm_core_check_feature(dev, DRIVER_SG)) return -EINVAL; + + if ( !dma ) return -EINVAL; + + if ( copy_from_user( &request, argp, sizeof(request) ) ) + return -EFAULT; + + count = request.count; + order = drm_order( request.size ); + size = 1 << order; + + alignment = (request.flags & _DRM_PAGE_ALIGN) + ? PAGE_ALIGN(size) : size; + page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; + total = PAGE_SIZE << page_order; + + byte_count = 0; + agp_offset = request.agp_start; + + DRM_DEBUG( "count: %d\n", count ); + DRM_DEBUG( "order: %d\n", order ); + DRM_DEBUG( "size: %d\n", size ); + DRM_DEBUG( "agp_offset: %lu\n", agp_offset ); + DRM_DEBUG( "alignment: %d\n", alignment ); + DRM_DEBUG( "page_order: %d\n", page_order ); + DRM_DEBUG( "total: %d\n", total ); + + if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; + if ( dev->queue_count ) return -EBUSY; /* Not while in use */ + + spin_lock( &dev->count_lock ); + if ( dev->buf_use ) { + spin_unlock( &dev->count_lock ); + return -EBUSY; + } + atomic_inc( &dev->buf_alloc ); + spin_unlock( &dev->count_lock ); + + down( &dev->struct_sem ); + entry = &dma->bufs[order]; + if ( entry->buf_count ) { + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; /* May only call once for each order */ + } + + if (count < 0 || count > 4096) { + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -EINVAL; + } + + entry->buflist = drm_alloc( count * sizeof(*entry->buflist), + DRM_MEM_BUFS ); + if ( !entry->buflist ) { + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; + } + memset( entry->buflist, 0, count * sizeof(*entry->buflist) ); + + entry->buf_size = size; + entry->page_order = page_order; + + offset = 0; + + while ( entry->buf_count < count ) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; + + buf->offset = (dma->byte_count + offset); + buf->bus_address = agp_offset + offset; + buf->address = (void *)(agp_offset + offset + dev->sg->handle); + buf->next = NULL; + buf->waiting = 0; + buf->pending = 0; + init_waitqueue_head( &buf->dma_wait ); + buf->filp = NULL; + + buf->dev_priv_size = dev->driver->dev_priv_size; + buf->dev_private = drm_alloc( buf->dev_priv_size, + DRM_MEM_BUFS ); + if(!buf->dev_private) { + /* Set count correctly so we free the proper amount. */ + entry->buf_count = count; + drm_cleanup_buf_error(dev,entry); + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; + } + + memset( buf->dev_private, 0, buf->dev_priv_size ); + + DRM_DEBUG( "buffer %d @ %p\n", + entry->buf_count, buf->address ); + + offset += alignment; + entry->buf_count++; + byte_count += PAGE_SIZE << page_order; + } + + DRM_DEBUG( "byte_count: %d\n", byte_count ); + + temp_buflist = drm_realloc( dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), + DRM_MEM_BUFS ); + if(!temp_buflist) { + /* Free the entry because it isn't valid */ + drm_cleanup_buf_error(dev,entry); + up( &dev->struct_sem ); + atomic_dec( &dev->buf_alloc ); + return -ENOMEM; + } + dma->buflist = temp_buflist; + + for ( i = 0 ; i < entry->buf_count ; i++ ) { + dma->buflist[i + dma->buf_count] = &entry->buflist[i]; + } + + dma->buf_count += entry->buf_count; + dma->byte_count += byte_count; + + DRM_DEBUG( "dma->buf_count : %d\n", dma->buf_count ); + DRM_DEBUG( "entry->buf_count : %d\n", entry->buf_count ); + + up( &dev->struct_sem ); + + request.count = entry->buf_count; + request.size = size; + + if ( copy_to_user( argp, &request, sizeof(request) ) ) + return -EFAULT; + + dma->flags = _DRM_DMA_USE_SG; + + atomic_dec( &dev->buf_alloc ); + return 0; +} + +/** + * Add buffers for DMA transfers (ioctl). + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_buf_desc_t request. + * \return zero on success or a negative number on failure. + * + * According with the memory type specified in drm_buf_desc::flags and the + * build options, it dispatches the call either to addbufs_agp(), + * addbufs_sg() or addbufs_pci() for AGP, scatter-gather or consistent + * PCI memory respectively. + */ +int drm_addbufs( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_buf_desc_t request; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + + if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) + return -EINVAL; + + if ( copy_from_user( &request, (drm_buf_desc_t __user *)arg, + sizeof(request) ) ) + return -EFAULT; + +#if __OS_HAS_AGP + if ( request.flags & _DRM_AGP_BUFFER ) + return drm_addbufs_agp( inode, filp, cmd, arg ); + else +#endif + if ( request.flags & _DRM_SG_BUFFER ) + return drm_addbufs_sg( inode, filp, cmd, arg ); + else + return drm_addbufs_pci( inode, filp, cmd, arg ); +} + + +/** + * Get information about the buffer mappings. + * + * This was originally mean for debugging purposes, or by a sophisticated + * client library to determine how best to use the available buffers (e.g., + * large buffers can be used for image transfer). + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_buf_info structure. + * \return zero on success or a negative number on failure. + * + * Increments drm_device::buf_use while holding the drm_device::count_lock + * lock, preventing of allocating more buffers after this call. Information + * about each requested buffer is then copied into user space. + */ +int drm_infobufs( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_info_t request; + drm_buf_info_t __user *argp = (void __user *)arg; + int i; + int count; + + if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) + return -EINVAL; + + if ( !dma ) return -EINVAL; + + spin_lock( &dev->count_lock ); + if ( atomic_read( &dev->buf_alloc ) ) { + spin_unlock( &dev->count_lock ); + return -EBUSY; + } + ++dev->buf_use; /* Can't allocate more after this call */ + spin_unlock( &dev->count_lock ); + + if ( copy_from_user( &request, argp, sizeof(request) ) ) + return -EFAULT; + + for ( i = 0, count = 0 ; i < DRM_MAX_ORDER + 1 ; i++ ) { + if ( dma->bufs[i].buf_count ) ++count; + } + + DRM_DEBUG( "count = %d\n", count ); + + if ( request.count >= count ) { + for ( i = 0, count = 0 ; i < DRM_MAX_ORDER + 1 ; i++ ) { + if ( dma->bufs[i].buf_count ) { + drm_buf_desc_t __user *to = &request.list[count]; + drm_buf_entry_t *from = &dma->bufs[i]; + drm_freelist_t *list = &dma->bufs[i].freelist; + if ( copy_to_user( &to->count, + &from->buf_count, + sizeof(from->buf_count) ) || + copy_to_user( &to->size, + &from->buf_size, + sizeof(from->buf_size) ) || + copy_to_user( &to->low_mark, + &list->low_mark, + sizeof(list->low_mark) ) || + copy_to_user( &to->high_mark, + &list->high_mark, + sizeof(list->high_mark) ) ) + return -EFAULT; + + DRM_DEBUG( "%d %d %d %d %d\n", + i, + dma->bufs[i].buf_count, + dma->bufs[i].buf_size, + dma->bufs[i].freelist.low_mark, + dma->bufs[i].freelist.high_mark ); + ++count; + } + } + } + request.count = count; + + if ( copy_to_user( argp, &request, sizeof(request) ) ) + return -EFAULT; + + return 0; +} + +/** + * Specifies a low and high water mark for buffer allocation + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg a pointer to a drm_buf_desc structure. + * \return zero on success or a negative number on failure. + * + * Verifies that the size order is bounded between the admissible orders and + * updates the respective drm_device_dma::bufs entry low and high water mark. + * + * \note This ioctl is deprecated and mostly never used. + */ +int drm_markbufs( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_desc_t request; + int order; + drm_buf_entry_t *entry; + + if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) + return -EINVAL; + + if ( !dma ) return -EINVAL; + + if ( copy_from_user( &request, + (drm_buf_desc_t __user *)arg, + sizeof(request) ) ) + return -EFAULT; + + DRM_DEBUG( "%d, %d, %d\n", + request.size, request.low_mark, request.high_mark ); + order = drm_order( request.size ); + if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; + entry = &dma->bufs[order]; + + if ( request.low_mark < 0 || request.low_mark > entry->buf_count ) + return -EINVAL; + if ( request.high_mark < 0 || request.high_mark > entry->buf_count ) + return -EINVAL; + + entry->freelist.low_mark = request.low_mark; + entry->freelist.high_mark = request.high_mark; + + return 0; +} + +/** + * Unreserve the buffers in list, previously reserved using drmDMA. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_buf_free structure. + * \return zero on success or a negative number on failure. + * + * Calls free_buffer() for each used buffer. + * This function is primarily used for debugging. + */ +int drm_freebufs( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_free_t request; + int i; + int idx; + drm_buf_t *buf; + + if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) + return -EINVAL; + + if ( !dma ) return -EINVAL; + + if ( copy_from_user( &request, + (drm_buf_free_t __user *)arg, + sizeof(request) ) ) + return -EFAULT; + + DRM_DEBUG( "%d\n", request.count ); + for ( i = 0 ; i < request.count ; i++ ) { + if ( copy_from_user( &idx, + &request.list[i], + sizeof(idx) ) ) + return -EFAULT; + if ( idx < 0 || idx >= dma->buf_count ) { + DRM_ERROR( "Index %d (of %d max)\n", + idx, dma->buf_count - 1 ); + return -EINVAL; + } + buf = dma->buflist[idx]; + if ( buf->filp != filp ) { + DRM_ERROR( "Process %d freeing buffer not owned\n", + current->pid ); + return -EINVAL; + } + drm_free_buffer( dev, buf ); + } + + return 0; +} + +/** + * Maps all of the DMA buffers into client-virtual space (ioctl). + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg pointer to a drm_buf_map structure. + * \return zero on success or a negative number on failure. + * + * Maps the AGP or SG buffer region with do_mmap(), and copies information + * about each buffer into user space. The PCI buffers are already mapped on the + * addbufs_pci() call. + */ +int drm_mapbufs( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_device_dma_t *dma = dev->dma; + drm_buf_map_t __user *argp = (void __user *)arg; + int retcode = 0; + const int zero = 0; + unsigned long virtual; + unsigned long address; + drm_buf_map_t request; + int i; + + if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) + return -EINVAL; + + if ( !dma ) return -EINVAL; + + spin_lock( &dev->count_lock ); + if ( atomic_read( &dev->buf_alloc ) ) { + spin_unlock( &dev->count_lock ); + return -EBUSY; + } + dev->buf_use++; /* Can't allocate more after this call */ + spin_unlock( &dev->count_lock ); + + if ( copy_from_user( &request, argp, sizeof(request) ) ) + return -EFAULT; + + if ( request.count >= dma->buf_count ) { + if ((drm_core_has_AGP(dev) && (dma->flags & _DRM_DMA_USE_AGP)) || + (drm_core_check_feature(dev, DRIVER_SG) && (dma->flags & _DRM_DMA_USE_SG)) ) { + drm_map_t *map = dev->agp_buffer_map; + + if ( !map ) { + retcode = -EINVAL; + goto done; + } + +#if LINUX_VERSION_CODE <= 0x020402 + down( ¤t->mm->mmap_sem ); +#else + down_write( ¤t->mm->mmap_sem ); +#endif + virtual = do_mmap( filp, 0, map->size, + PROT_READ | PROT_WRITE, + MAP_SHARED, + (unsigned long)map->offset ); +#if LINUX_VERSION_CODE <= 0x020402 + up( ¤t->mm->mmap_sem ); +#else + up_write( ¤t->mm->mmap_sem ); +#endif + } else { +#if LINUX_VERSION_CODE <= 0x020402 + down( ¤t->mm->mmap_sem ); +#else + down_write( ¤t->mm->mmap_sem ); +#endif + virtual = do_mmap( filp, 0, dma->byte_count, + PROT_READ | PROT_WRITE, + MAP_SHARED, 0 ); +#if LINUX_VERSION_CODE <= 0x020402 + up( ¤t->mm->mmap_sem ); +#else + up_write( ¤t->mm->mmap_sem ); +#endif + } + if ( virtual > -1024UL ) { + /* Real error */ + retcode = (signed long)virtual; + goto done; + } + request.virtual = (void __user *)virtual; + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + if ( copy_to_user( &request.list[i].idx, + &dma->buflist[i]->idx, + sizeof(request.list[0].idx) ) ) { + retcode = -EFAULT; + goto done; + } + if ( copy_to_user( &request.list[i].total, + &dma->buflist[i]->total, + sizeof(request.list[0].total) ) ) { + retcode = -EFAULT; + goto done; + } + if ( copy_to_user( &request.list[i].used, + &zero, + sizeof(zero) ) ) { + retcode = -EFAULT; + goto done; + } + address = virtual + dma->buflist[i]->offset; /* *** */ + if ( copy_to_user( &request.list[i].address, + &address, + sizeof(address) ) ) { + retcode = -EFAULT; + goto done; + } + } + } + done: + request.count = dma->buf_count; + DRM_DEBUG( "%d buffers, retcode = %d\n", request.count, retcode ); + + if ( copy_to_user( argp, &request, sizeof(request) ) ) + return -EFAULT; + + return retcode; +} + diff --git a/drivers/char/drm/drm_context.c b/drivers/char/drm/drm_context.c new file mode 100644 index 000000000000..f15c86c57875 --- /dev/null +++ b/drivers/char/drm/drm_context.c @@ -0,0 +1,578 @@ +/** + * \file drm_context.h + * IOCTLs for generic contexts + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Fri Nov 24 18:31:37 2000 by gareth@valinux.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * ChangeLog: + * 2001-11-16 Torsten Duwe + * added context constructor/destructor hooks, + * needed by SiS driver's memory management. + */ + +#include "drmP.h" + +/******************************************************************/ +/** \name Context bitmap support */ +/*@{*/ + +/** + * Free a handle from the context bitmap. + * + * \param dev DRM device. + * \param ctx_handle context handle. + * + * Clears the bit specified by \p ctx_handle in drm_device::ctx_bitmap and the entry + * in drm_device::context_sareas, while holding the drm_device::struct_sem + * lock. + */ +void drm_ctxbitmap_free( drm_device_t *dev, int ctx_handle ) +{ + if ( ctx_handle < 0 ) goto failed; + if ( !dev->ctx_bitmap ) goto failed; + + if ( ctx_handle < DRM_MAX_CTXBITMAP ) { + down(&dev->struct_sem); + clear_bit( ctx_handle, dev->ctx_bitmap ); + dev->context_sareas[ctx_handle] = NULL; + up(&dev->struct_sem); + return; + } +failed: + DRM_ERROR( "Attempt to free invalid context handle: %d\n", + ctx_handle ); + return; +} + +/** + * Context bitmap allocation. + * + * \param dev DRM device. + * \return (non-negative) context handle on success or a negative number on failure. + * + * Find the first zero bit in drm_device::ctx_bitmap and (re)allocates + * drm_device::context_sareas to accommodate the new entry while holding the + * drm_device::struct_sem lock. + */ +int drm_ctxbitmap_next( drm_device_t *dev ) +{ + int bit; + + if(!dev->ctx_bitmap) return -1; + + down(&dev->struct_sem); + bit = find_first_zero_bit( dev->ctx_bitmap, DRM_MAX_CTXBITMAP ); + if ( bit < DRM_MAX_CTXBITMAP ) { + set_bit( bit, dev->ctx_bitmap ); + DRM_DEBUG( "drm_ctxbitmap_next bit : %d\n", bit ); + if((bit+1) > dev->max_context) { + dev->max_context = (bit+1); + if(dev->context_sareas) { + drm_map_t **ctx_sareas; + + ctx_sareas = drm_realloc(dev->context_sareas, + (dev->max_context - 1) * + sizeof(*dev->context_sareas), + dev->max_context * + sizeof(*dev->context_sareas), + DRM_MEM_MAPS); + if(!ctx_sareas) { + clear_bit(bit, dev->ctx_bitmap); + up(&dev->struct_sem); + return -1; + } + dev->context_sareas = ctx_sareas; + dev->context_sareas[bit] = NULL; + } else { + /* max_context == 1 at this point */ + dev->context_sareas = drm_alloc( + dev->max_context * + sizeof(*dev->context_sareas), + DRM_MEM_MAPS); + if(!dev->context_sareas) { + clear_bit(bit, dev->ctx_bitmap); + up(&dev->struct_sem); + return -1; + } + dev->context_sareas[bit] = NULL; + } + } + up(&dev->struct_sem); + return bit; + } + up(&dev->struct_sem); + return -1; +} + +/** + * Context bitmap initialization. + * + * \param dev DRM device. + * + * Allocates and initialize drm_device::ctx_bitmap and drm_device::context_sareas, while holding + * the drm_device::struct_sem lock. + */ +int drm_ctxbitmap_init( drm_device_t *dev ) +{ + int i; + int temp; + + down(&dev->struct_sem); + dev->ctx_bitmap = (unsigned long *) drm_alloc( PAGE_SIZE, + DRM_MEM_CTXBITMAP ); + if ( dev->ctx_bitmap == NULL ) { + up(&dev->struct_sem); + return -ENOMEM; + } + memset( (void *)dev->ctx_bitmap, 0, PAGE_SIZE ); + dev->context_sareas = NULL; + dev->max_context = -1; + up(&dev->struct_sem); + + for ( i = 0 ; i < DRM_RESERVED_CONTEXTS ; i++ ) { + temp = drm_ctxbitmap_next( dev ); + DRM_DEBUG( "drm_ctxbitmap_init : %d\n", temp ); + } + + return 0; +} + +/** + * Context bitmap cleanup. + * + * \param dev DRM device. + * + * Frees drm_device::ctx_bitmap and drm_device::context_sareas, while holding + * the drm_device::struct_sem lock. + */ +void drm_ctxbitmap_cleanup( drm_device_t *dev ) +{ + down(&dev->struct_sem); + if( dev->context_sareas ) drm_free( dev->context_sareas, + sizeof(*dev->context_sareas) * + dev->max_context, + DRM_MEM_MAPS ); + drm_free( (void *)dev->ctx_bitmap, PAGE_SIZE, DRM_MEM_CTXBITMAP ); + up(&dev->struct_sem); +} + +/*@}*/ + +/******************************************************************/ +/** \name Per Context SAREA Support */ +/*@{*/ + +/** + * Get per-context SAREA. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument pointing to a drm_ctx_priv_map structure. + * \return zero on success or a negative number on failure. + * + * Gets the map from drm_device::context_sareas with the handle specified and + * returns its handle. + */ +int drm_getsareactx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_ctx_priv_map_t __user *argp = (void __user *)arg; + drm_ctx_priv_map_t request; + drm_map_t *map; + + if (copy_from_user(&request, argp, sizeof(request))) + return -EFAULT; + + down(&dev->struct_sem); + if (dev->max_context < 0 || request.ctx_id >= (unsigned) dev->max_context) { + up(&dev->struct_sem); + return -EINVAL; + } + + map = dev->context_sareas[request.ctx_id]; + up(&dev->struct_sem); + + request.handle = map->handle; + if (copy_to_user(argp, &request, sizeof(request))) + return -EFAULT; + return 0; +} + +/** + * Set per-context SAREA. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument pointing to a drm_ctx_priv_map structure. + * \return zero on success or a negative number on failure. + * + * Searches the mapping specified in \p arg and update the entry in + * drm_device::context_sareas with it. + */ +int drm_setsareactx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_ctx_priv_map_t request; + drm_map_t *map = NULL; + drm_map_list_t *r_list = NULL; + struct list_head *list; + + if (copy_from_user(&request, + (drm_ctx_priv_map_t __user *)arg, + sizeof(request))) + return -EFAULT; + + down(&dev->struct_sem); + list_for_each(list, &dev->maplist->head) { + r_list = list_entry(list, drm_map_list_t, head); + if(r_list->map && + r_list->map->handle == request.handle) + goto found; + } +bad: + up(&dev->struct_sem); + return -EINVAL; + +found: + map = r_list->map; + if (!map) goto bad; + if (dev->max_context < 0) + goto bad; + if (request.ctx_id >= (unsigned) dev->max_context) + goto bad; + dev->context_sareas[request.ctx_id] = map; + up(&dev->struct_sem); + return 0; +} + +/*@}*/ + +/******************************************************************/ +/** \name The actual DRM context handling routines */ +/*@{*/ + +/** + * Switch context. + * + * \param dev DRM device. + * \param old old context handle. + * \param new new context handle. + * \return zero on success or a negative number on failure. + * + * Attempt to set drm_device::context_flag. + */ +int drm_context_switch( drm_device_t *dev, int old, int new ) +{ + if ( test_and_set_bit( 0, &dev->context_flag ) ) { + DRM_ERROR( "Reentering -- FIXME\n" ); + return -EBUSY; + } + + + DRM_DEBUG( "Context switch from %d to %d\n", old, new ); + + if ( new == dev->last_context ) { + clear_bit( 0, &dev->context_flag ); + return 0; + } + + return 0; +} + +/** + * Complete context switch. + * + * \param dev DRM device. + * \param new new context handle. + * \return zero on success or a negative number on failure. + * + * Updates drm_device::last_context and drm_device::last_switch. Verifies the + * hardware lock is held, clears the drm_device::context_flag and wakes up + * drm_device::context_wait. + */ +int drm_context_switch_complete( drm_device_t *dev, int new ) +{ + dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ + dev->last_switch = jiffies; + + if ( !_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) ) { + DRM_ERROR( "Lock isn't held after context switch\n" ); + } + + /* If a context switch is ever initiated + when the kernel holds the lock, release + that lock here. */ + clear_bit( 0, &dev->context_flag ); + wake_up( &dev->context_wait ); + + return 0; +} + +/** + * Reserve contexts. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument pointing to a drm_ctx_res structure. + * \return zero on success or a negative number on failure. + */ +int drm_resctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_ctx_res_t res; + drm_ctx_t __user *argp = (void __user *)arg; + drm_ctx_t ctx; + int i; + + if ( copy_from_user( &res, argp, sizeof(res) ) ) + return -EFAULT; + + if ( res.count >= DRM_RESERVED_CONTEXTS ) { + memset( &ctx, 0, sizeof(ctx) ); + for ( i = 0 ; i < DRM_RESERVED_CONTEXTS ; i++ ) { + ctx.handle = i; + if ( copy_to_user( &res.contexts[i], + &i, sizeof(i) ) ) + return -EFAULT; + } + } + res.count = DRM_RESERVED_CONTEXTS; + + if ( copy_to_user( argp, &res, sizeof(res) ) ) + return -EFAULT; + return 0; +} + +/** + * Add context. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument pointing to a drm_ctx structure. + * \return zero on success or a negative number on failure. + * + * Get a new handle for the context and copy to userspace. + */ +int drm_addctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_ctx_list_t * ctx_entry; + drm_ctx_t __user *argp = (void __user *)arg; + drm_ctx_t ctx; + + if ( copy_from_user( &ctx, argp, sizeof(ctx) ) ) + return -EFAULT; + + ctx.handle = drm_ctxbitmap_next( dev ); + if ( ctx.handle == DRM_KERNEL_CONTEXT ) { + /* Skip kernel's context and get a new one. */ + ctx.handle = drm_ctxbitmap_next( dev ); + } + DRM_DEBUG( "%d\n", ctx.handle ); + if ( ctx.handle == -1 ) { + DRM_DEBUG( "Not enough free contexts.\n" ); + /* Should this return -EBUSY instead? */ + return -ENOMEM; + } + + if ( ctx.handle != DRM_KERNEL_CONTEXT ) + { + if (dev->driver->context_ctor) + dev->driver->context_ctor(dev, ctx.handle); + } + + ctx_entry = drm_alloc( sizeof(*ctx_entry), DRM_MEM_CTXLIST ); + if ( !ctx_entry ) { + DRM_DEBUG("out of memory\n"); + return -ENOMEM; + } + + INIT_LIST_HEAD( &ctx_entry->head ); + ctx_entry->handle = ctx.handle; + ctx_entry->tag = priv; + + down( &dev->ctxlist_sem ); + list_add( &ctx_entry->head, &dev->ctxlist->head ); + ++dev->ctx_count; + up( &dev->ctxlist_sem ); + + if ( copy_to_user( argp, &ctx, sizeof(ctx) ) ) + return -EFAULT; + return 0; +} + +int drm_modctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + /* This does nothing */ + return 0; +} + +/** + * Get context. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument pointing to a drm_ctx structure. + * \return zero on success or a negative number on failure. + */ +int drm_getctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_ctx_t __user *argp = (void __user *)arg; + drm_ctx_t ctx; + + if ( copy_from_user( &ctx, argp, sizeof(ctx) ) ) + return -EFAULT; + + /* This is 0, because we don't handle any context flags */ + ctx.flags = 0; + + if ( copy_to_user( argp, &ctx, sizeof(ctx) ) ) + return -EFAULT; + return 0; +} + +/** + * Switch context. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument pointing to a drm_ctx structure. + * \return zero on success or a negative number on failure. + * + * Calls context_switch(). + */ +int drm_switchctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_ctx_t ctx; + + if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) ) + return -EFAULT; + + DRM_DEBUG( "%d\n", ctx.handle ); + return drm_context_switch( dev, dev->last_context, ctx.handle ); +} + +/** + * New context. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument pointing to a drm_ctx structure. + * \return zero on success or a negative number on failure. + * + * Calls context_switch_complete(). + */ +int drm_newctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_ctx_t ctx; + + if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) ) + return -EFAULT; + + DRM_DEBUG( "%d\n", ctx.handle ); + drm_context_switch_complete( dev, ctx.handle ); + + return 0; +} + +/** + * Remove context. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument pointing to a drm_ctx structure. + * \return zero on success or a negative number on failure. + * + * If not the special kernel context, calls ctxbitmap_free() to free the specified context. + */ +int drm_rmctx( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_ctx_t ctx; + + if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) ) + return -EFAULT; + + DRM_DEBUG( "%d\n", ctx.handle ); + if ( ctx.handle == DRM_KERNEL_CONTEXT + 1 ) { + priv->remove_auth_on_close = 1; + } + if ( ctx.handle != DRM_KERNEL_CONTEXT ) { + if (dev->driver->context_dtor) + dev->driver->context_dtor(dev, ctx.handle); + drm_ctxbitmap_free( dev, ctx.handle ); + } + + down( &dev->ctxlist_sem ); + if ( !list_empty( &dev->ctxlist->head ) ) { + drm_ctx_list_t *pos, *n; + + list_for_each_entry_safe( pos, n, &dev->ctxlist->head, head ) { + if ( pos->handle == ctx.handle ) { + list_del( &pos->head ); + drm_free( pos, sizeof(*pos), DRM_MEM_CTXLIST ); + --dev->ctx_count; + } + } + } + up( &dev->ctxlist_sem ); + + return 0; +} + +/*@}*/ + diff --git a/drivers/char/drm/drm_core.h b/drivers/char/drm/drm_core.h new file mode 100644 index 000000000000..cc97bb906dda --- /dev/null +++ b/drivers/char/drm/drm_core.h @@ -0,0 +1,34 @@ +/* + * Copyright 2004 Jon Smirl + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#define CORE_AUTHOR "Gareth Hughes, Leif Delgass, José Fonseca, Jon Smirl" + +#define CORE_NAME "drm" +#define CORE_DESC "DRM shared core routines" +#define CORE_DATE "20040925" + +#define DRM_IF_MAJOR 1 +#define DRM_IF_MINOR 2 + +#define CORE_MAJOR 1 +#define CORE_MINOR 0 +#define CORE_PATCHLEVEL 0 diff --git a/drivers/char/drm/drm_dma.c b/drivers/char/drm/drm_dma.c new file mode 100644 index 000000000000..4a28c053c98b --- /dev/null +++ b/drivers/char/drm/drm_dma.c @@ -0,0 +1,180 @@ +/** + * \file drm_dma.h + * DMA IOCTL and function support + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Fri Mar 19 14:30:16 1999 by faith@valinux.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" + +/** + * Initialize the DMA data. + * + * \param dev DRM device. + * \return zero on success or a negative value on failure. + * + * Allocate and initialize a drm_device_dma structure. + */ +int drm_dma_setup( drm_device_t *dev ) +{ + int i; + + dev->dma = drm_alloc( sizeof(*dev->dma), DRM_MEM_DRIVER ); + if ( !dev->dma ) + return -ENOMEM; + + memset( dev->dma, 0, sizeof(*dev->dma) ); + + for ( i = 0 ; i <= DRM_MAX_ORDER ; i++ ) + memset(&dev->dma->bufs[i], 0, sizeof(dev->dma->bufs[0])); + + return 0; +} + +/** + * Cleanup the DMA resources. + * + * \param dev DRM device. + * + * Free all pages associated with DMA buffers, the buffers and pages lists, and + * finally the the drm_device::dma structure itself. + */ +void drm_dma_takedown(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + int i, j; + + if (!dma) return; + + /* Clear dma buffers */ + for (i = 0; i <= DRM_MAX_ORDER; i++) { + if (dma->bufs[i].seg_count) { + DRM_DEBUG("order %d: buf_count = %d," + " seg_count = %d\n", + i, + dma->bufs[i].buf_count, + dma->bufs[i].seg_count); + for (j = 0; j < dma->bufs[i].seg_count; j++) { + if (dma->bufs[i].seglist[j]) { + drm_free_pages(dma->bufs[i].seglist[j], + dma->bufs[i].page_order, + DRM_MEM_DMA); + } + } + drm_free(dma->bufs[i].seglist, + dma->bufs[i].seg_count + * sizeof(*dma->bufs[0].seglist), + DRM_MEM_SEGS); + } + if (dma->bufs[i].buf_count) { + for (j = 0; j < dma->bufs[i].buf_count; j++) { + if (dma->bufs[i].buflist[j].dev_private) { + drm_free(dma->bufs[i].buflist[j].dev_private, + dma->bufs[i].buflist[j].dev_priv_size, + DRM_MEM_BUFS); + } + } + drm_free(dma->bufs[i].buflist, + dma->bufs[i].buf_count * + sizeof(*dma->bufs[0].buflist), + DRM_MEM_BUFS); + } + } + + if (dma->buflist) { + drm_free(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + DRM_MEM_BUFS); + } + + if (dma->pagelist) { + drm_free(dma->pagelist, + dma->page_count * sizeof(*dma->pagelist), + DRM_MEM_PAGES); + } + drm_free(dev->dma, sizeof(*dev->dma), DRM_MEM_DRIVER); + dev->dma = NULL; +} + + +/** + * Free a buffer. + * + * \param dev DRM device. + * \param buf buffer to free. + * + * Resets the fields of \p buf. + */ +void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf) +{ + if (!buf) return; + + buf->waiting = 0; + buf->pending = 0; + buf->filp = NULL; + buf->used = 0; + + if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) && waitqueue_active(&buf->dma_wait)) { + wake_up_interruptible(&buf->dma_wait); + } +} + +/** + * Reclaim the buffers. + * + * \param filp file pointer. + * + * Frees each buffer associated with \p filp not already on the hardware. + */ +void drm_core_reclaim_buffers(drm_device_t *dev, struct file *filp) +{ + drm_device_dma_t *dma = dev->dma; + int i; + + if (!dma) return; + for (i = 0; i < dma->buf_count; i++) { + if (dma->buflist[i]->filp == filp) { + switch (dma->buflist[i]->list) { + case DRM_LIST_NONE: + drm_free_buffer(dev, dma->buflist[i]); + break; + case DRM_LIST_WAIT: + dma->buflist[i]->list = DRM_LIST_RECLAIM; + break; + default: + /* Buffer already on hardware. */ + break; + } + } + } +} +EXPORT_SYMBOL(drm_core_reclaim_buffers); + diff --git a/drivers/char/drm/drm_drawable.c b/drivers/char/drm/drm_drawable.c new file mode 100644 index 000000000000..e8e8e42be4c7 --- /dev/null +++ b/drivers/char/drm/drm_drawable.c @@ -0,0 +1,56 @@ +/** + * \file drm_drawable.h + * IOCTLs for drawables + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Tue Feb 2 08:37:54 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" + +/** No-op. */ +int drm_adddraw(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_draw_t draw; + + draw.handle = 0; /* NOOP */ + DRM_DEBUG("%d\n", draw.handle); + if (copy_to_user((drm_draw_t __user *)arg, &draw, sizeof(draw))) + return -EFAULT; + return 0; +} + +/** No-op. */ +int drm_rmdraw(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + return 0; /* NOOP */ +} diff --git a/drivers/char/drm/drm_drv.c b/drivers/char/drm/drm_drv.c new file mode 100644 index 000000000000..1e37ed0c6b8d --- /dev/null +++ b/drivers/char/drm/drm_drv.c @@ -0,0 +1,531 @@ +/** + * \file drm_drv.h + * Generic driver template + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + * + * To use this template, you must at least define the following (samples + * given for the MGA driver): + * + * \code + * #define DRIVER_AUTHOR "VA Linux Systems, Inc." + * + * #define DRIVER_NAME "mga" + * #define DRIVER_DESC "Matrox G200/G400" + * #define DRIVER_DATE "20001127" + * + * #define DRIVER_IOCTL_COUNT DRM_ARRAY_SIZE( mga_ioctls ) + * + * #define drm_x mga_##x + * \endcode + */ + +/* + * Created: Thu Nov 23 03:10:50 2000 by gareth@valinux.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" +#include "drm_core.h" + +/** Ioctl table */ +drm_ioctl_desc_t drm_ioctls[] = { + [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { drm_version, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_by_busid, 0, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAP)] = { drm_getmap, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CLIENT)] = { drm_getclient, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_STATS)] = { drm_getstats, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_SET_VERSION)] = { drm_setversion, 0, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_noop, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_noop, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_MAP)] = { drm_rmmap, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_SAREA_CTX)] = { drm_setsareactx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_SAREA_CTX)] = { drm_getsareactx, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { drm_addctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { drm_rmctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { drm_modctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { drm_getctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { drm_switchctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { drm_newctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { drm_resctx, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { drm_lock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { drm_unlock, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_noop, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { drm_addbufs, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { drm_markbufs, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { drm_infobufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = { drm_mapbufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { drm_freebufs, 1, 0 }, + /* The DRM_IOCTL_DMA ioctl should be defined by the driver. */ + + [DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = { drm_control, 1, 1 }, + +#if __OS_HAS_AGP + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = { drm_agp_enable, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = { drm_agp_info, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = { drm_agp_alloc, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = { drm_agp_free, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = { drm_agp_bind, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 }, +#endif + + [DRM_IOCTL_NR(DRM_IOCTL_SG_ALLOC)] = { drm_sg_alloc, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_SG_FREE)] = { drm_sg_free, 1, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_WAIT_VBLANK)] = { drm_wait_vblank, 0, 0 }, +}; + +#define DRIVER_IOCTL_COUNT DRM_ARRAY_SIZE( drm_ioctls ) + +/** + * Take down the DRM device. + * + * \param dev DRM device structure. + * + * Frees every resource in \p dev. + * + * \sa drm_device and setup(). + */ +int drm_takedown( drm_device_t *dev ) +{ + drm_magic_entry_t *pt, *next; + drm_map_t *map; + drm_map_list_t *r_list; + struct list_head *list, *list_next; + drm_vma_entry_t *vma, *vma_next; + int i; + + DRM_DEBUG( "\n" ); + + if (dev->driver->pretakedown) + dev->driver->pretakedown(dev); + + if (dev->unique) { + drm_free(dev->unique, strlen(dev->unique) + 1, DRM_MEM_DRIVER); + dev->unique = NULL; + dev->unique_len = 0; + } + + if ( dev->irq_enabled ) drm_irq_uninstall( dev ); + + down( &dev->struct_sem ); + del_timer( &dev->timer ); + + /* Clear pid list */ + for ( i = 0 ; i < DRM_HASH_SIZE ; i++ ) { + for ( pt = dev->magiclist[i].head ; pt ; pt = next ) { + next = pt->next; + drm_free( pt, sizeof(*pt), DRM_MEM_MAGIC ); + } + dev->magiclist[i].head = dev->magiclist[i].tail = NULL; + } + + /* Clear AGP information */ + if (drm_core_has_AGP(dev) && dev->agp) { + drm_agp_mem_t *entry; + drm_agp_mem_t *nexte; + + /* Remove AGP resources, but leave dev->agp + intact until drv_cleanup is called. */ + for ( entry = dev->agp->memory ; entry ; entry = nexte ) { + nexte = entry->next; + if ( entry->bound ) drm_unbind_agp( entry->memory ); + drm_free_agp( entry->memory, entry->pages ); + drm_free( entry, sizeof(*entry), DRM_MEM_AGPLISTS ); + } + dev->agp->memory = NULL; + + if ( dev->agp->acquired ) drm_agp_do_release(dev); + + dev->agp->acquired = 0; + dev->agp->enabled = 0; + } + + /* Clear vma list (only built for debugging) */ + if ( dev->vmalist ) { + for ( vma = dev->vmalist ; vma ; vma = vma_next ) { + vma_next = vma->next; + drm_free( vma, sizeof(*vma), DRM_MEM_VMAS ); + } + dev->vmalist = NULL; + } + + if( dev->maplist ) { + list_for_each_safe( list, list_next, &dev->maplist->head ) { + r_list = (drm_map_list_t *)list; + + if ( ( map = r_list->map ) ) { + switch ( map->type ) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: + if (drm_core_has_MTRR(dev)) { + if ( map->mtrr >= 0 ) { + int retcode; + retcode = mtrr_del( map->mtrr, + map->offset, + map->size ); + DRM_DEBUG( "mtrr_del=%d\n", retcode ); + } + } + drm_ioremapfree( map->handle, map->size, dev ); + break; + case _DRM_SHM: + vfree(map->handle); + break; + + case _DRM_AGP: + /* Do nothing here, because this is all + * handled in the AGP/GART driver. + */ + break; + case _DRM_SCATTER_GATHER: + /* Handle it */ + if (drm_core_check_feature(dev, DRIVER_SG) && dev->sg) { + drm_sg_cleanup(dev->sg); + dev->sg = NULL; + } + break; + } + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + } + list_del( list ); + drm_free(r_list, sizeof(*r_list), DRM_MEM_MAPS); + } + drm_free(dev->maplist, sizeof(*dev->maplist), DRM_MEM_MAPS); + dev->maplist = NULL; + } + + if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) && dev->queuelist ) { + for ( i = 0 ; i < dev->queue_count ; i++ ) { + if ( dev->queuelist[i] ) { + drm_free( dev->queuelist[i], + sizeof(*dev->queuelist[0]), + DRM_MEM_QUEUES ); + dev->queuelist[i] = NULL; + } + } + drm_free( dev->queuelist, + dev->queue_slots * sizeof(*dev->queuelist), + DRM_MEM_QUEUES ); + dev->queuelist = NULL; + } + dev->queue_count = 0; + + if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) + drm_dma_takedown( dev ); + + if ( dev->lock.hw_lock ) { + dev->sigdata.lock = dev->lock.hw_lock = NULL; /* SHM removed */ + dev->lock.filp = NULL; + wake_up_interruptible( &dev->lock.lock_queue ); + } + up( &dev->struct_sem ); + + return 0; +} + + + +/** + * Module initialization. Called via init_module at module load time, or via + * linux/init/main.c (this is not currently supported). + * + * \return zero on success or a negative number on failure. + * + * Initializes an array of drm_device structures, and attempts to + * initialize all available devices, using consecutive minors, registering the + * stubs and initializing the AGP device. + * + * Expands the \c DRIVER_PREINIT and \c DRIVER_POST_INIT macros before and + * after the initialization for driver customization. + */ +int drm_init( struct drm_driver *driver ) +{ + struct pci_dev *pdev = NULL; + struct pci_device_id *pid; + int i; + + DRM_DEBUG( "\n" ); + + drm_mem_init(); + + for (i=0; driver->pci_driver.id_table[i].vendor != 0; i++) { + pid = (struct pci_device_id *)&driver->pci_driver.id_table[i]; + + pdev=NULL; + /* pass back in pdev to account for multiple identical cards */ + while ((pdev = pci_get_subsys(pid->vendor, pid->device, pid->subvendor, pid->subdevice, pdev)) != NULL) { + /* stealth mode requires a manual probe */ + pci_dev_get(pdev); + drm_get_dev(pdev, pid, driver); + } + } + return 0; +} +EXPORT_SYMBOL(drm_init); + +/** + * Called via cleanup_module() at module unload time. + * + * Cleans up all DRM device, calling takedown(). + * + * \sa drm_init(). + */ +static void drm_cleanup( drm_device_t *dev ) +{ + DRM_DEBUG( "\n" ); + + if (!dev) { + DRM_ERROR("cleanup called no dev\n"); + return; + } + + drm_takedown( dev ); + + drm_ctxbitmap_cleanup( dev ); + + if (drm_core_has_MTRR(dev) && drm_core_has_AGP(dev) && + dev->agp && dev->agp->agp_mtrr >= 0) { + int retval; + retval = mtrr_del( dev->agp->agp_mtrr, + dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size*1024*1024 ); + DRM_DEBUG( "mtrr_del=%d\n", retval ); + } + + if (drm_core_has_AGP(dev) && dev->agp ) { + drm_free( dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS ); + dev->agp = NULL; + } + + if (dev->driver->postcleanup) + dev->driver->postcleanup(dev); + + drm_put_head(&dev->primary); + if ( drm_put_dev(dev) ) + DRM_ERROR( "Cannot unload module\n" ); +} + +void drm_exit (struct drm_driver *driver) +{ + int i; + drm_device_t *dev = NULL; + drm_head_t *head; + + DRM_DEBUG( "\n" ); + + for (i = 0; i < drm_cards_limit; i++) { + head = drm_heads[i]; + if (!head) + continue; + if (!head->dev) + continue; + if (head->dev->driver!=driver) + continue; + dev=head->dev; + } + if (dev) { + /* release the pci driver */ + if (dev->pdev) + pci_dev_put(dev->pdev); + drm_cleanup(dev); + } + DRM_INFO( "Module unloaded\n" ); +} +EXPORT_SYMBOL(drm_exit); + +/** File operations structure */ +static struct file_operations drm_stub_fops = { + .owner = THIS_MODULE, + .open = drm_stub_open +}; + +static int __init drm_core_init(void) +{ + int ret = -ENOMEM; + + drm_cards_limit = (drm_cards_limit < DRM_MAX_MINOR + 1 ? drm_cards_limit : DRM_MAX_MINOR + 1); + drm_heads = drm_calloc(drm_cards_limit, + sizeof(*drm_heads), DRM_MEM_STUB); + if(!drm_heads) + goto err_p1; + + if (register_chrdev(DRM_MAJOR, "drm", &drm_stub_fops)) + goto err_p1; + + drm_class = drm_sysfs_create(THIS_MODULE, "drm"); + if (IS_ERR(drm_class)) { + printk (KERN_ERR "DRM: Error creating drm class.\n"); + ret = PTR_ERR(drm_class); + goto err_p2; + } + + drm_proc_root = create_proc_entry("dri", S_IFDIR, NULL); + if (!drm_proc_root) { + DRM_ERROR("Cannot create /proc/dri\n"); + ret = -1; + goto err_p3; + } + + DRM_INFO( "Initialized %s %d.%d.%d %s\n", + CORE_NAME, CORE_MAJOR, CORE_MINOR, CORE_PATCHLEVEL, + CORE_DATE); + return 0; +err_p3: + drm_sysfs_destroy(drm_class); +err_p2: + unregister_chrdev(DRM_MAJOR, "drm"); + drm_free(drm_heads, sizeof(*drm_heads) * drm_cards_limit, DRM_MEM_STUB); +err_p1: + return ret; +} + +static void __exit drm_core_exit (void) +{ + remove_proc_entry("dri", NULL); + drm_sysfs_destroy(drm_class); + + unregister_chrdev(DRM_MAJOR, "drm"); + + drm_free(drm_heads, sizeof(*drm_heads) * + drm_cards_limit, DRM_MEM_STUB); +} + + +module_init( drm_core_init ); +module_exit( drm_core_exit ); + + +/** + * Get version information + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument, pointing to a drm_version structure. + * \return zero on success or negative number on failure. + * + * Fills in the version information in \p arg. + */ +int drm_version( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_version_t __user *argp = (void __user *)arg; + drm_version_t version; + int ret; + + if ( copy_from_user( &version, argp, sizeof(version) ) ) + return -EFAULT; + + /* version is a required function to return the personality module version */ + if ((ret = dev->driver->version(&version))) + return ret; + + if ( copy_to_user( argp, &version, sizeof(version) ) ) + return -EFAULT; + return 0; +} + + + +/** + * Called whenever a process performs an ioctl on /dev/drm. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument. + * \return zero on success or negative number on failure. + * + * Looks up the ioctl function in the ::ioctls table, checking for root + * previleges if so required, and dispatches to the respective function. + */ +int drm_ioctl( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_ioctl_desc_t *ioctl; + drm_ioctl_t *func; + unsigned int nr = DRM_IOCTL_NR(cmd); + int retcode = -EINVAL; + + atomic_inc( &dev->ioctl_count ); + atomic_inc( &dev->counts[_DRM_STAT_IOCTLS] ); + ++priv->ioctl_count; + + DRM_DEBUG( "pid=%d, cmd=0x%02x, nr=0x%02x, dev 0x%lx, auth=%d\n", + current->pid, cmd, nr, (long)old_encode_dev(priv->head->device), + priv->authenticated ); + + if (nr < DRIVER_IOCTL_COUNT) + ioctl = &drm_ioctls[nr]; + else if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) + ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE]; + else + goto err_i1; + + func = ioctl->func; + /* is there a local override? */ + if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl) + func = dev->driver->dma_ioctl; + + if ( !func ) { + DRM_DEBUG( "no function\n" ); + retcode = -EINVAL; + } else if ( ( ioctl->root_only && !capable( CAP_SYS_ADMIN ) )|| + ( ioctl->auth_needed && !priv->authenticated ) ) { + retcode = -EACCES; + } else { + retcode = func( inode, filp, cmd, arg ); + } + +err_i1: + atomic_dec( &dev->ioctl_count ); + if (retcode) DRM_DEBUG( "ret = %x\n", retcode); + return retcode; +} +EXPORT_SYMBOL(drm_ioctl); + diff --git a/drivers/char/drm/drm_fops.c b/drivers/char/drm/drm_fops.c new file mode 100644 index 000000000000..906794247aeb --- /dev/null +++ b/drivers/char/drm/drm_fops.c @@ -0,0 +1,451 @@ +/** + * \file drm_fops.h + * File operations for DRM + * + * \author Rickard E. (Rik) Faith + * \author Daryll Strauss + * \author Gareth Hughes + */ + +/* + * Created: Mon Jan 4 08:58:31 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" +#include + +static int drm_setup( drm_device_t *dev ) +{ + int i; + int ret; + + if (dev->driver->presetup) + { + ret=dev->driver->presetup(dev); + if (ret!=0) + return ret; + } + + atomic_set( &dev->ioctl_count, 0 ); + atomic_set( &dev->vma_count, 0 ); + dev->buf_use = 0; + atomic_set( &dev->buf_alloc, 0 ); + + if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) + { + i = drm_dma_setup( dev ); + if ( i < 0 ) + return i; + } + + for ( i = 0 ; i < DRM_ARRAY_SIZE(dev->counts) ; i++ ) + atomic_set( &dev->counts[i], 0 ); + + for ( i = 0 ; i < DRM_HASH_SIZE ; i++ ) { + dev->magiclist[i].head = NULL; + dev->magiclist[i].tail = NULL; + } + + dev->maplist = drm_alloc(sizeof(*dev->maplist), + DRM_MEM_MAPS); + if(dev->maplist == NULL) return -ENOMEM; + memset(dev->maplist, 0, sizeof(*dev->maplist)); + INIT_LIST_HEAD(&dev->maplist->head); + + dev->ctxlist = drm_alloc(sizeof(*dev->ctxlist), + DRM_MEM_CTXLIST); + if(dev->ctxlist == NULL) return -ENOMEM; + memset(dev->ctxlist, 0, sizeof(*dev->ctxlist)); + INIT_LIST_HEAD(&dev->ctxlist->head); + + dev->vmalist = NULL; + dev->sigdata.lock = dev->lock.hw_lock = NULL; + init_waitqueue_head( &dev->lock.lock_queue ); + dev->queue_count = 0; + dev->queue_reserved = 0; + dev->queue_slots = 0; + dev->queuelist = NULL; + dev->irq_enabled = 0; + dev->context_flag = 0; + dev->interrupt_flag = 0; + dev->dma_flag = 0; + dev->last_context = 0; + dev->last_switch = 0; + dev->last_checked = 0; + init_waitqueue_head( &dev->context_wait ); + dev->if_version = 0; + + dev->ctx_start = 0; + dev->lck_start = 0; + + dev->buf_rp = dev->buf; + dev->buf_wp = dev->buf; + dev->buf_end = dev->buf + DRM_BSZ; + dev->buf_async = NULL; + init_waitqueue_head( &dev->buf_readers ); + init_waitqueue_head( &dev->buf_writers ); + + DRM_DEBUG( "\n" ); + + /* + * The kernel's context could be created here, but is now created + * in drm_dma_enqueue. This is more resource-efficient for + * hardware that does not do DMA, but may mean that + * drm_select_queue fails between the time the interrupt is + * initialized and the time the queues are initialized. + */ + if (dev->driver->postsetup) + dev->driver->postsetup(dev); + + return 0; +} + +/** + * Open file. + * + * \param inode device inode + * \param filp file pointer. + * \return zero on success or a negative number on failure. + * + * Searches the DRM device with the same minor number, calls open_helper(), and + * increments the device open count. If the open count was previous at zero, + * i.e., it's the first that the device is open, then calls setup(). + */ +int drm_open( struct inode *inode, struct file *filp ) +{ + drm_device_t *dev = NULL; + int minor = iminor(inode); + int retcode = 0; + + if (!((minor >= 0) && (minor < drm_cards_limit))) + return -ENODEV; + + if (!drm_heads[minor]) + return -ENODEV; + + if (!(dev = drm_heads[minor]->dev)) + return -ENODEV; + + retcode = drm_open_helper( inode, filp, dev ); + if ( !retcode ) { + atomic_inc( &dev->counts[_DRM_STAT_OPENS] ); + spin_lock( &dev->count_lock ); + if ( !dev->open_count++ ) { + spin_unlock( &dev->count_lock ); + return drm_setup( dev ); + } + spin_unlock( &dev->count_lock ); + } + + return retcode; +} +EXPORT_SYMBOL(drm_open); + +/** + * Release file. + * + * \param inode device inode + * \param filp file pointer. + * \return zero on success or a negative number on failure. + * + * If the hardware lock is held then free it, and take it again for the kernel + * context since it's necessary to reclaim buffers. Unlink the file private + * data from its list and free it. Decreases the open count and if it reaches + * zero calls takedown(). + */ +int drm_release( struct inode *inode, struct file *filp ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + int retcode = 0; + + lock_kernel(); + dev = priv->head->dev; + + DRM_DEBUG( "open_count = %d\n", dev->open_count ); + + if (dev->driver->prerelease) + dev->driver->prerelease(dev, filp); + + /* ======================================================== + * Begin inline drm_release + */ + + DRM_DEBUG( "pid = %d, device = 0x%lx, open_count = %d\n", + current->pid, (long)old_encode_dev(priv->head->device), dev->open_count ); + + if ( priv->lock_count && dev->lock.hw_lock && + _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) && + dev->lock.filp == filp ) { + DRM_DEBUG( "File %p released, freeing lock for context %d\n", + filp, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) ); + + if (dev->driver->release) + dev->driver->release(dev, filp); + + drm_lock_free( dev, &dev->lock.hw_lock->lock, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) ); + + /* FIXME: may require heavy-handed reset of + hardware at this point, possibly + processed via a callback to the X + server. */ + } + else if ( dev->driver->release && priv->lock_count && dev->lock.hw_lock ) { + /* The lock is required to reclaim buffers */ + DECLARE_WAITQUEUE( entry, current ); + + add_wait_queue( &dev->lock.lock_queue, &entry ); + for (;;) { + __set_current_state(TASK_INTERRUPTIBLE); + if ( !dev->lock.hw_lock ) { + /* Device has been unregistered */ + retcode = -EINTR; + break; + } + if ( drm_lock_take( &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT ) ) { + dev->lock.filp = filp; + dev->lock.lock_time = jiffies; + atomic_inc( &dev->counts[_DRM_STAT_LOCKS] ); + break; /* Got lock */ + } + /* Contention */ + schedule(); + if ( signal_pending( current ) ) { + retcode = -ERESTARTSYS; + break; + } + } + __set_current_state(TASK_RUNNING); + remove_wait_queue( &dev->lock.lock_queue, &entry ); + if( !retcode ) { + if (dev->driver->release) + dev->driver->release(dev, filp); + drm_lock_free( dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT ); + } + } + + if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) + { + dev->driver->reclaim_buffers(dev, filp); + } + + drm_fasync( -1, filp, 0 ); + + down( &dev->ctxlist_sem ); + if ( !list_empty( &dev->ctxlist->head ) ) { + drm_ctx_list_t *pos, *n; + + list_for_each_entry_safe( pos, n, &dev->ctxlist->head, head ) { + if ( pos->tag == priv && + pos->handle != DRM_KERNEL_CONTEXT ) { + if (dev->driver->context_dtor) + dev->driver->context_dtor(dev, pos->handle); + + drm_ctxbitmap_free( dev, pos->handle ); + + list_del( &pos->head ); + drm_free( pos, sizeof(*pos), DRM_MEM_CTXLIST ); + --dev->ctx_count; + } + } + } + up( &dev->ctxlist_sem ); + + down( &dev->struct_sem ); + if ( priv->remove_auth_on_close == 1 ) { + drm_file_t *temp = dev->file_first; + while ( temp ) { + temp->authenticated = 0; + temp = temp->next; + } + } + if ( priv->prev ) { + priv->prev->next = priv->next; + } else { + dev->file_first = priv->next; + } + if ( priv->next ) { + priv->next->prev = priv->prev; + } else { + dev->file_last = priv->prev; + } + up( &dev->struct_sem ); + + if (dev->driver->free_filp_priv) + dev->driver->free_filp_priv(dev, priv); + + drm_free( priv, sizeof(*priv), DRM_MEM_FILES ); + + /* ======================================================== + * End inline drm_release + */ + + atomic_inc( &dev->counts[_DRM_STAT_CLOSES] ); + spin_lock( &dev->count_lock ); + if ( !--dev->open_count ) { + if ( atomic_read( &dev->ioctl_count ) || dev->blocked ) { + DRM_ERROR( "Device busy: %d %d\n", + atomic_read( &dev->ioctl_count ), + dev->blocked ); + spin_unlock( &dev->count_lock ); + unlock_kernel(); + return -EBUSY; + } + spin_unlock( &dev->count_lock ); + unlock_kernel(); + return drm_takedown( dev ); + } + spin_unlock( &dev->count_lock ); + + unlock_kernel(); + + return retcode; +} +EXPORT_SYMBOL(drm_release); + +/** + * Called whenever a process opens /dev/drm. + * + * \param inode device inode. + * \param filp file pointer. + * \param dev device. + * \return zero on success or a negative number on failure. + * + * Creates and initializes a drm_file structure for the file private data in \p + * filp and add it into the double linked list in \p dev. + */ +int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t *dev) +{ + int minor = iminor(inode); + drm_file_t *priv; + int ret; + + if (filp->f_flags & O_EXCL) return -EBUSY; /* No exclusive opens */ + if (!drm_cpu_valid()) return -EINVAL; + + DRM_DEBUG("pid = %d, minor = %d\n", current->pid, minor); + + priv = drm_alloc(sizeof(*priv), DRM_MEM_FILES); + if(!priv) return -ENOMEM; + + memset(priv, 0, sizeof(*priv)); + filp->private_data = priv; + priv->uid = current->euid; + priv->pid = current->pid; + priv->minor = minor; + priv->head = drm_heads[minor]; + priv->ioctl_count = 0; + priv->authenticated = capable(CAP_SYS_ADMIN); + priv->lock_count = 0; + + if (dev->driver->open_helper) { + ret=dev->driver->open_helper(dev, priv); + if (ret < 0) + goto out_free; + } + + down(&dev->struct_sem); + if (!dev->file_last) { + priv->next = NULL; + priv->prev = NULL; + dev->file_first = priv; + dev->file_last = priv; + } else { + priv->next = NULL; + priv->prev = dev->file_last; + dev->file_last->next = priv; + dev->file_last = priv; + } + up(&dev->struct_sem); + +#ifdef __alpha__ + /* + * Default the hose + */ + if (!dev->hose) { + struct pci_dev *pci_dev; + pci_dev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, NULL); + if (pci_dev) { + dev->hose = pci_dev->sysdata; + pci_dev_put(pci_dev); + } + if (!dev->hose) { + struct pci_bus *b = pci_bus_b(pci_root_buses.next); + if (b) dev->hose = b->sysdata; + } + } +#endif + + return 0; +out_free: + drm_free(priv, sizeof(*priv), DRM_MEM_FILES); + filp->private_data=NULL; + return ret; +} + +/** No-op. */ +int drm_flush(struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + + DRM_DEBUG("pid = %d, device = 0x%lx, open_count = %d\n", + current->pid, (long)old_encode_dev(priv->head->device), dev->open_count); + return 0; +} +EXPORT_SYMBOL(drm_flush); + +/** No-op. */ +int drm_fasync(int fd, struct file *filp, int on) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + int retcode; + + DRM_DEBUG("fd = %d, device = 0x%lx\n", fd, (long)old_encode_dev(priv->head->device)); + retcode = fasync_helper(fd, filp, on, &dev->buf_async); + if (retcode < 0) return retcode; + return 0; +} +EXPORT_SYMBOL(drm_fasync); + +/** No-op. */ +unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait) +{ + return 0; +} +EXPORT_SYMBOL(drm_poll); + + +/** No-op. */ +ssize_t drm_read(struct file *filp, char __user *buf, size_t count, loff_t *off) +{ + return 0; +} diff --git a/drivers/char/drm/drm_init.c b/drivers/char/drm/drm_init.c new file mode 100644 index 000000000000..62883b749e97 --- /dev/null +++ b/drivers/char/drm/drm_init.c @@ -0,0 +1,52 @@ +/** + * \file drm_init.h + * Setup/Cleanup for DRM + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Mon Jan 4 08:58:31 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" + +/** + * Check whether DRI will run on this CPU. + * + * \return non-zero if the DRI will run on this CPU, or zero otherwise. + */ +int drm_cpu_valid(void) +{ +#if defined(__i386__) + if (boot_cpu_data.x86 == 3) return 0; /* No cmpxchg on a 386 */ +#endif +#if defined(__sparc__) && !defined(__sparc_v9__) + return 0; /* No cmpxchg before v9 sparc. */ +#endif + return 1; +} diff --git a/drivers/char/drm/drm_ioctl.c b/drivers/char/drm/drm_ioctl.c new file mode 100644 index 000000000000..39afda0ccabe --- /dev/null +++ b/drivers/char/drm/drm_ioctl.c @@ -0,0 +1,370 @@ +/** + * \file drm_ioctl.h + * IOCTL processing for DRM + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Fri Jan 8 09:01:26 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" +#include "drm_core.h" + +#include "linux/pci.h" + +/** + * Get the bus id. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument, pointing to a drm_unique structure. + * \return zero on success or a negative number on failure. + * + * Copies the bus id from drm_device::unique into user space. + */ +int drm_getunique(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_unique_t __user *argp = (void __user *)arg; + drm_unique_t u; + + if (copy_from_user(&u, argp, sizeof(u))) + return -EFAULT; + if (u.unique_len >= dev->unique_len) { + if (copy_to_user(u.unique, dev->unique, dev->unique_len)) + return -EFAULT; + } + u.unique_len = dev->unique_len; + if (copy_to_user(argp, &u, sizeof(u))) + return -EFAULT; + return 0; +} + +/** + * Set the bus id. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument, pointing to a drm_unique structure. + * \return zero on success or a negative number on failure. + * + * Copies the bus id from userspace into drm_device::unique, and verifies that + * it matches the device this DRM is attached to (EINVAL otherwise). Deprecated + * in interface version 1.1 and will return EBUSY when setversion has requested + * version 1.1 or greater. + */ +int drm_setunique(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_unique_t u; + int domain, bus, slot, func, ret; + + if (dev->unique_len || dev->unique) return -EBUSY; + + if (copy_from_user(&u, (drm_unique_t __user *)arg, sizeof(u))) + return -EFAULT; + + if (!u.unique_len || u.unique_len > 1024) return -EINVAL; + + dev->unique_len = u.unique_len; + dev->unique = drm_alloc(u.unique_len + 1, DRM_MEM_DRIVER); + if(!dev->unique) return -ENOMEM; + if (copy_from_user(dev->unique, u.unique, dev->unique_len)) + return -EFAULT; + + dev->unique[dev->unique_len] = '\0'; + + dev->devname = drm_alloc(strlen(dev->driver->pci_driver.name) + strlen(dev->unique) + 2, + DRM_MEM_DRIVER); + if (!dev->devname) + return -ENOMEM; + + sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name, dev->unique); + + /* Return error if the busid submitted doesn't match the device's actual + * busid. + */ + ret = sscanf(dev->unique, "PCI:%d:%d:%d", &bus, &slot, &func); + if (ret != 3) + return DRM_ERR(EINVAL); + domain = bus >> 8; + bus &= 0xff; + + if ((domain != dev->pci_domain) || + (bus != dev->pci_bus) || + (slot != dev->pci_slot) || + (func != dev->pci_func)) + return -EINVAL; + + return 0; +} + +static int +drm_set_busid(drm_device_t *dev) +{ + if (dev->unique != NULL) + return EBUSY; + + dev->unique_len = 20; + dev->unique = drm_alloc(dev->unique_len + 1, DRM_MEM_DRIVER); + if (dev->unique == NULL) + return ENOMEM; + + snprintf(dev->unique, dev->unique_len, "pci:%04x:%02x:%02x.%d", + dev->pci_domain, dev->pci_bus, dev->pci_slot, dev->pci_func); + + dev->devname = drm_alloc(strlen(dev->driver->pci_driver.name) + dev->unique_len + 2, + DRM_MEM_DRIVER); + if (dev->devname == NULL) + return ENOMEM; + + sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name, dev->unique); + + return 0; +} + + +/** + * Get a mapping information. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument, pointing to a drm_map structure. + * + * \return zero on success or a negative number on failure. + * + * Searches for the mapping with the specified offset and copies its information + * into userspace + */ +int drm_getmap( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_map_t __user *argp = (void __user *)arg; + drm_map_t map; + drm_map_list_t *r_list = NULL; + struct list_head *list; + int idx; + int i; + + if (copy_from_user(&map, argp, sizeof(map))) + return -EFAULT; + idx = map.offset; + + down(&dev->struct_sem); + if (idx < 0) { + up(&dev->struct_sem); + return -EINVAL; + } + + i = 0; + list_for_each(list, &dev->maplist->head) { + if(i == idx) { + r_list = list_entry(list, drm_map_list_t, head); + break; + } + i++; + } + if(!r_list || !r_list->map) { + up(&dev->struct_sem); + return -EINVAL; + } + + map.offset = r_list->map->offset; + map.size = r_list->map->size; + map.type = r_list->map->type; + map.flags = r_list->map->flags; + map.handle = r_list->map->handle; + map.mtrr = r_list->map->mtrr; + up(&dev->struct_sem); + + if (copy_to_user(argp, &map, sizeof(map))) return -EFAULT; + return 0; +} + +/** + * Get client information. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument, pointing to a drm_client structure. + * + * \return zero on success or a negative number on failure. + * + * Searches for the client with the specified index and copies its information + * into userspace + */ +int drm_getclient( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_client_t __user *argp = (void __user *)arg; + drm_client_t client; + drm_file_t *pt; + int idx; + int i; + + if (copy_from_user(&client, argp, sizeof(client))) + return -EFAULT; + idx = client.idx; + down(&dev->struct_sem); + for (i = 0, pt = dev->file_first; i < idx && pt; i++, pt = pt->next) + ; + + if (!pt) { + up(&dev->struct_sem); + return -EINVAL; + } + client.auth = pt->authenticated; + client.pid = pt->pid; + client.uid = pt->uid; + client.magic = pt->magic; + client.iocs = pt->ioctl_count; + up(&dev->struct_sem); + + if (copy_to_user((drm_client_t __user *)arg, &client, sizeof(client))) + return -EFAULT; + return 0; +} + +/** + * Get statistics information. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument, pointing to a drm_stats structure. + * + * \return zero on success or a negative number on failure. + */ +int drm_getstats( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_stats_t stats; + int i; + + memset(&stats, 0, sizeof(stats)); + + down(&dev->struct_sem); + + for (i = 0; i < dev->counters; i++) { + if (dev->types[i] == _DRM_STAT_LOCK) + stats.data[i].value + = (dev->lock.hw_lock + ? dev->lock.hw_lock->lock : 0); + else + stats.data[i].value = atomic_read(&dev->counts[i]); + stats.data[i].type = dev->types[i]; + } + + stats.count = dev->counters; + + up(&dev->struct_sem); + + if (copy_to_user((drm_stats_t __user *)arg, &stats, sizeof(stats))) + return -EFAULT; + return 0; +} + +/** + * Setversion ioctl. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument, pointing to a drm_lock structure. + * \return zero on success or negative number on failure. + * + * Sets the requested interface version + */ +int drm_setversion(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_set_version_t sv; + drm_set_version_t retv; + int if_version; + drm_set_version_t __user *argp = (void __user *)data; + drm_version_t version; + + DRM_COPY_FROM_USER_IOCTL(sv, argp, sizeof(sv)); + + memset(&version, 0, sizeof(version)); + + dev->driver->version(&version); + retv.drm_di_major = DRM_IF_MAJOR; + retv.drm_di_minor = DRM_IF_MINOR; + retv.drm_dd_major = version.version_major; + retv.drm_dd_minor = version.version_minor; + + DRM_COPY_TO_USER_IOCTL(argp, retv, sizeof(sv)); + + if (sv.drm_di_major != -1) { + if (sv.drm_di_major != DRM_IF_MAJOR || + sv.drm_di_minor < 0 || sv.drm_di_minor > DRM_IF_MINOR) + return EINVAL; + if_version = DRM_IF_VERSION(sv.drm_di_major, sv.drm_dd_minor); + dev->if_version = DRM_MAX(if_version, dev->if_version); + if (sv.drm_di_minor >= 1) { + /* + * Version 1.1 includes tying of DRM to specific device + */ + drm_set_busid(dev); + } + } + + if (sv.drm_dd_major != -1) { + if (sv.drm_dd_major != version.version_major || + sv.drm_dd_minor < 0 || sv.drm_dd_minor > version.version_minor) + return EINVAL; + + if (dev->driver->set_version) + dev->driver->set_version(dev, &sv); + } + return 0; +} + +/** No-op ioctl. */ +int drm_noop(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + DRM_DEBUG("\n"); + return 0; +} diff --git a/drivers/char/drm/drm_irq.c b/drivers/char/drm/drm_irq.c new file mode 100644 index 000000000000..2e236ebcf27b --- /dev/null +++ b/drivers/char/drm/drm_irq.c @@ -0,0 +1,370 @@ +/** + * \file drm_irq.h + * IRQ support + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Fri Mar 19 14:30:16 1999 by faith@valinux.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" + +#include /* For task queue support */ + +/** + * Get interrupt from bus id. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument, pointing to a drm_irq_busid structure. + * \return zero on success or a negative number on failure. + * + * Finds the PCI device with the specified bus id and gets its IRQ number. + * This IOCTL is deprecated, and will now return EINVAL for any busid not equal + * to that of the device that this DRM instance attached to. + */ +int drm_irq_by_busid(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_irq_busid_t __user *argp = (void __user *)arg; + drm_irq_busid_t p; + + if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) + return -EINVAL; + + if (copy_from_user(&p, argp, sizeof(p))) + return -EFAULT; + + if ((p.busnum >> 8) != dev->pci_domain || + (p.busnum & 0xff) != dev->pci_bus || + p.devnum != dev->pci_slot || + p.funcnum != dev->pci_func) + return -EINVAL; + + p.irq = dev->irq; + + DRM_DEBUG("%d:%d:%d => IRQ %d\n", + p.busnum, p.devnum, p.funcnum, p.irq); + if (copy_to_user(argp, &p, sizeof(p))) + return -EFAULT; + return 0; +} + +/** + * Install IRQ handler. + * + * \param dev DRM device. + * \param irq IRQ number. + * + * Initializes the IRQ related data, and setups drm_device::vbl_queue. Installs the handler, calling the driver + * \c drm_driver_irq_preinstall() and \c drm_driver_irq_postinstall() functions + * before and after the installation. + */ +int drm_irq_install( drm_device_t *dev ) +{ + int ret; + unsigned long sh_flags=0; + + if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) + return -EINVAL; + + if ( dev->irq == 0 ) + return -EINVAL; + + down( &dev->struct_sem ); + + /* Driver must have been initialized */ + if ( !dev->dev_private ) { + up( &dev->struct_sem ); + return -EINVAL; + } + + if ( dev->irq_enabled ) { + up( &dev->struct_sem ); + return -EBUSY; + } + dev->irq_enabled = 1; + up( &dev->struct_sem ); + + DRM_DEBUG( "%s: irq=%d\n", __FUNCTION__, dev->irq ); + + if (drm_core_check_feature(dev, DRIVER_IRQ_VBL)) { + init_waitqueue_head(&dev->vbl_queue); + + spin_lock_init( &dev->vbl_lock ); + + INIT_LIST_HEAD( &dev->vbl_sigs.head ); + + dev->vbl_pending = 0; + } + + /* Before installing handler */ + dev->driver->irq_preinstall(dev); + + /* Install handler */ + if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED)) + sh_flags = SA_SHIRQ; + + ret = request_irq( dev->irq, dev->driver->irq_handler, + sh_flags, dev->devname, dev ); + if ( ret < 0 ) { + down( &dev->struct_sem ); + dev->irq_enabled = 0; + up( &dev->struct_sem ); + return ret; + } + + /* After installing handler */ + dev->driver->irq_postinstall(dev); + + return 0; +} + +/** + * Uninstall the IRQ handler. + * + * \param dev DRM device. + * + * Calls the driver's \c drm_driver_irq_uninstall() function, and stops the irq. + */ +int drm_irq_uninstall( drm_device_t *dev ) +{ + int irq_enabled; + + if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) + return -EINVAL; + + down( &dev->struct_sem ); + irq_enabled = dev->irq_enabled; + dev->irq_enabled = 0; + up( &dev->struct_sem ); + + if ( !irq_enabled ) + return -EINVAL; + + DRM_DEBUG( "%s: irq=%d\n", __FUNCTION__, dev->irq ); + + dev->driver->irq_uninstall(dev); + + free_irq( dev->irq, dev ); + + return 0; +} +EXPORT_SYMBOL(drm_irq_uninstall); + +/** + * IRQ control ioctl. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument, pointing to a drm_control structure. + * \return zero on success or a negative number on failure. + * + * Calls irq_install() or irq_uninstall() according to \p arg. + */ +int drm_control( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_control_t ctl; + + /* if we haven't irq we fallback for compatibility reasons - this used to be a separate function in drm_dma.h */ + + if ( copy_from_user( &ctl, (drm_control_t __user *)arg, sizeof(ctl) ) ) + return -EFAULT; + + switch ( ctl.func ) { + case DRM_INST_HANDLER: + if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) + return 0; + if (dev->if_version < DRM_IF_VERSION(1, 2) && + ctl.irq != dev->irq) + return -EINVAL; + return drm_irq_install( dev ); + case DRM_UNINST_HANDLER: + if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) + return 0; + return drm_irq_uninstall( dev ); + default: + return -EINVAL; + } +} + +/** + * Wait for VBLANK. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param data user argument, pointing to a drm_wait_vblank structure. + * \return zero on success or a negative number on failure. + * + * Verifies the IRQ is installed. + * + * If a signal is requested checks if this task has already scheduled the same signal + * for the same vblank sequence number - nothing to be done in + * that case. If the number of tasks waiting for the interrupt exceeds 100 the + * function fails. Otherwise adds a new entry to drm_device::vbl_sigs for this + * task. + * + * If a signal is not requested, then calls vblank_wait(). + */ +int drm_wait_vblank( DRM_IOCTL_ARGS ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_wait_vblank_t __user *argp = (void __user *)data; + drm_wait_vblank_t vblwait; + struct timeval now; + int ret = 0; + unsigned int flags; + + if (!drm_core_check_feature(dev, DRIVER_IRQ_VBL)) + return -EINVAL; + + if (!dev->irq) + return -EINVAL; + + DRM_COPY_FROM_USER_IOCTL( vblwait, argp, sizeof(vblwait) ); + + switch ( vblwait.request.type & ~_DRM_VBLANK_FLAGS_MASK ) { + case _DRM_VBLANK_RELATIVE: + vblwait.request.sequence += atomic_read( &dev->vbl_received ); + vblwait.request.type &= ~_DRM_VBLANK_RELATIVE; + case _DRM_VBLANK_ABSOLUTE: + break; + default: + return -EINVAL; + } + + flags = vblwait.request.type & _DRM_VBLANK_FLAGS_MASK; + + if ( flags & _DRM_VBLANK_SIGNAL ) { + unsigned long irqflags; + drm_vbl_sig_t *vbl_sig; + + vblwait.reply.sequence = atomic_read( &dev->vbl_received ); + + spin_lock_irqsave( &dev->vbl_lock, irqflags ); + + /* Check if this task has already scheduled the same signal + * for the same vblank sequence number; nothing to be done in + * that case + */ + list_for_each_entry( vbl_sig, &dev->vbl_sigs.head, head ) { + if (vbl_sig->sequence == vblwait.request.sequence + && vbl_sig->info.si_signo == vblwait.request.signal + && vbl_sig->task == current) + { + spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); + goto done; + } + } + + if ( dev->vbl_pending >= 100 ) { + spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); + return -EBUSY; + } + + dev->vbl_pending++; + + spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); + + if ( !( vbl_sig = drm_alloc( sizeof( drm_vbl_sig_t ), DRM_MEM_DRIVER ) ) ) { + return -ENOMEM; + } + + memset( (void *)vbl_sig, 0, sizeof(*vbl_sig) ); + + vbl_sig->sequence = vblwait.request.sequence; + vbl_sig->info.si_signo = vblwait.request.signal; + vbl_sig->task = current; + + spin_lock_irqsave( &dev->vbl_lock, irqflags ); + + list_add_tail( (struct list_head *) vbl_sig, &dev->vbl_sigs.head ); + + spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); + } else { + if (dev->driver->vblank_wait) + ret = dev->driver->vblank_wait( dev, &vblwait.request.sequence ); + + do_gettimeofday( &now ); + vblwait.reply.tval_sec = now.tv_sec; + vblwait.reply.tval_usec = now.tv_usec; + } + +done: + DRM_COPY_TO_USER_IOCTL( argp, vblwait, sizeof(vblwait) ); + + return ret; +} + +/** + * Send the VBLANK signals. + * + * \param dev DRM device. + * + * Sends a signal for each task in drm_device::vbl_sigs and empties the list. + * + * If a signal is not requested, then calls vblank_wait(). + */ +void drm_vbl_send_signals( drm_device_t *dev ) +{ + struct list_head *list, *tmp; + drm_vbl_sig_t *vbl_sig; + unsigned int vbl_seq = atomic_read( &dev->vbl_received ); + unsigned long flags; + + spin_lock_irqsave( &dev->vbl_lock, flags ); + + list_for_each_safe( list, tmp, &dev->vbl_sigs.head ) { + vbl_sig = list_entry( list, drm_vbl_sig_t, head ); + if ( ( vbl_seq - vbl_sig->sequence ) <= (1<<23) ) { + vbl_sig->info.si_code = vbl_seq; + send_sig_info( vbl_sig->info.si_signo, &vbl_sig->info, vbl_sig->task ); + + list_del( list ); + + drm_free( vbl_sig, sizeof(*vbl_sig), DRM_MEM_DRIVER ); + + dev->vbl_pending--; + } + } + + spin_unlock_irqrestore( &dev->vbl_lock, flags ); +} +EXPORT_SYMBOL(drm_vbl_send_signals); + + diff --git a/drivers/char/drm/drm_lock.c b/drivers/char/drm/drm_lock.c new file mode 100644 index 000000000000..d0d6fc661625 --- /dev/null +++ b/drivers/char/drm/drm_lock.c @@ -0,0 +1,303 @@ +/** + * \file drm_lock.h + * IOCTLs for locking + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Tue Feb 2 08:37:54 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" + +/** + * Lock ioctl. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument, pointing to a drm_lock structure. + * \return zero on success or negative number on failure. + * + * Add the current task to the lock wait queue, and attempt to take to lock. + */ +int drm_lock( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + DECLARE_WAITQUEUE( entry, current ); + drm_lock_t lock; + int ret = 0; + + ++priv->lock_count; + + if ( copy_from_user( &lock, (drm_lock_t __user *)arg, sizeof(lock) ) ) + return -EFAULT; + + if ( lock.context == DRM_KERNEL_CONTEXT ) { + DRM_ERROR( "Process %d using kernel context %d\n", + current->pid, lock.context ); + return -EINVAL; + } + + DRM_DEBUG( "%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", + lock.context, current->pid, + dev->lock.hw_lock->lock, lock.flags ); + + if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE)) + if ( lock.context < 0 ) + return -EINVAL; + + add_wait_queue( &dev->lock.lock_queue, &entry ); + for (;;) { + __set_current_state(TASK_INTERRUPTIBLE); + if ( !dev->lock.hw_lock ) { + /* Device has been unregistered */ + ret = -EINTR; + break; + } + if ( drm_lock_take( &dev->lock.hw_lock->lock, + lock.context ) ) { + dev->lock.filp = filp; + dev->lock.lock_time = jiffies; + atomic_inc( &dev->counts[_DRM_STAT_LOCKS] ); + break; /* Got lock */ + } + + /* Contention */ + schedule(); + if ( signal_pending( current ) ) { + ret = -ERESTARTSYS; + break; + } + } + __set_current_state(TASK_RUNNING); + remove_wait_queue( &dev->lock.lock_queue, &entry ); + + sigemptyset( &dev->sigmask ); + sigaddset( &dev->sigmask, SIGSTOP ); + sigaddset( &dev->sigmask, SIGTSTP ); + sigaddset( &dev->sigmask, SIGTTIN ); + sigaddset( &dev->sigmask, SIGTTOU ); + dev->sigdata.context = lock.context; + dev->sigdata.lock = dev->lock.hw_lock; + block_all_signals( drm_notifier, + &dev->sigdata, &dev->sigmask ); + + if (dev->driver->dma_ready && (lock.flags & _DRM_LOCK_READY)) + dev->driver->dma_ready(dev); + + if ( dev->driver->dma_quiescent && (lock.flags & _DRM_LOCK_QUIESCENT )) + return dev->driver->dma_quiescent(dev); + + /* dev->driver->kernel_context_switch isn't used by any of the x86 + * drivers but is used by the Sparc driver. + */ + + if (dev->driver->kernel_context_switch && + dev->last_context != lock.context) { + dev->driver->kernel_context_switch(dev, dev->last_context, + lock.context); + } + DRM_DEBUG( "%d %s\n", lock.context, ret ? "interrupted" : "has lock" ); + + return ret; +} + +/** + * Unlock ioctl. + * + * \param inode device inode. + * \param filp file pointer. + * \param cmd command. + * \param arg user argument, pointing to a drm_lock structure. + * \return zero on success or negative number on failure. + * + * Transfer and free the lock. + */ +int drm_unlock( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_lock_t lock; + + if ( copy_from_user( &lock, (drm_lock_t __user *)arg, sizeof(lock) ) ) + return -EFAULT; + + if ( lock.context == DRM_KERNEL_CONTEXT ) { + DRM_ERROR( "Process %d using kernel context %d\n", + current->pid, lock.context ); + return -EINVAL; + } + + atomic_inc( &dev->counts[_DRM_STAT_UNLOCKS] ); + + /* kernel_context_switch isn't used by any of the x86 drm + * modules but is required by the Sparc driver. + */ + if (dev->driver->kernel_context_switch_unlock) + dev->driver->kernel_context_switch_unlock(dev, &lock); + else { + drm_lock_transfer( dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT ); + + if ( drm_lock_free( dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT ) ) { + DRM_ERROR( "\n" ); + } + } + + unblock_all_signals(); + return 0; +} + +/** + * Take the heavyweight lock. + * + * \param lock lock pointer. + * \param context locking context. + * \return one if the lock is held, or zero otherwise. + * + * Attempt to mark the lock as held by the given context, via the \p cmpxchg instruction. + */ +int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context) +{ + unsigned int old, new, prev; + + do { + old = *lock; + if (old & _DRM_LOCK_HELD) new = old | _DRM_LOCK_CONT; + else new = context | _DRM_LOCK_HELD; + prev = cmpxchg(lock, old, new); + } while (prev != old); + if (_DRM_LOCKING_CONTEXT(old) == context) { + if (old & _DRM_LOCK_HELD) { + if (context != DRM_KERNEL_CONTEXT) { + DRM_ERROR("%d holds heavyweight lock\n", + context); + } + return 0; + } + } + if (new == (context | _DRM_LOCK_HELD)) { + /* Have lock */ + return 1; + } + return 0; +} + +/** + * This takes a lock forcibly and hands it to context. Should ONLY be used + * inside *_unlock to give lock to kernel before calling *_dma_schedule. + * + * \param dev DRM device. + * \param lock lock pointer. + * \param context locking context. + * \return always one. + * + * Resets the lock file pointer. + * Marks the lock as held by the given context, via the \p cmpxchg instruction. + */ +int drm_lock_transfer(drm_device_t *dev, + __volatile__ unsigned int *lock, unsigned int context) +{ + unsigned int old, new, prev; + + dev->lock.filp = NULL; + do { + old = *lock; + new = context | _DRM_LOCK_HELD; + prev = cmpxchg(lock, old, new); + } while (prev != old); + return 1; +} + +/** + * Free lock. + * + * \param dev DRM device. + * \param lock lock. + * \param context context. + * + * Resets the lock file pointer. + * Marks the lock as not held, via the \p cmpxchg instruction. Wakes any task + * waiting on the lock queue. + */ +int drm_lock_free(drm_device_t *dev, + __volatile__ unsigned int *lock, unsigned int context) +{ + unsigned int old, new, prev; + + dev->lock.filp = NULL; + do { + old = *lock; + new = 0; + prev = cmpxchg(lock, old, new); + } while (prev != old); + if (_DRM_LOCK_IS_HELD(old) && _DRM_LOCKING_CONTEXT(old) != context) { + DRM_ERROR("%d freed heavyweight lock held by %d\n", + context, + _DRM_LOCKING_CONTEXT(old)); + return 1; + } + wake_up_interruptible(&dev->lock.lock_queue); + return 0; +} + +/** + * If we get here, it means that the process has called DRM_IOCTL_LOCK + * without calling DRM_IOCTL_UNLOCK. + * + * If the lock is not held, then let the signal proceed as usual. If the lock + * is held, then set the contended flag and keep the signal blocked. + * + * \param priv pointer to a drm_sigdata structure. + * \return one if the signal should be delivered normally, or zero if the + * signal should be blocked. + */ +int drm_notifier(void *priv) +{ + drm_sigdata_t *s = (drm_sigdata_t *)priv; + unsigned int old, new, prev; + + + /* Allow signal delivery if lock isn't held */ + if (!s->lock || !_DRM_LOCK_IS_HELD(s->lock->lock) + || _DRM_LOCKING_CONTEXT(s->lock->lock) != s->context) return 1; + + /* Otherwise, set flag to force call to + drmUnlock */ + do { + old = s->lock->lock; + new = old | _DRM_LOCK_CONT; + prev = cmpxchg(&s->lock->lock, old, new); + } while (prev != old); + return 0; +} diff --git a/drivers/char/drm/drm_memory.c b/drivers/char/drm/drm_memory.c new file mode 100644 index 000000000000..7f53f756c052 --- /dev/null +++ b/drivers/char/drm/drm_memory.c @@ -0,0 +1,181 @@ +/** + * \file drm_memory.h + * Memory management wrappers for DRM + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "drmP.h" + +#ifdef DEBUG_MEMORY +#include "drm_memory_debug.h" +#else + +/** No-op. */ +void drm_mem_init(void) +{ +} + +/** + * Called when "/proc/dri/%dev%/mem" is read. + * + * \param buf output buffer. + * \param start start of output data. + * \param offset requested start offset. + * \param len requested number of bytes. + * \param eof whether there is no more data to return. + * \param data private data. + * \return number of written bytes. + * + * No-op. + */ +int drm_mem_info(char *buf, char **start, off_t offset, + int len, int *eof, void *data) +{ + return 0; +} + +/** Wrapper around kmalloc() */ +void *drm_calloc(size_t nmemb, size_t size, int area) +{ + void *addr; + + addr = kmalloc(size * nmemb, GFP_KERNEL); + if (addr != NULL) + memset((void *)addr, 0, size * nmemb); + + return addr; +} +EXPORT_SYMBOL(drm_calloc); + +/** Wrapper around kmalloc() and kfree() */ +void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area) +{ + void *pt; + + if (!(pt = kmalloc(size, GFP_KERNEL))) return NULL; + if (oldpt && oldsize) { + memcpy(pt, oldpt, oldsize); + kfree(oldpt); + } + return pt; +} + +/** + * Allocate pages. + * + * \param order size order. + * \param area memory area. (Not used.) + * \return page address on success, or zero on failure. + * + * Allocate and reserve free pages. + */ +unsigned long drm_alloc_pages(int order, int area) +{ + unsigned long address; + unsigned long bytes = PAGE_SIZE << order; + unsigned long addr; + unsigned int sz; + + address = __get_free_pages(GFP_KERNEL, order); + if (!address) + return 0; + + /* Zero */ + memset((void *)address, 0, bytes); + + /* Reserve */ + for (addr = address, sz = bytes; + sz > 0; + addr += PAGE_SIZE, sz -= PAGE_SIZE) { + SetPageReserved(virt_to_page(addr)); + } + + return address; +} + +/** + * Free pages. + * + * \param address address of the pages to free. + * \param order size order. + * \param area memory area. (Not used.) + * + * Unreserve and free pages allocated by alloc_pages(). + */ +void drm_free_pages(unsigned long address, int order, int area) +{ + unsigned long bytes = PAGE_SIZE << order; + unsigned long addr; + unsigned int sz; + + if (!address) + return; + + /* Unreserve */ + for (addr = address, sz = bytes; + sz > 0; + addr += PAGE_SIZE, sz -= PAGE_SIZE) { + ClearPageReserved(virt_to_page(addr)); + } + + free_pages(address, order); +} + + +#if __OS_HAS_AGP +/** Wrapper around agp_allocate_memory() */ +DRM_AGP_MEM *drm_alloc_agp(struct agp_bridge_data *bridge, int pages, u32 type) +{ + return drm_agp_allocate_memory(bridge, pages, type); +} + +/** Wrapper around agp_free_memory() */ +int drm_free_agp(DRM_AGP_MEM *handle, int pages) +{ + return drm_agp_free_memory(handle) ? 0 : -EINVAL; +} + +/** Wrapper around agp_bind_memory() */ +int drm_bind_agp(DRM_AGP_MEM *handle, unsigned int start) +{ + return drm_agp_bind_memory(handle, start); +} + +/** Wrapper around agp_unbind_memory() */ +int drm_unbind_agp(DRM_AGP_MEM *handle) +{ + return drm_agp_unbind_memory(handle); +} +#endif /* agp */ +#endif /* debug_memory */ diff --git a/drivers/char/drm/drm_memory.h b/drivers/char/drm/drm_memory.h new file mode 100644 index 000000000000..422b94268709 --- /dev/null +++ b/drivers/char/drm/drm_memory.h @@ -0,0 +1,197 @@ +/** + * \file drm_memory.h + * Memory management wrappers for DRM + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include "drmP.h" + +/** + * Cut down version of drm_memory_debug.h, which used to be called + * drm_memory.h. + */ + +#if __OS_HAS_AGP + +#include + +#ifdef HAVE_PAGE_AGP +#include +#else +# ifdef __powerpc__ +# define PAGE_AGP __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE) +# else +# define PAGE_AGP PAGE_KERNEL +# endif +#endif + +/* + * Find the drm_map that covers the range [offset, offset+size). + */ +static inline drm_map_t * +drm_lookup_map (unsigned long offset, unsigned long size, drm_device_t *dev) +{ + struct list_head *list; + drm_map_list_t *r_list; + drm_map_t *map; + + list_for_each(list, &dev->maplist->head) { + r_list = (drm_map_list_t *) list; + map = r_list->map; + if (!map) + continue; + if (map->offset <= offset && (offset + size) <= (map->offset + map->size)) + return map; + } + return NULL; +} + +static inline void * +agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev) +{ + unsigned long *phys_addr_map, i, num_pages = PAGE_ALIGN(size) / PAGE_SIZE; + struct drm_agp_mem *agpmem; + struct page **page_map; + void *addr; + + size = PAGE_ALIGN(size); + +#ifdef __alpha__ + offset -= dev->hose->mem_space->start; +#endif + + for (agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) + if (agpmem->bound <= offset + && (agpmem->bound + (agpmem->pages << PAGE_SHIFT)) >= (offset + size)) + break; + if (!agpmem) + return NULL; + + /* + * OK, we're mapping AGP space on a chipset/platform on which memory accesses by + * the CPU do not get remapped by the GART. We fix this by using the kernel's + * page-table instead (that's probably faster anyhow...). + */ + /* note: use vmalloc() because num_pages could be large... */ + page_map = vmalloc(num_pages * sizeof(struct page *)); + if (!page_map) + return NULL; + + phys_addr_map = agpmem->memory->memory + (offset - agpmem->bound) / PAGE_SIZE; + for (i = 0; i < num_pages; ++i) + page_map[i] = pfn_to_page(phys_addr_map[i] >> PAGE_SHIFT); + addr = vmap(page_map, num_pages, VM_IOREMAP, PAGE_AGP); + vfree(page_map); + + return addr; +} + +static inline unsigned long +drm_follow_page (void *vaddr) +{ + pgd_t *pgd = pgd_offset_k((unsigned long) vaddr); + pud_t *pud = pud_offset(pgd, (unsigned long) vaddr); + pmd_t *pmd = pmd_offset(pud, (unsigned long) vaddr); + pte_t *ptep = pte_offset_kernel(pmd, (unsigned long) vaddr); + return pte_pfn(*ptep) << PAGE_SHIFT; +} + +#else /* __OS_HAS_AGP */ + +static inline drm_map_t *drm_lookup_map(unsigned long offset, unsigned long size, drm_device_t *dev) +{ + return NULL; +} + +static inline void *agp_remap(unsigned long offset, unsigned long size, drm_device_t *dev) +{ + return NULL; +} + +static inline unsigned long drm_follow_page (void *vaddr) +{ + return 0; +} + +#endif + +static inline void *drm_ioremap(unsigned long offset, unsigned long size, drm_device_t *dev) +{ + if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture) { + drm_map_t *map = drm_lookup_map(offset, size, dev); + + if (map && map->type == _DRM_AGP) + return agp_remap(offset, size, dev); + } + return ioremap(offset, size); +} + +static inline void *drm_ioremap_nocache(unsigned long offset, unsigned long size, + drm_device_t *dev) +{ + if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture) { + drm_map_t *map = drm_lookup_map(offset, size, dev); + + if (map && map->type == _DRM_AGP) + return agp_remap(offset, size, dev); + } + return ioremap_nocache(offset, size); +} + +static inline void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *dev) +{ + /* + * This is a bit ugly. It would be much cleaner if the DRM API would use separate + * routines for handling mappings in the AGP space. Hopefully this can be done in + * a future revision of the interface... + */ + if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture + && ((unsigned long) pt >= VMALLOC_START && (unsigned long) pt < VMALLOC_END)) + { + unsigned long offset; + drm_map_t *map; + + offset = drm_follow_page(pt) | ((unsigned long) pt & ~PAGE_MASK); + map = drm_lookup_map(offset, size, dev); + if (map && map->type == _DRM_AGP) { + vunmap(pt); + return; + } + } + + iounmap(pt); +} + + diff --git a/drivers/char/drm/drm_memory_debug.h b/drivers/char/drm/drm_memory_debug.h new file mode 100644 index 000000000000..2c82e69a7fd2 --- /dev/null +++ b/drivers/char/drm/drm_memory_debug.h @@ -0,0 +1,459 @@ +/** + * \file drm_memory.h + * Memory management wrappers for DRM. + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "drmP.h" + +typedef struct drm_mem_stats { + const char *name; + int succeed_count; + int free_count; + int fail_count; + unsigned long bytes_allocated; + unsigned long bytes_freed; +} drm_mem_stats_t; + +static DEFINE_SPINLOCK(DRM(mem_lock)); +static unsigned long DRM(ram_available) = 0; /* In pages */ +static unsigned long DRM(ram_used) = 0; +static drm_mem_stats_t DRM(mem_stats)[] = { + [DRM_MEM_DMA] = { "dmabufs" }, + [DRM_MEM_SAREA] = { "sareas" }, + [DRM_MEM_DRIVER] = { "driver" }, + [DRM_MEM_MAGIC] = { "magic" }, + [DRM_MEM_IOCTLS] = { "ioctltab" }, + [DRM_MEM_MAPS] = { "maplist" }, + [DRM_MEM_VMAS] = { "vmalist" }, + [DRM_MEM_BUFS] = { "buflist" }, + [DRM_MEM_SEGS] = { "seglist" }, + [DRM_MEM_PAGES] = { "pagelist" }, + [DRM_MEM_FILES] = { "files" }, + [DRM_MEM_QUEUES] = { "queues" }, + [DRM_MEM_CMDS] = { "commands" }, + [DRM_MEM_MAPPINGS] = { "mappings" }, + [DRM_MEM_BUFLISTS] = { "buflists" }, + [DRM_MEM_AGPLISTS] = { "agplist" }, + [DRM_MEM_SGLISTS] = { "sglist" }, + [DRM_MEM_TOTALAGP] = { "totalagp" }, + [DRM_MEM_BOUNDAGP] = { "boundagp" }, + [DRM_MEM_CTXBITMAP] = { "ctxbitmap"}, + [DRM_MEM_CTXLIST] = { "ctxlist" }, + [DRM_MEM_STUB] = { "stub" }, + { NULL, 0, } /* Last entry must be null */ +}; + +void DRM(mem_init)(void) +{ + drm_mem_stats_t *mem; + struct sysinfo si; + + for (mem = DRM(mem_stats); mem->name; ++mem) { + mem->succeed_count = 0; + mem->free_count = 0; + mem->fail_count = 0; + mem->bytes_allocated = 0; + mem->bytes_freed = 0; + } + + si_meminfo(&si); + DRM(ram_available) = si.totalram; + DRM(ram_used) = 0; +} + +/* drm_mem_info is called whenever a process reads /dev/drm/mem. */ + +static int DRM(_mem_info)(char *buf, char **start, off_t offset, + int request, int *eof, void *data) +{ + drm_mem_stats_t *pt; + int len = 0; + + if (offset > DRM_PROC_LIMIT) { + *eof = 1; + return 0; + } + + *eof = 0; + *start = &buf[offset]; + + DRM_PROC_PRINT(" total counts " + " | outstanding \n"); + DRM_PROC_PRINT("type alloc freed fail bytes freed" + " | allocs bytes\n\n"); + DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu kB |\n", + "system", 0, 0, 0, + DRM(ram_available) << (PAGE_SHIFT - 10)); + DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu kB |\n", + "locked", 0, 0, 0, DRM(ram_used) >> 10); + DRM_PROC_PRINT("\n"); + for (pt = DRM(mem_stats); pt->name; pt++) { + DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu %10lu | %6d %10ld\n", + pt->name, + pt->succeed_count, + pt->free_count, + pt->fail_count, + pt->bytes_allocated, + pt->bytes_freed, + pt->succeed_count - pt->free_count, + (long)pt->bytes_allocated + - (long)pt->bytes_freed); + } + + if (len > request + offset) return request; + *eof = 1; + return len - offset; +} + +int DRM(mem_info)(char *buf, char **start, off_t offset, + int len, int *eof, void *data) +{ + int ret; + + spin_lock(&DRM(mem_lock)); + ret = DRM(_mem_info)(buf, start, offset, len, eof, data); + spin_unlock(&DRM(mem_lock)); + return ret; +} + +void *DRM(alloc)(size_t size, int area) +{ + void *pt; + + if (!size) { + DRM_MEM_ERROR(area, "Allocating 0 bytes\n"); + return NULL; + } + + if (!(pt = kmalloc(size, GFP_KERNEL))) { + spin_lock(&DRM(mem_lock)); + ++DRM(mem_stats)[area].fail_count; + spin_unlock(&DRM(mem_lock)); + return NULL; + } + spin_lock(&DRM(mem_lock)); + ++DRM(mem_stats)[area].succeed_count; + DRM(mem_stats)[area].bytes_allocated += size; + spin_unlock(&DRM(mem_lock)); + return pt; +} + +void *DRM(calloc)(size_t nmemb, size_t size, int area) +{ + void *addr; + + addr = DRM(alloc)(nmemb * size, area); + if (addr != NULL) + memset((void *)addr, 0, size * nmemb); + + return addr; +} + +void *DRM(realloc)(void *oldpt, size_t oldsize, size_t size, int area) +{ + void *pt; + + if (!(pt = DRM(alloc)(size, area))) return NULL; + if (oldpt && oldsize) { + memcpy(pt, oldpt, oldsize); + DRM(free)(oldpt, oldsize, area); + } + return pt; +} + +void DRM(free)(void *pt, size_t size, int area) +{ + int alloc_count; + int free_count; + + if (!pt) DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n"); + else kfree(pt); + spin_lock(&DRM(mem_lock)); + DRM(mem_stats)[area].bytes_freed += size; + free_count = ++DRM(mem_stats)[area].free_count; + alloc_count = DRM(mem_stats)[area].succeed_count; + spin_unlock(&DRM(mem_lock)); + if (free_count > alloc_count) { + DRM_MEM_ERROR(area, "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } +} + +unsigned long DRM(alloc_pages)(int order, int area) +{ + unsigned long address; + unsigned long bytes = PAGE_SIZE << order; + unsigned long addr; + unsigned int sz; + + spin_lock(&DRM(mem_lock)); + if ((DRM(ram_used) >> PAGE_SHIFT) + > (DRM_RAM_PERCENT * DRM(ram_available)) / 100) { + spin_unlock(&DRM(mem_lock)); + return 0; + } + spin_unlock(&DRM(mem_lock)); + + address = __get_free_pages(GFP_KERNEL, order); + if (!address) { + spin_lock(&DRM(mem_lock)); + ++DRM(mem_stats)[area].fail_count; + spin_unlock(&DRM(mem_lock)); + return 0; + } + spin_lock(&DRM(mem_lock)); + ++DRM(mem_stats)[area].succeed_count; + DRM(mem_stats)[area].bytes_allocated += bytes; + DRM(ram_used) += bytes; + spin_unlock(&DRM(mem_lock)); + + + /* Zero outside the lock */ + memset((void *)address, 0, bytes); + + /* Reserve */ + for (addr = address, sz = bytes; + sz > 0; + addr += PAGE_SIZE, sz -= PAGE_SIZE) { + SetPageReserved(virt_to_page(addr)); + } + + return address; +} + +void DRM(free_pages)(unsigned long address, int order, int area) +{ + unsigned long bytes = PAGE_SIZE << order; + int alloc_count; + int free_count; + unsigned long addr; + unsigned int sz; + + if (!address) { + DRM_MEM_ERROR(area, "Attempt to free address 0\n"); + } else { + /* Unreserve */ + for (addr = address, sz = bytes; + sz > 0; + addr += PAGE_SIZE, sz -= PAGE_SIZE) { + ClearPageReserved(virt_to_page(addr)); + } + free_pages(address, order); + } + + spin_lock(&DRM(mem_lock)); + free_count = ++DRM(mem_stats)[area].free_count; + alloc_count = DRM(mem_stats)[area].succeed_count; + DRM(mem_stats)[area].bytes_freed += bytes; + DRM(ram_used) -= bytes; + spin_unlock(&DRM(mem_lock)); + if (free_count > alloc_count) { + DRM_MEM_ERROR(area, + "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } +} + +void *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev) +{ + void *pt; + + if (!size) { + DRM_MEM_ERROR(DRM_MEM_MAPPINGS, + "Mapping 0 bytes at 0x%08lx\n", offset); + return NULL; + } + + if (!(pt = drm_ioremap(offset, size, dev))) { + spin_lock(&DRM(mem_lock)); + ++DRM(mem_stats)[DRM_MEM_MAPPINGS].fail_count; + spin_unlock(&DRM(mem_lock)); + return NULL; + } + spin_lock(&DRM(mem_lock)); + ++DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count; + DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_allocated += size; + spin_unlock(&DRM(mem_lock)); + return pt; +} + +void *DRM(ioremap_nocache)(unsigned long offset, unsigned long size, drm_device_t *dev) +{ + void *pt; + + if (!size) { + DRM_MEM_ERROR(DRM_MEM_MAPPINGS, + "Mapping 0 bytes at 0x%08lx\n", offset); + return NULL; + } + + if (!(pt = drm_ioremap_nocache(offset, size, dev))) { + spin_lock(&DRM(mem_lock)); + ++DRM(mem_stats)[DRM_MEM_MAPPINGS].fail_count; + spin_unlock(&DRM(mem_lock)); + return NULL; + } + spin_lock(&DRM(mem_lock)); + ++DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count; + DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_allocated += size; + spin_unlock(&DRM(mem_lock)); + return pt; +} + +void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev) +{ + int alloc_count; + int free_count; + + if (!pt) + DRM_MEM_ERROR(DRM_MEM_MAPPINGS, + "Attempt to free NULL pointer\n"); + else + drm_ioremapfree(pt, size, dev); + + spin_lock(&DRM(mem_lock)); + DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_freed += size; + free_count = ++DRM(mem_stats)[DRM_MEM_MAPPINGS].free_count; + alloc_count = DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count; + spin_unlock(&DRM(mem_lock)); + if (free_count > alloc_count) { + DRM_MEM_ERROR(DRM_MEM_MAPPINGS, + "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } +} + +#if __OS_HAS_AGP + +DRM_AGP_MEM *DRM(alloc_agp)(int pages, u32 type) +{ + DRM_AGP_MEM *handle; + + if (!pages) { + DRM_MEM_ERROR(DRM_MEM_TOTALAGP, "Allocating 0 pages\n"); + return NULL; + } + + if ((handle = DRM(agp_allocate_memory)(pages, type))) { + spin_lock(&DRM(mem_lock)); + ++DRM(mem_stats)[DRM_MEM_TOTALAGP].succeed_count; + DRM(mem_stats)[DRM_MEM_TOTALAGP].bytes_allocated + += pages << PAGE_SHIFT; + spin_unlock(&DRM(mem_lock)); + return handle; + } + spin_lock(&DRM(mem_lock)); + ++DRM(mem_stats)[DRM_MEM_TOTALAGP].fail_count; + spin_unlock(&DRM(mem_lock)); + return NULL; +} + +int DRM(free_agp)(DRM_AGP_MEM *handle, int pages) +{ + int alloc_count; + int free_count; + int retval = -EINVAL; + + if (!handle) { + DRM_MEM_ERROR(DRM_MEM_TOTALAGP, + "Attempt to free NULL AGP handle\n"); + return retval; + } + + if (DRM(agp_free_memory)(handle)) { + spin_lock(&DRM(mem_lock)); + free_count = ++DRM(mem_stats)[DRM_MEM_TOTALAGP].free_count; + alloc_count = DRM(mem_stats)[DRM_MEM_TOTALAGP].succeed_count; + DRM(mem_stats)[DRM_MEM_TOTALAGP].bytes_freed + += pages << PAGE_SHIFT; + spin_unlock(&DRM(mem_lock)); + if (free_count > alloc_count) { + DRM_MEM_ERROR(DRM_MEM_TOTALAGP, + "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } + return 0; + } + return retval; +} + +int DRM(bind_agp)(DRM_AGP_MEM *handle, unsigned int start) +{ + int retcode = -EINVAL; + + if (!handle) { + DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, + "Attempt to bind NULL AGP handle\n"); + return retcode; + } + + if (!(retcode = DRM(agp_bind_memory)(handle, start))) { + spin_lock(&DRM(mem_lock)); + ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].succeed_count; + DRM(mem_stats)[DRM_MEM_BOUNDAGP].bytes_allocated + += handle->page_count << PAGE_SHIFT; + spin_unlock(&DRM(mem_lock)); + return retcode; + } + spin_lock(&DRM(mem_lock)); + ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].fail_count; + spin_unlock(&DRM(mem_lock)); + return retcode; +} + +int DRM(unbind_agp)(DRM_AGP_MEM *handle) +{ + int alloc_count; + int free_count; + int retcode = -EINVAL; + + if (!handle) { + DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, + "Attempt to unbind NULL AGP handle\n"); + return retcode; + } + + if ((retcode = DRM(agp_unbind_memory)(handle))) return retcode; + spin_lock(&DRM(mem_lock)); + free_count = ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].free_count; + alloc_count = DRM(mem_stats)[DRM_MEM_BOUNDAGP].succeed_count; + DRM(mem_stats)[DRM_MEM_BOUNDAGP].bytes_freed + += handle->page_count << PAGE_SHIFT; + spin_unlock(&DRM(mem_lock)); + if (free_count > alloc_count) { + DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, + "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } + return retcode; +} +#endif diff --git a/drivers/char/drm/drm_os_linux.h b/drivers/char/drm/drm_os_linux.h new file mode 100644 index 000000000000..b14cd370dea5 --- /dev/null +++ b/drivers/char/drm/drm_os_linux.h @@ -0,0 +1,149 @@ +/** + * \file drm_os_linux.h + * OS abstraction macros. + */ + + +#include /* For task queue support */ +#include + +/** File pointer type */ +#define DRMFILE struct file * +/** Ioctl arguments */ +#define DRM_IOCTL_ARGS struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data +#define DRM_ERR(d) -(d) +/** Current process ID */ +#define DRM_CURRENTPID current->pid +#define DRM_UDELAY(d) udelay(d) +/** Read a byte from a MMIO region */ +#define DRM_READ8(map, offset) readb(((void __iomem *)(map)->handle) + (offset)) +/** Read a word from a MMIO region */ +#define DRM_READ16(map, offset) readw(((void __iomem *)(map)->handle) + (offset)) +/** Read a dword from a MMIO region */ +#define DRM_READ32(map, offset) readl(((void __iomem *)(map)->handle) + (offset)) +/** Write a byte into a MMIO region */ +#define DRM_WRITE8(map, offset, val) writeb(val, ((void __iomem *)(map)->handle) + (offset)) +/** Write a word into a MMIO region */ +#define DRM_WRITE16(map, offset, val) writew(val, ((void __iomem *)(map)->handle) + (offset)) +/** Write a dword into a MMIO region */ +#define DRM_WRITE32(map, offset, val) writel(val, ((void __iomem *)(map)->handle) + (offset)) +/** Read memory barrier */ +#define DRM_READMEMORYBARRIER() rmb() +/** Write memory barrier */ +#define DRM_WRITEMEMORYBARRIER() wmb() +/** Read/write memory barrier */ +#define DRM_MEMORYBARRIER() mb() +/** DRM device local declaration */ +#define DRM_DEVICE drm_file_t *priv = filp->private_data; \ + drm_device_t *dev = priv->head->dev + +/** IRQ handler arguments and return type and values */ +#define DRM_IRQ_ARGS int irq, void *arg, struct pt_regs *regs + +/** AGP types */ +#if __OS_HAS_AGP +#define DRM_AGP_MEM struct agp_memory +#define DRM_AGP_KERN struct agp_kern_info +#else +/* define some dummy types for non AGP supporting kernels */ +struct no_agp_kern { + unsigned long aper_base; + unsigned long aper_size; +}; +#define DRM_AGP_MEM int +#define DRM_AGP_KERN struct no_agp_kern +#endif + +#if !(__OS_HAS_MTRR) +static __inline__ int mtrr_add (unsigned long base, unsigned long size, + unsigned int type, char increment) +{ + return -ENODEV; +} + +static __inline__ int mtrr_del (int reg, unsigned long base, + unsigned long size) +{ + return -ENODEV; +} +#define MTRR_TYPE_WRCOMB 1 + +#endif + +/** Task queue handler arguments */ +#define DRM_TASKQUEUE_ARGS void *arg + +/** For data going into the kernel through the ioctl argument */ +#define DRM_COPY_FROM_USER_IOCTL(arg1, arg2, arg3) \ + if ( copy_from_user(&arg1, arg2, arg3) ) \ + return -EFAULT +/** For data going from the kernel through the ioctl argument */ +#define DRM_COPY_TO_USER_IOCTL(arg1, arg2, arg3) \ + if ( copy_to_user(arg1, &arg2, arg3) ) \ + return -EFAULT +/** Other copying of data to kernel space */ +#define DRM_COPY_FROM_USER(arg1, arg2, arg3) \ + copy_from_user(arg1, arg2, arg3) +/** Other copying of data from kernel space */ +#define DRM_COPY_TO_USER(arg1, arg2, arg3) \ + copy_to_user(arg1, arg2, arg3) +/* Macros for copyfrom user, but checking readability only once */ +#define DRM_VERIFYAREA_READ( uaddr, size ) \ + (access_ok( VERIFY_READ, uaddr, size ) ? 0 : -EFAULT) +#define DRM_COPY_FROM_USER_UNCHECKED(arg1, arg2, arg3) \ + __copy_from_user(arg1, arg2, arg3) +#define DRM_COPY_TO_USER_UNCHECKED(arg1, arg2, arg3) \ + __copy_to_user(arg1, arg2, arg3) +#define DRM_GET_USER_UNCHECKED(val, uaddr) \ + __get_user(val, uaddr) + +#define DRM_GET_PRIV_WITH_RETURN(_priv, _filp) _priv = _filp->private_data + +/** + * Get the pointer to the SAREA. + * + * Searches the SAREA on the mapping lists and points drm_device::sarea to it. + */ +#define DRM_GETSAREA() \ +do { \ + drm_map_list_t *entry; \ + list_for_each_entry( entry, &dev->maplist->head, head ) { \ + if ( entry->map && \ + entry->map->type == _DRM_SHM && \ + (entry->map->flags & _DRM_CONTAINS_LOCK) ) { \ + dev_priv->sarea = entry->map; \ + break; \ + } \ + } \ +} while (0) + +#define DRM_HZ HZ + +#define DRM_WAIT_ON( ret, queue, timeout, condition ) \ +do { \ + DECLARE_WAITQUEUE(entry, current); \ + unsigned long end = jiffies + (timeout); \ + add_wait_queue(&(queue), &entry); \ + \ + for (;;) { \ + __set_current_state(TASK_INTERRUPTIBLE); \ + if (condition) \ + break; \ + if (time_after_eq(jiffies, end)) { \ + ret = -EBUSY; \ + break; \ + } \ + schedule_timeout((HZ/100 > 1) ? HZ/100 : 1); \ + if (signal_pending(current)) { \ + ret = -EINTR; \ + break; \ + } \ + } \ + __set_current_state(TASK_RUNNING); \ + remove_wait_queue(&(queue), &entry); \ +} while (0) + + +#define DRM_WAKEUP( queue ) wake_up_interruptible( queue ) +#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue ) + diff --git a/drivers/char/drm/drm_pci.c b/drivers/char/drm/drm_pci.c new file mode 100644 index 000000000000..192e8762571c --- /dev/null +++ b/drivers/char/drm/drm_pci.c @@ -0,0 +1,140 @@ +/* drm_pci.h -- PCI DMA memory management wrappers for DRM -*- linux-c -*- */ +/** + * \file drm_pci.c + * \brief Functions and ioctls to manage PCI memory + * + * \warning These interfaces aren't stable yet. + * + * \todo Implement the remaining ioctl's for the PCI pools. + * \todo The wrappers here are so thin that they would be better off inlined.. + * + * \author Jose Fonseca + * \author Leif Delgass + */ + +/* + * Copyright 2003 Jos�Fonseca. + * Copyright 2003 Leif Delgass. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "drmP.h" + +/**********************************************************************/ +/** \name PCI memory */ +/*@{*/ + +/** + * \brief Allocate a PCI consistent memory block, for DMA. + */ +void *drm_pci_alloc(drm_device_t * dev, size_t size, size_t align, + dma_addr_t maxaddr, dma_addr_t * busaddr) +{ + void *address; +#if DRM_DEBUG_MEMORY + int area = DRM_MEM_DMA; + + spin_lock(&drm_mem_lock); + if ((drm_ram_used >> PAGE_SHIFT) + > (DRM_RAM_PERCENT * drm_ram_available) / 100) { + spin_unlock(&drm_mem_lock); + return 0; + } + spin_unlock(&drm_mem_lock); +#endif + + /* pci_alloc_consistent only guarantees alignment to the smallest + * PAGE_SIZE order which is greater than or equal to the requested size. + * Return NULL here for now to make sure nobody tries for larger alignment + */ + if (align > size) + return NULL; + + if (pci_set_dma_mask(dev->pdev, maxaddr) != 0) { + DRM_ERROR("Setting pci dma mask failed\n"); + return NULL; + } + + address = pci_alloc_consistent(dev->pdev, size, busaddr); + +#if DRM_DEBUG_MEMORY + if (address == NULL) { + spin_lock(&drm_mem_lock); + ++drm_mem_stats[area].fail_count; + spin_unlock(&drm_mem_lock); + return NULL; + } + + spin_lock(&drm_mem_lock); + ++drm_mem_stats[area].succeed_count; + drm_mem_stats[area].bytes_allocated += size; + drm_ram_used += size; + spin_unlock(&drm_mem_lock); +#else + if (address == NULL) + return NULL; +#endif + + memset(address, 0, size); + + return address; +} +EXPORT_SYMBOL(drm_pci_alloc); + +/** + * \brief Free a PCI consistent memory block. + */ +void +drm_pci_free(drm_device_t * dev, size_t size, void *vaddr, dma_addr_t busaddr) +{ +#if DRM_DEBUG_MEMORY + int area = DRM_MEM_DMA; + int alloc_count; + int free_count; +#endif + + if (!vaddr) { +#if DRM_DEBUG_MEMORY + DRM_MEM_ERROR(area, "Attempt to free address 0\n"); +#endif + } else { + pci_free_consistent(dev->pdev, size, vaddr, busaddr); + } + +#if DRM_DEBUG_MEMORY + spin_lock(&drm_mem_lock); + free_count = ++drm_mem_stats[area].free_count; + alloc_count = drm_mem_stats[area].succeed_count; + drm_mem_stats[area].bytes_freed += size; + drm_ram_used -= size; + spin_unlock(&drm_mem_lock); + if (free_count > alloc_count) { + DRM_MEM_ERROR(area, + "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } +#endif + +} +EXPORT_SYMBOL(drm_pci_free); + +/*@}*/ diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h new file mode 100644 index 000000000000..54a2914e3a32 --- /dev/null +++ b/drivers/char/drm/drm_pciids.h @@ -0,0 +1,224 @@ +/* + This file is auto-generated from the drm_pciids.txt in the DRM CVS + Please contact dri-devel@lists.sf.net to add new cards to this list +*/ +#define radeon_PCI_IDS \ + {0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|CHIP_IS_IGP}, \ + {0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|CHIP_IS_IGP}, \ + {0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ + {0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ + {0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ + {0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ + {0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ + {0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ + {0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ + {0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ + {0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ + {0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ + {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS250|CHIP_IS_IGP}, \ + {0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY}, \ + {0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY}, \ + {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY}, \ + {0x1002, 0x4964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250}, \ + {0x1002, 0x4965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250}, \ + {0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250}, \ + {0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250}, \ + {0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|CHIP_IS_MOBILITY}, \ + {0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|CHIP_IS_MOBILITY}, \ + {0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|CHIP_IS_MOBILITY}, \ + {0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|CHIP_IS_MOBILITY}, \ + {0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250|CHIP_IS_MOBILITY}, \ + {0x1002, 0x4C65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250|CHIP_IS_MOBILITY}, \ + {0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250|CHIP_IS_MOBILITY}, \ + {0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250|CHIP_IS_MOBILITY}, \ + {0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|CHIP_IS_MOBILITY}, \ + {0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|CHIP_SINGLE_CRTC}, \ + {0x1002, 0x5145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|CHIP_SINGLE_CRTC}, \ + {0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|CHIP_SINGLE_CRTC}, \ + {0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|CHIP_SINGLE_CRTC}, \ + {0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x5149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x514A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x514B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x514E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x514F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ + {0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ + {0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ + {0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ + {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ + {0x1002, 0x5168, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x5169, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x516A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x516B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x516C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ + {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|CHIP_IS_IGP}, \ + {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY}, \ + {0x1002, 0x5836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|CHIP_IS_IGP}, \ + {0x1002, 0x5837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|CHIP_IS_IGP}, \ + {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ + {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ + {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ + {0x1002, 0x5963, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ + {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ + {0x1002, 0x5968, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ + {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ + {0x1002, 0x596A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ + {0x1002, 0x596B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ + {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|CHIP_IS_MOBILITY}, \ + {0x1002, 0x5c62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ + {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|CHIP_IS_MOBILITY}, \ + {0x1002, 0x5c64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ + {0, 0, 0} + +#define r128_PCI_IDS \ + {0x1002, 0x4c45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4c46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4d46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5041, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5042, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5043, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5044, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5045, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5046, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5047, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5048, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5049, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x504A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x504B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x504C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x504D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x504E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x504F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5052, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x524b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x524c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x534d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x544C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x5452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0, 0, 0} + +#define mga_PCI_IDS \ + {0x102b, 0x0521, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x102b, 0x0525, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x102b, 0x2527, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0, 0, 0} + +#define mach64_PCI_IDS \ + {0x1002, 0x4749, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4750, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4751, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4742, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4744, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4c49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4c50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4c51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4c42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4c44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x474c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x474f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4752, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4753, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x474d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x474e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4c52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4c53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4c4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1002, 0x4c4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0, 0, 0} + +#define sisdrv_PCI_IDS \ + {0x1039, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1039, 0x5300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1039, 0x6300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1039, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0, 0, 0} + +#define tdfx_PCI_IDS \ + {0x121a, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x121a, 0x0004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x121a, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x121a, 0x0007, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x121a, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x121a, 0x000b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0, 0, 0} + +#define viadrv_PCI_IDS \ + {0x1106, 0x3022, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1106, 0x3122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1106, 0x7205, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x1106, 0x7204, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0, 0, 0} + +#define i810_PCI_IDS \ + {0x8086, 0x7121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x8086, 0x7123, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x8086, 0x7125, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x8086, 0x1132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0, 0, 0} + +#define i830_PCI_IDS \ + {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0, 0, 0} + +#define gamma_PCI_IDS \ + {0x3d3d, 0x0008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0, 0, 0} + +#define savage_PCI_IDS \ + {0x5333, 0x8a22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8a23, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c13, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c24, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c2a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c2b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c2c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8c2f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8a25, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8d01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8d02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x5333, 0x8d04, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0, 0, 0} + +#define ffb_PCI_IDS \ + {0, 0, 0} + +#define i915_PCI_IDS \ + {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x8086, 0x2582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0, 0, 0} + diff --git a/drivers/char/drm/drm_proc.c b/drivers/char/drm/drm_proc.c new file mode 100644 index 000000000000..6e06e8c6a516 --- /dev/null +++ b/drivers/char/drm/drm_proc.c @@ -0,0 +1,539 @@ +/** + * \file drm_proc.h + * /proc support for DRM + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + * + * \par Acknowledgements: + * Matthew J Sottek sent in a patch to fix + * the problem with the proc files not outputting all their information. + */ + +/* + * Created: Mon Jan 11 09:48:47 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" + +static int drm_name_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +static int drm_vm_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +static int drm_clients_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +static int drm_queues_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +static int drm_bufs_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +#if DRM_DEBUG_CODE +static int drm_vma_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +#endif + +/** + * Proc file list. + */ +struct drm_proc_list { + const char *name; /**< file name */ + int (*f)(char *, char **, off_t, int, int *, void *); /**< proc callback*/ +} drm_proc_list[] = { + { "name", drm_name_info }, + { "mem", drm_mem_info }, + { "vm", drm_vm_info }, + { "clients", drm_clients_info }, + { "queues", drm_queues_info }, + { "bufs", drm_bufs_info }, +#if DRM_DEBUG_CODE + { "vma", drm_vma_info }, +#endif +}; +#define DRM_PROC_ENTRIES (sizeof(drm_proc_list)/sizeof(drm_proc_list[0])) + +/** + * Initialize the DRI proc filesystem for a device. + * + * \param dev DRM device. + * \param minor device minor number. + * \param root DRI proc dir entry. + * \param dev_root resulting DRI device proc dir entry. + * \return root entry pointer on success, or NULL on failure. + * + * Create the DRI proc root entry "/proc/dri", the device proc root entry + * "/proc/dri/%minor%/", and each entry in proc_list as + * "/proc/dri/%minor%/%name%". + */ +int drm_proc_init(drm_device_t *dev, int minor, + struct proc_dir_entry *root, + struct proc_dir_entry **dev_root) +{ + struct proc_dir_entry *ent; + int i, j; + char name[64]; + + sprintf(name, "%d", minor); + *dev_root = create_proc_entry(name, S_IFDIR, root); + if (!*dev_root) { + DRM_ERROR("Cannot create /proc/dri/%s\n", name); + return -1; + } + + for (i = 0; i < DRM_PROC_ENTRIES; i++) { + ent = create_proc_entry(drm_proc_list[i].name, + S_IFREG|S_IRUGO, *dev_root); + if (!ent) { + DRM_ERROR("Cannot create /proc/dri/%s/%s\n", + name, drm_proc_list[i].name); + for (j = 0; j < i; j++) + remove_proc_entry(drm_proc_list[i].name, + *dev_root); + remove_proc_entry(name, root); + return -1; + } + ent->read_proc = drm_proc_list[i].f; + ent->data = dev; + } + + return 0; +} + + +/** + * Cleanup the proc filesystem resources. + * + * \param minor device minor number. + * \param root DRI proc dir entry. + * \param dev_root DRI device proc dir entry. + * \return always zero. + * + * Remove all proc entries created by proc_init(). + */ +int drm_proc_cleanup(int minor, struct proc_dir_entry *root, + struct proc_dir_entry *dev_root) +{ + int i; + char name[64]; + + if (!root || !dev_root) return 0; + + for (i = 0; i < DRM_PROC_ENTRIES; i++) + remove_proc_entry(drm_proc_list[i].name, dev_root); + sprintf(name, "%d", minor); + remove_proc_entry(name, root); + + return 0; +} + +/** + * Called when "/proc/dri/.../name" is read. + * + * \param buf output buffer. + * \param start start of output data. + * \param offset requested start offset. + * \param request requested number of bytes. + * \param eof whether there is no more data to return. + * \param data private data. + * \return number of written bytes. + * + * Prints the device name together with the bus id if available. + */ +static int drm_name_info(char *buf, char **start, off_t offset, int request, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int len = 0; + + if (offset > DRM_PROC_LIMIT) { + *eof = 1; + return 0; + } + + *start = &buf[offset]; + *eof = 0; + + if (dev->unique) { + DRM_PROC_PRINT("%s %s %s\n", + dev->driver->pci_driver.name, pci_name(dev->pdev), dev->unique); + } else { + DRM_PROC_PRINT("%s %s\n", dev->driver->pci_driver.name, pci_name(dev->pdev)); + } + + if (len > request + offset) return request; + *eof = 1; + return len - offset; +} + +/** + * Called when "/proc/dri/.../vm" is read. + * + * \param buf output buffer. + * \param start start of output data. + * \param offset requested start offset. + * \param request requested number of bytes. + * \param eof whether there is no more data to return. + * \param data private data. + * \return number of written bytes. + * + * Prints information about all mappings in drm_device::maplist. + */ +static int drm__vm_info(char *buf, char **start, off_t offset, int request, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int len = 0; + drm_map_t *map; + drm_map_list_t *r_list; + struct list_head *list; + + /* Hardcoded from _DRM_FRAME_BUFFER, + _DRM_REGISTERS, _DRM_SHM, _DRM_AGP, and + _DRM_SCATTER_GATHER. */ + const char *types[] = { "FB", "REG", "SHM", "AGP", "SG" }; + const char *type; + int i; + + if (offset > DRM_PROC_LIMIT) { + *eof = 1; + return 0; + } + + *start = &buf[offset]; + *eof = 0; + + DRM_PROC_PRINT("slot offset size type flags " + "address mtrr\n\n"); + i = 0; + if (dev->maplist != NULL) list_for_each(list, &dev->maplist->head) { + r_list = list_entry(list, drm_map_list_t, head); + map = r_list->map; + if(!map) continue; + if (map->type < 0 || map->type > 4) type = "??"; + else type = types[map->type]; + DRM_PROC_PRINT("%4d 0x%08lx 0x%08lx %4.4s 0x%02x 0x%08lx ", + i, + map->offset, + map->size, + type, + map->flags, + (unsigned long)map->handle); + if (map->mtrr < 0) { + DRM_PROC_PRINT("none\n"); + } else { + DRM_PROC_PRINT("%4d\n", map->mtrr); + } + i++; + } + + if (len > request + offset) return request; + *eof = 1; + return len - offset; +} + +/** + * Simply calls _vm_info() while holding the drm_device::struct_sem lock. + */ +static int drm_vm_info(char *buf, char **start, off_t offset, int request, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int ret; + + down(&dev->struct_sem); + ret = drm__vm_info(buf, start, offset, request, eof, data); + up(&dev->struct_sem); + return ret; +} + +/** + * Called when "/proc/dri/.../queues" is read. + * + * \param buf output buffer. + * \param start start of output data. + * \param offset requested start offset. + * \param request requested number of bytes. + * \param eof whether there is no more data to return. + * \param data private data. + * \return number of written bytes. + */ +static int drm__queues_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int len = 0; + int i; + drm_queue_t *q; + + if (offset > DRM_PROC_LIMIT) { + *eof = 1; + return 0; + } + + *start = &buf[offset]; + *eof = 0; + + DRM_PROC_PRINT(" ctx/flags use fin" + " blk/rw/rwf wait flushed queued" + " locks\n\n"); + for (i = 0; i < dev->queue_count; i++) { + q = dev->queuelist[i]; + atomic_inc(&q->use_count); + DRM_PROC_PRINT_RET(atomic_dec(&q->use_count), + "%5d/0x%03x %5d %5d" + " %5d/%c%c/%c%c%c %5Zd\n", + i, + q->flags, + atomic_read(&q->use_count), + atomic_read(&q->finalization), + atomic_read(&q->block_count), + atomic_read(&q->block_read) ? 'r' : '-', + atomic_read(&q->block_write) ? 'w' : '-', + waitqueue_active(&q->read_queue) ? 'r':'-', + waitqueue_active(&q->write_queue) ? 'w':'-', + waitqueue_active(&q->flush_queue) ? 'f':'-', + DRM_BUFCOUNT(&q->waitlist)); + atomic_dec(&q->use_count); + } + + if (len > request + offset) return request; + *eof = 1; + return len - offset; +} + +/** + * Simply calls _queues_info() while holding the drm_device::struct_sem lock. + */ +static int drm_queues_info(char *buf, char **start, off_t offset, int request, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int ret; + + down(&dev->struct_sem); + ret = drm__queues_info(buf, start, offset, request, eof, data); + up(&dev->struct_sem); + return ret; +} + +/** + * Called when "/proc/dri/.../bufs" is read. + * + * \param buf output buffer. + * \param start start of output data. + * \param offset requested start offset. + * \param request requested number of bytes. + * \param eof whether there is no more data to return. + * \param data private data. + * \return number of written bytes. + */ +static int drm__bufs_info(char *buf, char **start, off_t offset, int request, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int len = 0; + drm_device_dma_t *dma = dev->dma; + int i; + + if (!dma || offset > DRM_PROC_LIMIT) { + *eof = 1; + return 0; + } + + *start = &buf[offset]; + *eof = 0; + + DRM_PROC_PRINT(" o size count free segs pages kB\n\n"); + for (i = 0; i <= DRM_MAX_ORDER; i++) { + if (dma->bufs[i].buf_count) + DRM_PROC_PRINT("%2d %8d %5d %5d %5d %5d %5ld\n", + i, + dma->bufs[i].buf_size, + dma->bufs[i].buf_count, + atomic_read(&dma->bufs[i] + .freelist.count), + dma->bufs[i].seg_count, + dma->bufs[i].seg_count + *(1 << dma->bufs[i].page_order), + (dma->bufs[i].seg_count + * (1 << dma->bufs[i].page_order)) + * PAGE_SIZE / 1024); + } + DRM_PROC_PRINT("\n"); + for (i = 0; i < dma->buf_count; i++) { + if (i && !(i%32)) DRM_PROC_PRINT("\n"); + DRM_PROC_PRINT(" %d", dma->buflist[i]->list); + } + DRM_PROC_PRINT("\n"); + + if (len > request + offset) return request; + *eof = 1; + return len - offset; +} + +/** + * Simply calls _bufs_info() while holding the drm_device::struct_sem lock. + */ +static int drm_bufs_info(char *buf, char **start, off_t offset, int request, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int ret; + + down(&dev->struct_sem); + ret = drm__bufs_info(buf, start, offset, request, eof, data); + up(&dev->struct_sem); + return ret; +} + +/** + * Called when "/proc/dri/.../clients" is read. + * + * \param buf output buffer. + * \param start start of output data. + * \param offset requested start offset. + * \param request requested number of bytes. + * \param eof whether there is no more data to return. + * \param data private data. + * \return number of written bytes. + */ +static int drm__clients_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int len = 0; + drm_file_t *priv; + + if (offset > DRM_PROC_LIMIT) { + *eof = 1; + return 0; + } + + *start = &buf[offset]; + *eof = 0; + + DRM_PROC_PRINT("a dev pid uid magic ioctls\n\n"); + for (priv = dev->file_first; priv; priv = priv->next) { + DRM_PROC_PRINT("%c %3d %5d %5d %10u %10lu\n", + priv->authenticated ? 'y' : 'n', + priv->minor, + priv->pid, + priv->uid, + priv->magic, + priv->ioctl_count); + } + + if (len > request + offset) return request; + *eof = 1; + return len - offset; +} + +/** + * Simply calls _clients_info() while holding the drm_device::struct_sem lock. + */ +static int drm_clients_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int ret; + + down(&dev->struct_sem); + ret = drm__clients_info(buf, start, offset, request, eof, data); + up(&dev->struct_sem); + return ret; +} + +#if DRM_DEBUG_CODE + +static int drm__vma_info(char *buf, char **start, off_t offset, int request, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int len = 0; + drm_vma_entry_t *pt; + struct vm_area_struct *vma; +#if defined(__i386__) + unsigned int pgprot; +#endif + + if (offset > DRM_PROC_LIMIT) { + *eof = 1; + return 0; + } + + *start = &buf[offset]; + *eof = 0; + + DRM_PROC_PRINT("vma use count: %d, high_memory = %p, 0x%08lx\n", + atomic_read(&dev->vma_count), + high_memory, virt_to_phys(high_memory)); + for (pt = dev->vmalist; pt; pt = pt->next) { + if (!(vma = pt->vma)) continue; + DRM_PROC_PRINT("\n%5d 0x%08lx-0x%08lx %c%c%c%c%c%c 0x%08lx", + pt->pid, + vma->vm_start, + vma->vm_end, + vma->vm_flags & VM_READ ? 'r' : '-', + vma->vm_flags & VM_WRITE ? 'w' : '-', + vma->vm_flags & VM_EXEC ? 'x' : '-', + vma->vm_flags & VM_MAYSHARE ? 's' : 'p', + vma->vm_flags & VM_LOCKED ? 'l' : '-', + vma->vm_flags & VM_IO ? 'i' : '-', + VM_OFFSET(vma)); + +#if defined(__i386__) + pgprot = pgprot_val(vma->vm_page_prot); + DRM_PROC_PRINT(" %c%c%c%c%c%c%c%c%c", + pgprot & _PAGE_PRESENT ? 'p' : '-', + pgprot & _PAGE_RW ? 'w' : 'r', + pgprot & _PAGE_USER ? 'u' : 's', + pgprot & _PAGE_PWT ? 't' : 'b', + pgprot & _PAGE_PCD ? 'u' : 'c', + pgprot & _PAGE_ACCESSED ? 'a' : '-', + pgprot & _PAGE_DIRTY ? 'd' : '-', + pgprot & _PAGE_PSE ? 'm' : 'k', + pgprot & _PAGE_GLOBAL ? 'g' : 'l' ); +#endif + DRM_PROC_PRINT("\n"); + } + + if (len > request + offset) return request; + *eof = 1; + return len - offset; +} + +static int drm_vma_info(char *buf, char **start, off_t offset, int request, + int *eof, void *data) +{ + drm_device_t *dev = (drm_device_t *)data; + int ret; + + down(&dev->struct_sem); + ret = drm__vma_info(buf, start, offset, request, eof, data); + up(&dev->struct_sem); + return ret; +} +#endif + + diff --git a/drivers/char/drm/drm_sarea.h b/drivers/char/drm/drm_sarea.h new file mode 100644 index 000000000000..de782ed2f03a --- /dev/null +++ b/drivers/char/drm/drm_sarea.h @@ -0,0 +1,78 @@ +/** + * \file drm_sarea.h + * \brief SAREA definitions + * + * \author Michel Dänzer + */ + +/* + * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DRM_SAREA_H_ +#define _DRM_SAREA_H_ + +#include "drm.h" + +/* SAREA area needs to be at least a page */ +#if defined(__alpha__) +#define SAREA_MAX 0x2000 +#elif defined(__ia64__) +#define SAREA_MAX 0x10000 /* 64kB */ +#else +/* Intel 830M driver needs at least 8k SAREA */ +#define SAREA_MAX 0x2000 +#endif + +/** Maximum number of drawables in the SAREA */ +#define SAREA_MAX_DRAWABLES 256 + +#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000 + +/** SAREA drawable */ +typedef struct drm_sarea_drawable { + unsigned int stamp; + unsigned int flags; +} drm_sarea_drawable_t; + +/** SAREA frame */ +typedef struct drm_sarea_frame { + unsigned int x; + unsigned int y; + unsigned int width; + unsigned int height; + unsigned int fullscreen; +} drm_sarea_frame_t; + +/** SAREA */ +typedef struct drm_sarea { + /** first thing is always the DRM locking structure */ + drm_hw_lock_t lock; + /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ + drm_hw_lock_t drawable_lock; + drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ + drm_sarea_frame_t frame; /**< frame */ + drm_context_t dummy_context; +} drm_sarea_t; + +#endif /* _DRM_SAREA_H_ */ diff --git a/drivers/char/drm/drm_scatter.c b/drivers/char/drm/drm_scatter.c new file mode 100644 index 000000000000..54fddb6ea2d1 --- /dev/null +++ b/drivers/char/drm/drm_scatter.c @@ -0,0 +1,231 @@ +/** + * \file drm_scatter.h + * IOCTLs to manage scatter/gather memory + * + * \author Gareth Hughes + */ + +/* + * Created: Mon Dec 18 23:20:54 2000 by gareth@valinux.com + * + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "drmP.h" + +#define DEBUG_SCATTER 0 + +void drm_sg_cleanup( drm_sg_mem_t *entry ) +{ + struct page *page; + int i; + + for ( i = 0 ; i < entry->pages ; i++ ) { + page = entry->pagelist[i]; + if ( page ) + ClearPageReserved( page ); + } + + vfree( entry->virtual ); + + drm_free( entry->busaddr, + entry->pages * sizeof(*entry->busaddr), + DRM_MEM_PAGES ); + drm_free( entry->pagelist, + entry->pages * sizeof(*entry->pagelist), + DRM_MEM_PAGES ); + drm_free( entry, + sizeof(*entry), + DRM_MEM_SGLISTS ); +} + +int drm_sg_alloc( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_scatter_gather_t __user *argp = (void __user *)arg; + drm_scatter_gather_t request; + drm_sg_mem_t *entry; + unsigned long pages, i, j; + + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if (!drm_core_check_feature(dev, DRIVER_SG)) + return -EINVAL; + + if ( dev->sg ) + return -EINVAL; + + if ( copy_from_user( &request, argp, sizeof(request) ) ) + return -EFAULT; + + entry = drm_alloc( sizeof(*entry), DRM_MEM_SGLISTS ); + if ( !entry ) + return -ENOMEM; + + memset( entry, 0, sizeof(*entry) ); + + pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE; + DRM_DEBUG( "sg size=%ld pages=%ld\n", request.size, pages ); + + entry->pages = pages; + entry->pagelist = drm_alloc( pages * sizeof(*entry->pagelist), + DRM_MEM_PAGES ); + if ( !entry->pagelist ) { + drm_free( entry, sizeof(*entry), DRM_MEM_SGLISTS ); + return -ENOMEM; + } + + memset(entry->pagelist, 0, pages * sizeof(*entry->pagelist)); + + entry->busaddr = drm_alloc( pages * sizeof(*entry->busaddr), + DRM_MEM_PAGES ); + if ( !entry->busaddr ) { + drm_free( entry->pagelist, + entry->pages * sizeof(*entry->pagelist), + DRM_MEM_PAGES ); + drm_free( entry, + sizeof(*entry), + DRM_MEM_SGLISTS ); + return -ENOMEM; + } + memset( (void *)entry->busaddr, 0, pages * sizeof(*entry->busaddr) ); + + entry->virtual = vmalloc_32( pages << PAGE_SHIFT ); + if ( !entry->virtual ) { + drm_free( entry->busaddr, + entry->pages * sizeof(*entry->busaddr), + DRM_MEM_PAGES ); + drm_free( entry->pagelist, + entry->pages * sizeof(*entry->pagelist), + DRM_MEM_PAGES ); + drm_free( entry, + sizeof(*entry), + DRM_MEM_SGLISTS ); + return -ENOMEM; + } + + /* This also forces the mapping of COW pages, so our page list + * will be valid. Please don't remove it... + */ + memset( entry->virtual, 0, pages << PAGE_SHIFT ); + + entry->handle = (unsigned long)entry->virtual; + + DRM_DEBUG( "sg alloc handle = %08lx\n", entry->handle ); + DRM_DEBUG( "sg alloc virtual = %p\n", entry->virtual ); + + for ( i = entry->handle, j = 0 ; j < pages ; i += PAGE_SIZE, j++ ) { + entry->pagelist[j] = vmalloc_to_page((void *)i); + if (!entry->pagelist[j]) + goto failed; + SetPageReserved(entry->pagelist[j]); + } + + request.handle = entry->handle; + + if ( copy_to_user( argp, &request, sizeof(request) ) ) { + drm_sg_cleanup( entry ); + return -EFAULT; + } + + dev->sg = entry; + +#if DEBUG_SCATTER + /* Verify that each page points to its virtual address, and vice + * versa. + */ + { + int error = 0; + + for ( i = 0 ; i < pages ; i++ ) { + unsigned long *tmp; + + tmp = page_address( entry->pagelist[i] ); + for ( j = 0 ; + j < PAGE_SIZE / sizeof(unsigned long) ; + j++, tmp++ ) { + *tmp = 0xcafebabe; + } + tmp = (unsigned long *)((u8 *)entry->virtual + + (PAGE_SIZE * i)); + for( j = 0 ; + j < PAGE_SIZE / sizeof(unsigned long) ; + j++, tmp++ ) { + if ( *tmp != 0xcafebabe && error == 0 ) { + error = 1; + DRM_ERROR( "Scatter allocation error, " + "pagelist does not match " + "virtual mapping\n" ); + } + } + tmp = page_address( entry->pagelist[i] ); + for(j = 0 ; + j < PAGE_SIZE / sizeof(unsigned long) ; + j++, tmp++) { + *tmp = 0; + } + } + if (error == 0) + DRM_ERROR( "Scatter allocation matches pagelist\n" ); + } +#endif + + return 0; + + failed: + drm_sg_cleanup( entry ); + return -ENOMEM; +} + +int drm_sg_free( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_scatter_gather_t request; + drm_sg_mem_t *entry; + + if (!drm_core_check_feature(dev, DRIVER_SG)) + return -EINVAL; + + if ( copy_from_user( &request, + (drm_scatter_gather_t __user *)arg, + sizeof(request) ) ) + return -EFAULT; + + entry = dev->sg; + dev->sg = NULL; + + if ( !entry || entry->handle != request.handle ) + return -EINVAL; + + DRM_DEBUG( "sg free virtual = %p\n", entry->virtual ); + + drm_sg_cleanup( entry ); + + return 0; +} diff --git a/drivers/char/drm/drm_stub.c b/drivers/char/drm/drm_stub.c new file mode 100644 index 000000000000..8ccbdef7bb3e --- /dev/null +++ b/drivers/char/drm/drm_stub.c @@ -0,0 +1,319 @@ +/** + * \file drm_stub.h + * Stub support + * + * \author Rickard E. (Rik) Faith + */ + +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "drmP.h" +#include "drm_core.h" + +unsigned int drm_cards_limit = 16; /* Enough for one machine */ +unsigned int drm_debug = 0; /* 1 to enable debug output */ +EXPORT_SYMBOL(drm_debug); + +MODULE_AUTHOR( CORE_AUTHOR ); +MODULE_DESCRIPTION( CORE_DESC ); +MODULE_LICENSE("GPL and additional rights"); +MODULE_PARM_DESC(cards_limit, "Maximum number of graphics cards"); +MODULE_PARM_DESC(debug, "Enable debug output"); + +module_param_named(cards_limit, drm_cards_limit, int, 0444); +module_param_named(debug, drm_debug, int, 0666); + +drm_head_t **drm_heads; +struct drm_sysfs_class *drm_class; +struct proc_dir_entry *drm_proc_root; + +static int drm_fill_in_dev(drm_device_t *dev, struct pci_dev *pdev, const struct pci_device_id *ent, struct drm_driver *driver) +{ + int retcode; + + spin_lock_init(&dev->count_lock); + init_timer( &dev->timer ); + sema_init( &dev->struct_sem, 1 ); + sema_init( &dev->ctxlist_sem, 1 ); + + dev->pdev = pdev; + +#ifdef __alpha__ + dev->hose = pdev->sysdata; + dev->pci_domain = dev->hose->bus->number; +#else + dev->pci_domain = 0; +#endif + dev->pci_bus = pdev->bus->number; + dev->pci_slot = PCI_SLOT(pdev->devfn); + dev->pci_func = PCI_FUNC(pdev->devfn); + dev->irq = pdev->irq; + + /* the DRM has 6 basic counters */ + dev->counters = 6; + dev->types[0] = _DRM_STAT_LOCK; + dev->types[1] = _DRM_STAT_OPENS; + dev->types[2] = _DRM_STAT_CLOSES; + dev->types[3] = _DRM_STAT_IOCTLS; + dev->types[4] = _DRM_STAT_LOCKS; + dev->types[5] = _DRM_STAT_UNLOCKS; + + dev->driver = driver; + + if (dev->driver->preinit) + if ((retcode = dev->driver->preinit(dev, ent->driver_data))) + goto error_out_unreg; + + if (drm_core_has_AGP(dev)) { + dev->agp = drm_agp_init(dev); + if (drm_core_check_feature(dev, DRIVER_REQUIRE_AGP) && (dev->agp == NULL)) { + DRM_ERROR( "Cannot initialize the agpgart module.\n" ); + retcode = -EINVAL; + goto error_out_unreg; + } + if (drm_core_has_MTRR(dev)) { + if (dev->agp) + dev->agp->agp_mtrr = mtrr_add( dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size*1024*1024, + MTRR_TYPE_WRCOMB, + 1 ); + } + } + + retcode = drm_ctxbitmap_init( dev ); + if( retcode ) { + DRM_ERROR( "Cannot allocate memory for context bitmap.\n" ); + goto error_out_unreg; + } + + return 0; + +error_out_unreg: + drm_takedown(dev); + return retcode; +} + +/** + * File \c open operation. + * + * \param inode device inode. + * \param filp file pointer. + * + * Puts the dev->fops corresponding to the device minor number into + * \p filp, call the \c open method, and restore the file operations. + */ +int drm_stub_open(struct inode *inode, struct file *filp) +{ + drm_device_t *dev = NULL; + int minor = iminor(inode); + int err = -ENODEV; + struct file_operations *old_fops; + + DRM_DEBUG("\n"); + + if (!((minor >= 0) && (minor < drm_cards_limit))) + return -ENODEV; + + if (!drm_heads[minor]) + return -ENODEV; + + if (!(dev = drm_heads[minor]->dev)) + return -ENODEV; + + old_fops = filp->f_op; + filp->f_op = fops_get(&dev->driver->fops); + if (filp->f_op->open && (err = filp->f_op->open(inode, filp))) { + fops_put(filp->f_op); + filp->f_op = fops_get(old_fops); + } + fops_put(old_fops); + + return err; +} + + +/** + * Register. + * + * \param pdev - PCI device structure + * \param ent entry from the PCI ID table with device type flags + * \return zero on success or a negative number on failure. + * + * Attempt to gets inter module "drm" information. If we are first + * then register the character device and inter module information. + * Try and register, if we fail to register, backout previous work. + */ +int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent, + struct drm_driver *driver) +{ + drm_device_t *dev; + int ret; + + DRM_DEBUG("\n"); + + dev = drm_calloc(1, sizeof(*dev), DRM_MEM_STUB); + if (!dev) + return -ENOMEM; + + pci_enable_device(pdev); + + if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { + printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); + goto err_g1; + } + if ((ret = drm_get_head(dev, &dev->primary))) + goto err_g1; + + /* postinit is a required function to display the signon banner */ + /* drivers add secondary heads here if needed */ + if ((ret = dev->driver->postinit(dev, ent->driver_data))) + goto err_g1; + + return 0; + +err_g1: + drm_free(dev, sizeof(*dev), DRM_MEM_STUB); + return ret; +} +EXPORT_SYMBOL(drm_get_dev); + +/** + * Get a secondary minor number. + * + * \param dev device data structure + * \param sec-minor structure to hold the assigned minor + * \return negative number on failure. + * + * Search an empty entry and initialize it to the given parameters, and + * create the proc init entry via proc_init(). This routines assigns + * minor numbers to secondary heads of multi-headed cards + */ +int drm_get_head(drm_device_t *dev, drm_head_t *head) +{ + drm_head_t **heads = drm_heads; + int ret; + int minor; + + DRM_DEBUG("\n"); + + for (minor = 0; minor < drm_cards_limit; minor++, heads++) { + if (!*heads) { + + *head = (drm_head_t) { + .dev = dev, + .device = MKDEV(DRM_MAJOR, minor), + .minor = minor, + }; + + if ((ret = drm_proc_init(dev, minor, drm_proc_root, &head->dev_root))) { + printk (KERN_ERR "DRM: Failed to initialize /proc/dri.\n"); + goto err_g1; + } + + + head->dev_class = drm_sysfs_device_add(drm_class, + MKDEV(DRM_MAJOR, + minor), + &dev->pdev->dev, + "card%d", minor); + if (IS_ERR(head->dev_class)) { + printk(KERN_ERR "DRM: Error sysfs_device_add.\n"); + ret = PTR_ERR(head->dev_class); + goto err_g2; + } + *heads = head; + + DRM_DEBUG("new minor assigned %d\n", minor); + return 0; + } + } + DRM_ERROR("out of minors\n"); + return -ENOMEM; +err_g2: + drm_proc_cleanup(minor, drm_proc_root, head->dev_root); +err_g1: + *head = (drm_head_t) {.dev = NULL}; + return ret; +} + + +/** + * Put a device minor number. + * + * \param dev device data structure + * \return always zero + * + * Cleans up the proc resources. If it is the last minor then release the foreign + * "drm" data, otherwise unregisters the "drm" data, frees the dev list and + * unregisters the character device. + */ +int drm_put_dev(drm_device_t * dev) +{ + DRM_DEBUG("release primary %s\n", dev->driver->pci_driver.name); + + if (dev->unique) { + drm_free(dev->unique, strlen(dev->unique) + 1, DRM_MEM_DRIVER); + dev->unique = NULL; + dev->unique_len = 0; + } + if (dev->devname) { + drm_free(dev->devname, strlen(dev->devname) + 1, + DRM_MEM_DRIVER); + dev->devname = NULL; + } + drm_free(dev, sizeof(*dev), DRM_MEM_STUB); + return 0; +} + +/** + * Put a secondary minor number. + * + * \param sec_minor - structure to be released + * \return always zero + * + * Cleans up the proc resources. Not legal for this to be the + * last minor released. + * + */ +int drm_put_head(drm_head_t *head) +{ + int minor = head->minor; + + DRM_DEBUG("release secondary minor %d\n", minor); + + drm_proc_cleanup(minor, drm_proc_root, head->dev_root); + drm_sysfs_device_remove(MKDEV(DRM_MAJOR, head->minor)); + + *head = (drm_head_t){.dev = NULL}; + + drm_heads[minor] = NULL; + + return 0; +} + diff --git a/drivers/char/drm/drm_sysfs.c b/drivers/char/drm/drm_sysfs.c new file mode 100644 index 000000000000..2fc10c4bbcdf --- /dev/null +++ b/drivers/char/drm/drm_sysfs.c @@ -0,0 +1,208 @@ +/* + * drm_sysfs.c - Modifications to drm_sysfs_class.c to support + * extra sysfs attribute from DRM. Normal drm_sysfs_class + * does not allow adding attributes. + * + * Copyright (c) 2004 Jon Smirl + * Copyright (c) 2003-2004 Greg Kroah-Hartman + * Copyright (c) 2003-2004 IBM Corp. + * + * This file is released under the GPLv2 + * + */ + +#include +#include +#include +#include + +#include "drm_core.h" + +struct drm_sysfs_class { + struct class_device_attribute attr; + struct class class; +}; +#define to_drm_sysfs_class(d) container_of(d, struct drm_sysfs_class, class) + +struct simple_dev { + struct list_head node; + dev_t dev; + struct class_device class_dev; +}; +#define to_simple_dev(d) container_of(d, struct simple_dev, class_dev) + +static LIST_HEAD(simple_dev_list); +static DEFINE_SPINLOCK(simple_dev_list_lock); + +static void release_simple_dev(struct class_device *class_dev) +{ + struct simple_dev *s_dev = to_simple_dev(class_dev); + kfree(s_dev); +} + +static ssize_t show_dev(struct class_device *class_dev, char *buf) +{ + struct simple_dev *s_dev = to_simple_dev(class_dev); + return print_dev_t(buf, s_dev->dev); +} + +static void drm_sysfs_class_release(struct class *class) +{ + struct drm_sysfs_class *cs = to_drm_sysfs_class(class); + kfree(cs); +} + +/* Display the version of drm_core. This doesn't work right in current design */ +static ssize_t version_show(struct class *dev, char *buf) +{ + return sprintf(buf, "%s %d.%d.%d %s\n", CORE_NAME, CORE_MAJOR, + CORE_MINOR, CORE_PATCHLEVEL, CORE_DATE); +} + +static CLASS_ATTR(version, S_IRUGO, version_show, NULL); + +/** + * drm_sysfs_create - create a struct drm_sysfs_class structure + * @owner: pointer to the module that is to "own" this struct drm_sysfs_class + * @name: pointer to a string for the name of this class. + * + * This is used to create a struct drm_sysfs_class pointer that can then be used + * in calls to drm_sysfs_device_add(). + * + * Note, the pointer created here is to be destroyed when finished by making a + * call to drm_sysfs_destroy(). + */ +struct drm_sysfs_class *drm_sysfs_create(struct module *owner, char *name) +{ + struct drm_sysfs_class *cs; + int retval; + + cs = kmalloc(sizeof(*cs), GFP_KERNEL); + if (!cs) { + retval = -ENOMEM; + goto error; + } + memset(cs, 0x00, sizeof(*cs)); + + cs->class.name = name; + cs->class.class_release = drm_sysfs_class_release; + cs->class.release = release_simple_dev; + + cs->attr.attr.name = "dev"; + cs->attr.attr.mode = S_IRUGO; + cs->attr.attr.owner = owner; + cs->attr.show = show_dev; + cs->attr.store = NULL; + + retval = class_register(&cs->class); + if (retval) + goto error; + class_create_file(&cs->class, &class_attr_version); + + return cs; + + error: + kfree(cs); + return ERR_PTR(retval); +} + +/** + * drm_sysfs_destroy - destroys a struct drm_sysfs_class structure + * @cs: pointer to the struct drm_sysfs_class that is to be destroyed + * + * Note, the pointer to be destroyed must have been created with a call to + * drm_sysfs_create(). + */ +void drm_sysfs_destroy(struct drm_sysfs_class *cs) +{ + if ((cs == NULL) || (IS_ERR(cs))) + return; + + class_unregister(&cs->class); +} + +/** + * drm_sysfs_device_add - adds a class device to sysfs for a character driver + * @cs: pointer to the struct drm_sysfs_class that this device should be registered to. + * @dev: the dev_t for the device to be added. + * @device: a pointer to a struct device that is assiociated with this class device. + * @fmt: string for the class device's name + * + * A struct class_device will be created in sysfs, registered to the specified + * class. A "dev" file will be created, showing the dev_t for the device. The + * pointer to the struct class_device will be returned from the call. Any further + * sysfs files that might be required can be created using this pointer. + * Note: the struct drm_sysfs_class passed to this function must have previously been + * created with a call to drm_sysfs_create(). + */ +struct class_device *drm_sysfs_device_add(struct drm_sysfs_class *cs, dev_t dev, + struct device *device, + const char *fmt, ...) +{ + va_list args; + struct simple_dev *s_dev = NULL; + int retval; + + if ((cs == NULL) || (IS_ERR(cs))) { + retval = -ENODEV; + goto error; + } + + s_dev = kmalloc(sizeof(*s_dev), GFP_KERNEL); + if (!s_dev) { + retval = -ENOMEM; + goto error; + } + memset(s_dev, 0x00, sizeof(*s_dev)); + + s_dev->dev = dev; + s_dev->class_dev.dev = device; + s_dev->class_dev.class = &cs->class; + + va_start(args, fmt); + vsnprintf(s_dev->class_dev.class_id, BUS_ID_SIZE, fmt, args); + va_end(args); + retval = class_device_register(&s_dev->class_dev); + if (retval) + goto error; + + class_device_create_file(&s_dev->class_dev, &cs->attr); + + spin_lock(&simple_dev_list_lock); + list_add(&s_dev->node, &simple_dev_list); + spin_unlock(&simple_dev_list_lock); + + return &s_dev->class_dev; + + error: + kfree(s_dev); + return ERR_PTR(retval); +} + +/** + * drm_sysfs_device_remove - removes a class device that was created with drm_sysfs_device_add() + * @dev: the dev_t of the device that was previously registered. + * + * This call unregisters and cleans up a class device that was created with a + * call to drm_sysfs_device_add() + */ +void drm_sysfs_device_remove(dev_t dev) +{ + struct simple_dev *s_dev = NULL; + int found = 0; + + spin_lock(&simple_dev_list_lock); + list_for_each_entry(s_dev, &simple_dev_list, node) { + if (s_dev->dev == dev) { + found = 1; + break; + } + } + if (found) { + list_del(&s_dev->node); + spin_unlock(&simple_dev_list_lock); + class_device_unregister(&s_dev->class_dev); + } else { + spin_unlock(&simple_dev_list_lock); + } +} diff --git a/drivers/char/drm/drm_vm.c b/drivers/char/drm/drm_vm.c new file mode 100644 index 000000000000..fc72f30f312b --- /dev/null +++ b/drivers/char/drm/drm_vm.c @@ -0,0 +1,678 @@ +/** + * \file drm_vm.h + * Memory mapping for DRM + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Mon Jan 4 08:58:31 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "drmP.h" +#if defined(__ia64__) +#include +#endif + + +/** + * \c nopage method for AGP virtual memory. + * + * \param vma virtual memory area. + * \param address access address. + * \return pointer to the page structure. + * + * Find the right map and if it's AGP memory find the real physical page to + * map, get the page, increment the use count and return it. + */ +#if __OS_HAS_AGP +static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma, + unsigned long address) +{ + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->head->dev; + drm_map_t *map = NULL; + drm_map_list_t *r_list; + struct list_head *list; + + /* + * Find the right map + */ + if (!drm_core_has_AGP(dev)) + goto vm_nopage_error; + + if(!dev->agp || !dev->agp->cant_use_aperture) goto vm_nopage_error; + + list_for_each(list, &dev->maplist->head) { + r_list = list_entry(list, drm_map_list_t, head); + map = r_list->map; + if (!map) continue; + if (map->offset == VM_OFFSET(vma)) break; + } + + if (map && map->type == _DRM_AGP) { + unsigned long offset = address - vma->vm_start; + unsigned long baddr = VM_OFFSET(vma) + offset; + struct drm_agp_mem *agpmem; + struct page *page; + +#ifdef __alpha__ + /* + * Adjust to a bus-relative address + */ + baddr -= dev->hose->mem_space->start; +#endif + + /* + * It's AGP memory - find the real physical page to map + */ + for(agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) { + if (agpmem->bound <= baddr && + agpmem->bound + agpmem->pages * PAGE_SIZE > baddr) + break; + } + + if (!agpmem) goto vm_nopage_error; + + /* + * Get the page, inc the use count, and return it + */ + offset = (baddr - agpmem->bound) >> PAGE_SHIFT; + page = virt_to_page(__va(agpmem->memory->memory[offset])); + get_page(page); + + DRM_DEBUG("baddr = 0x%lx page = 0x%p, offset = 0x%lx, count=%d\n", + baddr, __va(agpmem->memory->memory[offset]), offset, + page_count(page)); + + return page; + } +vm_nopage_error: + return NOPAGE_SIGBUS; /* Disallow mremap */ +} +#else /* __OS_HAS_AGP */ +static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma, + unsigned long address) +{ + return NOPAGE_SIGBUS; +} +#endif /* __OS_HAS_AGP */ + +/** + * \c nopage method for shared virtual memory. + * + * \param vma virtual memory area. + * \param address access address. + * \return pointer to the page structure. + * + * Get the the mapping, find the real physical page to map, get the page, and + * return it. + */ +static __inline__ struct page *drm_do_vm_shm_nopage(struct vm_area_struct *vma, + unsigned long address) +{ + drm_map_t *map = (drm_map_t *)vma->vm_private_data; + unsigned long offset; + unsigned long i; + struct page *page; + + if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ + if (!map) return NOPAGE_OOM; /* Nothing allocated */ + + offset = address - vma->vm_start; + i = (unsigned long)map->handle + offset; + page = vmalloc_to_page((void *)i); + if (!page) + return NOPAGE_OOM; + get_page(page); + + DRM_DEBUG("shm_nopage 0x%lx\n", address); + return page; +} + + +/** + * \c close method for shared virtual memory. + * + * \param vma virtual memory area. + * + * Deletes map information if we are the last + * person to close a mapping and it's not in the global maplist. + */ +void drm_vm_shm_close(struct vm_area_struct *vma) +{ + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->head->dev; + drm_vma_entry_t *pt, *prev, *next; + drm_map_t *map; + drm_map_list_t *r_list; + struct list_head *list; + int found_maps = 0; + + DRM_DEBUG("0x%08lx,0x%08lx\n", + vma->vm_start, vma->vm_end - vma->vm_start); + atomic_dec(&dev->vma_count); + + map = vma->vm_private_data; + + down(&dev->struct_sem); + for (pt = dev->vmalist, prev = NULL; pt; pt = next) { + next = pt->next; + if (pt->vma->vm_private_data == map) found_maps++; + if (pt->vma == vma) { + if (prev) { + prev->next = pt->next; + } else { + dev->vmalist = pt->next; + } + drm_free(pt, sizeof(*pt), DRM_MEM_VMAS); + } else { + prev = pt; + } + } + /* We were the only map that was found */ + if(found_maps == 1 && + map->flags & _DRM_REMOVABLE) { + /* Check to see if we are in the maplist, if we are not, then + * we delete this mappings information. + */ + found_maps = 0; + list = &dev->maplist->head; + list_for_each(list, &dev->maplist->head) { + r_list = list_entry(list, drm_map_list_t, head); + if (r_list->map == map) found_maps++; + } + + if(!found_maps) { + switch (map->type) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: + if (drm_core_has_MTRR(dev) && map->mtrr >= 0) { + int retcode; + retcode = mtrr_del(map->mtrr, + map->offset, + map->size); + DRM_DEBUG("mtrr_del = %d\n", retcode); + } + drm_ioremapfree(map->handle, map->size, dev); + break; + case _DRM_SHM: + vfree(map->handle); + break; + case _DRM_AGP: + case _DRM_SCATTER_GATHER: + break; + } + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + } + } + up(&dev->struct_sem); +} + +/** + * \c nopage method for DMA virtual memory. + * + * \param vma virtual memory area. + * \param address access address. + * \return pointer to the page structure. + * + * Determine the page number from the page offset and get it from drm_device_dma::pagelist. + */ +static __inline__ struct page *drm_do_vm_dma_nopage(struct vm_area_struct *vma, + unsigned long address) +{ + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->head->dev; + drm_device_dma_t *dma = dev->dma; + unsigned long offset; + unsigned long page_nr; + struct page *page; + + if (!dma) return NOPAGE_SIGBUS; /* Error */ + if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ + if (!dma->pagelist) return NOPAGE_OOM ; /* Nothing allocated */ + + offset = address - vma->vm_start; /* vm_[pg]off[set] should be 0 */ + page_nr = offset >> PAGE_SHIFT; + page = virt_to_page((dma->pagelist[page_nr] + + (offset & (~PAGE_MASK)))); + + get_page(page); + + DRM_DEBUG("dma_nopage 0x%lx (page %lu)\n", address, page_nr); + return page; +} + +/** + * \c nopage method for scatter-gather virtual memory. + * + * \param vma virtual memory area. + * \param address access address. + * \return pointer to the page structure. + * + * Determine the map offset from the page offset and get it from drm_sg_mem::pagelist. + */ +static __inline__ struct page *drm_do_vm_sg_nopage(struct vm_area_struct *vma, + unsigned long address) +{ + drm_map_t *map = (drm_map_t *)vma->vm_private_data; + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->head->dev; + drm_sg_mem_t *entry = dev->sg; + unsigned long offset; + unsigned long map_offset; + unsigned long page_offset; + struct page *page; + + if (!entry) return NOPAGE_SIGBUS; /* Error */ + if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ + if (!entry->pagelist) return NOPAGE_OOM ; /* Nothing allocated */ + + + offset = address - vma->vm_start; + map_offset = map->offset - dev->sg->handle; + page_offset = (offset >> PAGE_SHIFT) + (map_offset >> PAGE_SHIFT); + page = entry->pagelist[page_offset]; + get_page(page); + + return page; +} + + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + +static struct page *drm_vm_nopage(struct vm_area_struct *vma, + unsigned long address, + int *type) { + if (type) *type = VM_FAULT_MINOR; + return drm_do_vm_nopage(vma, address); +} + +static struct page *drm_vm_shm_nopage(struct vm_area_struct *vma, + unsigned long address, + int *type) { + if (type) *type = VM_FAULT_MINOR; + return drm_do_vm_shm_nopage(vma, address); +} + +static struct page *drm_vm_dma_nopage(struct vm_area_struct *vma, + unsigned long address, + int *type) { + if (type) *type = VM_FAULT_MINOR; + return drm_do_vm_dma_nopage(vma, address); +} + +static struct page *drm_vm_sg_nopage(struct vm_area_struct *vma, + unsigned long address, + int *type) { + if (type) *type = VM_FAULT_MINOR; + return drm_do_vm_sg_nopage(vma, address); +} + +#else /* LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,0) */ + +static struct page *drm_vm_nopage(struct vm_area_struct *vma, + unsigned long address, + int unused) { + return drm_do_vm_nopage(vma, address); +} + +static struct page *drm_vm_shm_nopage(struct vm_area_struct *vma, + unsigned long address, + int unused) { + return drm_do_vm_shm_nopage(vma, address); +} + +static struct page *drm_vm_dma_nopage(struct vm_area_struct *vma, + unsigned long address, + int unused) { + return drm_do_vm_dma_nopage(vma, address); +} + +static struct page *drm_vm_sg_nopage(struct vm_area_struct *vma, + unsigned long address, + int unused) { + return drm_do_vm_sg_nopage(vma, address); +} + +#endif + + +/** AGP virtual memory operations */ +static struct vm_operations_struct drm_vm_ops = { + .nopage = drm_vm_nopage, + .open = drm_vm_open, + .close = drm_vm_close, +}; + +/** Shared virtual memory operations */ +static struct vm_operations_struct drm_vm_shm_ops = { + .nopage = drm_vm_shm_nopage, + .open = drm_vm_open, + .close = drm_vm_shm_close, +}; + +/** DMA virtual memory operations */ +static struct vm_operations_struct drm_vm_dma_ops = { + .nopage = drm_vm_dma_nopage, + .open = drm_vm_open, + .close = drm_vm_close, +}; + +/** Scatter-gather virtual memory operations */ +static struct vm_operations_struct drm_vm_sg_ops = { + .nopage = drm_vm_sg_nopage, + .open = drm_vm_open, + .close = drm_vm_close, +}; + + +/** + * \c open method for shared virtual memory. + * + * \param vma virtual memory area. + * + * Create a new drm_vma_entry structure as the \p vma private data entry and + * add it to drm_device::vmalist. + */ +void drm_vm_open(struct vm_area_struct *vma) +{ + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->head->dev; + drm_vma_entry_t *vma_entry; + + DRM_DEBUG("0x%08lx,0x%08lx\n", + vma->vm_start, vma->vm_end - vma->vm_start); + atomic_inc(&dev->vma_count); + + vma_entry = drm_alloc(sizeof(*vma_entry), DRM_MEM_VMAS); + if (vma_entry) { + down(&dev->struct_sem); + vma_entry->vma = vma; + vma_entry->next = dev->vmalist; + vma_entry->pid = current->pid; + dev->vmalist = vma_entry; + up(&dev->struct_sem); + } +} + +/** + * \c close method for all virtual memory types. + * + * \param vma virtual memory area. + * + * Search the \p vma private data entry in drm_device::vmalist, unlink it, and + * free it. + */ +void drm_vm_close(struct vm_area_struct *vma) +{ + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->head->dev; + drm_vma_entry_t *pt, *prev; + + DRM_DEBUG("0x%08lx,0x%08lx\n", + vma->vm_start, vma->vm_end - vma->vm_start); + atomic_dec(&dev->vma_count); + + down(&dev->struct_sem); + for (pt = dev->vmalist, prev = NULL; pt; prev = pt, pt = pt->next) { + if (pt->vma == vma) { + if (prev) { + prev->next = pt->next; + } else { + dev->vmalist = pt->next; + } + drm_free(pt, sizeof(*pt), DRM_MEM_VMAS); + break; + } + } + up(&dev->struct_sem); +} + +/** + * mmap DMA memory. + * + * \param filp file pointer. + * \param vma virtual memory area. + * \return zero on success or a negative number on failure. + * + * Sets the virtual memory area operations structure to vm_dma_ops, the file + * pointer, and calls vm_open(). + */ +int drm_mmap_dma(struct file *filp, struct vm_area_struct *vma) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + drm_device_dma_t *dma; + unsigned long length = vma->vm_end - vma->vm_start; + + lock_kernel(); + dev = priv->head->dev; + dma = dev->dma; + DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n", + vma->vm_start, vma->vm_end, VM_OFFSET(vma)); + + /* Length must match exact page count */ + if (!dma || (length >> PAGE_SHIFT) != dma->page_count) { + unlock_kernel(); + return -EINVAL; + } + unlock_kernel(); + + vma->vm_ops = &drm_vm_dma_ops; + +#if LINUX_VERSION_CODE <= 0x02040e /* KERNEL_VERSION(2,4,14) */ + vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */ +#else + vma->vm_flags |= VM_RESERVED; /* Don't swap */ +#endif + + vma->vm_file = filp; /* Needed for drm_vm_open() */ + drm_vm_open(vma); + return 0; +} + +unsigned long drm_core_get_map_ofs(drm_map_t *map) +{ + return map->offset; +} +EXPORT_SYMBOL(drm_core_get_map_ofs); + +unsigned long drm_core_get_reg_ofs(struct drm_device *dev) +{ +#ifdef __alpha__ + return dev->hose->dense_mem_base - dev->hose->mem_space->start; +#else + return 0; +#endif +} +EXPORT_SYMBOL(drm_core_get_reg_ofs); + +/** + * mmap DMA memory. + * + * \param filp file pointer. + * \param vma virtual memory area. + * \return zero on success or a negative number on failure. + * + * If the virtual memory area has no offset associated with it then it's a DMA + * area, so calls mmap_dma(). Otherwise searches the map in drm_device::maplist, + * checks that the restricted flag is not set, sets the virtual memory operations + * according to the mapping type and remaps the pages. Finally sets the file + * pointer and calls vm_open(). + */ +int drm_mmap(struct file *filp, struct vm_area_struct *vma) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_map_t *map = NULL; + drm_map_list_t *r_list; + unsigned long offset = 0; + struct list_head *list; + + DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n", + vma->vm_start, vma->vm_end, VM_OFFSET(vma)); + + if ( !priv->authenticated ) return -EACCES; + + /* We check for "dma". On Apple's UniNorth, it's valid to have + * the AGP mapped at physical address 0 + * --BenH. + */ + if (!VM_OFFSET(vma) +#if __OS_HAS_AGP + && (!dev->agp || dev->agp->agp_info.device->vendor != PCI_VENDOR_ID_APPLE) +#endif + ) + return drm_mmap_dma(filp, vma); + + /* A sequential search of a linked list is + fine here because: 1) there will only be + about 5-10 entries in the list and, 2) a + DRI client only has to do this mapping + once, so it doesn't have to be optimized + for performance, even if the list was a + bit longer. */ + list_for_each(list, &dev->maplist->head) { + unsigned long off; + + r_list = list_entry(list, drm_map_list_t, head); + map = r_list->map; + if (!map) continue; + off = dev->driver->get_map_ofs(map); + if (off == VM_OFFSET(vma)) break; + } + + if (!map || ((map->flags&_DRM_RESTRICTED) && !capable(CAP_SYS_ADMIN))) + return -EPERM; + + /* Check for valid size. */ + if (map->size != vma->vm_end - vma->vm_start) return -EINVAL; + + if (!capable(CAP_SYS_ADMIN) && (map->flags & _DRM_READ_ONLY)) { + vma->vm_flags &= ~(VM_WRITE | VM_MAYWRITE); +#if defined(__i386__) || defined(__x86_64__) + pgprot_val(vma->vm_page_prot) &= ~_PAGE_RW; +#else + /* Ye gads this is ugly. With more thought + we could move this up higher and use + `protection_map' instead. */ + vma->vm_page_prot = __pgprot(pte_val(pte_wrprotect( + __pte(pgprot_val(vma->vm_page_prot))))); +#endif + } + + switch (map->type) { + case _DRM_AGP: + if (drm_core_has_AGP(dev) && dev->agp->cant_use_aperture) { + /* + * On some platforms we can't talk to bus dma address from the CPU, so for + * memory of type DRM_AGP, we'll deal with sorting out the real physical + * pages and mappings in nopage() + */ +#if defined(__powerpc__) + pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE; +#endif + vma->vm_ops = &drm_vm_ops; + break; + } + /* fall through to _DRM_FRAME_BUFFER... */ + case _DRM_FRAME_BUFFER: + case _DRM_REGISTERS: + if (VM_OFFSET(vma) >= __pa(high_memory)) { +#if defined(__i386__) || defined(__x86_64__) + if (boot_cpu_data.x86 > 3 && map->type != _DRM_AGP) { + pgprot_val(vma->vm_page_prot) |= _PAGE_PCD; + pgprot_val(vma->vm_page_prot) &= ~_PAGE_PWT; + } +#elif defined(__powerpc__) + pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE | _PAGE_GUARDED; +#endif + vma->vm_flags |= VM_IO; /* not in core dump */ + } +#if defined(__ia64__) + if (efi_range_is_wc(vma->vm_start, vma->vm_end - + vma->vm_start)) + vma->vm_page_prot = + pgprot_writecombine(vma->vm_page_prot); + else + vma->vm_page_prot = + pgprot_noncached(vma->vm_page_prot); +#endif + offset = dev->driver->get_reg_ofs(dev); +#ifdef __sparc__ + if (io_remap_pfn_range(DRM_RPR_ARG(vma) vma->vm_start, + (VM_OFFSET(vma) + offset) >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) +#else + if (io_remap_pfn_range(vma, vma->vm_start, + (VM_OFFSET(vma) + offset) >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) +#endif + return -EAGAIN; + DRM_DEBUG(" Type = %d; start = 0x%lx, end = 0x%lx," + " offset = 0x%lx\n", + map->type, + vma->vm_start, vma->vm_end, VM_OFFSET(vma) + offset); + vma->vm_ops = &drm_vm_ops; + break; + case _DRM_SHM: + vma->vm_ops = &drm_vm_shm_ops; + vma->vm_private_data = (void *)map; + /* Don't let this area swap. Change when + DRM_KERNEL advisory is supported. */ +#if LINUX_VERSION_CODE <= 0x02040e /* KERNEL_VERSION(2,4,14) */ + vma->vm_flags |= VM_LOCKED; +#else + vma->vm_flags |= VM_RESERVED; +#endif + break; + case _DRM_SCATTER_GATHER: + vma->vm_ops = &drm_vm_sg_ops; + vma->vm_private_data = (void *)map; +#if LINUX_VERSION_CODE <= 0x02040e /* KERNEL_VERSION(2,4,14) */ + vma->vm_flags |= VM_LOCKED; +#else + vma->vm_flags |= VM_RESERVED; +#endif + break; + default: + return -EINVAL; /* This should never happen. */ + } +#if LINUX_VERSION_CODE <= 0x02040e /* KERNEL_VERSION(2,4,14) */ + vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */ +#else + vma->vm_flags |= VM_RESERVED; /* Don't swap */ +#endif + + vma->vm_file = filp; /* Needed for drm_vm_open() */ + drm_vm_open(vma); + return 0; +} +EXPORT_SYMBOL(drm_mmap); diff --git a/drivers/char/drm/ffb_context.c b/drivers/char/drm/ffb_context.c new file mode 100644 index 000000000000..f51812078010 --- /dev/null +++ b/drivers/char/drm/ffb_context.c @@ -0,0 +1,551 @@ +/* $Id: ffb_context.c,v 1.5 2001/08/09 17:47:51 davem Exp $ + * ffb_context.c: Creator/Creator3D DRI/DRM context switching. + * + * Copyright (C) 2000 David S. Miller (davem@redhat.com) + * + * Almost entirely stolen from tdfx_context.c, see there + * for authors. + */ + +#include +#include + +#include "ffb.h" +#include "drmP.h" + +#include "ffb_drv.h" + +static int DRM(alloc_queue)(drm_device_t *dev, int is_2d_only) +{ + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; + int i; + + for (i = 0; i < FFB_MAX_CTXS; i++) { + if (fpriv->hw_state[i] == NULL) + break; + } + if (i == FFB_MAX_CTXS) + return -1; + + fpriv->hw_state[i] = kmalloc(sizeof(struct ffb_hw_context), GFP_KERNEL); + if (fpriv->hw_state[i] == NULL) + return -1; + + fpriv->hw_state[i]->is_2d_only = is_2d_only; + + /* Plus one because 0 is the special DRM_KERNEL_CONTEXT. */ + return i + 1; +} + +static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) +{ + ffb_fbcPtr ffb = fpriv->regs; + struct ffb_hw_context *ctx; + int i; + + ctx = fpriv->hw_state[idx - 1]; + if (idx == 0 || ctx == NULL) + return; + + if (ctx->is_2d_only) { + /* 2D applications only care about certain pieces + * of state. + */ + ctx->drawop = upa_readl(&ffb->drawop); + ctx->ppc = upa_readl(&ffb->ppc); + ctx->wid = upa_readl(&ffb->wid); + ctx->fg = upa_readl(&ffb->fg); + ctx->bg = upa_readl(&ffb->bg); + ctx->xclip = upa_readl(&ffb->xclip); + ctx->fbc = upa_readl(&ffb->fbc); + ctx->rop = upa_readl(&ffb->rop); + ctx->cmp = upa_readl(&ffb->cmp); + ctx->matchab = upa_readl(&ffb->matchab); + ctx->magnab = upa_readl(&ffb->magnab); + ctx->pmask = upa_readl(&ffb->pmask); + ctx->xpmask = upa_readl(&ffb->xpmask); + ctx->lpat = upa_readl(&ffb->lpat); + ctx->fontxy = upa_readl(&ffb->fontxy); + ctx->fontw = upa_readl(&ffb->fontw); + ctx->fontinc = upa_readl(&ffb->fontinc); + + /* stencil/stencilctl only exists on FFB2+ and later + * due to the introduction of 3DRAM-III. + */ + if (fpriv->ffb_type == ffb2_vertical_plus || + fpriv->ffb_type == ffb2_horizontal_plus) { + ctx->stencil = upa_readl(&ffb->stencil); + ctx->stencilctl = upa_readl(&ffb->stencilctl); + } + + for (i = 0; i < 32; i++) + ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]); + ctx->ucsr = upa_readl(&ffb->ucsr); + return; + } + + /* Fetch drawop. */ + ctx->drawop = upa_readl(&ffb->drawop); + + /* If we were saving the vertex registers, this is where + * we would do it. We would save 32 32-bit words starting + * at ffb->suvtx. + */ + + /* Capture rendering attributes. */ + + ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */ + ctx->wid = upa_readl(&ffb->wid); /* Current WID */ + ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */ + ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */ + ctx->consty = upa_readl(&ffb->consty); /* Constant Y */ + ctx->constz = upa_readl(&ffb->constz); /* Constant Z */ + ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */ + ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */ + ctx->vclipmin = upa_readl(&ffb->vclipmin); /* Primary XY clip, minimum */ + ctx->vclipmax = upa_readl(&ffb->vclipmax); /* Primary XY clip, maximum */ + ctx->vclipzmin = upa_readl(&ffb->vclipzmin); /* Primary Z clip, minimum */ + ctx->vclipzmax = upa_readl(&ffb->vclipzmax); /* Primary Z clip, maximum */ + ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */ + ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */ + ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */ + ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */ + ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */ + ctx->blendc1 = upa_readl(&ffb->blendc1); /* Alpha Blend Color 1 */ + ctx->blendc2 = upa_readl(&ffb->blendc2); /* Alpha Blend Color 2 */ + ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */ + ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */ + ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */ + ctx->matchab = upa_readl(&ffb->matchab); /* Buffer A/B Match Ops */ + ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */ + ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */ + ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */ + ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */ + ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */ + ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */ + ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */ + + /* Auxiliary Clips. */ + ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min); + ctx->auxclip0max = upa_readl(&ffb->auxclip[0].max); + ctx->auxclip1min = upa_readl(&ffb->auxclip[1].min); + ctx->auxclip1max = upa_readl(&ffb->auxclip[1].max); + ctx->auxclip2min = upa_readl(&ffb->auxclip[2].min); + ctx->auxclip2max = upa_readl(&ffb->auxclip[2].max); + ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min); + ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max); + + ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */ + ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */ + ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */ + ctx->fontinc = upa_readl(&ffb->fontinc); /* Font X/Y Increment */ + + /* These registers/features only exist on FFB2 and later chips. */ + if (fpriv->ffb_type >= ffb2_prototype) { + ctx->dcss1 = upa_readl(&ffb->dcss1); /* Depth Cue Scale Slope 1 */ + ctx->dcss2 = upa_readl(&ffb->dcss2); /* Depth Cue Scale Slope 2 */ + ctx->dcss2 = upa_readl(&ffb->dcss3); /* Depth Cue Scale Slope 3 */ + ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */ + ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */ + ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */ + ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */ + ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */ + ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */ + + /* And stencil/stencilctl only exists on FFB2+ and later + * due to the introduction of 3DRAM-III. + */ + if (fpriv->ffb_type == ffb2_vertical_plus || + fpriv->ffb_type == ffb2_horizontal_plus) { + ctx->stencil = upa_readl(&ffb->stencil); + ctx->stencilctl = upa_readl(&ffb->stencilctl); + } + } + + /* Save the 32x32 area pattern. */ + for (i = 0; i < 32; i++) + ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]); + + /* Finally, stash away the User Constol/Status Register. */ + ctx->ucsr = upa_readl(&ffb->ucsr); +} + +static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx) +{ + ffb_fbcPtr ffb = fpriv->regs; + struct ffb_hw_context *ctx; + int i; + + ctx = fpriv->hw_state[idx - 1]; + if (idx == 0 || ctx == NULL) + return; + + if (ctx->is_2d_only) { + /* 2D applications only care about certain pieces + * of state. + */ + upa_writel(ctx->drawop, &ffb->drawop); + + /* If we were restoring the vertex registers, this is where + * we would do it. We would restore 32 32-bit words starting + * at ffb->suvtx. + */ + + upa_writel(ctx->ppc, &ffb->ppc); + upa_writel(ctx->wid, &ffb->wid); + upa_writel(ctx->fg, &ffb->fg); + upa_writel(ctx->bg, &ffb->bg); + upa_writel(ctx->xclip, &ffb->xclip); + upa_writel(ctx->fbc, &ffb->fbc); + upa_writel(ctx->rop, &ffb->rop); + upa_writel(ctx->cmp, &ffb->cmp); + upa_writel(ctx->matchab, &ffb->matchab); + upa_writel(ctx->magnab, &ffb->magnab); + upa_writel(ctx->pmask, &ffb->pmask); + upa_writel(ctx->xpmask, &ffb->xpmask); + upa_writel(ctx->lpat, &ffb->lpat); + upa_writel(ctx->fontxy, &ffb->fontxy); + upa_writel(ctx->fontw, &ffb->fontw); + upa_writel(ctx->fontinc, &ffb->fontinc); + + /* stencil/stencilctl only exists on FFB2+ and later + * due to the introduction of 3DRAM-III. + */ + if (fpriv->ffb_type == ffb2_vertical_plus || + fpriv->ffb_type == ffb2_horizontal_plus) { + upa_writel(ctx->stencil, &ffb->stencil); + upa_writel(ctx->stencilctl, &ffb->stencilctl); + upa_writel(0x80000000, &ffb->fbc); + upa_writel((ctx->stencilctl | 0x80000), + &ffb->rawstencilctl); + upa_writel(ctx->fbc, &ffb->fbc); + } + + for (i = 0; i < 32; i++) + upa_writel(ctx->area_pattern[i], &ffb->pattern[i]); + upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr); + return; + } + + /* Restore drawop. */ + upa_writel(ctx->drawop, &ffb->drawop); + + /* If we were restoring the vertex registers, this is where + * we would do it. We would restore 32 32-bit words starting + * at ffb->suvtx. + */ + + /* Restore rendering attributes. */ + + upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */ + upa_writel(ctx->wid, &ffb->wid); /* Current WID */ + upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */ + upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */ + upa_writel(ctx->consty, &ffb->consty); /* Constant Y */ + upa_writel(ctx->constz, &ffb->constz); /* Constant Z */ + upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */ + upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */ + upa_writel(ctx->vclipmin, &ffb->vclipmin); /* Primary XY clip, minimum */ + upa_writel(ctx->vclipmax, &ffb->vclipmax); /* Primary XY clip, maximum */ + upa_writel(ctx->vclipzmin, &ffb->vclipzmin); /* Primary Z clip, minimum */ + upa_writel(ctx->vclipzmax, &ffb->vclipzmax); /* Primary Z clip, maximum */ + upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */ + upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */ + upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */ + upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */ + upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */ + upa_writel(ctx->blendc1, &ffb->blendc1); /* Alpha Blend Color 1 */ + upa_writel(ctx->blendc2, &ffb->blendc2); /* Alpha Blend Color 2 */ + upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */ + upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */ + upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */ + upa_writel(ctx->matchab, &ffb->matchab); /* Buffer A/B Match Ops */ + upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */ + upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */ + upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */ + upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */ + upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */ + upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */ + upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */ + + /* Auxiliary Clips. */ + upa_writel(ctx->auxclip0min, &ffb->auxclip[0].min); + upa_writel(ctx->auxclip0max, &ffb->auxclip[0].max); + upa_writel(ctx->auxclip1min, &ffb->auxclip[1].min); + upa_writel(ctx->auxclip1max, &ffb->auxclip[1].max); + upa_writel(ctx->auxclip2min, &ffb->auxclip[2].min); + upa_writel(ctx->auxclip2max, &ffb->auxclip[2].max); + upa_writel(ctx->auxclip3min, &ffb->auxclip[3].min); + upa_writel(ctx->auxclip3max, &ffb->auxclip[3].max); + + upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */ + upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */ + upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */ + upa_writel(ctx->fontinc, &ffb->fontinc); /* Font X/Y Increment */ + + /* These registers/features only exist on FFB2 and later chips. */ + if (fpriv->ffb_type >= ffb2_prototype) { + upa_writel(ctx->dcss1, &ffb->dcss1); /* Depth Cue Scale Slope 1 */ + upa_writel(ctx->dcss2, &ffb->dcss2); /* Depth Cue Scale Slope 2 */ + upa_writel(ctx->dcss3, &ffb->dcss2); /* Depth Cue Scale Slope 3 */ + upa_writel(ctx->dcs2, &ffb->dcs2); /* Depth Cue Scale 2 */ + upa_writel(ctx->dcs3, &ffb->dcs3); /* Depth Cue Scale 3 */ + upa_writel(ctx->dcs4, &ffb->dcs4); /* Depth Cue Scale 4 */ + upa_writel(ctx->dcd2, &ffb->dcd2); /* Depth Cue Depth 2 */ + upa_writel(ctx->dcd3, &ffb->dcd3); /* Depth Cue Depth 3 */ + upa_writel(ctx->dcd4, &ffb->dcd4); /* Depth Cue Depth 4 */ + + /* And stencil/stencilctl only exists on FFB2+ and later + * due to the introduction of 3DRAM-III. + */ + if (fpriv->ffb_type == ffb2_vertical_plus || + fpriv->ffb_type == ffb2_horizontal_plus) { + /* Unfortunately, there is a hardware bug on + * the FFB2+ chips which prevents a normal write + * to the stencil control register from working + * as it should. + * + * The state controlled by the FFB stencilctl register + * really gets transferred to the per-buffer instances + * of the stencilctl register in the 3DRAM chips. + * + * The bug is that FFB does not update buffer C correctly, + * so we have to do it by hand for them. + */ + + /* This will update buffers A and B. */ + upa_writel(ctx->stencil, &ffb->stencil); + upa_writel(ctx->stencilctl, &ffb->stencilctl); + + /* Force FFB to use buffer C 3dram regs. */ + upa_writel(0x80000000, &ffb->fbc); + upa_writel((ctx->stencilctl | 0x80000), + &ffb->rawstencilctl); + + /* Now restore the correct FBC controls. */ + upa_writel(ctx->fbc, &ffb->fbc); + } + } + + /* Restore the 32x32 area pattern. */ + for (i = 0; i < 32; i++) + upa_writel(ctx->area_pattern[i], &ffb->pattern[i]); + + /* Finally, stash away the User Constol/Status Register. + * The only state we really preserve here is the picking + * control. + */ + upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr); +} + +#define FFB_UCSR_FB_BUSY 0x01000000 +#define FFB_UCSR_RP_BUSY 0x02000000 +#define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY) + +static void FFBWait(ffb_fbcPtr ffb) +{ + int limit = 100000; + + do { + u32 regval = upa_readl(&ffb->ucsr); + + if ((regval & FFB_UCSR_ALL_BUSY) == 0) + break; + } while (--limit); +} + +int ffb_driver_context_switch(drm_device_t *dev, int old, int new) +{ + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; + +#ifdef DRM_DMA_HISTOGRAM + dev->ctx_start = get_cycles(); +#endif + + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new == dev->last_context || + dev->last_context == 0) { + dev->last_context = new; + return 0; + } + + FFBWait(fpriv->regs); + ffb_save_context(fpriv, old); + ffb_restore_context(fpriv, old, new); + FFBWait(fpriv->regs); + + dev->last_context = new; + + return 0; +} + +int ffb_driver_resctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; + + DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); + if (copy_from_user(&res, (drm_ctx_res_t __user *)arg, sizeof(res))) + return -EFAULT; + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + ctx.handle = i; + if (copy_to_user(&res.contexts[i], + &i, + sizeof(i))) + return -EFAULT; + } + } + res.count = DRM_RESERVED_CONTEXTS; + if (copy_to_user((drm_ctx_res_t __user *)arg, &res, sizeof(res))) + return -EFAULT; + return 0; +} + + +int ffb_driver_addctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + int idx; + + if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + return -EFAULT; + idx = DRM(alloc_queue)(dev, (ctx.flags & _DRM_CONTEXT_2DONLY)); + if (idx < 0) + return -ENFILE; + + DRM_DEBUG("%d\n", ctx.handle); + ctx.handle = idx; + if (copy_to_user((drm_ctx_t __user *)arg, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int ffb_driver_modctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; + struct ffb_hw_context *hwctx; + drm_ctx_t ctx; + int idx; + + if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + return -EFAULT; + + idx = ctx.handle; + if (idx <= 0 || idx >= FFB_MAX_CTXS) + return -EINVAL; + + hwctx = fpriv->hw_state[idx - 1]; + if (hwctx == NULL) + return -EINVAL; + + if ((ctx.flags & _DRM_CONTEXT_2DONLY) == 0) + hwctx->is_2d_only = 0; + else + hwctx->is_2d_only = 1; + + return 0; +} + +int ffb_driver_getctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; + struct ffb_hw_context *hwctx; + drm_ctx_t ctx; + int idx; + + if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + return -EFAULT; + + idx = ctx.handle; + if (idx <= 0 || idx >= FFB_MAX_CTXS) + return -EINVAL; + + hwctx = fpriv->hw_state[idx - 1]; + if (hwctx == NULL) + return -EINVAL; + + if (hwctx->is_2d_only != 0) + ctx.flags = _DRM_CONTEXT_2DONLY; + else + ctx.flags = 0; + + if (copy_to_user((drm_ctx_t __user *)arg, &ctx, sizeof(ctx))) + return -EFAULT; + + return 0; +} + +int ffb_driver_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + return ffb_driver_context_switch(dev, dev->last_context, ctx.handle); +} + +int ffb_driver_newctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + + return 0; +} + +int ffb_driver_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; + int idx; + + if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + + idx = ctx.handle - 1; + if (idx < 0 || idx >= FFB_MAX_CTXS) + return -EINVAL; + + if (fpriv->hw_state[idx] != NULL) { + kfree(fpriv->hw_state[idx]); + fpriv->hw_state[idx] = NULL; + } + return 0; +} + +void ffb_set_context_ioctls(void) +{ + DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)].func = ffb_driver_addctx; + DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)].func = ffb_driver_rmctx; + DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)].func = ffb_driver_modctx; + DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)].func = ffb_driver_getctx; + DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)].func = ffb_driver_switchctx; + DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)].func = ffb_driver_newctx; + DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)].func = ffb_driver_resctx; + +} diff --git a/drivers/char/drm/ffb_drv.c b/drivers/char/drm/ffb_drv.c new file mode 100644 index 000000000000..ec614fff8f04 --- /dev/null +++ b/drivers/char/drm/ffb_drv.c @@ -0,0 +1,365 @@ +/* $Id: ffb_drv.c,v 1.16 2001/10/18 16:00:24 davem Exp $ + * ffb_drv.c: Creator/Creator3D direct rendering driver. + * + * Copyright (C) 2000 David S. Miller (davem@redhat.com) + */ + +#include +#include "ffb.h" +#include "drmP.h" + +#include "ffb_drv.h" + +#include +#include +#include +#include +#include + +#define DRIVER_AUTHOR "David S. Miller" + +#define DRIVER_NAME "ffb" +#define DRIVER_DESC "Creator/Creator3D" +#define DRIVER_DATE "20000517" + +#define DRIVER_MAJOR 0 +#define DRIVER_MINOR 0 +#define DRIVER_PATCHLEVEL 1 + +typedef struct _ffb_position_t { + int node; + int root; +} ffb_position_t; + +static ffb_position_t *ffb_position; + +static void get_ffb_type(ffb_dev_priv_t *ffb_priv, int instance) +{ + volatile unsigned char *strap_bits; + unsigned char val; + + strap_bits = (volatile unsigned char *) + (ffb_priv->card_phys_base + 0x00200000UL); + + /* Don't ask, you have to read the value twice for whatever + * reason to get correct contents. + */ + val = upa_readb(strap_bits); + val = upa_readb(strap_bits); + switch (val & 0x78) { + case (0x0 << 5) | (0x0 << 3): + ffb_priv->ffb_type = ffb1_prototype; + printk("ffb%d: Detected FFB1 pre-FCS prototype\n", instance); + break; + case (0x0 << 5) | (0x1 << 3): + ffb_priv->ffb_type = ffb1_standard; + printk("ffb%d: Detected FFB1\n", instance); + break; + case (0x0 << 5) | (0x3 << 3): + ffb_priv->ffb_type = ffb1_speedsort; + printk("ffb%d: Detected FFB1-SpeedSort\n", instance); + break; + case (0x1 << 5) | (0x0 << 3): + ffb_priv->ffb_type = ffb2_prototype; + printk("ffb%d: Detected FFB2/vertical pre-FCS prototype\n", instance); + break; + case (0x1 << 5) | (0x1 << 3): + ffb_priv->ffb_type = ffb2_vertical; + printk("ffb%d: Detected FFB2/vertical\n", instance); + break; + case (0x1 << 5) | (0x2 << 3): + ffb_priv->ffb_type = ffb2_vertical_plus; + printk("ffb%d: Detected FFB2+/vertical\n", instance); + break; + case (0x2 << 5) | (0x0 << 3): + ffb_priv->ffb_type = ffb2_horizontal; + printk("ffb%d: Detected FFB2/horizontal\n", instance); + break; + case (0x2 << 5) | (0x2 << 3): + ffb_priv->ffb_type = ffb2_horizontal; + printk("ffb%d: Detected FFB2+/horizontal\n", instance); + break; + default: + ffb_priv->ffb_type = ffb2_vertical; + printk("ffb%d: Unknown boardID[%08x], assuming FFB2\n", instance, val); + break; + }; +} + +static void ffb_apply_upa_parent_ranges(int parent, + struct linux_prom64_registers *regs) +{ + struct linux_prom64_ranges ranges[PROMREG_MAX]; + char name[128]; + int len, i; + + prom_getproperty(parent, "name", name, sizeof(name)); + if (strcmp(name, "upa") != 0) + return; + + len = prom_getproperty(parent, "ranges", (void *) ranges, sizeof(ranges)); + if (len <= 0) + return; + + len /= sizeof(struct linux_prom64_ranges); + for (i = 0; i < len; i++) { + struct linux_prom64_ranges *rng = &ranges[i]; + u64 phys_addr = regs->phys_addr; + + if (phys_addr >= rng->ot_child_base && + phys_addr < (rng->ot_child_base + rng->or_size)) { + regs->phys_addr -= rng->ot_child_base; + regs->phys_addr += rng->ot_parent_base; + return; + } + } + + return; +} + +static int ffb_init_one(drm_device_t *dev, int prom_node, int parent_node, + int instance) +{ + struct linux_prom64_registers regs[2*PROMREG_MAX]; + ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *)dev->dev_private; + int i; + + ffb_priv->prom_node = prom_node; + if (prom_getproperty(ffb_priv->prom_node, "reg", + (void *)regs, sizeof(regs)) <= 0) { + return -EINVAL; + } + ffb_apply_upa_parent_ranges(parent_node, ®s[0]); + ffb_priv->card_phys_base = regs[0].phys_addr; + ffb_priv->regs = (ffb_fbcPtr) + (regs[0].phys_addr + 0x00600000UL); + get_ffb_type(ffb_priv, instance); + for (i = 0; i < FFB_MAX_CTXS; i++) + ffb_priv->hw_state[i] = NULL; + + return 0; +} + +static drm_map_t *ffb_find_map(struct file *filp, unsigned long off) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + drm_map_list_t *r_list; + struct list_head *list; + drm_map_t *map; + + if (!priv || (dev = priv->dev) == NULL) + return NULL; + + list_for_each(list, &dev->maplist->head) { + unsigned long uoff; + + r_list = (drm_map_list_t *)list; + map = r_list->map; + if (!map) + continue; + uoff = (map->offset & 0xffffffff); + if (uoff == off) + return map; + } + + return NULL; +} + +unsigned long ffb_get_unmapped_area(struct file *filp, + unsigned long hint, + unsigned long len, + unsigned long pgoff, + unsigned long flags) +{ + drm_map_t *map = ffb_find_map(filp, pgoff << PAGE_SHIFT); + unsigned long addr = -ENOMEM; + + if (!map) + return get_unmapped_area(NULL, hint, len, pgoff, flags); + + if (map->type == _DRM_FRAME_BUFFER || + map->type == _DRM_REGISTERS) { +#ifdef HAVE_ARCH_FB_UNMAPPED_AREA + addr = get_fb_unmapped_area(filp, hint, len, pgoff, flags); +#else + addr = get_unmapped_area(NULL, hint, len, pgoff, flags); +#endif + } else if (map->type == _DRM_SHM && SHMLBA > PAGE_SIZE) { + unsigned long slack = SHMLBA - PAGE_SIZE; + + addr = get_unmapped_area(NULL, hint, len + slack, pgoff, flags); + if (!(addr & ~PAGE_MASK)) { + unsigned long kvirt = (unsigned long) map->handle; + + if ((kvirt & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) { + unsigned long koff, aoff; + + koff = kvirt & (SHMLBA - 1); + aoff = addr & (SHMLBA - 1); + if (koff < aoff) + koff += SHMLBA; + + addr += (koff - aoff); + } + } + } else { + addr = get_unmapped_area(NULL, hint, len, pgoff, flags); + } + + return addr; +} + +static int ffb_presetup(drm_device_t *dev) +{ + ffb_dev_priv_t *ffb_priv; + int ret = 0; + int i = 0; + + /* Check for the case where no device was found. */ + if (ffb_position == NULL) + return -ENODEV; + + /* code used to use numdevs no numdevs anymore */ + ffb_priv = kmalloc(sizeof(ffb_dev_priv_t), GFP_KERNEL); + if (!ffb_priv) + return -ENOMEM; + memset(ffb_priv, 0, sizeof(*ffb_priv)); + dev->dev_private = ffb_priv; + + ret = ffb_init_one(dev, + ffb_position[i].node, + ffb_position[i].root, + i); + return ret; +} + +static void ffb_driver_release(drm_device_t *dev, struct file *filp) +{ + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; + int context = _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock); + int idx; + + idx = context - 1; + if (fpriv && + context != DRM_KERNEL_CONTEXT && + fpriv->hw_state[idx] != NULL) { + kfree(fpriv->hw_state[idx]); + fpriv->hw_state[idx] = NULL; + } +} + +static void ffb_driver_pretakedown(drm_device_t *dev) +{ + if (dev->dev_private) kfree(dev->dev_private); +} + +static int ffb_driver_postcleanup(drm_device_t *dev) +{ + if (ffb_position != NULL) kfree(ffb_position); + return 0; +} + +static void ffb_driver_kernel_context_switch_unlock(struct drm_device *dev, drm_lock_t *lock) +{ + dev->lock.filp = 0; + { + __volatile__ unsigned int *plock = &dev->lock.hw_lock->lock; + unsigned int old, new, prev, ctx; + + ctx = lock->context; + do { + old = *plock; + new = ctx; + prev = cmpxchg(plock, old, new); + } while (prev != old); + } + wake_up_interruptible(&dev->lock.lock_queue); +} + +static unsigned long ffb_driver_get_map_ofs(drm_map_t *map) +{ + return (map->offset & 0xffffffff); +} + +static unsigned long ffb_driver_get_reg_ofs(drm_device_t *dev) +{ + ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *)dev->dev_private; + + if (ffb_priv) + return ffb_priv->card_phys_base; + + return 0; +} + +static int postinit( struct drm_device *dev, unsigned long flags ) +{ + DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, + dev->minor + ); + return 0; +} + +static int version( drm_version_t *version ) +{ + int len; + + version->version_major = DRIVER_MAJOR; + version->version_minor = DRIVER_MINOR; + version->version_patchlevel = DRIVER_PATCHLEVEL; + DRM_COPY( version->name, DRIVER_NAME ); + DRM_COPY( version->date, DRIVER_DATE ); + DRM_COPY( version->desc, DRIVER_DESC ); + return 0; +} + +static drm_ioctl_desc_t ioctls[] = { + +}; + +static struct drm_driver driver = { + .driver_features = 0, + .dev_priv_size = sizeof(u32), + .release = ffb_driver_release, + .presetup = ffb_presetup, + .pretakedown = ffb_driver_pretakedown, + .postcleanup = ffb_driver_postcleanup, + .kernel_context_switch = ffb_driver_context_switch, + .kernel_context_switch_unlock = ffb_driver_kernel_context_switch_unlock, + .get_map_ofs = ffb_driver_get_map_ofs, + .get_reg_ofs = ffb_driver_get_reg_ofs, + .postinit = postinit, + .version = version, + .ioctls = ioctls, + .num_ioctls = DRM_ARRAY_SIZE(ioctls), + .fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + }, +}; + +static int __init ffb_init(void) +{ + return -ENODEV; +} + +static void __exit ffb_exit(void) +{ +} + +module_init(ffb_init); +module_exit(ffb_exit); + +MODULE_AUTHOR( DRIVER_AUTHOR ); +MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/ffb_drv.h b/drivers/char/drm/ffb_drv.h new file mode 100644 index 000000000000..8bf7f1e143f1 --- /dev/null +++ b/drivers/char/drm/ffb_drv.h @@ -0,0 +1,286 @@ +/* $Id: ffb_drv.h,v 1.1 2000/06/01 04:24:39 davem Exp $ + * ffb_drv.h: Creator/Creator3D direct rendering driver. + * + * Copyright (C) 2000 David S. Miller (davem@redhat.com) + */ + +/* Auxilliary clips. */ +typedef struct { + volatile unsigned int min; + volatile unsigned int max; +} ffb_auxclip, *ffb_auxclipPtr; + +/* FFB register set. */ +typedef struct _ffb_fbc { + /* Next vertex registers, on the right we list which drawops + * use said register and the logical name the register has in + * that context. + */ /* DESCRIPTION DRAWOP(NAME) */ +/*0x00*/unsigned int pad1[3]; /* Reserved */ +/*0x0c*/volatile unsigned int alpha; /* ALPHA Transparency */ +/*0x10*/volatile unsigned int red; /* RED */ +/*0x14*/volatile unsigned int green; /* GREEN */ +/*0x18*/volatile unsigned int blue; /* BLUE */ +/*0x1c*/volatile unsigned int z; /* DEPTH */ +/*0x20*/volatile unsigned int y; /* Y triangle(DOYF) */ + /* aadot(DYF) */ + /* ddline(DYF) */ + /* aaline(DYF) */ +/*0x24*/volatile unsigned int x; /* X triangle(DOXF) */ + /* aadot(DXF) */ + /* ddline(DXF) */ + /* aaline(DXF) */ +/*0x28*/unsigned int pad2[2]; /* Reserved */ +/*0x30*/volatile unsigned int ryf; /* Y (alias to DOYF) ddline(RYF) */ + /* aaline(RYF) */ + /* triangle(RYF) */ +/*0x34*/volatile unsigned int rxf; /* X ddline(RXF) */ + /* aaline(RXF) */ + /* triangle(RXF) */ +/*0x38*/unsigned int pad3[2]; /* Reserved */ +/*0x40*/volatile unsigned int dmyf; /* Y (alias to DOYF) triangle(DMYF) */ +/*0x44*/volatile unsigned int dmxf; /* X triangle(DMXF) */ +/*0x48*/unsigned int pad4[2]; /* Reserved */ +/*0x50*/volatile unsigned int ebyi; /* Y (alias to RYI) polygon(EBYI) */ +/*0x54*/volatile unsigned int ebxi; /* X polygon(EBXI) */ +/*0x58*/unsigned int pad5[2]; /* Reserved */ +/*0x60*/volatile unsigned int by; /* Y brline(RYI) */ + /* fastfill(OP) */ + /* polygon(YI) */ + /* rectangle(YI) */ + /* bcopy(SRCY) */ + /* vscroll(SRCY) */ +/*0x64*/volatile unsigned int bx; /* X brline(RXI) */ + /* polygon(XI) */ + /* rectangle(XI) */ + /* bcopy(SRCX) */ + /* vscroll(SRCX) */ + /* fastfill(GO) */ +/*0x68*/volatile unsigned int dy; /* destination Y fastfill(DSTY) */ + /* bcopy(DSRY) */ + /* vscroll(DSRY) */ +/*0x6c*/volatile unsigned int dx; /* destination X fastfill(DSTX) */ + /* bcopy(DSTX) */ + /* vscroll(DSTX) */ +/*0x70*/volatile unsigned int bh; /* Y (alias to RYI) brline(DYI) */ + /* dot(DYI) */ + /* polygon(ETYI) */ + /* Height fastfill(H) */ + /* bcopy(H) */ + /* vscroll(H) */ + /* Y count fastfill(NY) */ +/*0x74*/volatile unsigned int bw; /* X dot(DXI) */ + /* brline(DXI) */ + /* polygon(ETXI) */ + /* fastfill(W) */ + /* bcopy(W) */ + /* vscroll(W) */ + /* fastfill(NX) */ +/*0x78*/unsigned int pad6[2]; /* Reserved */ +/*0x80*/unsigned int pad7[32]; /* Reserved */ + + /* Setup Unit's vertex state register */ +/*100*/ volatile unsigned int suvtx; +/*104*/ unsigned int pad8[63]; /* Reserved */ + + /* Frame Buffer Control Registers */ +/*200*/ volatile unsigned int ppc; /* Pixel Processor Control */ +/*204*/ volatile unsigned int wid; /* Current WID */ +/*208*/ volatile unsigned int fg; /* FG data */ +/*20c*/ volatile unsigned int bg; /* BG data */ +/*210*/ volatile unsigned int consty; /* Constant Y */ +/*214*/ volatile unsigned int constz; /* Constant Z */ +/*218*/ volatile unsigned int xclip; /* X Clip */ +/*21c*/ volatile unsigned int dcss; /* Depth Cue Scale Slope */ +/*220*/ volatile unsigned int vclipmin; /* Viewclip XY Min Bounds */ +/*224*/ volatile unsigned int vclipmax; /* Viewclip XY Max Bounds */ +/*228*/ volatile unsigned int vclipzmin; /* Viewclip Z Min Bounds */ +/*22c*/ volatile unsigned int vclipzmax; /* Viewclip Z Max Bounds */ +/*230*/ volatile unsigned int dcsf; /* Depth Cue Scale Front Bound */ +/*234*/ volatile unsigned int dcsb; /* Depth Cue Scale Back Bound */ +/*238*/ volatile unsigned int dczf; /* Depth Cue Z Front */ +/*23c*/ volatile unsigned int dczb; /* Depth Cue Z Back */ +/*240*/ unsigned int pad9; /* Reserved */ +/*244*/ volatile unsigned int blendc; /* Alpha Blend Control */ +/*248*/ volatile unsigned int blendc1; /* Alpha Blend Color 1 */ +/*24c*/ volatile unsigned int blendc2; /* Alpha Blend Color 2 */ +/*250*/ volatile unsigned int fbramitc; /* FB RAM Interleave Test Control */ +/*254*/ volatile unsigned int fbc; /* Frame Buffer Control */ +/*258*/ volatile unsigned int rop; /* Raster OPeration */ +/*25c*/ volatile unsigned int cmp; /* Frame Buffer Compare */ +/*260*/ volatile unsigned int matchab; /* Buffer AB Match Mask */ +/*264*/ volatile unsigned int matchc; /* Buffer C(YZ) Match Mask */ +/*268*/ volatile unsigned int magnab; /* Buffer AB Magnitude Mask */ +/*26c*/ volatile unsigned int magnc; /* Buffer C(YZ) Magnitude Mask */ +/*270*/ volatile unsigned int fbcfg0; /* Frame Buffer Config 0 */ +/*274*/ volatile unsigned int fbcfg1; /* Frame Buffer Config 1 */ +/*278*/ volatile unsigned int fbcfg2; /* Frame Buffer Config 2 */ +/*27c*/ volatile unsigned int fbcfg3; /* Frame Buffer Config 3 */ +/*280*/ volatile unsigned int ppcfg; /* Pixel Processor Config */ +/*284*/ volatile unsigned int pick; /* Picking Control */ +/*288*/ volatile unsigned int fillmode; /* FillMode */ +/*28c*/ volatile unsigned int fbramwac; /* FB RAM Write Address Control */ +/*290*/ volatile unsigned int pmask; /* RGB PlaneMask */ +/*294*/ volatile unsigned int xpmask; /* X PlaneMask */ +/*298*/ volatile unsigned int ypmask; /* Y PlaneMask */ +/*29c*/ volatile unsigned int zpmask; /* Z PlaneMask */ +/*2a0*/ ffb_auxclip auxclip[4]; /* Auxilliary Viewport Clip */ + + /* New 3dRAM III support regs */ +/*2c0*/ volatile unsigned int rawblend2; +/*2c4*/ volatile unsigned int rawpreblend; +/*2c8*/ volatile unsigned int rawstencil; +/*2cc*/ volatile unsigned int rawstencilctl; +/*2d0*/ volatile unsigned int threedram1; +/*2d4*/ volatile unsigned int threedram2; +/*2d8*/ volatile unsigned int passin; +/*2dc*/ volatile unsigned int rawclrdepth; +/*2e0*/ volatile unsigned int rawpmask; +/*2e4*/ volatile unsigned int rawcsrc; +/*2e8*/ volatile unsigned int rawmatch; +/*2ec*/ volatile unsigned int rawmagn; +/*2f0*/ volatile unsigned int rawropblend; +/*2f4*/ volatile unsigned int rawcmp; +/*2f8*/ volatile unsigned int rawwac; +/*2fc*/ volatile unsigned int fbramid; + +/*300*/ volatile unsigned int drawop; /* Draw OPeration */ +/*304*/ unsigned int pad10[2]; /* Reserved */ +/*30c*/ volatile unsigned int lpat; /* Line Pattern control */ +/*310*/ unsigned int pad11; /* Reserved */ +/*314*/ volatile unsigned int fontxy; /* XY Font coordinate */ +/*318*/ volatile unsigned int fontw; /* Font Width */ +/*31c*/ volatile unsigned int fontinc; /* Font Increment */ +/*320*/ volatile unsigned int font; /* Font bits */ +/*324*/ unsigned int pad12[3]; /* Reserved */ +/*330*/ volatile unsigned int blend2; +/*334*/ volatile unsigned int preblend; +/*338*/ volatile unsigned int stencil; +/*33c*/ volatile unsigned int stencilctl; + +/*340*/ unsigned int pad13[4]; /* Reserved */ +/*350*/ volatile unsigned int dcss1; /* Depth Cue Scale Slope 1 */ +/*354*/ volatile unsigned int dcss2; /* Depth Cue Scale Slope 2 */ +/*358*/ volatile unsigned int dcss3; /* Depth Cue Scale Slope 3 */ +/*35c*/ volatile unsigned int widpmask; +/*360*/ volatile unsigned int dcs2; +/*364*/ volatile unsigned int dcs3; +/*368*/ volatile unsigned int dcs4; +/*36c*/ unsigned int pad14; /* Reserved */ +/*370*/ volatile unsigned int dcd2; +/*374*/ volatile unsigned int dcd3; +/*378*/ volatile unsigned int dcd4; +/*37c*/ unsigned int pad15; /* Reserved */ +/*380*/ volatile unsigned int pattern[32]; /* area Pattern */ +/*400*/ unsigned int pad16[8]; /* Reserved */ +/*420*/ volatile unsigned int reset; /* chip RESET */ +/*424*/ unsigned int pad17[247]; /* Reserved */ +/*800*/ volatile unsigned int devid; /* Device ID */ +/*804*/ unsigned int pad18[63]; /* Reserved */ +/*900*/ volatile unsigned int ucsr; /* User Control & Status Register */ +/*904*/ unsigned int pad19[31]; /* Reserved */ +/*980*/ volatile unsigned int mer; /* Mode Enable Register */ +/*984*/ unsigned int pad20[1439]; /* Reserved */ +} ffb_fbc, *ffb_fbcPtr; + +struct ffb_hw_context { + int is_2d_only; + + unsigned int ppc; + unsigned int wid; + unsigned int fg; + unsigned int bg; + unsigned int consty; + unsigned int constz; + unsigned int xclip; + unsigned int dcss; + unsigned int vclipmin; + unsigned int vclipmax; + unsigned int vclipzmin; + unsigned int vclipzmax; + unsigned int dcsf; + unsigned int dcsb; + unsigned int dczf; + unsigned int dczb; + unsigned int blendc; + unsigned int blendc1; + unsigned int blendc2; + unsigned int fbc; + unsigned int rop; + unsigned int cmp; + unsigned int matchab; + unsigned int matchc; + unsigned int magnab; + unsigned int magnc; + unsigned int pmask; + unsigned int xpmask; + unsigned int ypmask; + unsigned int zpmask; + unsigned int auxclip0min; + unsigned int auxclip0max; + unsigned int auxclip1min; + unsigned int auxclip1max; + unsigned int auxclip2min; + unsigned int auxclip2max; + unsigned int auxclip3min; + unsigned int auxclip3max; + unsigned int drawop; + unsigned int lpat; + unsigned int fontxy; + unsigned int fontw; + unsigned int fontinc; + unsigned int area_pattern[32]; + unsigned int ucsr; + unsigned int stencil; + unsigned int stencilctl; + unsigned int dcss1; + unsigned int dcss2; + unsigned int dcss3; + unsigned int dcs2; + unsigned int dcs3; + unsigned int dcs4; + unsigned int dcd2; + unsigned int dcd3; + unsigned int dcd4; + unsigned int mer; +}; + +#define FFB_MAX_CTXS 32 + +enum ffb_chip_type { + ffb1_prototype = 0, /* Early pre-FCS FFB */ + ffb1_standard, /* First FCS FFB, 100Mhz UPA, 66MHz gclk */ + ffb1_speedsort, /* Second FCS FFB, 100Mhz UPA, 75MHz gclk */ + ffb2_prototype, /* Early pre-FCS vertical FFB2 */ + ffb2_vertical, /* First FCS FFB2/vertical, 100Mhz UPA, 100MHZ gclk, + 75(SingleBuffer)/83(DoubleBuffer) MHz fclk */ + ffb2_vertical_plus, /* Second FCS FFB2/vertical, same timings */ + ffb2_horizontal, /* First FCS FFB2/horizontal, same timings as FFB2/vert */ + ffb2_horizontal_plus, /* Second FCS FFB2/horizontal, same timings */ + afb_m3, /* FCS Elite3D, 3 float chips */ + afb_m6 /* FCS Elite3D, 6 float chips */ +}; + +typedef struct ffb_dev_priv { + /* Misc software state. */ + int prom_node; + enum ffb_chip_type ffb_type; + u64 card_phys_base; + struct miscdevice miscdev; + + /* Controller registers. */ + ffb_fbcPtr regs; + + /* Context table. */ + struct ffb_hw_context *hw_state[FFB_MAX_CTXS]; +} ffb_dev_priv_t; + +extern unsigned long ffb_get_unmapped_area(struct file *filp, + unsigned long hint, + unsigned long len, + unsigned long pgoff, + unsigned long flags); +extern void ffb_set_context_ioctls(void); +extern drm_ioctl_desc_t DRM(ioctls)[]; + +extern int ffb_driver_context_switch(drm_device_t *dev, int old, int new); diff --git a/drivers/char/drm/gamma_context.h b/drivers/char/drm/gamma_context.h new file mode 100644 index 000000000000..d11b507f87ee --- /dev/null +++ b/drivers/char/drm/gamma_context.h @@ -0,0 +1,492 @@ +/* drm_context.h -- IOCTLs for generic contexts -*- linux-c -*- + * Created: Fri Nov 24 18:31:37 2000 by gareth@valinux.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Gareth Hughes + * ChangeLog: + * 2001-11-16 Torsten Duwe + * added context constructor/destructor hooks, + * needed by SiS driver's memory management. + */ + +/* ================================================================ + * Old-style context support -- only used by gamma. + */ + + +/* The drm_read and drm_write_string code (especially that which manages + the circular buffer), is based on Alessandro Rubini's LINUX DEVICE + DRIVERS (Cambridge: O'Reilly, 1998), pages 111-113. */ + +ssize_t gamma_fops_read(struct file *filp, char __user *buf, size_t count, loff_t *off) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int left; + int avail; + int send; + int cur; + + DRM_DEBUG("%p, %p\n", dev->buf_rp, dev->buf_wp); + + while (dev->buf_rp == dev->buf_wp) { + DRM_DEBUG(" sleeping\n"); + if (filp->f_flags & O_NONBLOCK) { + return -EAGAIN; + } + interruptible_sleep_on(&dev->buf_readers); + if (signal_pending(current)) { + DRM_DEBUG(" interrupted\n"); + return -ERESTARTSYS; + } + DRM_DEBUG(" awake\n"); + } + + left = (dev->buf_rp + DRM_BSZ - dev->buf_wp) % DRM_BSZ; + avail = DRM_BSZ - left; + send = DRM_MIN(avail, count); + + while (send) { + if (dev->buf_wp > dev->buf_rp) { + cur = DRM_MIN(send, dev->buf_wp - dev->buf_rp); + } else { + cur = DRM_MIN(send, dev->buf_end - dev->buf_rp); + } + if (copy_to_user(buf, dev->buf_rp, cur)) + return -EFAULT; + dev->buf_rp += cur; + if (dev->buf_rp == dev->buf_end) dev->buf_rp = dev->buf; + send -= cur; + } + + wake_up_interruptible(&dev->buf_writers); + return DRM_MIN(avail, count); +} + + +/* In an incredibly convoluted setup, the kernel module actually calls + * back into the X server to perform context switches on behalf of the + * 3d clients. + */ +int DRM(write_string)(drm_device_t *dev, const char *s) +{ + int left = (dev->buf_rp + DRM_BSZ - dev->buf_wp) % DRM_BSZ; + int send = strlen(s); + int count; + + DRM_DEBUG("%d left, %d to send (%p, %p)\n", + left, send, dev->buf_rp, dev->buf_wp); + + if (left == 1 || dev->buf_wp != dev->buf_rp) { + DRM_ERROR("Buffer not empty (%d left, wp = %p, rp = %p)\n", + left, + dev->buf_wp, + dev->buf_rp); + } + + while (send) { + if (dev->buf_wp >= dev->buf_rp) { + count = DRM_MIN(send, dev->buf_end - dev->buf_wp); + if (count == left) --count; /* Leave a hole */ + } else { + count = DRM_MIN(send, dev->buf_rp - dev->buf_wp - 1); + } + strncpy(dev->buf_wp, s, count); + dev->buf_wp += count; + if (dev->buf_wp == dev->buf_end) dev->buf_wp = dev->buf; + send -= count; + } + + if (dev->buf_async) kill_fasync(&dev->buf_async, SIGIO, POLL_IN); + + DRM_DEBUG("waking\n"); + wake_up_interruptible(&dev->buf_readers); + return 0; +} + +unsigned int gamma_fops_poll(struct file *filp, struct poll_table_struct *wait) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + + poll_wait(filp, &dev->buf_readers, wait); + if (dev->buf_wp != dev->buf_rp) return POLLIN | POLLRDNORM; + return 0; +} + +int DRM(context_switch)(drm_device_t *dev, int old, int new) +{ + char buf[64]; + drm_queue_t *q; + + if (test_and_set_bit(0, &dev->context_flag)) { + DRM_ERROR("Reentering -- FIXME\n"); + return -EBUSY; + } + + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new >= dev->queue_count) { + clear_bit(0, &dev->context_flag); + return -EINVAL; + } + + if (new == dev->last_context) { + clear_bit(0, &dev->context_flag); + return 0; + } + + q = dev->queuelist[new]; + atomic_inc(&q->use_count); + if (atomic_read(&q->use_count) == 1) { + atomic_dec(&q->use_count); + clear_bit(0, &dev->context_flag); + return -EINVAL; + } + + /* This causes the X server to wake up & do a bunch of hardware + * interaction to actually effect the context switch. + */ + sprintf(buf, "C %d %d\n", old, new); + DRM(write_string)(dev, buf); + + atomic_dec(&q->use_count); + + return 0; +} + +int DRM(context_switch_complete)(drm_device_t *dev, int new) +{ + drm_device_dma_t *dma = dev->dma; + + dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ + dev->last_switch = jiffies; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Lock isn't held after context switch\n"); + } + + if (!dma || !(dma->next_buffer && dma->next_buffer->while_locked)) { + if (DRM(lock_free)(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("Cannot free lock\n"); + } + } + + clear_bit(0, &dev->context_flag); + wake_up_interruptible(&dev->context_wait); + + return 0; +} + +static int DRM(init_queue)(drm_device_t *dev, drm_queue_t *q, drm_ctx_t *ctx) +{ + DRM_DEBUG("\n"); + + if (atomic_read(&q->use_count) != 1 + || atomic_read(&q->finalization) + || atomic_read(&q->block_count)) { + DRM_ERROR("New queue is already in use: u%d f%d b%d\n", + atomic_read(&q->use_count), + atomic_read(&q->finalization), + atomic_read(&q->block_count)); + } + + atomic_set(&q->finalization, 0); + atomic_set(&q->block_count, 0); + atomic_set(&q->block_read, 0); + atomic_set(&q->block_write, 0); + atomic_set(&q->total_queued, 0); + atomic_set(&q->total_flushed, 0); + atomic_set(&q->total_locks, 0); + + init_waitqueue_head(&q->write_queue); + init_waitqueue_head(&q->read_queue); + init_waitqueue_head(&q->flush_queue); + + q->flags = ctx->flags; + + DRM(waitlist_create)(&q->waitlist, dev->dma->buf_count); + + return 0; +} + + +/* drm_alloc_queue: +PRE: 1) dev->queuelist[0..dev->queue_count] is allocated and will not + disappear (so all deallocation must be done after IOCTLs are off) + 2) dev->queue_count < dev->queue_slots + 3) dev->queuelist[i].use_count == 0 and + dev->queuelist[i].finalization == 0 if i not in use +POST: 1) dev->queuelist[i].use_count == 1 + 2) dev->queue_count < dev->queue_slots */ + +static int DRM(alloc_queue)(drm_device_t *dev) +{ + int i; + drm_queue_t *queue; + int oldslots; + int newslots; + /* Check for a free queue */ + for (i = 0; i < dev->queue_count; i++) { + atomic_inc(&dev->queuelist[i]->use_count); + if (atomic_read(&dev->queuelist[i]->use_count) == 1 + && !atomic_read(&dev->queuelist[i]->finalization)) { + DRM_DEBUG("%d (free)\n", i); + return i; + } + atomic_dec(&dev->queuelist[i]->use_count); + } + /* Allocate a new queue */ + down(&dev->struct_sem); + + queue = DRM(alloc)(sizeof(*queue), DRM_MEM_QUEUES); + memset(queue, 0, sizeof(*queue)); + atomic_set(&queue->use_count, 1); + + ++dev->queue_count; + if (dev->queue_count >= dev->queue_slots) { + oldslots = dev->queue_slots * sizeof(*dev->queuelist); + if (!dev->queue_slots) dev->queue_slots = 1; + dev->queue_slots *= 2; + newslots = dev->queue_slots * sizeof(*dev->queuelist); + + dev->queuelist = DRM(realloc)(dev->queuelist, + oldslots, + newslots, + DRM_MEM_QUEUES); + if (!dev->queuelist) { + up(&dev->struct_sem); + DRM_DEBUG("out of memory\n"); + return -ENOMEM; + } + } + dev->queuelist[dev->queue_count-1] = queue; + + up(&dev->struct_sem); + DRM_DEBUG("%d (new)\n", dev->queue_count - 1); + return dev->queue_count - 1; +} + +int DRM(resctx)(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_ctx_res_t __user *argp = (void __user *)arg; + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; + + DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); + if (copy_from_user(&res, argp, sizeof(res))) + return -EFAULT; + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + ctx.handle = i; + if (copy_to_user(&res.contexts[i], + &i, + sizeof(i))) + return -EFAULT; + } + } + res.count = DRM_RESERVED_CONTEXTS; + if (copy_to_user(argp, &res, sizeof(res))) + return -EFAULT; + return 0; +} + +int DRM(addctx)(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + drm_ctx_t __user *argp = (void __user *)arg; + + if (copy_from_user(&ctx, argp, sizeof(ctx))) + return -EFAULT; + if ((ctx.handle = DRM(alloc_queue)(dev)) == DRM_KERNEL_CONTEXT) { + /* Init kernel's context and get a new one. */ + DRM(init_queue)(dev, dev->queuelist[ctx.handle], &ctx); + ctx.handle = DRM(alloc_queue)(dev); + } + DRM(init_queue)(dev, dev->queuelist[ctx.handle], &ctx); + DRM_DEBUG("%d\n", ctx.handle); + if (copy_to_user(argp, &ctx, sizeof(ctx))) + return -EFAULT; + return 0; +} + +int DRM(modctx)(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + drm_queue_t *q; + + if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + return -EFAULT; + + DRM_DEBUG("%d\n", ctx.handle); + + if (ctx.handle < 0 || ctx.handle >= dev->queue_count) return -EINVAL; + q = dev->queuelist[ctx.handle]; + + atomic_inc(&q->use_count); + if (atomic_read(&q->use_count) == 1) { + /* No longer in use */ + atomic_dec(&q->use_count); + return -EINVAL; + } + + if (DRM_BUFCOUNT(&q->waitlist)) { + atomic_dec(&q->use_count); + return -EBUSY; + } + + q->flags = ctx.flags; + + atomic_dec(&q->use_count); + return 0; +} + +int DRM(getctx)(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t __user *argp = (void __user *)arg; + drm_ctx_t ctx; + drm_queue_t *q; + + if (copy_from_user(&ctx, argp, sizeof(ctx))) + return -EFAULT; + + DRM_DEBUG("%d\n", ctx.handle); + + if (ctx.handle >= dev->queue_count) return -EINVAL; + q = dev->queuelist[ctx.handle]; + + atomic_inc(&q->use_count); + if (atomic_read(&q->use_count) == 1) { + /* No longer in use */ + atomic_dec(&q->use_count); + return -EINVAL; + } + + ctx.flags = q->flags; + atomic_dec(&q->use_count); + + if (copy_to_user(argp, &ctx, sizeof(ctx))) + return -EFAULT; + + return 0; +} + +int DRM(switchctx)(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + return DRM(context_switch)(dev, dev->last_context, ctx.handle); +} + +int DRM(newctx)(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + DRM(context_switch_complete)(dev, ctx.handle); + + return 0; +} + +int DRM(rmctx)(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + drm_queue_t *q; + drm_buf_t *buf; + + if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + return -EFAULT; + DRM_DEBUG("%d\n", ctx.handle); + + if (ctx.handle >= dev->queue_count) return -EINVAL; + q = dev->queuelist[ctx.handle]; + + atomic_inc(&q->use_count); + if (atomic_read(&q->use_count) == 1) { + /* No longer in use */ + atomic_dec(&q->use_count); + return -EINVAL; + } + + atomic_inc(&q->finalization); /* Mark queue in finalization state */ + atomic_sub(2, &q->use_count); /* Mark queue as unused (pending + finalization) */ + + while (test_and_set_bit(0, &dev->interrupt_flag)) { + schedule(); + if (signal_pending(current)) { + clear_bit(0, &dev->interrupt_flag); + return -EINTR; + } + } + /* Remove queued buffers */ + while ((buf = DRM(waitlist_get)(&q->waitlist))) { + DRM(free_buffer)(dev, buf); + } + clear_bit(0, &dev->interrupt_flag); + + /* Wakeup blocked processes */ + wake_up_interruptible(&q->read_queue); + wake_up_interruptible(&q->write_queue); + wake_up_interruptible(&q->flush_queue); + + /* Finalization over. Queue is made + available when both use_count and + finalization become 0, which won't + happen until all the waiting processes + stop waiting. */ + atomic_dec(&q->finalization); + return 0; +} + diff --git a/drivers/char/drm/gamma_dma.c b/drivers/char/drm/gamma_dma.c new file mode 100644 index 000000000000..e486fb8d31e9 --- /dev/null +++ b/drivers/char/drm/gamma_dma.c @@ -0,0 +1,946 @@ +/* gamma_dma.c -- DMA support for GMX 2000 -*- linux-c -*- + * Created: Fri Mar 19 14:30:16 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#include "gamma.h" +#include "drmP.h" +#include "drm.h" +#include "gamma_drm.h" +#include "gamma_drv.h" + +#include /* For task queue support */ +#include + +static inline void gamma_dma_dispatch(drm_device_t *dev, unsigned long address, + unsigned long length) +{ + drm_gamma_private_t *dev_priv = + (drm_gamma_private_t *)dev->dev_private; + mb(); + while ( GAMMA_READ(GAMMA_INFIFOSPACE) < 2) + cpu_relax(); + + GAMMA_WRITE(GAMMA_DMAADDRESS, address); + + while (GAMMA_READ(GAMMA_GCOMMANDSTATUS) != 4) + cpu_relax(); + + GAMMA_WRITE(GAMMA_DMACOUNT, length / 4); +} + +void gamma_dma_quiescent_single(drm_device_t *dev) +{ + drm_gamma_private_t *dev_priv = + (drm_gamma_private_t *)dev->dev_private; + while (GAMMA_READ(GAMMA_DMACOUNT)) + cpu_relax(); + + while (GAMMA_READ(GAMMA_INFIFOSPACE) < 2) + cpu_relax(); + + GAMMA_WRITE(GAMMA_FILTERMODE, 1 << 10); + GAMMA_WRITE(GAMMA_SYNC, 0); + + do { + while (!GAMMA_READ(GAMMA_OUTFIFOWORDS)) + cpu_relax(); + } while (GAMMA_READ(GAMMA_OUTPUTFIFO) != GAMMA_SYNC_TAG); +} + +void gamma_dma_quiescent_dual(drm_device_t *dev) +{ + drm_gamma_private_t *dev_priv = + (drm_gamma_private_t *)dev->dev_private; + while (GAMMA_READ(GAMMA_DMACOUNT)) + cpu_relax(); + + while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3) + cpu_relax(); + + GAMMA_WRITE(GAMMA_BROADCASTMASK, 3); + GAMMA_WRITE(GAMMA_FILTERMODE, 1 << 10); + GAMMA_WRITE(GAMMA_SYNC, 0); + + /* Read from first MX */ + do { + while (!GAMMA_READ(GAMMA_OUTFIFOWORDS)) + cpu_relax(); + } while (GAMMA_READ(GAMMA_OUTPUTFIFO) != GAMMA_SYNC_TAG); + + /* Read from second MX */ + do { + while (!GAMMA_READ(GAMMA_OUTFIFOWORDS + 0x10000)) + cpu_relax(); + } while (GAMMA_READ(GAMMA_OUTPUTFIFO + 0x10000) != GAMMA_SYNC_TAG); +} + +void gamma_dma_ready(drm_device_t *dev) +{ + drm_gamma_private_t *dev_priv = + (drm_gamma_private_t *)dev->dev_private; + while (GAMMA_READ(GAMMA_DMACOUNT)) + cpu_relax(); +} + +static inline int gamma_dma_is_ready(drm_device_t *dev) +{ + drm_gamma_private_t *dev_priv = + (drm_gamma_private_t *)dev->dev_private; + return (!GAMMA_READ(GAMMA_DMACOUNT)); +} + +irqreturn_t gamma_driver_irq_handler( DRM_IRQ_ARGS ) +{ + drm_device_t *dev = (drm_device_t *)arg; + drm_device_dma_t *dma = dev->dma; + drm_gamma_private_t *dev_priv = + (drm_gamma_private_t *)dev->dev_private; + + /* FIXME: should check whether we're actually interested in the interrupt? */ + atomic_inc(&dev->counts[6]); /* _DRM_STAT_IRQ */ + + while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3) + cpu_relax(); + + GAMMA_WRITE(GAMMA_GDELAYTIMER, 0xc350/2); /* 0x05S */ + GAMMA_WRITE(GAMMA_GCOMMANDINTFLAGS, 8); + GAMMA_WRITE(GAMMA_GINTFLAGS, 0x2001); + if (gamma_dma_is_ready(dev)) { + /* Free previous buffer */ + if (test_and_set_bit(0, &dev->dma_flag)) + return IRQ_HANDLED; + if (dma->this_buffer) { + gamma_free_buffer(dev, dma->this_buffer); + dma->this_buffer = NULL; + } + clear_bit(0, &dev->dma_flag); + + /* Dispatch new buffer */ + schedule_work(&dev->work); + } + return IRQ_HANDLED; +} + +/* Only called by gamma_dma_schedule. */ +static int gamma_do_dma(drm_device_t *dev, int locked) +{ + unsigned long address; + unsigned long length; + drm_buf_t *buf; + int retcode = 0; + drm_device_dma_t *dma = dev->dma; + + if (test_and_set_bit(0, &dev->dma_flag)) return -EBUSY; + + + if (!dma->next_buffer) { + DRM_ERROR("No next_buffer\n"); + clear_bit(0, &dev->dma_flag); + return -EINVAL; + } + + buf = dma->next_buffer; + /* WE NOW ARE ON LOGICAL PAGES!! - using page table setup in dma_init */ + /* So we pass the buffer index value into the physical page offset */ + address = buf->idx << 12; + length = buf->used; + + DRM_DEBUG("context %d, buffer %d (%ld bytes)\n", + buf->context, buf->idx, length); + + if (buf->list == DRM_LIST_RECLAIM) { + gamma_clear_next_buffer(dev); + gamma_free_buffer(dev, buf); + clear_bit(0, &dev->dma_flag); + return -EINVAL; + } + + if (!length) { + DRM_ERROR("0 length buffer\n"); + gamma_clear_next_buffer(dev); + gamma_free_buffer(dev, buf); + clear_bit(0, &dev->dma_flag); + return 0; + } + + if (!gamma_dma_is_ready(dev)) { + clear_bit(0, &dev->dma_flag); + return -EBUSY; + } + + if (buf->while_locked) { + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Dispatching buffer %d from pid %d" + " \"while locked\", but no lock held\n", + buf->idx, current->pid); + } + } else { + if (!locked && !gamma_lock_take(&dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + clear_bit(0, &dev->dma_flag); + return -EBUSY; + } + } + + if (dev->last_context != buf->context + && !(dev->queuelist[buf->context]->flags + & _DRM_CONTEXT_PRESERVED)) { + /* PRE: dev->last_context != buf->context */ + if (DRM(context_switch)(dev, dev->last_context, + buf->context)) { + DRM(clear_next_buffer)(dev); + DRM(free_buffer)(dev, buf); + } + retcode = -EBUSY; + goto cleanup; + + /* POST: we will wait for the context + switch and will dispatch on a later call + when dev->last_context == buf->context. + NOTE WE HOLD THE LOCK THROUGHOUT THIS + TIME! */ + } + + gamma_clear_next_buffer(dev); + buf->pending = 1; + buf->waiting = 0; + buf->list = DRM_LIST_PEND; + + /* WE NOW ARE ON LOGICAL PAGES!!! - overriding address */ + address = buf->idx << 12; + + gamma_dma_dispatch(dev, address, length); + gamma_free_buffer(dev, dma->this_buffer); + dma->this_buffer = buf; + + atomic_inc(&dev->counts[7]); /* _DRM_STAT_DMA */ + atomic_add(length, &dev->counts[8]); /* _DRM_STAT_PRIMARY */ + + if (!buf->while_locked && !dev->context_flag && !locked) { + if (gamma_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); + } + } +cleanup: + + clear_bit(0, &dev->dma_flag); + + + return retcode; +} + +static void gamma_dma_timer_bh(unsigned long dev) +{ + gamma_dma_schedule((drm_device_t *)dev, 0); +} + +void gamma_irq_immediate_bh(void *dev) +{ + gamma_dma_schedule(dev, 0); +} + +int gamma_dma_schedule(drm_device_t *dev, int locked) +{ + int next; + drm_queue_t *q; + drm_buf_t *buf; + int retcode = 0; + int processed = 0; + int missed; + int expire = 20; + drm_device_dma_t *dma = dev->dma; + + if (test_and_set_bit(0, &dev->interrupt_flag)) { + /* Not reentrant */ + atomic_inc(&dev->counts[10]); /* _DRM_STAT_MISSED */ + return -EBUSY; + } + missed = atomic_read(&dev->counts[10]); + + +again: + if (dev->context_flag) { + clear_bit(0, &dev->interrupt_flag); + return -EBUSY; + } + if (dma->next_buffer) { + /* Unsent buffer that was previously + selected, but that couldn't be sent + because the lock could not be obtained + or the DMA engine wasn't ready. Try + again. */ + if (!(retcode = gamma_do_dma(dev, locked))) ++processed; + } else { + do { + next = gamma_select_queue(dev, gamma_dma_timer_bh); + if (next >= 0) { + q = dev->queuelist[next]; + buf = gamma_waitlist_get(&q->waitlist); + dma->next_buffer = buf; + dma->next_queue = q; + if (buf && buf->list == DRM_LIST_RECLAIM) { + gamma_clear_next_buffer(dev); + gamma_free_buffer(dev, buf); + } + } + } while (next >= 0 && !dma->next_buffer); + if (dma->next_buffer) { + if (!(retcode = gamma_do_dma(dev, locked))) { + ++processed; + } + } + } + + if (--expire) { + if (missed != atomic_read(&dev->counts[10])) { + if (gamma_dma_is_ready(dev)) goto again; + } + if (processed && gamma_dma_is_ready(dev)) { + processed = 0; + goto again; + } + } + + clear_bit(0, &dev->interrupt_flag); + + return retcode; +} + +static int gamma_dma_priority(struct file *filp, + drm_device_t *dev, drm_dma_t *d) +{ + unsigned long address; + unsigned long length; + int must_free = 0; + int retcode = 0; + int i; + int idx; + drm_buf_t *buf; + drm_buf_t *last_buf = NULL; + drm_device_dma_t *dma = dev->dma; + int *send_indices = NULL; + int *send_sizes = NULL; + + DECLARE_WAITQUEUE(entry, current); + + /* Turn off interrupt handling */ + while (test_and_set_bit(0, &dev->interrupt_flag)) { + schedule(); + if (signal_pending(current)) return -EINTR; + } + if (!(d->flags & _DRM_DMA_WHILE_LOCKED)) { + while (!gamma_lock_take(&dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + schedule(); + if (signal_pending(current)) { + clear_bit(0, &dev->interrupt_flag); + return -EINTR; + } + } + ++must_free; + } + + send_indices = DRM(alloc)(d->send_count * sizeof(*send_indices), + DRM_MEM_DRIVER); + if (send_indices == NULL) + return -ENOMEM; + if (copy_from_user(send_indices, d->send_indices, + d->send_count * sizeof(*send_indices))) { + retcode = -EFAULT; + goto cleanup; + } + + send_sizes = DRM(alloc)(d->send_count * sizeof(*send_sizes), + DRM_MEM_DRIVER); + if (send_sizes == NULL) + return -ENOMEM; + if (copy_from_user(send_sizes, d->send_sizes, + d->send_count * sizeof(*send_sizes))) { + retcode = -EFAULT; + goto cleanup; + } + + for (i = 0; i < d->send_count; i++) { + idx = send_indices[i]; + if (idx < 0 || idx >= dma->buf_count) { + DRM_ERROR("Index %d (of %d max)\n", + send_indices[i], dma->buf_count - 1); + continue; + } + buf = dma->buflist[ idx ]; + if (buf->filp != filp) { + DRM_ERROR("Process %d using buffer not owned\n", + current->pid); + retcode = -EINVAL; + goto cleanup; + } + if (buf->list != DRM_LIST_NONE) { + DRM_ERROR("Process %d using buffer on list %d\n", + current->pid, buf->list); + retcode = -EINVAL; + goto cleanup; + } + /* This isn't a race condition on + buf->list, since our concern is the + buffer reclaim during the time the + process closes the /dev/drm? handle, so + it can't also be doing DMA. */ + buf->list = DRM_LIST_PRIO; + buf->used = send_sizes[i]; + buf->context = d->context; + buf->while_locked = d->flags & _DRM_DMA_WHILE_LOCKED; + address = (unsigned long)buf->address; + length = buf->used; + if (!length) { + DRM_ERROR("0 length buffer\n"); + } + if (buf->pending) { + DRM_ERROR("Sending pending buffer:" + " buffer %d, offset %d\n", + send_indices[i], i); + retcode = -EINVAL; + goto cleanup; + } + if (buf->waiting) { + DRM_ERROR("Sending waiting buffer:" + " buffer %d, offset %d\n", + send_indices[i], i); + retcode = -EINVAL; + goto cleanup; + } + buf->pending = 1; + + if (dev->last_context != buf->context + && !(dev->queuelist[buf->context]->flags + & _DRM_CONTEXT_PRESERVED)) { + add_wait_queue(&dev->context_wait, &entry); + current->state = TASK_INTERRUPTIBLE; + /* PRE: dev->last_context != buf->context */ + DRM(context_switch)(dev, dev->last_context, + buf->context); + /* POST: we will wait for the context + switch and will dispatch on a later call + when dev->last_context == buf->context. + NOTE WE HOLD THE LOCK THROUGHOUT THIS + TIME! */ + schedule(); + current->state = TASK_RUNNING; + remove_wait_queue(&dev->context_wait, &entry); + if (signal_pending(current)) { + retcode = -EINTR; + goto cleanup; + } + if (dev->last_context != buf->context) { + DRM_ERROR("Context mismatch: %d %d\n", + dev->last_context, + buf->context); + } + } + + gamma_dma_dispatch(dev, address, length); + atomic_inc(&dev->counts[9]); /* _DRM_STAT_SPECIAL */ + atomic_add(length, &dev->counts[8]); /* _DRM_STAT_PRIMARY */ + + if (last_buf) { + gamma_free_buffer(dev, last_buf); + } + last_buf = buf; + } + + +cleanup: + if (last_buf) { + gamma_dma_ready(dev); + gamma_free_buffer(dev, last_buf); + } + if (send_indices) + DRM(free)(send_indices, d->send_count * sizeof(*send_indices), + DRM_MEM_DRIVER); + if (send_sizes) + DRM(free)(send_sizes, d->send_count * sizeof(*send_sizes), + DRM_MEM_DRIVER); + + if (must_free && !dev->context_flag) { + if (gamma_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); + } + } + clear_bit(0, &dev->interrupt_flag); + return retcode; +} + +static int gamma_dma_send_buffers(struct file *filp, + drm_device_t *dev, drm_dma_t *d) +{ + DECLARE_WAITQUEUE(entry, current); + drm_buf_t *last_buf = NULL; + int retcode = 0; + drm_device_dma_t *dma = dev->dma; + int send_index; + + if (get_user(send_index, &d->send_indices[d->send_count-1])) + return -EFAULT; + + if (d->flags & _DRM_DMA_BLOCK) { + last_buf = dma->buflist[send_index]; + add_wait_queue(&last_buf->dma_wait, &entry); + } + + if ((retcode = gamma_dma_enqueue(filp, d))) { + if (d->flags & _DRM_DMA_BLOCK) + remove_wait_queue(&last_buf->dma_wait, &entry); + return retcode; + } + + gamma_dma_schedule(dev, 0); + + if (d->flags & _DRM_DMA_BLOCK) { + DRM_DEBUG("%d waiting\n", current->pid); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!last_buf->waiting && !last_buf->pending) + break; /* finished */ + schedule(); + if (signal_pending(current)) { + retcode = -EINTR; /* Can't restart */ + break; + } + } + current->state = TASK_RUNNING; + DRM_DEBUG("%d running\n", current->pid); + remove_wait_queue(&last_buf->dma_wait, &entry); + if (!retcode + || (last_buf->list==DRM_LIST_PEND && !last_buf->pending)) { + if (!waitqueue_active(&last_buf->dma_wait)) { + gamma_free_buffer(dev, last_buf); + } + } + if (retcode) { + DRM_ERROR("ctx%d w%d p%d c%ld i%d l%d pid:%d\n", + d->context, + last_buf->waiting, + last_buf->pending, + (long)DRM_WAITCOUNT(dev, d->context), + last_buf->idx, + last_buf->list, + current->pid); + } + } + return retcode; +} + +int gamma_dma(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + int retcode = 0; + drm_dma_t __user *argp = (void __user *)arg; + drm_dma_t d; + + if (copy_from_user(&d, argp, sizeof(d))) + return -EFAULT; + + if (d.send_count < 0 || d.send_count > dma->buf_count) { + DRM_ERROR("Process %d trying to send %d buffers (of %d max)\n", + current->pid, d.send_count, dma->buf_count); + return -EINVAL; + } + + if (d.request_count < 0 || d.request_count > dma->buf_count) { + DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", + current->pid, d.request_count, dma->buf_count); + return -EINVAL; + } + + if (d.send_count) { + if (d.flags & _DRM_DMA_PRIORITY) + retcode = gamma_dma_priority(filp, dev, &d); + else + retcode = gamma_dma_send_buffers(filp, dev, &d); + } + + d.granted_count = 0; + + if (!retcode && d.request_count) { + retcode = gamma_dma_get_buffers(filp, &d); + } + + DRM_DEBUG("%d returning, granted = %d\n", + current->pid, d.granted_count); + if (copy_to_user(argp, &d, sizeof(d))) + return -EFAULT; + + return retcode; +} + +/* ============================================================= + * DMA initialization, cleanup + */ + +static int gamma_do_init_dma( drm_device_t *dev, drm_gamma_init_t *init ) +{ + drm_gamma_private_t *dev_priv; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + int i; + struct list_head *list; + unsigned long *pgt; + + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + dev_priv = DRM(alloc)( sizeof(drm_gamma_private_t), + DRM_MEM_DRIVER ); + if ( !dev_priv ) + return -ENOMEM; + + dev->dev_private = (void *)dev_priv; + + memset( dev_priv, 0, sizeof(drm_gamma_private_t) ); + + dev_priv->num_rast = init->num_rast; + + list_for_each(list, &dev->maplist->head) { + drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); + if( r_list->map && + r_list->map->type == _DRM_SHM && + r_list->map->flags & _DRM_CONTAINS_LOCK ) { + dev_priv->sarea = r_list->map; + break; + } + } + + dev_priv->mmio0 = drm_core_findmap(dev, init->mmio0); + dev_priv->mmio1 = drm_core_findmap(dev, init->mmio1); + dev_priv->mmio2 = drm_core_findmap(dev, init->mmio2); + dev_priv->mmio3 = drm_core_findmap(dev, init->mmio3); + + dev_priv->sarea_priv = (drm_gamma_sarea_t *) + ((u8 *)dev_priv->sarea->handle + + init->sarea_priv_offset); + + if (init->pcimode) { + buf = dma->buflist[GLINT_DRI_BUF_COUNT]; + pgt = buf->address; + + for (i = 0; i < GLINT_DRI_BUF_COUNT; i++) { + buf = dma->buflist[i]; + *pgt = virt_to_phys((void*)buf->address) | 0x07; + pgt++; + } + + buf = dma->buflist[GLINT_DRI_BUF_COUNT]; + } else { + dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); + drm_core_ioremap( dev->agp_buffer_map, dev); + + buf = dma->buflist[GLINT_DRI_BUF_COUNT]; + pgt = buf->address; + + for (i = 0; i < GLINT_DRI_BUF_COUNT; i++) { + buf = dma->buflist[i]; + *pgt = (unsigned long)buf->address + 0x07; + pgt++; + } + + buf = dma->buflist[GLINT_DRI_BUF_COUNT]; + + while (GAMMA_READ(GAMMA_INFIFOSPACE) < 1); + GAMMA_WRITE( GAMMA_GDMACONTROL, 0xe); + } + while (GAMMA_READ(GAMMA_INFIFOSPACE) < 2); + GAMMA_WRITE( GAMMA_PAGETABLEADDR, virt_to_phys((void*)buf->address) ); + GAMMA_WRITE( GAMMA_PAGETABLELENGTH, 2 ); + + return 0; +} + +int gamma_do_cleanup_dma( drm_device_t *dev ) +{ + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + /* Make sure interrupts are disabled here because the uninstall ioctl + * may not have been called from userspace and after dev_private + * is freed, it's too late. + */ + if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) + if ( dev->irq_enabled ) + DRM(irq_uninstall)(dev); + + if ( dev->dev_private ) { + + if ( dev->agp_buffer_map != NULL ) + drm_core_ioremapfree( dev->agp_buffer_map, dev ); + + DRM(free)( dev->dev_private, sizeof(drm_gamma_private_t), + DRM_MEM_DRIVER ); + dev->dev_private = NULL; + } + + return 0; +} + +int gamma_dma_init( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_gamma_init_t init; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( copy_from_user( &init, (drm_gamma_init_t __user *)arg, sizeof(init) ) ) + return -EFAULT; + + switch ( init.func ) { + case GAMMA_INIT_DMA: + return gamma_do_init_dma( dev, &init ); + case GAMMA_CLEANUP_DMA: + return gamma_do_cleanup_dma( dev ); + } + + return -EINVAL; +} + +static int gamma_do_copy_dma( drm_device_t *dev, drm_gamma_copy_t *copy ) +{ + drm_device_dma_t *dma = dev->dma; + unsigned int *screenbuf; + + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + /* We've DRM_RESTRICTED this DMA buffer */ + + screenbuf = dma->buflist[ GLINT_DRI_BUF_COUNT + 1 ]->address; + +#if 0 + *buffer++ = 0x180; /* Tag (FilterMode) */ + *buffer++ = 0x200; /* Allow FBColor through */ + *buffer++ = 0x53B; /* Tag */ + *buffer++ = copy->Pitch; + *buffer++ = 0x53A; /* Tag */ + *buffer++ = copy->SrcAddress; + *buffer++ = 0x539; /* Tag */ + *buffer++ = copy->WidthHeight; /* Initiates transfer */ + *buffer++ = 0x53C; /* Tag - DMAOutputAddress */ + *buffer++ = virt_to_phys((void*)screenbuf); + *buffer++ = 0x53D; /* Tag - DMAOutputCount */ + *buffer++ = copy->Count; /* Reads HostOutFifo BLOCKS until ..*/ + + /* Data now sitting in dma->buflist[ GLINT_DRI_BUF_COUNT + 1 ] */ + /* Now put it back to the screen */ + + *buffer++ = 0x180; /* Tag (FilterMode) */ + *buffer++ = 0x400; /* Allow Sync through */ + *buffer++ = 0x538; /* Tag - DMARectangleReadTarget */ + *buffer++ = 0x155; /* FBSourceData | count */ + *buffer++ = 0x537; /* Tag */ + *buffer++ = copy->Pitch; + *buffer++ = 0x536; /* Tag */ + *buffer++ = copy->DstAddress; + *buffer++ = 0x535; /* Tag */ + *buffer++ = copy->WidthHeight; /* Initiates transfer */ + *buffer++ = 0x530; /* Tag - DMAAddr */ + *buffer++ = virt_to_phys((void*)screenbuf); + *buffer++ = 0x531; + *buffer++ = copy->Count; /* initiates DMA transfer of color data */ +#endif + + /* need to dispatch it now */ + + return 0; +} + +int gamma_dma_copy( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_gamma_copy_t copy; + + if ( copy_from_user( ©, (drm_gamma_copy_t __user *)arg, sizeof(copy) ) ) + return -EFAULT; + + return gamma_do_copy_dma( dev, © ); +} + +/* ============================================================= + * Per Context SAREA Support + */ + +int gamma_getsareactx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_priv_map_t __user *argp = (void __user *)arg; + drm_ctx_priv_map_t request; + drm_map_t *map; + + if (copy_from_user(&request, argp, sizeof(request))) + return -EFAULT; + + down(&dev->struct_sem); + if ((int)request.ctx_id >= dev->max_context) { + up(&dev->struct_sem); + return -EINVAL; + } + + map = dev->context_sareas[request.ctx_id]; + up(&dev->struct_sem); + + request.handle = map->handle; + if (copy_to_user(argp, &request, sizeof(request))) + return -EFAULT; + return 0; +} + +int gamma_setsareactx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_priv_map_t request; + drm_map_t *map = NULL; + drm_map_list_t *r_list; + struct list_head *list; + + if (copy_from_user(&request, + (drm_ctx_priv_map_t __user *)arg, + sizeof(request))) + return -EFAULT; + + down(&dev->struct_sem); + r_list = NULL; + list_for_each(list, &dev->maplist->head) { + r_list = list_entry(list, drm_map_list_t, head); + if(r_list->map && + r_list->map->handle == request.handle) break; + } + if (list == &(dev->maplist->head)) { + up(&dev->struct_sem); + return -EINVAL; + } + map = r_list->map; + up(&dev->struct_sem); + + if (!map) return -EINVAL; + + down(&dev->struct_sem); + if ((int)request.ctx_id >= dev->max_context) { + up(&dev->struct_sem); + return -EINVAL; + } + dev->context_sareas[request.ctx_id] = map; + up(&dev->struct_sem); + return 0; +} + +void gamma_driver_irq_preinstall( drm_device_t *dev ) { + drm_gamma_private_t *dev_priv = + (drm_gamma_private_t *)dev->dev_private; + + while(GAMMA_READ(GAMMA_INFIFOSPACE) < 2) + cpu_relax(); + + GAMMA_WRITE( GAMMA_GCOMMANDMODE, 0x00000004 ); + GAMMA_WRITE( GAMMA_GDMACONTROL, 0x00000000 ); +} + +void gamma_driver_irq_postinstall( drm_device_t *dev ) { + drm_gamma_private_t *dev_priv = + (drm_gamma_private_t *)dev->dev_private; + + while(GAMMA_READ(GAMMA_INFIFOSPACE) < 3) + cpu_relax(); + + GAMMA_WRITE( GAMMA_GINTENABLE, 0x00002001 ); + GAMMA_WRITE( GAMMA_COMMANDINTENABLE, 0x00000008 ); + GAMMA_WRITE( GAMMA_GDELAYTIMER, 0x00039090 ); +} + +void gamma_driver_irq_uninstall( drm_device_t *dev ) { + drm_gamma_private_t *dev_priv = + (drm_gamma_private_t *)dev->dev_private; + if (!dev_priv) + return; + + while(GAMMA_READ(GAMMA_INFIFOSPACE) < 3) + cpu_relax(); + + GAMMA_WRITE( GAMMA_GDELAYTIMER, 0x00000000 ); + GAMMA_WRITE( GAMMA_COMMANDINTENABLE, 0x00000000 ); + GAMMA_WRITE( GAMMA_GINTENABLE, 0x00000000 ); +} + +extern drm_ioctl_desc_t DRM(ioctls)[]; + +static int gamma_driver_preinit(drm_device_t *dev) +{ + /* reset the finish ioctl */ + DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_FINISH)].func = DRM(finish); + return 0; +} + +static void gamma_driver_pretakedown(drm_device_t *dev) +{ + gamma_do_cleanup_dma(dev); +} + +static void gamma_driver_dma_ready(drm_device_t *dev) +{ + gamma_dma_ready(dev); +} + +static int gamma_driver_dma_quiescent(drm_device_t *dev) +{ + drm_gamma_private_t *dev_priv = ( + drm_gamma_private_t *)dev->dev_private; + if (dev_priv->num_rast == 2) + gamma_dma_quiescent_dual(dev); + else gamma_dma_quiescent_single(dev); + return 0; +} + +void gamma_driver_register_fns(drm_device_t *dev) +{ + dev->driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ; + DRM(fops).read = gamma_fops_read; + DRM(fops).poll = gamma_fops_poll; + dev->driver.preinit = gamma_driver_preinit; + dev->driver.pretakedown = gamma_driver_pretakedown; + dev->driver.dma_ready = gamma_driver_dma_ready; + dev->driver.dma_quiescent = gamma_driver_dma_quiescent; + dev->driver.dma_flush_block_and_flush = gamma_flush_block_and_flush; + dev->driver.dma_flush_unblock = gamma_flush_unblock; +} diff --git a/drivers/char/drm/gamma_drm.h b/drivers/char/drm/gamma_drm.h new file mode 100644 index 000000000000..20819ded0e15 --- /dev/null +++ b/drivers/char/drm/gamma_drm.h @@ -0,0 +1,90 @@ +#ifndef _GAMMA_DRM_H_ +#define _GAMMA_DRM_H_ + +typedef struct _drm_gamma_tex_region { + unsigned char next, prev; /* indices to form a circular LRU */ + unsigned char in_use; /* owned by a client, or free? */ + int age; /* tracked by clients to update local LRU's */ +} drm_gamma_tex_region_t; + +typedef struct { + unsigned int GDeltaMode; + unsigned int GDepthMode; + unsigned int GGeometryMode; + unsigned int GTransformMode; +} drm_gamma_context_regs_t; + +typedef struct _drm_gamma_sarea { + drm_gamma_context_regs_t context_state; + + unsigned int dirty; + + + /* Maintain an LRU of contiguous regions of texture space. If + * you think you own a region of texture memory, and it has an + * age different to the one you set, then you are mistaken and + * it has been stolen by another client. If global texAge + * hasn't changed, there is no need to walk the list. + * + * These regions can be used as a proxy for the fine-grained + * texture information of other clients - by maintaining them + * in the same lru which is used to age their own textures, + * clients have an approximate lru for the whole of global + * texture space, and can make informed decisions as to which + * areas to kick out. There is no need to choose whether to + * kick out your own texture or someone else's - simply eject + * them all in LRU order. + */ + +#define GAMMA_NR_TEX_REGIONS 64 + drm_gamma_tex_region_t texList[GAMMA_NR_TEX_REGIONS+1]; + /* Last elt is sentinal */ + int texAge; /* last time texture was uploaded */ + int last_enqueue; /* last time a buffer was enqueued */ + int last_dispatch; /* age of the most recently dispatched buffer */ + int last_quiescent; /* */ + int ctxOwner; /* last context to upload state */ + + int vertex_prim; +} drm_gamma_sarea_t; + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmGamma.h) + */ + +/* Gamma specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_GAMMA_INIT DRM_IOW( 0x40, drm_gamma_init_t) +#define DRM_IOCTL_GAMMA_COPY DRM_IOW( 0x41, drm_gamma_copy_t) + +typedef struct drm_gamma_copy { + unsigned int DMAOutputAddress; + unsigned int DMAOutputCount; + unsigned int DMAReadGLINTSource; + unsigned int DMARectangleWriteAddress; + unsigned int DMARectangleWriteLinePitch; + unsigned int DMARectangleWrite; + unsigned int DMARectangleReadAddress; + unsigned int DMARectangleReadLinePitch; + unsigned int DMARectangleRead; + unsigned int DMARectangleReadTarget; +} drm_gamma_copy_t; + +typedef struct drm_gamma_init { + enum { + GAMMA_INIT_DMA = 0x01, + GAMMA_CLEANUP_DMA = 0x02 + } func; + + int sarea_priv_offset; + int pcimode; + unsigned int mmio0; + unsigned int mmio1; + unsigned int mmio2; + unsigned int mmio3; + unsigned int buffers_offset; + int num_rast; +} drm_gamma_init_t; + +#endif /* _GAMMA_DRM_H_ */ diff --git a/drivers/char/drm/gamma_drv.c b/drivers/char/drm/gamma_drv.c new file mode 100644 index 000000000000..e7e64b62792a --- /dev/null +++ b/drivers/char/drm/gamma_drv.c @@ -0,0 +1,59 @@ +/* gamma.c -- 3dlabs GMX 2000 driver -*- linux-c -*- + * Created: Mon Jan 4 08:58:31 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Gareth Hughes + */ + +#include +#include "gamma.h" +#include "drmP.h" +#include "drm.h" +#include "gamma_drm.h" +#include "gamma_drv.h" + +#include "drm_auth.h" +#include "drm_agpsupport.h" +#include "drm_bufs.h" +#include "gamma_context.h" /* NOTE! */ +#include "drm_dma.h" +#include "gamma_old_dma.h" /* NOTE */ +#include "drm_drawable.h" +#include "drm_drv.h" + +#include "drm_fops.h" +#include "drm_init.h" +#include "drm_ioctl.h" +#include "drm_irq.h" +#include "gamma_lists.h" /* NOTE */ +#include "drm_lock.h" +#include "gamma_lock.h" /* NOTE */ +#include "drm_memory.h" +#include "drm_proc.h" +#include "drm_vm.h" +#include "drm_stub.h" +#include "drm_scatter.h" diff --git a/drivers/char/drm/gamma_drv.h b/drivers/char/drm/gamma_drv.h new file mode 100644 index 000000000000..146fcc6253cd --- /dev/null +++ b/drivers/char/drm/gamma_drv.h @@ -0,0 +1,147 @@ +/* gamma_drv.h -- Private header for 3dlabs GMX 2000 driver -*- linux-c -*- + * Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * + */ + +#ifndef _GAMMA_DRV_H_ +#define _GAMMA_DRV_H_ + +typedef struct drm_gamma_private { + drm_gamma_sarea_t *sarea_priv; + drm_map_t *sarea; + drm_map_t *mmio0; + drm_map_t *mmio1; + drm_map_t *mmio2; + drm_map_t *mmio3; + int num_rast; +} drm_gamma_private_t; + + /* gamma_dma.c */ +extern int gamma_dma_init( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int gamma_dma_copy( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); + +extern int gamma_do_cleanup_dma( drm_device_t *dev ); +extern void gamma_dma_ready(drm_device_t *dev); +extern void gamma_dma_quiescent_single(drm_device_t *dev); +extern void gamma_dma_quiescent_dual(drm_device_t *dev); + + /* gamma_dma.c */ +extern int gamma_dma_schedule(drm_device_t *dev, int locked); +extern int gamma_dma(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int gamma_find_devices(void); +extern int gamma_found(void); + +/* Gamma-specific code pulled from drm_fops.h: + */ +extern int DRM(finish)(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int DRM(flush_unblock)(drm_device_t *dev, int context, + drm_lock_flags_t flags); +extern int DRM(flush_block_and_flush)(drm_device_t *dev, int context, + drm_lock_flags_t flags); + +/* Gamma-specific code pulled from drm_dma.h: + */ +extern void DRM(clear_next_buffer)(drm_device_t *dev); +extern int DRM(select_queue)(drm_device_t *dev, + void (*wrapper)(unsigned long)); +extern int DRM(dma_enqueue)(struct file *filp, drm_dma_t *dma); +extern int DRM(dma_get_buffers)(struct file *filp, drm_dma_t *dma); + + +/* Gamma-specific code pulled from drm_lists.h (now renamed gamma_lists.h): + */ +extern int DRM(waitlist_create)(drm_waitlist_t *bl, int count); +extern int DRM(waitlist_destroy)(drm_waitlist_t *bl); +extern int DRM(waitlist_put)(drm_waitlist_t *bl, drm_buf_t *buf); +extern drm_buf_t *DRM(waitlist_get)(drm_waitlist_t *bl); +extern int DRM(freelist_create)(drm_freelist_t *bl, int count); +extern int DRM(freelist_destroy)(drm_freelist_t *bl); +extern int DRM(freelist_put)(drm_device_t *dev, drm_freelist_t *bl, + drm_buf_t *buf); +extern drm_buf_t *DRM(freelist_get)(drm_freelist_t *bl, int block); + +/* externs for gamma changes to the ops */ +extern struct file_operations DRM(fops); +extern unsigned int gamma_fops_poll(struct file *filp, struct poll_table_struct *wait); +extern ssize_t gamma_fops_read(struct file *filp, char __user *buf, size_t count, loff_t *off); + + +#define GLINT_DRI_BUF_COUNT 256 + +#define GAMMA_OFF(reg) \ + ((reg < 0x1000) \ + ? reg \ + : ((reg < 0x10000) \ + ? (reg - 0x1000) \ + : ((reg < 0x11000) \ + ? (reg - 0x10000) \ + : (reg - 0x11000)))) + +#define GAMMA_BASE(reg) ((unsigned long) \ + ((reg < 0x1000) ? dev_priv->mmio0->handle : \ + ((reg < 0x10000) ? dev_priv->mmio1->handle : \ + ((reg < 0x11000) ? dev_priv->mmio2->handle : \ + dev_priv->mmio3->handle)))) +#define GAMMA_ADDR(reg) (GAMMA_BASE(reg) + GAMMA_OFF(reg)) +#define GAMMA_DEREF(reg) *(__volatile__ int *)GAMMA_ADDR(reg) +#define GAMMA_READ(reg) GAMMA_DEREF(reg) +#define GAMMA_WRITE(reg,val) do { GAMMA_DEREF(reg) = val; } while (0) + +#define GAMMA_BROADCASTMASK 0x9378 +#define GAMMA_COMMANDINTENABLE 0x0c48 +#define GAMMA_DMAADDRESS 0x0028 +#define GAMMA_DMACOUNT 0x0030 +#define GAMMA_FILTERMODE 0x8c00 +#define GAMMA_GCOMMANDINTFLAGS 0x0c50 +#define GAMMA_GCOMMANDMODE 0x0c40 +#define GAMMA_QUEUED_DMA_MODE 1<<1 +#define GAMMA_GCOMMANDSTATUS 0x0c60 +#define GAMMA_GDELAYTIMER 0x0c38 +#define GAMMA_GDMACONTROL 0x0060 +#define GAMMA_USE_AGP 1<<1 +#define GAMMA_GINTENABLE 0x0808 +#define GAMMA_GINTFLAGS 0x0810 +#define GAMMA_INFIFOSPACE 0x0018 +#define GAMMA_OUTFIFOWORDS 0x0020 +#define GAMMA_OUTPUTFIFO 0x2000 +#define GAMMA_SYNC 0x8c40 +#define GAMMA_SYNC_TAG 0x0188 +#define GAMMA_PAGETABLEADDR 0x0C00 +#define GAMMA_PAGETABLELENGTH 0x0C08 + +#define GAMMA_PASSTHROUGH 0x1FE +#define GAMMA_DMAADDRTAG 0x530 +#define GAMMA_DMACOUNTTAG 0x531 +#define GAMMA_COMMANDINTTAG 0x532 + +#endif diff --git a/drivers/char/drm/gamma_lists.h b/drivers/char/drm/gamma_lists.h new file mode 100644 index 000000000000..2d93f412b96b --- /dev/null +++ b/drivers/char/drm/gamma_lists.h @@ -0,0 +1,215 @@ +/* drm_lists.h -- Buffer list handling routines -*- linux-c -*- + * Created: Mon Apr 19 20:54:22 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Gareth Hughes + */ + +#include "drmP.h" + + +int DRM(waitlist_create)(drm_waitlist_t *bl, int count) +{ + if (bl->count) return -EINVAL; + + bl->bufs = DRM(alloc)((bl->count + 2) * sizeof(*bl->bufs), + DRM_MEM_BUFLISTS); + + if(!bl->bufs) return -ENOMEM; + memset(bl->bufs, 0, sizeof(*bl->bufs)); + bl->count = count; + bl->rp = bl->bufs; + bl->wp = bl->bufs; + bl->end = &bl->bufs[bl->count+1]; + spin_lock_init(&bl->write_lock); + spin_lock_init(&bl->read_lock); + return 0; +} + +int DRM(waitlist_destroy)(drm_waitlist_t *bl) +{ + if (bl->rp != bl->wp) return -EINVAL; + if (bl->bufs) DRM(free)(bl->bufs, + (bl->count + 2) * sizeof(*bl->bufs), + DRM_MEM_BUFLISTS); + bl->count = 0; + bl->bufs = NULL; + bl->rp = NULL; + bl->wp = NULL; + bl->end = NULL; + return 0; +} + +int DRM(waitlist_put)(drm_waitlist_t *bl, drm_buf_t *buf) +{ + int left; + unsigned long flags; + + left = DRM_LEFTCOUNT(bl); + if (!left) { + DRM_ERROR("Overflow while adding buffer %d from filp %p\n", + buf->idx, buf->filp); + return -EINVAL; + } + buf->list = DRM_LIST_WAIT; + + spin_lock_irqsave(&bl->write_lock, flags); + *bl->wp = buf; + if (++bl->wp >= bl->end) bl->wp = bl->bufs; + spin_unlock_irqrestore(&bl->write_lock, flags); + + return 0; +} + +drm_buf_t *DRM(waitlist_get)(drm_waitlist_t *bl) +{ + drm_buf_t *buf; + unsigned long flags; + + spin_lock_irqsave(&bl->read_lock, flags); + buf = *bl->rp; + if (bl->rp == bl->wp) { + spin_unlock_irqrestore(&bl->read_lock, flags); + return NULL; + } + if (++bl->rp >= bl->end) bl->rp = bl->bufs; + spin_unlock_irqrestore(&bl->read_lock, flags); + + return buf; +} + +int DRM(freelist_create)(drm_freelist_t *bl, int count) +{ + atomic_set(&bl->count, 0); + bl->next = NULL; + init_waitqueue_head(&bl->waiting); + bl->low_mark = 0; + bl->high_mark = 0; + atomic_set(&bl->wfh, 0); + spin_lock_init(&bl->lock); + ++bl->initialized; + return 0; +} + +int DRM(freelist_destroy)(drm_freelist_t *bl) +{ + atomic_set(&bl->count, 0); + bl->next = NULL; + return 0; +} + +int DRM(freelist_put)(drm_device_t *dev, drm_freelist_t *bl, drm_buf_t *buf) +{ + drm_device_dma_t *dma = dev->dma; + + if (!dma) { + DRM_ERROR("No DMA support\n"); + return 1; + } + + if (buf->waiting || buf->pending || buf->list == DRM_LIST_FREE) { + DRM_ERROR("Freed buffer %d: w%d, p%d, l%d\n", + buf->idx, buf->waiting, buf->pending, buf->list); + } + if (!bl) return 1; + buf->list = DRM_LIST_FREE; + + spin_lock(&bl->lock); + buf->next = bl->next; + bl->next = buf; + spin_unlock(&bl->lock); + + atomic_inc(&bl->count); + if (atomic_read(&bl->count) > dma->buf_count) { + DRM_ERROR("%d of %d buffers free after addition of %d\n", + atomic_read(&bl->count), dma->buf_count, buf->idx); + return 1; + } + /* Check for high water mark */ + if (atomic_read(&bl->wfh) && atomic_read(&bl->count)>=bl->high_mark) { + atomic_set(&bl->wfh, 0); + wake_up_interruptible(&bl->waiting); + } + return 0; +} + +static drm_buf_t *DRM(freelist_try)(drm_freelist_t *bl) +{ + drm_buf_t *buf; + + if (!bl) return NULL; + + /* Get buffer */ + spin_lock(&bl->lock); + if (!bl->next) { + spin_unlock(&bl->lock); + return NULL; + } + buf = bl->next; + bl->next = bl->next->next; + spin_unlock(&bl->lock); + + atomic_dec(&bl->count); + buf->next = NULL; + buf->list = DRM_LIST_NONE; + if (buf->waiting || buf->pending) { + DRM_ERROR("Free buffer %d: w%d, p%d, l%d\n", + buf->idx, buf->waiting, buf->pending, buf->list); + } + + return buf; +} + +drm_buf_t *DRM(freelist_get)(drm_freelist_t *bl, int block) +{ + drm_buf_t *buf = NULL; + DECLARE_WAITQUEUE(entry, current); + + if (!bl || !bl->initialized) return NULL; + + /* Check for low water mark */ + if (atomic_read(&bl->count) <= bl->low_mark) /* Became low */ + atomic_set(&bl->wfh, 1); + if (atomic_read(&bl->wfh)) { + if (block) { + add_wait_queue(&bl->waiting, &entry); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!atomic_read(&bl->wfh) + && (buf = DRM(freelist_try)(bl))) break; + schedule(); + if (signal_pending(current)) break; + } + current->state = TASK_RUNNING; + remove_wait_queue(&bl->waiting, &entry); + } + return buf; + } + + return DRM(freelist_try)(bl); +} + diff --git a/drivers/char/drm/gamma_lock.h b/drivers/char/drm/gamma_lock.h new file mode 100644 index 000000000000..ddec67e4ed16 --- /dev/null +++ b/drivers/char/drm/gamma_lock.h @@ -0,0 +1,140 @@ +/* lock.c -- IOCTLs for locking -*- linux-c -*- + * Created: Tue Feb 2 08:37:54 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Gareth Hughes + */ + + +/* Gamma-specific code extracted from drm_lock.h: + */ +static int DRM(flush_queue)(drm_device_t *dev, int context) +{ + DECLARE_WAITQUEUE(entry, current); + int ret = 0; + drm_queue_t *q = dev->queuelist[context]; + + DRM_DEBUG("\n"); + + atomic_inc(&q->use_count); + if (atomic_read(&q->use_count) > 1) { + atomic_inc(&q->block_write); + add_wait_queue(&q->flush_queue, &entry); + atomic_inc(&q->block_count); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!DRM_BUFCOUNT(&q->waitlist)) break; + schedule(); + if (signal_pending(current)) { + ret = -EINTR; /* Can't restart */ + break; + } + } + atomic_dec(&q->block_count); + current->state = TASK_RUNNING; + remove_wait_queue(&q->flush_queue, &entry); + } + atomic_dec(&q->use_count); + + /* NOTE: block_write is still incremented! + Use drm_flush_unlock_queue to decrement. */ + return ret; +} + +static int DRM(flush_unblock_queue)(drm_device_t *dev, int context) +{ + drm_queue_t *q = dev->queuelist[context]; + + DRM_DEBUG("\n"); + + atomic_inc(&q->use_count); + if (atomic_read(&q->use_count) > 1) { + if (atomic_read(&q->block_write)) { + atomic_dec(&q->block_write); + wake_up_interruptible(&q->write_queue); + } + } + atomic_dec(&q->use_count); + return 0; +} + +int DRM(flush_block_and_flush)(drm_device_t *dev, int context, + drm_lock_flags_t flags) +{ + int ret = 0; + int i; + + DRM_DEBUG("\n"); + + if (flags & _DRM_LOCK_FLUSH) { + ret = DRM(flush_queue)(dev, DRM_KERNEL_CONTEXT); + if (!ret) ret = DRM(flush_queue)(dev, context); + } + if (flags & _DRM_LOCK_FLUSH_ALL) { + for (i = 0; !ret && i < dev->queue_count; i++) { + ret = DRM(flush_queue)(dev, i); + } + } + return ret; +} + +int DRM(flush_unblock)(drm_device_t *dev, int context, drm_lock_flags_t flags) +{ + int ret = 0; + int i; + + DRM_DEBUG("\n"); + + if (flags & _DRM_LOCK_FLUSH) { + ret = DRM(flush_unblock_queue)(dev, DRM_KERNEL_CONTEXT); + if (!ret) ret = DRM(flush_unblock_queue)(dev, context); + } + if (flags & _DRM_LOCK_FLUSH_ALL) { + for (i = 0; !ret && i < dev->queue_count; i++) { + ret = DRM(flush_unblock_queue)(dev, i); + } + } + + return ret; +} + +int DRM(finish)(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int ret = 0; + drm_lock_t lock; + + DRM_DEBUG("\n"); + + if (copy_from_user(&lock, (drm_lock_t __user *)arg, sizeof(lock))) + return -EFAULT; + ret = DRM(flush_block_and_flush)(dev, lock.context, lock.flags); + DRM(flush_unblock)(dev, lock.context, lock.flags); + return ret; +} diff --git a/drivers/char/drm/gamma_old_dma.h b/drivers/char/drm/gamma_old_dma.h new file mode 100644 index 000000000000..abdd454aab9f --- /dev/null +++ b/drivers/char/drm/gamma_old_dma.h @@ -0,0 +1,313 @@ +/* drm_dma.c -- DMA IOCTL and function support -*- linux-c -*- + * Created: Fri Mar 19 14:30:16 1999 by faith@valinux.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Gareth Hughes + */ + + +/* Gamma-specific code pulled from drm_dma.h: + */ + +void DRM(clear_next_buffer)(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + + dma->next_buffer = NULL; + if (dma->next_queue && !DRM_BUFCOUNT(&dma->next_queue->waitlist)) { + wake_up_interruptible(&dma->next_queue->flush_queue); + } + dma->next_queue = NULL; +} + +int DRM(select_queue)(drm_device_t *dev, void (*wrapper)(unsigned long)) +{ + int i; + int candidate = -1; + int j = jiffies; + + if (!dev) { + DRM_ERROR("No device\n"); + return -1; + } + if (!dev->queuelist || !dev->queuelist[DRM_KERNEL_CONTEXT]) { + /* This only happens between the time the + interrupt is initialized and the time + the queues are initialized. */ + return -1; + } + + /* Doing "while locked" DMA? */ + if (DRM_WAITCOUNT(dev, DRM_KERNEL_CONTEXT)) { + return DRM_KERNEL_CONTEXT; + } + + /* If there are buffers on the last_context + queue, and we have not been executing + this context very long, continue to + execute this context. */ + if (dev->last_switch <= j + && dev->last_switch + DRM_TIME_SLICE > j + && DRM_WAITCOUNT(dev, dev->last_context)) { + return dev->last_context; + } + + /* Otherwise, find a candidate */ + for (i = dev->last_checked + 1; i < dev->queue_count; i++) { + if (DRM_WAITCOUNT(dev, i)) { + candidate = dev->last_checked = i; + break; + } + } + + if (candidate < 0) { + for (i = 0; i < dev->queue_count; i++) { + if (DRM_WAITCOUNT(dev, i)) { + candidate = dev->last_checked = i; + break; + } + } + } + + if (wrapper + && candidate >= 0 + && candidate != dev->last_context + && dev->last_switch <= j + && dev->last_switch + DRM_TIME_SLICE > j) { + if (dev->timer.expires != dev->last_switch + DRM_TIME_SLICE) { + del_timer(&dev->timer); + dev->timer.function = wrapper; + dev->timer.data = (unsigned long)dev; + dev->timer.expires = dev->last_switch+DRM_TIME_SLICE; + add_timer(&dev->timer); + } + return -1; + } + + return candidate; +} + + +int DRM(dma_enqueue)(struct file *filp, drm_dma_t *d) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int i; + drm_queue_t *q; + drm_buf_t *buf; + int idx; + int while_locked = 0; + drm_device_dma_t *dma = dev->dma; + int *ind; + int err; + DECLARE_WAITQUEUE(entry, current); + + DRM_DEBUG("%d\n", d->send_count); + + if (d->flags & _DRM_DMA_WHILE_LOCKED) { + int context = dev->lock.hw_lock->lock; + + if (!_DRM_LOCK_IS_HELD(context)) { + DRM_ERROR("No lock held during \"while locked\"" + " request\n"); + return -EINVAL; + } + if (d->context != _DRM_LOCKING_CONTEXT(context) + && _DRM_LOCKING_CONTEXT(context) != DRM_KERNEL_CONTEXT) { + DRM_ERROR("Lock held by %d while %d makes" + " \"while locked\" request\n", + _DRM_LOCKING_CONTEXT(context), + d->context); + return -EINVAL; + } + q = dev->queuelist[DRM_KERNEL_CONTEXT]; + while_locked = 1; + } else { + q = dev->queuelist[d->context]; + } + + + atomic_inc(&q->use_count); + if (atomic_read(&q->block_write)) { + add_wait_queue(&q->write_queue, &entry); + atomic_inc(&q->block_count); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + if (!atomic_read(&q->block_write)) break; + schedule(); + if (signal_pending(current)) { + atomic_dec(&q->use_count); + remove_wait_queue(&q->write_queue, &entry); + return -EINTR; + } + } + atomic_dec(&q->block_count); + current->state = TASK_RUNNING; + remove_wait_queue(&q->write_queue, &entry); + } + + ind = DRM(alloc)(d->send_count * sizeof(int), DRM_MEM_DRIVER); + if (!ind) + return -ENOMEM; + + if (copy_from_user(ind, d->send_indices, d->send_count * sizeof(int))) { + err = -EFAULT; + goto out; + } + + err = -EINVAL; + for (i = 0; i < d->send_count; i++) { + idx = ind[i]; + if (idx < 0 || idx >= dma->buf_count) { + DRM_ERROR("Index %d (of %d max)\n", + ind[i], dma->buf_count - 1); + goto out; + } + buf = dma->buflist[ idx ]; + if (buf->filp != filp) { + DRM_ERROR("Process %d using buffer not owned\n", + current->pid); + goto out; + } + if (buf->list != DRM_LIST_NONE) { + DRM_ERROR("Process %d using buffer %d on list %d\n", + current->pid, buf->idx, buf->list); + goto out; + } + buf->used = ind[i]; + buf->while_locked = while_locked; + buf->context = d->context; + if (!buf->used) { + DRM_ERROR("Queueing 0 length buffer\n"); + } + if (buf->pending) { + DRM_ERROR("Queueing pending buffer:" + " buffer %d, offset %d\n", + ind[i], i); + goto out; + } + if (buf->waiting) { + DRM_ERROR("Queueing waiting buffer:" + " buffer %d, offset %d\n", + ind[i], i); + goto out; + } + buf->waiting = 1; + if (atomic_read(&q->use_count) == 1 + || atomic_read(&q->finalization)) { + DRM(free_buffer)(dev, buf); + } else { + DRM(waitlist_put)(&q->waitlist, buf); + atomic_inc(&q->total_queued); + } + } + atomic_dec(&q->use_count); + + return 0; + +out: + DRM(free)(ind, d->send_count * sizeof(int), DRM_MEM_DRIVER); + atomic_dec(&q->use_count); + return err; +} + +static int DRM(dma_get_buffers_of_order)(struct file *filp, drm_dma_t *d, + int order) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int i; + drm_buf_t *buf; + drm_device_dma_t *dma = dev->dma; + + for (i = d->granted_count; i < d->request_count; i++) { + buf = DRM(freelist_get)(&dma->bufs[order].freelist, + d->flags & _DRM_DMA_WAIT); + if (!buf) break; + if (buf->pending || buf->waiting) { + DRM_ERROR("Free buffer %d in use: filp %p (w%d, p%d)\n", + buf->idx, + buf->filp, + buf->waiting, + buf->pending); + } + buf->filp = filp; + if (copy_to_user(&d->request_indices[i], + &buf->idx, + sizeof(buf->idx))) + return -EFAULT; + + if (copy_to_user(&d->request_sizes[i], + &buf->total, + sizeof(buf->total))) + return -EFAULT; + + ++d->granted_count; + } + return 0; +} + + +int DRM(dma_get_buffers)(struct file *filp, drm_dma_t *dma) +{ + int order; + int retcode = 0; + int tmp_order; + + order = DRM(order)(dma->request_size); + + dma->granted_count = 0; + retcode = DRM(dma_get_buffers_of_order)(filp, dma, order); + + if (dma->granted_count < dma->request_count + && (dma->flags & _DRM_DMA_SMALLER_OK)) { + for (tmp_order = order - 1; + !retcode + && dma->granted_count < dma->request_count + && tmp_order >= DRM_MIN_ORDER; + --tmp_order) { + + retcode = DRM(dma_get_buffers_of_order)(filp, dma, + tmp_order); + } + } + + if (dma->granted_count < dma->request_count + && (dma->flags & _DRM_DMA_LARGER_OK)) { + for (tmp_order = order + 1; + !retcode + && dma->granted_count < dma->request_count + && tmp_order <= DRM_MAX_ORDER; + ++tmp_order) { + + retcode = DRM(dma_get_buffers_of_order)(filp, dma, + tmp_order); + } + } + return 0; +} + diff --git a/drivers/char/drm/i810_dma.c b/drivers/char/drm/i810_dma.c new file mode 100644 index 000000000000..24857cc6c23b --- /dev/null +++ b/drivers/char/drm/i810_dma.c @@ -0,0 +1,1385 @@ +/* i810_dma.c -- DMA support for the i810 -*- linux-c -*- + * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * Jeff Hartmann + * Keith Whitwell + * + */ + +#include "drmP.h" +#include "drm.h" +#include "i810_drm.h" +#include "i810_drv.h" +#include /* For task queue support */ +#include +#include + +#define I810_BUF_FREE 2 +#define I810_BUF_CLIENT 1 +#define I810_BUF_HARDWARE 0 + +#define I810_BUF_UNMAPPED 0 +#define I810_BUF_MAPPED 1 + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,2) +#define down_write down +#define up_write up +#endif + +static drm_buf_t *i810_freelist_get(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + int i; + int used; + + /* Linear search might not be the best solution */ + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + /* In use is already a pointer */ + used = cmpxchg(buf_priv->in_use, I810_BUF_FREE, + I810_BUF_CLIENT); + if (used == I810_BUF_FREE) { + return buf; + } + } + return NULL; +} + +/* This should only be called if the buffer is not sent to the hardware + * yet, the hardware updates in use for us once its on the ring buffer. + */ + +static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf) +{ + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + int used; + + /* In use is already a pointer */ + used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE); + if (used != I810_BUF_CLIENT) { + DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); + return -EINVAL; + } + + return 0; +} + +static struct file_operations i810_buffer_fops = { + .open = drm_open, + .flush = drm_flush, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = i810_mmap_buffers, + .fasync = drm_fasync, +}; + +int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + drm_i810_private_t *dev_priv; + drm_buf_t *buf; + drm_i810_buf_priv_t *buf_priv; + + lock_kernel(); + dev = priv->head->dev; + dev_priv = dev->dev_private; + buf = dev_priv->mmap_buffer; + buf_priv = buf->dev_private; + + vma->vm_flags |= (VM_IO | VM_DONTCOPY); + vma->vm_file = filp; + + buf_priv->currently_mapped = I810_BUF_MAPPED; + unlock_kernel(); + + if (io_remap_pfn_range(vma, vma->vm_start, + VM_OFFSET(vma) >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) return -EAGAIN; + return 0; +} + +static int i810_map_buffer(drm_buf_t *buf, struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; + struct file_operations *old_fops; + int retcode = 0; + + if (buf_priv->currently_mapped == I810_BUF_MAPPED) + return -EINVAL; + + down_write( ¤t->mm->mmap_sem ); + old_fops = filp->f_op; + filp->f_op = &i810_buffer_fops; + dev_priv->mmap_buffer = buf; + buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total, + PROT_READ|PROT_WRITE, + MAP_SHARED, + buf->bus_address); + dev_priv->mmap_buffer = NULL; + filp->f_op = old_fops; + if ((unsigned long)buf_priv->virtual > -1024UL) { + /* Real error */ + DRM_ERROR("mmap error\n"); + retcode = (signed int)buf_priv->virtual; + buf_priv->virtual = NULL; + } + up_write( ¤t->mm->mmap_sem ); + + return retcode; +} + +static int i810_unmap_buffer(drm_buf_t *buf) +{ + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + int retcode = 0; + + if (buf_priv->currently_mapped != I810_BUF_MAPPED) + return -EINVAL; + + down_write(¤t->mm->mmap_sem); + retcode = do_munmap(current->mm, + (unsigned long)buf_priv->virtual, + (size_t) buf->total); + up_write(¤t->mm->mmap_sem); + + buf_priv->currently_mapped = I810_BUF_UNMAPPED; + buf_priv->virtual = NULL; + + return retcode; +} + +static int i810_dma_get_buffer(drm_device_t *dev, drm_i810_dma_t *d, + struct file *filp) +{ + drm_buf_t *buf; + drm_i810_buf_priv_t *buf_priv; + int retcode = 0; + + buf = i810_freelist_get(dev); + if (!buf) { + retcode = -ENOMEM; + DRM_DEBUG("retcode=%d\n", retcode); + return retcode; + } + + retcode = i810_map_buffer(buf, filp); + if (retcode) { + i810_freelist_put(dev, buf); + DRM_ERROR("mapbuf failed, retcode %d\n", retcode); + return retcode; + } + buf->filp = filp; + buf_priv = buf->dev_private; + d->granted = 1; + d->request_idx = buf->idx; + d->request_size = buf->total; + d->virtual = buf_priv->virtual; + + return retcode; +} + +static int i810_dma_cleanup(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + + /* Make sure interrupts are disabled here because the uninstall ioctl + * may not have been called from userspace and after dev_private + * is freed, it's too late. + */ + if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled) + drm_irq_uninstall(dev); + + if (dev->dev_private) { + int i; + drm_i810_private_t *dev_priv = + (drm_i810_private_t *) dev->dev_private; + + if (dev_priv->ring.virtual_start) { + drm_ioremapfree((void *) dev_priv->ring.virtual_start, + dev_priv->ring.Size, dev); + } + if (dev_priv->hw_status_page) { + pci_free_consistent(dev->pdev, PAGE_SIZE, + dev_priv->hw_status_page, + dev_priv->dma_status_page); + /* Need to rewrite hardware status page */ + I810_WRITE(0x02080, 0x1ffff000); + } + drm_free(dev->dev_private, sizeof(drm_i810_private_t), + DRM_MEM_DRIVER); + dev->dev_private = NULL; + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + if ( buf_priv->kernel_virtual && buf->total ) + drm_ioremapfree(buf_priv->kernel_virtual, buf->total, dev); + } + } + return 0; +} + +static int i810_wait_ring(drm_device_t *dev, int n) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_ring_buffer_t *ring = &(dev_priv->ring); + int iters = 0; + unsigned long end; + unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + + end = jiffies + (HZ*3); + while (ring->space < n) { + ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->space = ring->head - (ring->tail+8); + if (ring->space < 0) ring->space += ring->Size; + + if (ring->head != last_head) { + end = jiffies + (HZ*3); + last_head = ring->head; + } + + iters++; + if (time_before(end, jiffies)) { + DRM_ERROR("space: %d wanted %d\n", ring->space, n); + DRM_ERROR("lockup\n"); + goto out_wait_ring; + } + udelay(1); + } + +out_wait_ring: + return iters; +} + +static void i810_kernel_lost_context(drm_device_t *dev) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_ring_buffer_t *ring = &(dev_priv->ring); + + ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->tail = I810_READ(LP_RING + RING_TAIL); + ring->space = ring->head - (ring->tail+8); + if (ring->space < 0) ring->space += ring->Size; +} + +static int i810_freelist_init(drm_device_t *dev, drm_i810_private_t *dev_priv) +{ + drm_device_dma_t *dma = dev->dma; + int my_idx = 24; + u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx); + int i; + + if (dma->buf_count > 1019) { + /* Not enough space in the status page for the freelist */ + return -EINVAL; + } + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + + buf_priv->in_use = hw_status++; + buf_priv->my_use_idx = my_idx; + my_idx += 4; + + *buf_priv->in_use = I810_BUF_FREE; + + buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, + buf->total, dev); + } + return 0; +} + +static int i810_dma_initialize(drm_device_t *dev, + drm_i810_private_t *dev_priv, + drm_i810_init_t *init) +{ + struct list_head *list; + + memset(dev_priv, 0, sizeof(drm_i810_private_t)); + + list_for_each(list, &dev->maplist->head) { + drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); + if (r_list->map && + r_list->map->type == _DRM_SHM && + r_list->map->flags & _DRM_CONTAINS_LOCK ) { + dev_priv->sarea_map = r_list->map; + break; + } + } + if (!dev_priv->sarea_map) { + dev->dev_private = (void *)dev_priv; + i810_dma_cleanup(dev); + DRM_ERROR("can not find sarea!\n"); + return -EINVAL; + } + dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); + if (!dev_priv->mmio_map) { + dev->dev_private = (void *)dev_priv; + i810_dma_cleanup(dev); + DRM_ERROR("can not find mmio map!\n"); + return -EINVAL; + } + dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); + if (!dev->agp_buffer_map) { + dev->dev_private = (void *)dev_priv; + i810_dma_cleanup(dev); + DRM_ERROR("can not find dma buffer map!\n"); + return -EINVAL; + } + + dev_priv->sarea_priv = (drm_i810_sarea_t *) + ((u8 *)dev_priv->sarea_map->handle + + init->sarea_priv_offset); + + dev_priv->ring.Start = init->ring_start; + dev_priv->ring.End = init->ring_end; + dev_priv->ring.Size = init->ring_size; + + dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + + init->ring_start, + init->ring_size, dev); + + if (dev_priv->ring.virtual_start == NULL) { + dev->dev_private = (void *) dev_priv; + i810_dma_cleanup(dev); + DRM_ERROR("can not ioremap virtual address for" + " ring buffer\n"); + return -ENOMEM; + } + + dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; + + dev_priv->w = init->w; + dev_priv->h = init->h; + dev_priv->pitch = init->pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->depth_offset = init->depth_offset; + dev_priv->front_offset = init->front_offset; + + dev_priv->overlay_offset = init->overlay_offset; + dev_priv->overlay_physical = init->overlay_physical; + + dev_priv->front_di1 = init->front_offset | init->pitch_bits; + dev_priv->back_di1 = init->back_offset | init->pitch_bits; + dev_priv->zi1 = init->depth_offset | init->pitch_bits; + + /* Program Hardware Status Page */ + dev_priv->hw_status_page = + pci_alloc_consistent(dev->pdev, PAGE_SIZE, + &dev_priv->dma_status_page); + if (!dev_priv->hw_status_page) { + dev->dev_private = (void *)dev_priv; + i810_dma_cleanup(dev); + DRM_ERROR("Can not allocate hardware status page\n"); + return -ENOMEM; + } + memset(dev_priv->hw_status_page, 0, PAGE_SIZE); + DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); + + I810_WRITE(0x02080, dev_priv->dma_status_page); + DRM_DEBUG("Enabled hardware status page\n"); + + /* Now we need to init our freelist */ + if (i810_freelist_init(dev, dev_priv) != 0) { + dev->dev_private = (void *)dev_priv; + i810_dma_cleanup(dev); + DRM_ERROR("Not enough space in the status page for" + " the freelist\n"); + return -ENOMEM; + } + dev->dev_private = (void *)dev_priv; + + return 0; +} + +/* i810 DRM version 1.1 used a smaller init structure with different + * ordering of values than is currently used (drm >= 1.2). There is + * no defined way to detect the XFree version to correct this problem, + * however by checking using this procedure we can detect the correct + * thing to do. + * + * #1 Read the Smaller init structure from user-space + * #2 Verify the overlay_physical is a valid physical address, or NULL + * If it isn't then we have a v1.1 client. Fix up params. + * If it is, then we have a 1.2 client... get the rest of the data. + */ +static int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg) +{ + + /* Get v1.1 init data */ + if (copy_from_user(init, (drm_i810_pre12_init_t __user *)arg, + sizeof(drm_i810_pre12_init_t))) { + return -EFAULT; + } + + if ((!init->overlay_physical) || (init->overlay_physical > 4096)) { + + /* This is a v1.2 client, just get the v1.2 init data */ + DRM_INFO("Using POST v1.2 init.\n"); + if (copy_from_user(init, (drm_i810_init_t __user *)arg, + sizeof(drm_i810_init_t))) { + return -EFAULT; + } + } else { + + /* This is a v1.1 client, fix the params */ + DRM_INFO("Using PRE v1.2 init.\n"); + init->pitch_bits = init->h; + init->pitch = init->w; + init->h = init->overlay_physical; + init->w = init->overlay_offset; + init->overlay_physical = 0; + init->overlay_offset = 0; + } + + return 0; +} + +static int i810_dma_init(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i810_private_t *dev_priv; + drm_i810_init_t init; + int retcode = 0; + + /* Get only the init func */ + if (copy_from_user(&init, (void __user *)arg, sizeof(drm_i810_init_func_t))) + return -EFAULT; + + switch(init.func) { + case I810_INIT_DMA: + /* This case is for backward compatibility. It + * handles XFree 4.1.0 and 4.2.0, and has to + * do some parameter checking as described below. + * It will someday go away. + */ + retcode = i810_dma_init_compat(&init, arg); + if (retcode) + return retcode; + + dev_priv = drm_alloc(sizeof(drm_i810_private_t), + DRM_MEM_DRIVER); + if (dev_priv == NULL) + return -ENOMEM; + retcode = i810_dma_initialize(dev, dev_priv, &init); + break; + + default: + case I810_INIT_DMA_1_4: + DRM_INFO("Using v1.4 init.\n"); + if (copy_from_user(&init, (drm_i810_init_t __user *)arg, + sizeof(drm_i810_init_t))) { + return -EFAULT; + } + dev_priv = drm_alloc(sizeof(drm_i810_private_t), + DRM_MEM_DRIVER); + if (dev_priv == NULL) + return -ENOMEM; + retcode = i810_dma_initialize(dev, dev_priv, &init); + break; + + case I810_CLEANUP_DMA: + DRM_INFO("DMA Cleanup\n"); + retcode = i810_dma_cleanup(dev); + break; + } + + return retcode; +} + + + +/* Most efficient way to verify state for the i810 is as it is + * emitted. Non-conformant state is silently dropped. + * + * Use 'volatile' & local var tmp to force the emitted values to be + * identical to the verified ones. + */ +static void i810EmitContextVerified( drm_device_t *dev, + volatile unsigned int *code ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + int i, j = 0; + unsigned int tmp; + RING_LOCALS; + + BEGIN_LP_RING( I810_CTX_SETUP_SIZE ); + + OUT_RING( GFX_OP_COLOR_FACTOR ); + OUT_RING( code[I810_CTXREG_CF1] ); + + OUT_RING( GFX_OP_STIPPLE ); + OUT_RING( code[I810_CTXREG_ST1] ); + + for ( i = 4 ; i < I810_CTX_SETUP_SIZE ; i++ ) { + tmp = code[i]; + + if ((tmp & (7<<29)) == (3<<29) && + (tmp & (0x1f<<24)) < (0x1d<<24)) + { + OUT_RING( tmp ); + j++; + } + else printk("constext state dropped!!!\n"); + } + + if (j & 1) + OUT_RING( 0 ); + + ADVANCE_LP_RING(); +} + +static void i810EmitTexVerified( drm_device_t *dev, + volatile unsigned int *code ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + int i, j = 0; + unsigned int tmp; + RING_LOCALS; + + BEGIN_LP_RING( I810_TEX_SETUP_SIZE ); + + OUT_RING( GFX_OP_MAP_INFO ); + OUT_RING( code[I810_TEXREG_MI1] ); + OUT_RING( code[I810_TEXREG_MI2] ); + OUT_RING( code[I810_TEXREG_MI3] ); + + for ( i = 4 ; i < I810_TEX_SETUP_SIZE ; i++ ) { + tmp = code[i]; + + if ((tmp & (7<<29)) == (3<<29) && + (tmp & (0x1f<<24)) < (0x1d<<24)) + { + OUT_RING( tmp ); + j++; + } + else printk("texture state dropped!!!\n"); + } + + if (j & 1) + OUT_RING( 0 ); + + ADVANCE_LP_RING(); +} + + +/* Need to do some additional checking when setting the dest buffer. + */ +static void i810EmitDestVerified( drm_device_t *dev, + volatile unsigned int *code ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + unsigned int tmp; + RING_LOCALS; + + BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 ); + + tmp = code[I810_DESTREG_DI1]; + if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { + OUT_RING( CMD_OP_DESTBUFFER_INFO ); + OUT_RING( tmp ); + } else + DRM_DEBUG("bad di1 %x (allow %x or %x)\n", + tmp, dev_priv->front_di1, dev_priv->back_di1); + + /* invarient: + */ + OUT_RING( CMD_OP_Z_BUFFER_INFO ); + OUT_RING( dev_priv->zi1 ); + + OUT_RING( GFX_OP_DESTBUFFER_VARS ); + OUT_RING( code[I810_DESTREG_DV1] ); + + OUT_RING( GFX_OP_DRAWRECT_INFO ); + OUT_RING( code[I810_DESTREG_DR1] ); + OUT_RING( code[I810_DESTREG_DR2] ); + OUT_RING( code[I810_DESTREG_DR3] ); + OUT_RING( code[I810_DESTREG_DR4] ); + OUT_RING( 0 ); + + ADVANCE_LP_RING(); +} + + + +static void i810EmitState( drm_device_t *dev ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int dirty = sarea_priv->dirty; + + DRM_DEBUG("%s %x\n", __FUNCTION__, dirty); + + if (dirty & I810_UPLOAD_BUFFERS) { + i810EmitDestVerified( dev, sarea_priv->BufferState ); + sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS; + } + + if (dirty & I810_UPLOAD_CTX) { + i810EmitContextVerified( dev, sarea_priv->ContextState ); + sarea_priv->dirty &= ~I810_UPLOAD_CTX; + } + + if (dirty & I810_UPLOAD_TEX0) { + i810EmitTexVerified( dev, sarea_priv->TexState[0] ); + sarea_priv->dirty &= ~I810_UPLOAD_TEX0; + } + + if (dirty & I810_UPLOAD_TEX1) { + i810EmitTexVerified( dev, sarea_priv->TexState[1] ); + sarea_priv->dirty &= ~I810_UPLOAD_TEX1; + } +} + + + +/* need to verify + */ +static void i810_dma_dispatch_clear( drm_device_t *dev, int flags, + unsigned int clear_color, + unsigned int clear_zval ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int pitch = dev_priv->pitch; + int cpp = 2; + int i; + RING_LOCALS; + + if ( dev_priv->current_page == 1 ) { + unsigned int tmp = flags; + + flags &= ~(I810_FRONT | I810_BACK); + if (tmp & I810_FRONT) flags |= I810_BACK; + if (tmp & I810_BACK) flags |= I810_FRONT; + } + + i810_kernel_lost_context(dev); + + if (nbox > I810_NR_SAREA_CLIPRECTS) + nbox = I810_NR_SAREA_CLIPRECTS; + + for (i = 0 ; i < nbox ; i++, pbox++) { + unsigned int x = pbox->x1; + unsigned int y = pbox->y1; + unsigned int width = (pbox->x2 - x) * cpp; + unsigned int height = pbox->y2 - y; + unsigned int start = y * pitch + x * cpp; + + if (pbox->x1 > pbox->x2 || + pbox->y1 > pbox->y2 || + pbox->x2 > dev_priv->w || + pbox->y2 > dev_priv->h) + continue; + + if ( flags & I810_FRONT ) { + BEGIN_LP_RING( 6 ); + OUT_RING( BR00_BITBLT_CLIENT | + BR00_OP_COLOR_BLT | 0x3 ); + OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); + OUT_RING( (height << 16) | width ); + OUT_RING( start ); + OUT_RING( clear_color ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + } + + if ( flags & I810_BACK ) { + BEGIN_LP_RING( 6 ); + OUT_RING( BR00_BITBLT_CLIENT | + BR00_OP_COLOR_BLT | 0x3 ); + OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); + OUT_RING( (height << 16) | width ); + OUT_RING( dev_priv->back_offset + start ); + OUT_RING( clear_color ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + } + + if ( flags & I810_DEPTH ) { + BEGIN_LP_RING( 6 ); + OUT_RING( BR00_BITBLT_CLIENT | + BR00_OP_COLOR_BLT | 0x3 ); + OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); + OUT_RING( (height << 16) | width ); + OUT_RING( dev_priv->depth_offset + start ); + OUT_RING( clear_zval ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + } + } +} + +static void i810_dma_dispatch_swap( drm_device_t *dev ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int pitch = dev_priv->pitch; + int cpp = 2; + int i; + RING_LOCALS; + + DRM_DEBUG("swapbuffers\n"); + + i810_kernel_lost_context(dev); + + if (nbox > I810_NR_SAREA_CLIPRECTS) + nbox = I810_NR_SAREA_CLIPRECTS; + + for (i = 0 ; i < nbox; i++, pbox++) + { + unsigned int w = pbox->x2 - pbox->x1; + unsigned int h = pbox->y2 - pbox->y1; + unsigned int dst = pbox->x1*cpp + pbox->y1*pitch; + unsigned int start = dst; + + if (pbox->x1 > pbox->x2 || + pbox->y1 > pbox->y2 || + pbox->x2 > dev_priv->w || + pbox->y2 > dev_priv->h) + continue; + + BEGIN_LP_RING( 6 ); + OUT_RING( BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4 ); + OUT_RING( pitch | (0xCC << 16)); + OUT_RING( (h << 16) | (w * cpp)); + if (dev_priv->current_page == 0) + OUT_RING(dev_priv->front_offset + start); + else + OUT_RING(dev_priv->back_offset + start); + OUT_RING( pitch ); + if (dev_priv->current_page == 0) + OUT_RING(dev_priv->back_offset + start); + else + OUT_RING(dev_priv->front_offset + start); + ADVANCE_LP_RING(); + } +} + + +static void i810_dma_dispatch_vertex(drm_device_t *dev, + drm_buf_t *buf, + int discard, + int used) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_clip_rect_t *box = sarea_priv->boxes; + int nbox = sarea_priv->nbox; + unsigned long address = (unsigned long)buf->bus_address; + unsigned long start = address - dev->agp->base; + int i = 0; + RING_LOCALS; + + i810_kernel_lost_context(dev); + + if (nbox > I810_NR_SAREA_CLIPRECTS) + nbox = I810_NR_SAREA_CLIPRECTS; + + if (used > 4*1024) + used = 0; + + if (sarea_priv->dirty) + i810EmitState( dev ); + + if (buf_priv->currently_mapped == I810_BUF_MAPPED) { + unsigned int prim = (sarea_priv->vertex_prim & PR_MASK); + + *(u32 *)buf_priv->kernel_virtual = ((GFX_OP_PRIMITIVE | prim | ((used/4)-2))); + + if (used & 4) { + *(u32 *)((u32)buf_priv->kernel_virtual + used) = 0; + used += 4; + } + + i810_unmap_buffer(buf); + } + + if (used) { + do { + if (i < nbox) { + BEGIN_LP_RING(4); + OUT_RING( GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | + SC_ENABLE ); + OUT_RING( GFX_OP_SCISSOR_INFO ); + OUT_RING( box[i].x1 | (box[i].y1<<16) ); + OUT_RING( (box[i].x2-1) | ((box[i].y2-1)<<16) ); + ADVANCE_LP_RING(); + } + + BEGIN_LP_RING(4); + OUT_RING( CMD_OP_BATCH_BUFFER ); + OUT_RING( start | BB1_PROTECTED ); + OUT_RING( start + used - 4 ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + + } while (++i < nbox); + } + + if (discard) { + dev_priv->counter++; + + (void) cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, + I810_BUF_HARDWARE); + + BEGIN_LP_RING(8); + OUT_RING( CMD_STORE_DWORD_IDX ); + OUT_RING( 20 ); + OUT_RING( dev_priv->counter ); + OUT_RING( CMD_STORE_DWORD_IDX ); + OUT_RING( buf_priv->my_use_idx ); + OUT_RING( I810_BUF_FREE ); + OUT_RING( CMD_REPORT_HEAD ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + } +} + +static void i810_dma_dispatch_flip( drm_device_t *dev ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + int pitch = dev_priv->pitch; + RING_LOCALS; + + DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, + dev_priv->sarea_priv->pf_current_page); + + i810_kernel_lost_context(dev); + + BEGIN_LP_RING( 2 ); + OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + + BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 ); + /* On i815 at least ASYNC is buggy */ + /* pitch<<5 is from 11.2.8 p158, + its the pitch / 8 then left shifted 8, + so (pitch >> 3) << 8 */ + OUT_RING( CMD_OP_FRONTBUFFER_INFO | (pitch<<5) /*| ASYNC_FLIP */ ); + if ( dev_priv->current_page == 0 ) { + OUT_RING( dev_priv->back_offset ); + dev_priv->current_page = 1; + } else { + OUT_RING( dev_priv->front_offset ); + dev_priv->current_page = 0; + } + OUT_RING(0); + ADVANCE_LP_RING(); + + BEGIN_LP_RING(2); + OUT_RING( CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + + /* Increment the frame counter. The client-side 3D driver must + * throttle the framerate by waiting for this value before + * performing the swapbuffer ioctl. + */ + dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; + +} + +static void i810_dma_quiescent(drm_device_t *dev) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + +/* printk("%s\n", __FUNCTION__); */ + + i810_kernel_lost_context(dev); + + BEGIN_LP_RING(4); + OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); + OUT_RING( CMD_REPORT_HEAD ); + OUT_RING( 0 ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + + i810_wait_ring( dev, dev_priv->ring.Size - 8 ); +} + +static int i810_flush_queue(drm_device_t *dev) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + int i, ret = 0; + RING_LOCALS; + +/* printk("%s\n", __FUNCTION__); */ + + i810_kernel_lost_context(dev); + + BEGIN_LP_RING(2); + OUT_RING( CMD_REPORT_HEAD ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + + i810_wait_ring( dev, dev_priv->ring.Size - 8 ); + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + + int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE, + I810_BUF_FREE); + + if (used == I810_BUF_HARDWARE) + DRM_DEBUG("reclaimed from HARDWARE\n"); + if (used == I810_BUF_CLIENT) + DRM_DEBUG("still on client\n"); + } + + return ret; +} + +/* Must be called with the lock held */ +void i810_reclaim_buffers(drm_device_t *dev, struct file *filp) +{ + drm_device_dma_t *dma = dev->dma; + int i; + + if (!dma) return; + if (!dev->dev_private) return; + if (!dma->buflist) return; + + i810_flush_queue(dev); + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + + if (buf->filp == filp && buf_priv) { + int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, + I810_BUF_FREE); + + if (used == I810_BUF_CLIENT) + DRM_DEBUG("reclaimed from client\n"); + if (buf_priv->currently_mapped == I810_BUF_MAPPED) + buf_priv->currently_mapped = I810_BUF_UNMAPPED; + } + } +} + +int i810_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + + LOCK_TEST_WITH_RETURN(dev, filp); + + i810_flush_queue(dev); + return 0; +} + + +static int i810_dma_vertex(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_device_dma_t *dma = dev->dma; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + drm_i810_vertex_t vertex; + + if (copy_from_user(&vertex, (drm_i810_vertex_t __user *)arg, sizeof(vertex))) + return -EFAULT; + + LOCK_TEST_WITH_RETURN(dev, filp); + + DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n", + vertex.idx, vertex.used, vertex.discard); + + if (vertex.idx < 0 || vertex.idx > dma->buf_count) + return -EINVAL; + + i810_dma_dispatch_vertex( dev, + dma->buflist[ vertex.idx ], + vertex.discard, vertex.used ); + + atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]); + atomic_inc(&dev->counts[_DRM_STAT_DMA]); + sarea_priv->last_enqueue = dev_priv->counter-1; + sarea_priv->last_dispatch = (int) hw_status[5]; + + return 0; +} + + + +static int i810_clear_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i810_clear_t clear; + + if (copy_from_user(&clear, (drm_i810_clear_t __user *)arg, sizeof(clear))) + return -EFAULT; + + LOCK_TEST_WITH_RETURN(dev, filp); + + /* GH: Someone's doing nasty things... */ + if (!dev->dev_private) { + return -EINVAL; + } + + i810_dma_dispatch_clear( dev, clear.flags, + clear.clear_color, + clear.clear_depth ); + return 0; +} + +static int i810_swap_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + + DRM_DEBUG("i810_swap_bufs\n"); + + LOCK_TEST_WITH_RETURN(dev, filp); + + i810_dma_dispatch_swap( dev ); + return 0; +} + +static int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + + sarea_priv->last_dispatch = (int) hw_status[5]; + return 0; +} + +static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + int retcode = 0; + drm_i810_dma_t d; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + + if (copy_from_user(&d, (drm_i810_dma_t __user *)arg, sizeof(d))) + return -EFAULT; + + LOCK_TEST_WITH_RETURN(dev, filp); + + d.granted = 0; + + retcode = i810_dma_get_buffer(dev, &d, filp); + + DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n", + current->pid, retcode, d.granted); + + if (copy_to_user((drm_dma_t __user *)arg, &d, sizeof(d))) + return -EFAULT; + sarea_priv->last_dispatch = (int) hw_status[5]; + + return retcode; +} + +static int i810_copybuf(struct inode *inode, + struct file *filp, unsigned int cmd, unsigned long arg) +{ + /* Never copy - 2.4.x doesn't need it */ + return 0; +} + +static int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + /* Never copy - 2.4.x doesn't need it */ + return 0; +} + +static void i810_dma_dispatch_mc(drm_device_t *dev, drm_buf_t *buf, int used, + unsigned int last_render) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned long address = (unsigned long)buf->bus_address; + unsigned long start = address - dev->agp->base; + int u; + RING_LOCALS; + + i810_kernel_lost_context(dev); + + u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, + I810_BUF_HARDWARE); + if (u != I810_BUF_CLIENT) { + DRM_DEBUG("MC found buffer that isn't mine!\n"); + } + + if (used > 4*1024) + used = 0; + + sarea_priv->dirty = 0x7f; + + DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", + address, used); + + dev_priv->counter++; + DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter); + DRM_DEBUG("i810_dma_dispatch_mc\n"); + DRM_DEBUG("start : %lx\n", start); + DRM_DEBUG("used : %d\n", used); + DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4); + + if (buf_priv->currently_mapped == I810_BUF_MAPPED) { + if (used & 4) { + *(u32 *)((u32)buf_priv->virtual + used) = 0; + used += 4; + } + + i810_unmap_buffer(buf); + } + BEGIN_LP_RING(4); + OUT_RING( CMD_OP_BATCH_BUFFER ); + OUT_RING( start | BB1_PROTECTED ); + OUT_RING( start + used - 4 ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + + + BEGIN_LP_RING(8); + OUT_RING( CMD_STORE_DWORD_IDX ); + OUT_RING( buf_priv->my_use_idx ); + OUT_RING( I810_BUF_FREE ); + OUT_RING( 0 ); + + OUT_RING( CMD_STORE_DWORD_IDX ); + OUT_RING( 16 ); + OUT_RING( last_render ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); +} + +static int i810_dma_mc(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_device_dma_t *dma = dev->dma; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + drm_i810_mc_t mc; + + if (copy_from_user(&mc, (drm_i810_mc_t __user *)arg, sizeof(mc))) + return -EFAULT; + + LOCK_TEST_WITH_RETURN(dev, filp); + + if (mc.idx >= dma->buf_count || mc.idx < 0) + return -EINVAL; + + i810_dma_dispatch_mc(dev, dma->buflist[mc.idx], mc.used, + mc.last_render ); + + atomic_add(mc.used, &dev->counts[_DRM_STAT_SECONDARY]); + atomic_inc(&dev->counts[_DRM_STAT_DMA]); + sarea_priv->last_enqueue = dev_priv->counter-1; + sarea_priv->last_dispatch = (int) hw_status[5]; + + return 0; +} + +static int i810_rstatus(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + + return (int)(((u32 *)(dev_priv->hw_status_page))[4]); +} + +static int i810_ov0_info(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + drm_i810_overlay_t data; + + data.offset = dev_priv->overlay_offset; + data.physical = dev_priv->overlay_physical; + if (copy_to_user((drm_i810_overlay_t __user *)arg,&data,sizeof(data))) + return -EFAULT; + return 0; +} + +static int i810_fstatus(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + + LOCK_TEST_WITH_RETURN(dev, filp); + + return I810_READ(0x30008); +} + +static int i810_ov0_flip(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + + LOCK_TEST_WITH_RETURN(dev, filp); + + //Tell the overlay to update + I810_WRITE(0x30000,dev_priv->overlay_physical | 0x80000000); + + return 0; +} + + +/* Not sure why this isn't set all the time: + */ +static void i810_do_init_pageflip( drm_device_t *dev ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("%s\n", __FUNCTION__); + dev_priv->page_flipping = 1; + dev_priv->current_page = 0; + dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; +} + +static int i810_do_cleanup_pageflip( drm_device_t *dev ) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("%s\n", __FUNCTION__); + if (dev_priv->current_page != 0) + i810_dma_dispatch_flip( dev ); + + dev_priv->page_flipping = 0; + return 0; +} + +static int i810_flip_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i810_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("%s\n", __FUNCTION__); + + LOCK_TEST_WITH_RETURN(dev, filp); + + if (!dev_priv->page_flipping) + i810_do_init_pageflip( dev ); + + i810_dma_dispatch_flip( dev ); + return 0; +} + +void i810_driver_pretakedown(drm_device_t *dev) +{ + i810_dma_cleanup( dev ); +} + +void i810_driver_prerelease(drm_device_t *dev, DRMFILE filp) +{ + if (dev->dev_private) { + drm_i810_private_t *dev_priv = dev->dev_private; + if (dev_priv->page_flipping) { + i810_do_cleanup_pageflip(dev); + } + } +} + +void i810_driver_release(drm_device_t *dev, struct file *filp) +{ + i810_reclaim_buffers(dev, filp); +} + +int i810_driver_dma_quiescent(drm_device_t *dev) +{ + i810_dma_quiescent( dev ); + return 0; +} + +drm_ioctl_desc_t i810_ioctls[] = { + [DRM_IOCTL_NR(DRM_I810_INIT)] = { i810_dma_init, 1, 1 }, + [DRM_IOCTL_NR(DRM_I810_VERTEX)] = { i810_dma_vertex, 1, 0 }, + [DRM_IOCTL_NR(DRM_I810_CLEAR)] = { i810_clear_bufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_I810_FLUSH)] = { i810_flush_ioctl, 1, 0 }, + [DRM_IOCTL_NR(DRM_I810_GETAGE)] = { i810_getage, 1, 0 }, + [DRM_IOCTL_NR(DRM_I810_GETBUF)] = { i810_getbuf, 1, 0 }, + [DRM_IOCTL_NR(DRM_I810_SWAP)] = { i810_swap_bufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_I810_COPY)] = { i810_copybuf, 1, 0 }, + [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = { i810_docopy, 1, 0 }, + [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = { i810_ov0_info, 1, 0 }, + [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = { i810_fstatus, 1, 0 }, + [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = { i810_ov0_flip, 1, 0 }, + [DRM_IOCTL_NR(DRM_I810_MC)] = { i810_dma_mc, 1, 1 }, + [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = { i810_rstatus, 1, 0 }, + [DRM_IOCTL_NR(DRM_I810_FLIP)] = { i810_flip_bufs, 1, 0 } +}; + +int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls); diff --git a/drivers/char/drm/i810_drm.h b/drivers/char/drm/i810_drm.h new file mode 100644 index 000000000000..73ac40563b1d --- /dev/null +++ b/drivers/char/drm/i810_drm.h @@ -0,0 +1,289 @@ +#ifndef _I810_DRM_H_ +#define _I810_DRM_H_ + +/* WARNING: These defines must be the same as what the Xserver uses. + * if you change them, you must change the defines in the Xserver. + */ + +#ifndef _I810_DEFINES_ +#define _I810_DEFINES_ + +#define I810_DMA_BUF_ORDER 12 +#define I810_DMA_BUF_SZ (1< + * Jeff Hartmann + * Gareth Hughes + */ + +#include +#include "drmP.h" +#include "drm.h" +#include "i810_drm.h" +#include "i810_drv.h" + +#include "drm_pciids.h" + +static int postinit( struct drm_device *dev, unsigned long flags ) +{ + /* i810 has 4 more counters */ + dev->counters += 4; + dev->types[6] = _DRM_STAT_IRQ; + dev->types[7] = _DRM_STAT_PRIMARY; + dev->types[8] = _DRM_STAT_SECONDARY; + dev->types[9] = _DRM_STAT_DMA; + + DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, + dev->primary.minor, + pci_pretty_name(dev->pdev) + ); + return 0; +} + +static int version( drm_version_t *version ) +{ + int len; + + version->version_major = DRIVER_MAJOR; + version->version_minor = DRIVER_MINOR; + version->version_patchlevel = DRIVER_PATCHLEVEL; + DRM_COPY( version->name, DRIVER_NAME ); + DRM_COPY( version->date, DRIVER_DATE ); + DRM_COPY( version->desc, DRIVER_DESC ); + return 0; +} + +static struct pci_device_id pciidlist[] = { + i810_PCI_IDS +}; + +extern drm_ioctl_desc_t i810_ioctls[]; +extern int i810_max_ioctl; + +static struct drm_driver driver = { + .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE, + .dev_priv_size = sizeof(drm_i810_buf_priv_t), + .pretakedown = i810_driver_pretakedown, + .prerelease = i810_driver_prerelease, + .release = i810_driver_release, + .dma_quiescent = i810_driver_dma_quiescent, + .reclaim_buffers = i810_reclaim_buffers, + .get_map_ofs = drm_core_get_map_ofs, + .get_reg_ofs = drm_core_get_reg_ofs, + .postinit = postinit, + .version = version, + .ioctls = i810_ioctls, + .fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + }, + .pci_driver = { + .name = DRIVER_NAME, + .id_table = pciidlist, + }, +}; + +static int __init i810_init(void) +{ + driver.num_ioctls = i810_max_ioctl; + return drm_init(&driver); +} + +static void __exit i810_exit(void) +{ + drm_exit(&driver); +} + +module_init(i810_init); +module_exit(i810_exit); + +MODULE_AUTHOR( DRIVER_AUTHOR ); +MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/i810_drv.h b/drivers/char/drm/i810_drv.h new file mode 100644 index 000000000000..fa23ca454e57 --- /dev/null +++ b/drivers/char/drm/i810_drv.h @@ -0,0 +1,236 @@ +/* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*- + * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * Jeff Hartmann + * + */ + +#ifndef _I810_DRV_H_ +#define _I810_DRV_H_ + +/* General customization: + */ + +#define DRIVER_AUTHOR "VA Linux Systems Inc." + +#define DRIVER_NAME "i810" +#define DRIVER_DESC "Intel i810" +#define DRIVER_DATE "20030605" + +/* Interface history + * + * 1.1 - XFree86 4.1 + * 1.2 - XvMC interfaces + * - XFree86 4.2 + * 1.2.1 - Disable copying code (leave stub ioctls for backwards compatibility) + * - Remove requirement for interrupt (leave stubs again) + * 1.3 - Add page flipping. + * 1.4 - fix DRM interface + */ +#define DRIVER_MAJOR 1 +#define DRIVER_MINOR 4 +#define DRIVER_PATCHLEVEL 0 + +typedef struct drm_i810_buf_priv { + u32 *in_use; + int my_use_idx; + int currently_mapped; + void *virtual; + void *kernel_virtual; +} drm_i810_buf_priv_t; + +typedef struct _drm_i810_ring_buffer{ + int tail_mask; + unsigned long Start; + unsigned long End; + unsigned long Size; + u8 *virtual_start; + int head; + int tail; + int space; +} drm_i810_ring_buffer_t; + +typedef struct drm_i810_private { + drm_map_t *sarea_map; + drm_map_t *mmio_map; + + drm_i810_sarea_t *sarea_priv; + drm_i810_ring_buffer_t ring; + + void *hw_status_page; + unsigned long counter; + + dma_addr_t dma_status_page; + + drm_buf_t *mmap_buffer; + + + u32 front_di1, back_di1, zi1; + + int back_offset; + int depth_offset; + int overlay_offset; + int overlay_physical; + int w, h; + int pitch; + int back_pitch; + int depth_pitch; + + int do_boxes; + int dma_used; + + int current_page; + int page_flipping; + + wait_queue_head_t irq_queue; + atomic_t irq_received; + atomic_t irq_emitted; + + int front_offset; +} drm_i810_private_t; + + /* i810_dma.c */ +extern void i810_reclaim_buffers(drm_device_t *dev, struct file *filp); +extern int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma); + +extern int i810_driver_dma_quiescent(drm_device_t *dev); +extern void i810_driver_release(drm_device_t *dev, struct file *filp); +extern void i810_driver_pretakedown(drm_device_t *dev); +extern void i810_driver_prerelease(drm_device_t *dev, DRMFILE filp); + +#define I810_BASE(reg) ((unsigned long) \ + dev_priv->mmio_map->handle) +#define I810_ADDR(reg) (I810_BASE(reg) + reg) +#define I810_DEREF(reg) *(__volatile__ int *)I810_ADDR(reg) +#define I810_READ(reg) I810_DEREF(reg) +#define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0) +#define I810_DEREF16(reg) *(__volatile__ u16 *)I810_ADDR(reg) +#define I810_READ16(reg) I810_DEREF16(reg) +#define I810_WRITE16(reg,val) do { I810_DEREF16(reg) = val; } while (0) + +#define I810_VERBOSE 0 +#define RING_LOCALS unsigned int outring, ringmask; \ + volatile char *virt; + +#define BEGIN_LP_RING(n) do { \ + if (I810_VERBOSE) \ + DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", n, __FUNCTION__); \ + if (dev_priv->ring.space < n*4) \ + i810_wait_ring(dev, n*4); \ + dev_priv->ring.space -= n*4; \ + outring = dev_priv->ring.tail; \ + ringmask = dev_priv->ring.tail_mask; \ + virt = dev_priv->ring.virtual_start; \ +} while (0) + +#define ADVANCE_LP_RING() do { \ + if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n"); \ + dev_priv->ring.tail = outring; \ + I810_WRITE(LP_RING + RING_TAIL, outring); \ +} while(0) + +#define OUT_RING(n) do { \ + if (I810_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ + *(volatile unsigned int *)(virt + outring) = n; \ + outring += 4; \ + outring &= ringmask; \ +} while (0) + +#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) +#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) +#define CMD_REPORT_HEAD (7<<23) +#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) +#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) + +#define INST_PARSER_CLIENT 0x00000000 +#define INST_OP_FLUSH 0x02000000 +#define INST_FLUSH_MAP_CACHE 0x00000001 + + +#define BB1_START_ADDR_MASK (~0x7) +#define BB1_PROTECTED (1<<0) +#define BB1_UNPROTECTED (0<<0) +#define BB2_END_ADDR_MASK (~0x7) + +#define I810REG_HWSTAM 0x02098 +#define I810REG_INT_IDENTITY_R 0x020a4 +#define I810REG_INT_MASK_R 0x020a8 +#define I810REG_INT_ENABLE_R 0x020a0 + +#define LP_RING 0x2030 +#define HP_RING 0x2040 +#define RING_TAIL 0x00 +#define TAIL_ADDR 0x000FFFF8 +#define RING_HEAD 0x04 +#define HEAD_WRAP_COUNT 0xFFE00000 +#define HEAD_WRAP_ONE 0x00200000 +#define HEAD_ADDR 0x001FFFFC +#define RING_START 0x08 +#define START_ADDR 0x00FFFFF8 +#define RING_LEN 0x0C +#define RING_NR_PAGES 0x000FF000 +#define RING_REPORT_MASK 0x00000006 +#define RING_REPORT_64K 0x00000002 +#define RING_REPORT_128K 0x00000004 +#define RING_NO_REPORT 0x00000000 +#define RING_VALID_MASK 0x00000001 +#define RING_VALID 0x00000001 +#define RING_INVALID 0x00000000 + +#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) +#define SC_UPDATE_SCISSOR (0x1<<1) +#define SC_ENABLE_MASK (0x1<<0) +#define SC_ENABLE (0x1<<0) + +#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) +#define SCI_YMIN_MASK (0xffff<<16) +#define SCI_XMIN_MASK (0xffff<<0) +#define SCI_YMAX_MASK (0xffff<<16) +#define SCI_XMAX_MASK (0xffff<<0) + +#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) +#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) +#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x2) +#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) +#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) +#define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24)) + +#define CMD_OP_Z_BUFFER_INFO ((0x0<<29)|(0x16<<23)) +#define CMD_OP_DESTBUFFER_INFO ((0x0<<29)|(0x15<<23)) +#define CMD_OP_FRONTBUFFER_INFO ((0x0<<29)|(0x14<<23)) +#define CMD_OP_WAIT_FOR_EVENT ((0x0<<29)|(0x03<<23)) + +#define BR00_BITBLT_CLIENT 0x40000000 +#define BR00_OP_COLOR_BLT 0x10000000 +#define BR00_OP_SRC_COPY_BLT 0x10C00000 +#define BR13_SOLID_PATTERN 0x80000000 + +#define WAIT_FOR_PLANE_A_SCANLINES (1<<1) +#define WAIT_FOR_PLANE_A_FLIP (1<<2) +#define WAIT_FOR_VBLANK (1<<3) + +#endif diff --git a/drivers/char/drm/i830_dma.c b/drivers/char/drm/i830_dma.c new file mode 100644 index 000000000000..98adccf8e434 --- /dev/null +++ b/drivers/char/drm/i830_dma.c @@ -0,0 +1,1588 @@ +/* i830_dma.c -- DMA support for the I830 -*- linux-c -*- + * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * Jeff Hartmann + * Keith Whitwell + * Abraham vd Merwe + * + */ + +#include "drmP.h" +#include "drm.h" +#include "i830_drm.h" +#include "i830_drv.h" +#include /* For task queue support */ +#include /* For FASTCALL on unlock_page() */ +#include +#include + +#define I830_BUF_FREE 2 +#define I830_BUF_CLIENT 1 +#define I830_BUF_HARDWARE 0 + +#define I830_BUF_UNMAPPED 0 +#define I830_BUF_MAPPED 1 + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,2) +#define down_write down +#define up_write up +#endif + +static drm_buf_t *i830_freelist_get(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + int i; + int used; + + /* Linear search might not be the best solution */ + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + /* In use is already a pointer */ + used = cmpxchg(buf_priv->in_use, I830_BUF_FREE, + I830_BUF_CLIENT); + if(used == I830_BUF_FREE) { + return buf; + } + } + return NULL; +} + +/* This should only be called if the buffer is not sent to the hardware + * yet, the hardware updates in use for us once its on the ring buffer. + */ + +static int i830_freelist_put(drm_device_t *dev, drm_buf_t *buf) +{ + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + int used; + + /* In use is already a pointer */ + used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE); + if(used != I830_BUF_CLIENT) { + DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); + return -EINVAL; + } + + return 0; +} + +static struct file_operations i830_buffer_fops = { + .open = drm_open, + .flush = drm_flush, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = i830_mmap_buffers, + .fasync = drm_fasync, +}; + +int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + drm_i830_private_t *dev_priv; + drm_buf_t *buf; + drm_i830_buf_priv_t *buf_priv; + + lock_kernel(); + dev = priv->head->dev; + dev_priv = dev->dev_private; + buf = dev_priv->mmap_buffer; + buf_priv = buf->dev_private; + + vma->vm_flags |= (VM_IO | VM_DONTCOPY); + vma->vm_file = filp; + + buf_priv->currently_mapped = I830_BUF_MAPPED; + unlock_kernel(); + + if (io_remap_pfn_range(vma, vma->vm_start, + VM_OFFSET(vma) >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) return -EAGAIN; + return 0; +} + +static int i830_map_buffer(drm_buf_t *buf, struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; + struct file_operations *old_fops; + unsigned long virtual; + int retcode = 0; + + if(buf_priv->currently_mapped == I830_BUF_MAPPED) return -EINVAL; + + down_write( ¤t->mm->mmap_sem ); + old_fops = filp->f_op; + filp->f_op = &i830_buffer_fops; + dev_priv->mmap_buffer = buf; + virtual = do_mmap(filp, 0, buf->total, PROT_READ|PROT_WRITE, + MAP_SHARED, buf->bus_address); + dev_priv->mmap_buffer = NULL; + filp->f_op = old_fops; + if (IS_ERR((void *)virtual)) { /* ugh */ + /* Real error */ + DRM_ERROR("mmap error\n"); + retcode = virtual; + buf_priv->virtual = NULL; + } else { + buf_priv->virtual = (void __user *)virtual; + } + up_write( ¤t->mm->mmap_sem ); + + return retcode; +} + +static int i830_unmap_buffer(drm_buf_t *buf) +{ + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + int retcode = 0; + + if(buf_priv->currently_mapped != I830_BUF_MAPPED) + return -EINVAL; + + down_write(¤t->mm->mmap_sem); + retcode = do_munmap(current->mm, + (unsigned long)buf_priv->virtual, + (size_t) buf->total); + up_write(¤t->mm->mmap_sem); + + buf_priv->currently_mapped = I830_BUF_UNMAPPED; + buf_priv->virtual = NULL; + + return retcode; +} + +static int i830_dma_get_buffer(drm_device_t *dev, drm_i830_dma_t *d, + struct file *filp) +{ + drm_buf_t *buf; + drm_i830_buf_priv_t *buf_priv; + int retcode = 0; + + buf = i830_freelist_get(dev); + if (!buf) { + retcode = -ENOMEM; + DRM_DEBUG("retcode=%d\n", retcode); + return retcode; + } + + retcode = i830_map_buffer(buf, filp); + if(retcode) { + i830_freelist_put(dev, buf); + DRM_ERROR("mapbuf failed, retcode %d\n", retcode); + return retcode; + } + buf->filp = filp; + buf_priv = buf->dev_private; + d->granted = 1; + d->request_idx = buf->idx; + d->request_size = buf->total; + d->virtual = buf_priv->virtual; + + return retcode; +} + +static int i830_dma_cleanup(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + + /* Make sure interrupts are disabled here because the uninstall ioctl + * may not have been called from userspace and after dev_private + * is freed, it's too late. + */ + if ( dev->irq_enabled ) drm_irq_uninstall(dev); + + if (dev->dev_private) { + int i; + drm_i830_private_t *dev_priv = + (drm_i830_private_t *) dev->dev_private; + + if (dev_priv->ring.virtual_start) { + drm_ioremapfree((void *) dev_priv->ring.virtual_start, + dev_priv->ring.Size, dev); + } + if (dev_priv->hw_status_page) { + pci_free_consistent(dev->pdev, PAGE_SIZE, + dev_priv->hw_status_page, + dev_priv->dma_status_page); + /* Need to rewrite hardware status page */ + I830_WRITE(0x02080, 0x1ffff000); + } + + drm_free(dev->dev_private, sizeof(drm_i830_private_t), + DRM_MEM_DRIVER); + dev->dev_private = NULL; + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + if ( buf_priv->kernel_virtual && buf->total ) + drm_ioremapfree(buf_priv->kernel_virtual, buf->total, dev); + } + } + return 0; +} + +int i830_wait_ring(drm_device_t *dev, int n, const char *caller) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_ring_buffer_t *ring = &(dev_priv->ring); + int iters = 0; + unsigned long end; + unsigned int last_head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + + end = jiffies + (HZ*3); + while (ring->space < n) { + ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->space = ring->head - (ring->tail+8); + if (ring->space < 0) ring->space += ring->Size; + + if (ring->head != last_head) { + end = jiffies + (HZ*3); + last_head = ring->head; + } + + iters++; + if(time_before(end, jiffies)) { + DRM_ERROR("space: %d wanted %d\n", ring->space, n); + DRM_ERROR("lockup\n"); + goto out_wait_ring; + } + udelay(1); + dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT; + } + +out_wait_ring: + return iters; +} + +static void i830_kernel_lost_context(drm_device_t *dev) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_ring_buffer_t *ring = &(dev_priv->ring); + + ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR; + ring->space = ring->head - (ring->tail+8); + if (ring->space < 0) ring->space += ring->Size; + + if (ring->head == ring->tail) + dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY; +} + +static int i830_freelist_init(drm_device_t *dev, drm_i830_private_t *dev_priv) +{ + drm_device_dma_t *dma = dev->dma; + int my_idx = 36; + u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx); + int i; + + if(dma->buf_count > 1019) { + /* Not enough space in the status page for the freelist */ + return -EINVAL; + } + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + + buf_priv->in_use = hw_status++; + buf_priv->my_use_idx = my_idx; + my_idx += 4; + + *buf_priv->in_use = I830_BUF_FREE; + + buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, + buf->total, dev); + } + return 0; +} + +static int i830_dma_initialize(drm_device_t *dev, + drm_i830_private_t *dev_priv, + drm_i830_init_t *init) +{ + struct list_head *list; + + memset(dev_priv, 0, sizeof(drm_i830_private_t)); + + list_for_each(list, &dev->maplist->head) { + drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); + if( r_list->map && + r_list->map->type == _DRM_SHM && + r_list->map->flags & _DRM_CONTAINS_LOCK ) { + dev_priv->sarea_map = r_list->map; + break; + } + } + + if(!dev_priv->sarea_map) { + dev->dev_private = (void *)dev_priv; + i830_dma_cleanup(dev); + DRM_ERROR("can not find sarea!\n"); + return -EINVAL; + } + dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); + if(!dev_priv->mmio_map) { + dev->dev_private = (void *)dev_priv; + i830_dma_cleanup(dev); + DRM_ERROR("can not find mmio map!\n"); + return -EINVAL; + } + dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); + if(!dev->agp_buffer_map) { + dev->dev_private = (void *)dev_priv; + i830_dma_cleanup(dev); + DRM_ERROR("can not find dma buffer map!\n"); + return -EINVAL; + } + + dev_priv->sarea_priv = (drm_i830_sarea_t *) + ((u8 *)dev_priv->sarea_map->handle + + init->sarea_priv_offset); + + dev_priv->ring.Start = init->ring_start; + dev_priv->ring.End = init->ring_end; + dev_priv->ring.Size = init->ring_size; + + dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + + init->ring_start, + init->ring_size, dev); + + if (dev_priv->ring.virtual_start == NULL) { + dev->dev_private = (void *) dev_priv; + i830_dma_cleanup(dev); + DRM_ERROR("can not ioremap virtual address for" + " ring buffer\n"); + return -ENOMEM; + } + + dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; + + dev_priv->w = init->w; + dev_priv->h = init->h; + dev_priv->pitch = init->pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->depth_offset = init->depth_offset; + dev_priv->front_offset = init->front_offset; + + dev_priv->front_di1 = init->front_offset | init->pitch_bits; + dev_priv->back_di1 = init->back_offset | init->pitch_bits; + dev_priv->zi1 = init->depth_offset | init->pitch_bits; + + DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1); + DRM_DEBUG("back_offset %x\n", dev_priv->back_offset); + DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1); + DRM_DEBUG("pitch_bits %x\n", init->pitch_bits); + + dev_priv->cpp = init->cpp; + /* We are using separate values as placeholders for mechanisms for + * private backbuffer/depthbuffer usage. + */ + + dev_priv->back_pitch = init->back_pitch; + dev_priv->depth_pitch = init->depth_pitch; + dev_priv->do_boxes = 0; + dev_priv->use_mi_batchbuffer_start = 0; + + /* Program Hardware Status Page */ + dev_priv->hw_status_page = + pci_alloc_consistent(dev->pdev, PAGE_SIZE, + &dev_priv->dma_status_page); + if (!dev_priv->hw_status_page) { + dev->dev_private = (void *)dev_priv; + i830_dma_cleanup(dev); + DRM_ERROR("Can not allocate hardware status page\n"); + return -ENOMEM; + } + memset(dev_priv->hw_status_page, 0, PAGE_SIZE); + DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); + + I830_WRITE(0x02080, dev_priv->dma_status_page); + DRM_DEBUG("Enabled hardware status page\n"); + + /* Now we need to init our freelist */ + if(i830_freelist_init(dev, dev_priv) != 0) { + dev->dev_private = (void *)dev_priv; + i830_dma_cleanup(dev); + DRM_ERROR("Not enough space in the status page for" + " the freelist\n"); + return -ENOMEM; + } + dev->dev_private = (void *)dev_priv; + + return 0; +} + +static int i830_dma_init(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i830_private_t *dev_priv; + drm_i830_init_t init; + int retcode = 0; + + if (copy_from_user(&init, (void * __user) arg, sizeof(init))) + return -EFAULT; + + switch(init.func) { + case I830_INIT_DMA: + dev_priv = drm_alloc(sizeof(drm_i830_private_t), + DRM_MEM_DRIVER); + if(dev_priv == NULL) return -ENOMEM; + retcode = i830_dma_initialize(dev, dev_priv, &init); + break; + case I830_CLEANUP_DMA: + retcode = i830_dma_cleanup(dev); + break; + default: + retcode = -EINVAL; + break; + } + + return retcode; +} + +#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) +#define ST1_ENABLE (1<<16) +#define ST1_MASK (0xffff) + +/* Most efficient way to verify state for the i830 is as it is + * emitted. Non-conformant state is silently dropped. + */ +static void i830EmitContextVerified( drm_device_t *dev, + unsigned int *code ) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + int i, j = 0; + unsigned int tmp; + RING_LOCALS; + + BEGIN_LP_RING( I830_CTX_SETUP_SIZE + 4 ); + + for ( i = 0 ; i < I830_CTXREG_BLENDCOLR0 ; i++ ) { + tmp = code[i]; + if ((tmp & (7<<29)) == CMD_3D && + (tmp & (0x1f<<24)) < (0x1d<<24)) { + OUT_RING( tmp ); + j++; + } else { + DRM_ERROR("Skipping %d\n", i); + } + } + + OUT_RING( STATE3D_CONST_BLEND_COLOR_CMD ); + OUT_RING( code[I830_CTXREG_BLENDCOLR] ); + j += 2; + + for ( i = I830_CTXREG_VF ; i < I830_CTXREG_MCSB0 ; i++ ) { + tmp = code[i]; + if ((tmp & (7<<29)) == CMD_3D && + (tmp & (0x1f<<24)) < (0x1d<<24)) { + OUT_RING( tmp ); + j++; + } else { + DRM_ERROR("Skipping %d\n", i); + } + } + + OUT_RING( STATE3D_MAP_COORD_SETBIND_CMD ); + OUT_RING( code[I830_CTXREG_MCSB1] ); + j += 2; + + if (j & 1) + OUT_RING( 0 ); + + ADVANCE_LP_RING(); +} + +static void i830EmitTexVerified( drm_device_t *dev, unsigned int *code ) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + int i, j = 0; + unsigned int tmp; + RING_LOCALS; + + if (code[I830_TEXREG_MI0] == GFX_OP_MAP_INFO || + (code[I830_TEXREG_MI0] & ~(0xf*LOAD_TEXTURE_MAP0)) == + (STATE3D_LOAD_STATE_IMMEDIATE_2|4)) { + + BEGIN_LP_RING( I830_TEX_SETUP_SIZE ); + + OUT_RING( code[I830_TEXREG_MI0] ); /* TM0LI */ + OUT_RING( code[I830_TEXREG_MI1] ); /* TM0S0 */ + OUT_RING( code[I830_TEXREG_MI2] ); /* TM0S1 */ + OUT_RING( code[I830_TEXREG_MI3] ); /* TM0S2 */ + OUT_RING( code[I830_TEXREG_MI4] ); /* TM0S3 */ + OUT_RING( code[I830_TEXREG_MI5] ); /* TM0S4 */ + + for ( i = 6 ; i < I830_TEX_SETUP_SIZE ; i++ ) { + tmp = code[i]; + OUT_RING( tmp ); + j++; + } + + if (j & 1) + OUT_RING( 0 ); + + ADVANCE_LP_RING(); + } + else + printk("rejected packet %x\n", code[0]); +} + +static void i830EmitTexBlendVerified( drm_device_t *dev, + unsigned int *code, + unsigned int num) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + int i, j = 0; + unsigned int tmp; + RING_LOCALS; + + if (!num) + return; + + BEGIN_LP_RING( num + 1 ); + + for ( i = 0 ; i < num ; i++ ) { + tmp = code[i]; + OUT_RING( tmp ); + j++; + } + + if (j & 1) + OUT_RING( 0 ); + + ADVANCE_LP_RING(); +} + +static void i830EmitTexPalette( drm_device_t *dev, + unsigned int *palette, + int number, + int is_shared ) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + int i; + RING_LOCALS; + + return; + + BEGIN_LP_RING( 258 ); + + if(is_shared == 1) { + OUT_RING(CMD_OP_MAP_PALETTE_LOAD | + MAP_PALETTE_NUM(0) | + MAP_PALETTE_BOTH); + } else { + OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(number)); + } + for(i = 0; i < 256; i++) { + OUT_RING(palette[i]); + } + OUT_RING(0); + /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop! + */ +} + +/* Need to do some additional checking when setting the dest buffer. + */ +static void i830EmitDestVerified( drm_device_t *dev, + unsigned int *code ) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + unsigned int tmp; + RING_LOCALS; + + BEGIN_LP_RING( I830_DEST_SETUP_SIZE + 10 ); + + + tmp = code[I830_DESTREG_CBUFADDR]; + if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { + if (((int)outring) & 8) { + OUT_RING(0); + OUT_RING(0); + } + + OUT_RING( CMD_OP_DESTBUFFER_INFO ); + OUT_RING( BUF_3D_ID_COLOR_BACK | + BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) | + BUF_3D_USE_FENCE); + OUT_RING( tmp ); + OUT_RING( 0 ); + + OUT_RING( CMD_OP_DESTBUFFER_INFO ); + OUT_RING( BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE | + BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp)); + OUT_RING( dev_priv->zi1 ); + OUT_RING( 0 ); + } else { + DRM_ERROR("bad di1 %x (allow %x or %x)\n", + tmp, dev_priv->front_di1, dev_priv->back_di1); + } + + /* invarient: + */ + + + OUT_RING( GFX_OP_DESTBUFFER_VARS ); + OUT_RING( code[I830_DESTREG_DV1] ); + + OUT_RING( GFX_OP_DRAWRECT_INFO ); + OUT_RING( code[I830_DESTREG_DR1] ); + OUT_RING( code[I830_DESTREG_DR2] ); + OUT_RING( code[I830_DESTREG_DR3] ); + OUT_RING( code[I830_DESTREG_DR4] ); + + /* Need to verify this */ + tmp = code[I830_DESTREG_SENABLE]; + if((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) { + OUT_RING( tmp ); + } else { + DRM_ERROR("bad scissor enable\n"); + OUT_RING( 0 ); + } + + OUT_RING( GFX_OP_SCISSOR_RECT ); + OUT_RING( code[I830_DESTREG_SR1] ); + OUT_RING( code[I830_DESTREG_SR2] ); + OUT_RING( 0 ); + + ADVANCE_LP_RING(); +} + +static void i830EmitStippleVerified( drm_device_t *dev, + unsigned int *code ) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + + BEGIN_LP_RING( 2 ); + OUT_RING( GFX_OP_STIPPLE ); + OUT_RING( code[1] ); + ADVANCE_LP_RING(); +} + + +static void i830EmitState( drm_device_t *dev ) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int dirty = sarea_priv->dirty; + + DRM_DEBUG("%s %x\n", __FUNCTION__, dirty); + + if (dirty & I830_UPLOAD_BUFFERS) { + i830EmitDestVerified( dev, sarea_priv->BufferState ); + sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS; + } + + if (dirty & I830_UPLOAD_CTX) { + i830EmitContextVerified( dev, sarea_priv->ContextState ); + sarea_priv->dirty &= ~I830_UPLOAD_CTX; + } + + if (dirty & I830_UPLOAD_TEX0) { + i830EmitTexVerified( dev, sarea_priv->TexState[0] ); + sarea_priv->dirty &= ~I830_UPLOAD_TEX0; + } + + if (dirty & I830_UPLOAD_TEX1) { + i830EmitTexVerified( dev, sarea_priv->TexState[1] ); + sarea_priv->dirty &= ~I830_UPLOAD_TEX1; + } + + if (dirty & I830_UPLOAD_TEXBLEND0) { + i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[0], + sarea_priv->TexBlendStateWordsUsed[0]); + sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0; + } + + if (dirty & I830_UPLOAD_TEXBLEND1) { + i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[1], + sarea_priv->TexBlendStateWordsUsed[1]); + sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1; + } + + if (dirty & I830_UPLOAD_TEX_PALETTE_SHARED) { + i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 1); + } else { + if (dirty & I830_UPLOAD_TEX_PALETTE_N(0)) { + i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 0); + sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(0); + } + if (dirty & I830_UPLOAD_TEX_PALETTE_N(1)) { + i830EmitTexPalette(dev, sarea_priv->Palette[1], 1, 0); + sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(1); + } + + /* 1.3: + */ +#if 0 + if (dirty & I830_UPLOAD_TEX_PALETTE_N(2)) { + i830EmitTexPalette(dev, sarea_priv->Palette2[0], 0, 0); + sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2); + } + if (dirty & I830_UPLOAD_TEX_PALETTE_N(3)) { + i830EmitTexPalette(dev, sarea_priv->Palette2[1], 1, 0); + sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2); + } +#endif + } + + /* 1.3: + */ + if (dirty & I830_UPLOAD_STIPPLE) { + i830EmitStippleVerified( dev, + sarea_priv->StippleState); + sarea_priv->dirty &= ~I830_UPLOAD_STIPPLE; + } + + if (dirty & I830_UPLOAD_TEX2) { + i830EmitTexVerified( dev, sarea_priv->TexState2 ); + sarea_priv->dirty &= ~I830_UPLOAD_TEX2; + } + + if (dirty & I830_UPLOAD_TEX3) { + i830EmitTexVerified( dev, sarea_priv->TexState3 ); + sarea_priv->dirty &= ~I830_UPLOAD_TEX3; + } + + + if (dirty & I830_UPLOAD_TEXBLEND2) { + i830EmitTexBlendVerified( + dev, + sarea_priv->TexBlendState2, + sarea_priv->TexBlendStateWordsUsed2); + + sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND2; + } + + if (dirty & I830_UPLOAD_TEXBLEND3) { + i830EmitTexBlendVerified( + dev, + sarea_priv->TexBlendState3, + sarea_priv->TexBlendStateWordsUsed3); + sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND3; + } +} + +/* ================================================================ + * Performance monitoring functions + */ + +static void i830_fill_box( drm_device_t *dev, + int x, int y, int w, int h, + int r, int g, int b ) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + u32 color; + unsigned int BR13, CMD; + RING_LOCALS; + + BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1<<24); + CMD = XY_COLOR_BLT_CMD; + x += dev_priv->sarea_priv->boxes[0].x1; + y += dev_priv->sarea_priv->boxes[0].y1; + + if (dev_priv->cpp == 4) { + BR13 |= (1<<25); + CMD |= (XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB); + color = (((0xff) << 24) | (r << 16) | (g << 8) | b); + } else { + color = (((r & 0xf8) << 8) | + ((g & 0xfc) << 3) | + ((b & 0xf8) >> 3)); + } + + BEGIN_LP_RING( 6 ); + OUT_RING( CMD ); + OUT_RING( BR13 ); + OUT_RING( (y << 16) | x ); + OUT_RING( ((y+h) << 16) | (x+w) ); + + if ( dev_priv->current_page == 1 ) { + OUT_RING( dev_priv->front_offset ); + } else { + OUT_RING( dev_priv->back_offset ); + } + + OUT_RING( color ); + ADVANCE_LP_RING(); +} + +static void i830_cp_performance_boxes( drm_device_t *dev ) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + + /* Purple box for page flipping + */ + if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP ) + i830_fill_box( dev, 4, 4, 8, 8, 255, 0, 255 ); + + /* Red box if we have to wait for idle at any point + */ + if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT ) + i830_fill_box( dev, 16, 4, 8, 8, 255, 0, 0 ); + + /* Blue box: lost context? + */ + if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT ) + i830_fill_box( dev, 28, 4, 8, 8, 0, 0, 255 ); + + /* Yellow box for texture swaps + */ + if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD ) + i830_fill_box( dev, 40, 4, 8, 8, 255, 255, 0 ); + + /* Green box if hardware never idles (as far as we can tell) + */ + if ( !(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY) ) + i830_fill_box( dev, 64, 4, 8, 8, 0, 255, 0 ); + + + /* Draw bars indicating number of buffers allocated + * (not a great measure, easily confused) + */ + if (dev_priv->dma_used) { + int bar = dev_priv->dma_used / 10240; + if (bar > 100) bar = 100; + if (bar < 1) bar = 1; + i830_fill_box( dev, 4, 16, bar, 4, 196, 128, 128 ); + dev_priv->dma_used = 0; + } + + dev_priv->sarea_priv->perf_boxes = 0; +} + +static void i830_dma_dispatch_clear( drm_device_t *dev, int flags, + unsigned int clear_color, + unsigned int clear_zval, + unsigned int clear_depthmask) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int pitch = dev_priv->pitch; + int cpp = dev_priv->cpp; + int i; + unsigned int BR13, CMD, D_CMD; + RING_LOCALS; + + + if ( dev_priv->current_page == 1 ) { + unsigned int tmp = flags; + + flags &= ~(I830_FRONT | I830_BACK); + if ( tmp & I830_FRONT ) flags |= I830_BACK; + if ( tmp & I830_BACK ) flags |= I830_FRONT; + } + + i830_kernel_lost_context(dev); + + switch(cpp) { + case 2: + BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24); + D_CMD = CMD = XY_COLOR_BLT_CMD; + break; + case 4: + BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24) | (1<<25); + CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA | + XY_COLOR_BLT_WRITE_RGB); + D_CMD = XY_COLOR_BLT_CMD; + if(clear_depthmask & 0x00ffffff) + D_CMD |= XY_COLOR_BLT_WRITE_RGB; + if(clear_depthmask & 0xff000000) + D_CMD |= XY_COLOR_BLT_WRITE_ALPHA; + break; + default: + BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24); + D_CMD = CMD = XY_COLOR_BLT_CMD; + break; + } + + if (nbox > I830_NR_SAREA_CLIPRECTS) + nbox = I830_NR_SAREA_CLIPRECTS; + + for (i = 0 ; i < nbox ; i++, pbox++) { + if (pbox->x1 > pbox->x2 || + pbox->y1 > pbox->y2 || + pbox->x2 > dev_priv->w || + pbox->y2 > dev_priv->h) + continue; + + if ( flags & I830_FRONT ) { + DRM_DEBUG("clear front\n"); + BEGIN_LP_RING( 6 ); + OUT_RING( CMD ); + OUT_RING( BR13 ); + OUT_RING( (pbox->y1 << 16) | pbox->x1 ); + OUT_RING( (pbox->y2 << 16) | pbox->x2 ); + OUT_RING( dev_priv->front_offset ); + OUT_RING( clear_color ); + ADVANCE_LP_RING(); + } + + if ( flags & I830_BACK ) { + DRM_DEBUG("clear back\n"); + BEGIN_LP_RING( 6 ); + OUT_RING( CMD ); + OUT_RING( BR13 ); + OUT_RING( (pbox->y1 << 16) | pbox->x1 ); + OUT_RING( (pbox->y2 << 16) | pbox->x2 ); + OUT_RING( dev_priv->back_offset ); + OUT_RING( clear_color ); + ADVANCE_LP_RING(); + } + + if ( flags & I830_DEPTH ) { + DRM_DEBUG("clear depth\n"); + BEGIN_LP_RING( 6 ); + OUT_RING( D_CMD ); + OUT_RING( BR13 ); + OUT_RING( (pbox->y1 << 16) | pbox->x1 ); + OUT_RING( (pbox->y2 << 16) | pbox->x2 ); + OUT_RING( dev_priv->depth_offset ); + OUT_RING( clear_zval ); + ADVANCE_LP_RING(); + } + } +} + +static void i830_dma_dispatch_swap( drm_device_t *dev ) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int pitch = dev_priv->pitch; + int cpp = dev_priv->cpp; + int i; + unsigned int CMD, BR13; + RING_LOCALS; + + DRM_DEBUG("swapbuffers\n"); + + i830_kernel_lost_context(dev); + + if (dev_priv->do_boxes) + i830_cp_performance_boxes( dev ); + + switch(cpp) { + case 2: + BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24); + CMD = XY_SRC_COPY_BLT_CMD; + break; + case 4: + BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24) | (1<<25); + CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | + XY_SRC_COPY_BLT_WRITE_RGB); + break; + default: + BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24); + CMD = XY_SRC_COPY_BLT_CMD; + break; + } + + + if (nbox > I830_NR_SAREA_CLIPRECTS) + nbox = I830_NR_SAREA_CLIPRECTS; + + for (i = 0 ; i < nbox; i++, pbox++) + { + if (pbox->x1 > pbox->x2 || + pbox->y1 > pbox->y2 || + pbox->x2 > dev_priv->w || + pbox->y2 > dev_priv->h) + continue; + + DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n", + pbox->x1, pbox->y1, + pbox->x2, pbox->y2); + + BEGIN_LP_RING( 8 ); + OUT_RING( CMD ); + OUT_RING( BR13 ); + OUT_RING( (pbox->y1 << 16) | pbox->x1 ); + OUT_RING( (pbox->y2 << 16) | pbox->x2 ); + + if (dev_priv->current_page == 0) + OUT_RING( dev_priv->front_offset ); + else + OUT_RING( dev_priv->back_offset ); + + OUT_RING( (pbox->y1 << 16) | pbox->x1 ); + OUT_RING( BR13 & 0xffff ); + + if (dev_priv->current_page == 0) + OUT_RING( dev_priv->back_offset ); + else + OUT_RING( dev_priv->front_offset ); + + ADVANCE_LP_RING(); + } +} + +static void i830_dma_dispatch_flip( drm_device_t *dev ) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + + DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, + dev_priv->sarea_priv->pf_current_page); + + i830_kernel_lost_context(dev); + + if (dev_priv->do_boxes) { + dev_priv->sarea_priv->perf_boxes |= I830_BOX_FLIP; + i830_cp_performance_boxes( dev ); + } + + + BEGIN_LP_RING( 2 ); + OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + + BEGIN_LP_RING( 6 ); + OUT_RING( CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP ); + OUT_RING( 0 ); + if ( dev_priv->current_page == 0 ) { + OUT_RING( dev_priv->back_offset ); + dev_priv->current_page = 1; + } else { + OUT_RING( dev_priv->front_offset ); + dev_priv->current_page = 0; + } + OUT_RING(0); + ADVANCE_LP_RING(); + + + BEGIN_LP_RING( 2 ); + OUT_RING( MI_WAIT_FOR_EVENT | + MI_WAIT_FOR_PLANE_A_FLIP ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + + + dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; +} + +static void i830_dma_dispatch_vertex(drm_device_t *dev, + drm_buf_t *buf, + int discard, + int used) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_clip_rect_t *box = sarea_priv->boxes; + int nbox = sarea_priv->nbox; + unsigned long address = (unsigned long)buf->bus_address; + unsigned long start = address - dev->agp->base; + int i = 0, u; + RING_LOCALS; + + i830_kernel_lost_context(dev); + + if (nbox > I830_NR_SAREA_CLIPRECTS) + nbox = I830_NR_SAREA_CLIPRECTS; + + if (discard) { + u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, + I830_BUF_HARDWARE); + if(u != I830_BUF_CLIENT) { + DRM_DEBUG("xxxx 2\n"); + } + } + + if (used > 4*1023) + used = 0; + + if (sarea_priv->dirty) + i830EmitState( dev ); + + DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n", + address, used, nbox); + + dev_priv->counter++; + DRM_DEBUG( "dispatch counter : %ld\n", dev_priv->counter); + DRM_DEBUG( "i830_dma_dispatch\n"); + DRM_DEBUG( "start : %lx\n", start); + DRM_DEBUG( "used : %d\n", used); + DRM_DEBUG( "start + used - 4 : %ld\n", start + used - 4); + + if (buf_priv->currently_mapped == I830_BUF_MAPPED) { + u32 *vp = buf_priv->kernel_virtual; + + vp[0] = (GFX_OP_PRIMITIVE | + sarea_priv->vertex_prim | + ((used/4)-2)); + + if (dev_priv->use_mi_batchbuffer_start) { + vp[used/4] = MI_BATCH_BUFFER_END; + used += 4; + } + + if (used & 4) { + vp[used/4] = 0; + used += 4; + } + + i830_unmap_buffer(buf); + } + + if (used) { + do { + if (i < nbox) { + BEGIN_LP_RING(6); + OUT_RING( GFX_OP_DRAWRECT_INFO ); + OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR1] ); + OUT_RING( box[i].x1 | (box[i].y1<<16) ); + OUT_RING( box[i].x2 | (box[i].y2<<16) ); + OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR4] ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + } + + if (dev_priv->use_mi_batchbuffer_start) { + BEGIN_LP_RING(2); + OUT_RING( MI_BATCH_BUFFER_START | (2<<6) ); + OUT_RING( start | MI_BATCH_NON_SECURE ); + ADVANCE_LP_RING(); + } + else { + BEGIN_LP_RING(4); + OUT_RING( MI_BATCH_BUFFER ); + OUT_RING( start | MI_BATCH_NON_SECURE ); + OUT_RING( start + used - 4 ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + } + + } while (++i < nbox); + } + + if (discard) { + dev_priv->counter++; + + (void) cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, + I830_BUF_HARDWARE); + + BEGIN_LP_RING(8); + OUT_RING( CMD_STORE_DWORD_IDX ); + OUT_RING( 20 ); + OUT_RING( dev_priv->counter ); + OUT_RING( CMD_STORE_DWORD_IDX ); + OUT_RING( buf_priv->my_use_idx ); + OUT_RING( I830_BUF_FREE ); + OUT_RING( CMD_REPORT_HEAD ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + } +} + + +static void i830_dma_quiescent(drm_device_t *dev) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + + i830_kernel_lost_context(dev); + + BEGIN_LP_RING(4); + OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); + OUT_RING( CMD_REPORT_HEAD ); + OUT_RING( 0 ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + + i830_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ ); +} + +static int i830_flush_queue(drm_device_t *dev) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + int i, ret = 0; + RING_LOCALS; + + i830_kernel_lost_context(dev); + + BEGIN_LP_RING(2); + OUT_RING( CMD_REPORT_HEAD ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + + i830_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ ); + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + + int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE, + I830_BUF_FREE); + + if (used == I830_BUF_HARDWARE) + DRM_DEBUG("reclaimed from HARDWARE\n"); + if (used == I830_BUF_CLIENT) + DRM_DEBUG("still on client\n"); + } + + return ret; +} + +/* Must be called with the lock held */ +void i830_reclaim_buffers(drm_device_t *dev, struct file *filp) +{ + drm_device_dma_t *dma = dev->dma; + int i; + + if (!dma) return; + if (!dev->dev_private) return; + if (!dma->buflist) return; + + i830_flush_queue(dev); + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + + if (buf->filp == filp && buf_priv) { + int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, + I830_BUF_FREE); + + if (used == I830_BUF_CLIENT) + DRM_DEBUG("reclaimed from client\n"); + if(buf_priv->currently_mapped == I830_BUF_MAPPED) + buf_priv->currently_mapped = I830_BUF_UNMAPPED; + } + } +} + +static int i830_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + + LOCK_TEST_WITH_RETURN(dev, filp); + + i830_flush_queue(dev); + return 0; +} + +static int i830_dma_vertex(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_device_dma_t *dma = dev->dma; + drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) + dev_priv->sarea_priv; + drm_i830_vertex_t vertex; + + if (copy_from_user(&vertex, (drm_i830_vertex_t __user *)arg, sizeof(vertex))) + return -EFAULT; + + LOCK_TEST_WITH_RETURN(dev, filp); + + DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n", + vertex.idx, vertex.used, vertex.discard); + + if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL; + + i830_dma_dispatch_vertex( dev, + dma->buflist[ vertex.idx ], + vertex.discard, vertex.used ); + + sarea_priv->last_enqueue = dev_priv->counter-1; + sarea_priv->last_dispatch = (int) hw_status[5]; + + return 0; +} + +static int i830_clear_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i830_clear_t clear; + + if (copy_from_user(&clear, (drm_i830_clear_t __user *)arg, sizeof(clear))) + return -EFAULT; + + LOCK_TEST_WITH_RETURN(dev, filp); + + /* GH: Someone's doing nasty things... */ + if (!dev->dev_private) { + return -EINVAL; + } + + i830_dma_dispatch_clear( dev, clear.flags, + clear.clear_color, + clear.clear_depth, + clear.clear_depthmask); + return 0; +} + +static int i830_swap_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + + DRM_DEBUG("i830_swap_bufs\n"); + + LOCK_TEST_WITH_RETURN(dev, filp); + + i830_dma_dispatch_swap( dev ); + return 0; +} + + + +/* Not sure why this isn't set all the time: + */ +static void i830_do_init_pageflip( drm_device_t *dev ) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("%s\n", __FUNCTION__); + dev_priv->page_flipping = 1; + dev_priv->current_page = 0; + dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; +} + +static int i830_do_cleanup_pageflip( drm_device_t *dev ) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("%s\n", __FUNCTION__); + if (dev_priv->current_page != 0) + i830_dma_dispatch_flip( dev ); + + dev_priv->page_flipping = 0; + return 0; +} + +static int i830_flip_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i830_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("%s\n", __FUNCTION__); + + LOCK_TEST_WITH_RETURN(dev, filp); + + if (!dev_priv->page_flipping) + i830_do_init_pageflip( dev ); + + i830_dma_dispatch_flip( dev ); + return 0; +} + +static int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) + dev_priv->sarea_priv; + + sarea_priv->last_dispatch = (int) hw_status[5]; + return 0; +} + +static int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + int retcode = 0; + drm_i830_dma_t d; + drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) + dev_priv->sarea_priv; + + DRM_DEBUG("getbuf\n"); + if (copy_from_user(&d, (drm_i830_dma_t __user *)arg, sizeof(d))) + return -EFAULT; + + LOCK_TEST_WITH_RETURN(dev, filp); + + d.granted = 0; + + retcode = i830_dma_get_buffer(dev, &d, filp); + + DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n", + current->pid, retcode, d.granted); + + if (copy_to_user((drm_dma_t __user *)arg, &d, sizeof(d))) + return -EFAULT; + sarea_priv->last_dispatch = (int) hw_status[5]; + + return retcode; +} + +static int i830_copybuf(struct inode *inode, + struct file *filp, unsigned int cmd, unsigned long arg) +{ + /* Never copy - 2.4.x doesn't need it */ + return 0; +} + +static int i830_docopy(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + return 0; +} + + + +static int i830_getparam( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_getparam_t param; + int value; + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return -EINVAL; + } + + if (copy_from_user(¶m, (drm_i830_getparam_t __user *)arg, sizeof(param) )) + return -EFAULT; + + switch( param.param ) { + case I830_PARAM_IRQ_ACTIVE: + value = dev->irq_enabled; + break; + default: + return -EINVAL; + } + + if ( copy_to_user( param.value, &value, sizeof(int) ) ) { + DRM_ERROR( "copy_to_user\n" ); + return -EFAULT; + } + + return 0; +} + + +static int i830_setparam( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_setparam_t param; + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return -EINVAL; + } + + if (copy_from_user(¶m, (drm_i830_setparam_t __user *)arg, sizeof(param) )) + return -EFAULT; + + switch( param.param ) { + case I830_SETPARAM_USE_MI_BATCHBUFFER_START: + dev_priv->use_mi_batchbuffer_start = param.value; + break; + default: + return -EINVAL; + } + + return 0; +} + + +void i830_driver_pretakedown(drm_device_t *dev) +{ + i830_dma_cleanup( dev ); +} + +void i830_driver_prerelease(drm_device_t *dev, DRMFILE filp) +{ + if (dev->dev_private) { + drm_i830_private_t *dev_priv = dev->dev_private; + if (dev_priv->page_flipping) { + i830_do_cleanup_pageflip(dev); + } + } +} + +void i830_driver_release(drm_device_t *dev, struct file *filp) +{ + i830_reclaim_buffers(dev, filp); +} + +int i830_driver_dma_quiescent(drm_device_t *dev) +{ + i830_dma_quiescent( dev ); + return 0; +} + +drm_ioctl_desc_t i830_ioctls[] = { + [DRM_IOCTL_NR(DRM_I830_INIT)] = { i830_dma_init, 1, 1 }, + [DRM_IOCTL_NR(DRM_I830_VERTEX)] = { i830_dma_vertex, 1, 0 }, + [DRM_IOCTL_NR(DRM_I830_CLEAR)] = { i830_clear_bufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_I830_FLUSH)] = { i830_flush_ioctl, 1, 0 }, + [DRM_IOCTL_NR(DRM_I830_GETAGE)] = { i830_getage, 1, 0 }, + [DRM_IOCTL_NR(DRM_I830_GETBUF)] = { i830_getbuf, 1, 0 }, + [DRM_IOCTL_NR(DRM_I830_SWAP)] = { i830_swap_bufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_I830_COPY)] = { i830_copybuf, 1, 0 }, + [DRM_IOCTL_NR(DRM_I830_DOCOPY)] = { i830_docopy, 1, 0 }, + [DRM_IOCTL_NR(DRM_I830_FLIP)] = { i830_flip_bufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT)] = { i830_irq_emit, 1, 0 }, + [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT)] = { i830_irq_wait, 1, 0 }, + [DRM_IOCTL_NR(DRM_I830_GETPARAM)] = { i830_getparam, 1, 0 }, + [DRM_IOCTL_NR(DRM_I830_SETPARAM)] = { i830_setparam, 1, 0 } +}; + +int i830_max_ioctl = DRM_ARRAY_SIZE(i830_ioctls); diff --git a/drivers/char/drm/i830_drm.h b/drivers/char/drm/i830_drm.h new file mode 100644 index 000000000000..03382c0beee3 --- /dev/null +++ b/drivers/char/drm/i830_drm.h @@ -0,0 +1,350 @@ +#ifndef _I830_DRM_H_ +#define _I830_DRM_H_ + +/* WARNING: These defines must be the same as what the Xserver uses. + * if you change them, you must change the defines in the Xserver. + * + * KW: Actually, you can't ever change them because doing so would + * break backwards compatibility. + */ + +#ifndef _I830_DEFINES_ +#define _I830_DEFINES_ + +#define I830_DMA_BUF_ORDER 12 +#define I830_DMA_BUF_SZ (1< + * Jeff Hartmann + * Gareth Hughes + * Abraham vd Merwe + * Keith Whitwell + */ + +#include +#include "drmP.h" +#include "drm.h" +#include "i830_drm.h" +#include "i830_drv.h" + +#include "drm_pciids.h" + +int postinit( struct drm_device *dev, unsigned long flags ) +{ + dev->counters += 4; + dev->types[6] = _DRM_STAT_IRQ; + dev->types[7] = _DRM_STAT_PRIMARY; + dev->types[8] = _DRM_STAT_SECONDARY; + dev->types[9] = _DRM_STAT_DMA; + + DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, + dev->primary.minor, + pci_pretty_name(dev->pdev) + ); + return 0; +} + +static int version( drm_version_t *version ) +{ + int len; + + version->version_major = DRIVER_MAJOR; + version->version_minor = DRIVER_MINOR; + version->version_patchlevel = DRIVER_PATCHLEVEL; + DRM_COPY( version->name, DRIVER_NAME ); + DRM_COPY( version->date, DRIVER_DATE ); + DRM_COPY( version->desc, DRIVER_DESC ); + return 0; +} + +static struct pci_device_id pciidlist[] = { + i830_PCI_IDS +}; + +extern drm_ioctl_desc_t i830_ioctls[]; +extern int i830_max_ioctl; + +static struct drm_driver driver = { + .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE, +#if USE_IRQS + .driver_features |= DRIVER_HAVE_IRQ | DRIVER_SHARED_IRQ, +#endif + .dev_priv_size = sizeof(drm_i830_buf_priv_t), + .pretakedown = i830_driver_pretakedown, + .prerelease = i830_driver_prerelease, + .release = i830_driver_release, + .dma_quiescent = i830_driver_dma_quiescent, + .reclaim_buffers = i830_reclaim_buffers, + .get_map_ofs = drm_core_get_map_ofs, + .get_reg_ofs = drm_core_get_reg_ofs, +#if USE_IRQS + .irq_preinstall = i830_driver_irq_preinstall, + .irq_postinstall = i830_driver_irq_postinstall, + .irq_uninstall = i830_driver_irq_uninstall, + .irq_handler = i830_driver_irq_handler, +#endif + .postinit = postinit, + .version = version, + .ioctls = i830_ioctls, + .fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + }, + .pci_driver = { + .name = DRIVER_NAME, + .id_table = pciidlist, + } + +}; + +static int __init i830_init(void) +{ + driver.num_ioctls = i830_max_ioctl; + return drm_init(&driver); +} + +static void __exit i830_exit(void) +{ + drm_exit(&driver); +} + +module_init(i830_init); +module_exit(i830_exit); + +MODULE_AUTHOR( DRIVER_AUTHOR ); +MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/i830_drv.h b/drivers/char/drm/i830_drv.h new file mode 100644 index 000000000000..d4b2d093d6ab --- /dev/null +++ b/drivers/char/drm/i830_drv.h @@ -0,0 +1,301 @@ +/* i830_drv.h -- Private header for the I830 driver -*- linux-c -*- + * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * Jeff Hartmann + * + */ + +#ifndef _I830_DRV_H_ +#define _I830_DRV_H_ + +/* General customization: + */ + +#define DRIVER_AUTHOR "VA Linux Systems Inc." + +#define DRIVER_NAME "i830" +#define DRIVER_DESC "Intel 830M" +#define DRIVER_DATE "20021108" + +/* Interface history: + * + * 1.1: Original. + * 1.2: ? + * 1.3: New irq emit/wait ioctls. + * New pageflip ioctl. + * New getparam ioctl. + * State for texunits 3&4 in sarea. + * New (alternative) layout for texture state. + */ +#define DRIVER_MAJOR 1 +#define DRIVER_MINOR 3 +#define DRIVER_PATCHLEVEL 2 + +/* Driver will work either way: IRQ's save cpu time when waiting for + * the card, but are subject to subtle interactions between bios, + * hardware and the driver. + */ +/* XXX: Add vblank support? */ +#define USE_IRQS 0 + +typedef struct drm_i830_buf_priv { + u32 *in_use; + int my_use_idx; + int currently_mapped; + void __user *virtual; + void *kernel_virtual; +} drm_i830_buf_priv_t; + +typedef struct _drm_i830_ring_buffer{ + int tail_mask; + unsigned long Start; + unsigned long End; + unsigned long Size; + u8 *virtual_start; + int head; + int tail; + int space; +} drm_i830_ring_buffer_t; + +typedef struct drm_i830_private { + drm_map_t *sarea_map; + drm_map_t *mmio_map; + + drm_i830_sarea_t *sarea_priv; + drm_i830_ring_buffer_t ring; + + void * hw_status_page; + unsigned long counter; + + dma_addr_t dma_status_page; + + drm_buf_t *mmap_buffer; + + u32 front_di1, back_di1, zi1; + + int back_offset; + int depth_offset; + int front_offset; + int w, h; + int pitch; + int back_pitch; + int depth_pitch; + unsigned int cpp; + + int do_boxes; + int dma_used; + + int current_page; + int page_flipping; + + wait_queue_head_t irq_queue; + atomic_t irq_received; + atomic_t irq_emitted; + + int use_mi_batchbuffer_start; + +} drm_i830_private_t; + +/* i830_dma.c */ +extern void i830_reclaim_buffers(drm_device_t *dev, struct file *filp); + +extern int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma); + +/* i830_irq.c */ +extern int i830_irq_emit( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); +extern int i830_irq_wait( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); + +extern irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS ); +extern void i830_driver_irq_preinstall( drm_device_t *dev ); +extern void i830_driver_irq_postinstall( drm_device_t *dev ); +extern void i830_driver_irq_uninstall( drm_device_t *dev ); +extern void i830_driver_pretakedown(drm_device_t *dev); +extern void i830_driver_release(drm_device_t *dev, struct file *filp); +extern int i830_driver_dma_quiescent(drm_device_t *dev); +extern void i830_driver_prerelease(drm_device_t *dev, DRMFILE filp); + +#define I830_BASE(reg) ((unsigned long) \ + dev_priv->mmio_map->handle) +#define I830_ADDR(reg) (I830_BASE(reg) + reg) +#define I830_DEREF(reg) *(__volatile__ unsigned int *)I830_ADDR(reg) +#define I830_READ(reg) readl((volatile u32 *)I830_ADDR(reg)) +#define I830_WRITE(reg,val) writel(val, (volatile u32 *)I830_ADDR(reg)) +#define I830_DEREF16(reg) *(__volatile__ u16 *)I830_ADDR(reg) +#define I830_READ16(reg) I830_DEREF16(reg) +#define I830_WRITE16(reg,val) do { I830_DEREF16(reg) = val; } while (0) + + + +#define I830_VERBOSE 0 + +#define RING_LOCALS unsigned int outring, ringmask, outcount; \ + volatile char *virt; + +#define BEGIN_LP_RING(n) do { \ + if (I830_VERBOSE) \ + printk("BEGIN_LP_RING(%d) in %s\n", \ + n, __FUNCTION__); \ + if (dev_priv->ring.space < n*4) \ + i830_wait_ring(dev, n*4, __FUNCTION__); \ + outcount = 0; \ + outring = dev_priv->ring.tail; \ + ringmask = dev_priv->ring.tail_mask; \ + virt = dev_priv->ring.virtual_start; \ +} while (0) + + +#define OUT_RING(n) do { \ + if (I830_VERBOSE) printk(" OUT_RING %x\n", (int)(n)); \ + *(volatile unsigned int *)(virt + outring) = n; \ + outcount++; \ + outring += 4; \ + outring &= ringmask; \ +} while (0) + +#define ADVANCE_LP_RING() do { \ + if (I830_VERBOSE) printk("ADVANCE_LP_RING %x\n", outring); \ + dev_priv->ring.tail = outring; \ + dev_priv->ring.space -= outcount * 4; \ + I830_WRITE(LP_RING + RING_TAIL, outring); \ +} while(0) + +extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); + + +#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) +#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) +#define CMD_REPORT_HEAD (7<<23) +#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) +#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) + +#define STATE3D_LOAD_STATE_IMMEDIATE_2 ((0x3<<29)|(0x1d<<24)|(0x03<<16)) +#define LOAD_TEXTURE_MAP0 (1<<11) + +#define INST_PARSER_CLIENT 0x00000000 +#define INST_OP_FLUSH 0x02000000 +#define INST_FLUSH_MAP_CACHE 0x00000001 + + +#define BB1_START_ADDR_MASK (~0x7) +#define BB1_PROTECTED (1<<0) +#define BB1_UNPROTECTED (0<<0) +#define BB2_END_ADDR_MASK (~0x7) + +#define I830REG_HWSTAM 0x02098 +#define I830REG_INT_IDENTITY_R 0x020a4 +#define I830REG_INT_MASK_R 0x020a8 +#define I830REG_INT_ENABLE_R 0x020a0 + +#define I830_IRQ_RESERVED ((1<<13)|(3<<2)) + + +#define LP_RING 0x2030 +#define HP_RING 0x2040 +#define RING_TAIL 0x00 +#define TAIL_ADDR 0x001FFFF8 +#define RING_HEAD 0x04 +#define HEAD_WRAP_COUNT 0xFFE00000 +#define HEAD_WRAP_ONE 0x00200000 +#define HEAD_ADDR 0x001FFFFC +#define RING_START 0x08 +#define START_ADDR 0x0xFFFFF000 +#define RING_LEN 0x0C +#define RING_NR_PAGES 0x001FF000 +#define RING_REPORT_MASK 0x00000006 +#define RING_REPORT_64K 0x00000002 +#define RING_REPORT_128K 0x00000004 +#define RING_NO_REPORT 0x00000000 +#define RING_VALID_MASK 0x00000001 +#define RING_VALID 0x00000001 +#define RING_INVALID 0x00000000 + +#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) +#define SC_UPDATE_SCISSOR (0x1<<1) +#define SC_ENABLE_MASK (0x1<<0) +#define SC_ENABLE (0x1<<0) + +#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) +#define SCI_YMIN_MASK (0xffff<<16) +#define SCI_XMIN_MASK (0xffff<<0) +#define SCI_YMAX_MASK (0xffff<<16) +#define SCI_XMAX_MASK (0xffff<<0) + +#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) +#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) +#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) +#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) +#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) +#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) +#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) +#define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24)) + +#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) + +#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) +#define ASYNC_FLIP (1<<22) + +#define CMD_3D (0x3<<29) +#define STATE3D_CONST_BLEND_COLOR_CMD (CMD_3D|(0x1d<<24)|(0x88<<16)) +#define STATE3D_MAP_COORD_SETBIND_CMD (CMD_3D|(0x1d<<24)|(0x02<<16)) + +#define BR00_BITBLT_CLIENT 0x40000000 +#define BR00_OP_COLOR_BLT 0x10000000 +#define BR00_OP_SRC_COPY_BLT 0x10C00000 +#define BR13_SOLID_PATTERN 0x80000000 + +#define BUF_3D_ID_COLOR_BACK (0x3<<24) +#define BUF_3D_ID_DEPTH (0x7<<24) +#define BUF_3D_USE_FENCE (1<<23) +#define BUF_3D_PITCH(x) (((x)/4)<<2) + +#define CMD_OP_MAP_PALETTE_LOAD ((3<<29)|(0x1d<<24)|(0x82<<16)|255) +#define MAP_PALETTE_NUM(x) ((x<<8) & (1<<8)) +#define MAP_PALETTE_BOTH (1<<11) + +#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4) +#define XY_COLOR_BLT_WRITE_ALPHA (1<<21) +#define XY_COLOR_BLT_WRITE_RGB (1<<20) + +#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) +#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) +#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) + +#define MI_BATCH_BUFFER ((0x30<<23)|1) +#define MI_BATCH_BUFFER_START (0x31<<23) +#define MI_BATCH_BUFFER_END (0xA<<23) +#define MI_BATCH_NON_SECURE (1) + +#define MI_WAIT_FOR_EVENT ((0x3<<23)) +#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) +#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) + +#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) + +#endif + diff --git a/drivers/char/drm/i830_irq.c b/drivers/char/drm/i830_irq.c new file mode 100644 index 000000000000..6d7729ffe2dc --- /dev/null +++ b/drivers/char/drm/i830_irq.c @@ -0,0 +1,204 @@ +/* i830_dma.c -- DMA support for the I830 -*- linux-c -*- + * + * Copyright 2002 Tungsten Graphics, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Keith Whitwell + * + */ + +#include "drmP.h" +#include "drm.h" +#include "i830_drm.h" +#include "i830_drv.h" +#include /* For task queue support */ +#include + + +irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS ) +{ + drm_device_t *dev = (drm_device_t *)arg; + drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; + u16 temp; + + temp = I830_READ16(I830REG_INT_IDENTITY_R); + DRM_DEBUG("%x\n", temp); + + if ( !( temp & 2 ) ) + return IRQ_NONE; + + I830_WRITE16(I830REG_INT_IDENTITY_R, temp); + + atomic_inc(&dev_priv->irq_received); + wake_up_interruptible(&dev_priv->irq_queue); + + return IRQ_HANDLED; +} + + +int i830_emit_irq(drm_device_t *dev) +{ + drm_i830_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + + DRM_DEBUG("%s\n", __FUNCTION__); + + atomic_inc(&dev_priv->irq_emitted); + + BEGIN_LP_RING(2); + OUT_RING( 0 ); + OUT_RING( GFX_OP_USER_INTERRUPT ); + ADVANCE_LP_RING(); + + return atomic_read(&dev_priv->irq_emitted); +} + + +int i830_wait_irq(drm_device_t *dev, int irq_nr) +{ + drm_i830_private_t *dev_priv = + (drm_i830_private_t *)dev->dev_private; + DECLARE_WAITQUEUE(entry, current); + unsigned long end = jiffies + HZ*3; + int ret = 0; + + DRM_DEBUG("%s\n", __FUNCTION__); + + if (atomic_read(&dev_priv->irq_received) >= irq_nr) + return 0; + + dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT; + + add_wait_queue(&dev_priv->irq_queue, &entry); + + for (;;) { + __set_current_state(TASK_INTERRUPTIBLE); + if (atomic_read(&dev_priv->irq_received) >= irq_nr) + break; + if((signed)(end - jiffies) <= 0) { + DRM_ERROR("timeout iir %x imr %x ier %x hwstam %x\n", + I830_READ16( I830REG_INT_IDENTITY_R ), + I830_READ16( I830REG_INT_MASK_R ), + I830_READ16( I830REG_INT_ENABLE_R ), + I830_READ16( I830REG_HWSTAM )); + + ret = -EBUSY; /* Lockup? Missed irq? */ + break; + } + schedule_timeout(HZ*3); + if (signal_pending(current)) { + ret = -EINTR; + break; + } + } + + __set_current_state(TASK_RUNNING); + remove_wait_queue(&dev_priv->irq_queue, &entry); + return ret; +} + + +/* Needs the lock as it touches the ring. + */ +int i830_irq_emit( struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_irq_emit_t emit; + int result; + + LOCK_TEST_WITH_RETURN(dev, filp); + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return -EINVAL; + } + + if (copy_from_user( &emit, (drm_i830_irq_emit_t __user *)arg, sizeof(emit) )) + return -EFAULT; + + result = i830_emit_irq( dev ); + + if ( copy_to_user( emit.irq_seq, &result, sizeof(int) ) ) { + DRM_ERROR( "copy_to_user\n" ); + return -EFAULT; + } + + return 0; +} + + +/* Doesn't need the hardware lock. + */ +int i830_irq_wait( struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg ) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_irq_wait_t irqwait; + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return -EINVAL; + } + + if (copy_from_user( &irqwait, (drm_i830_irq_wait_t __user *)arg, + sizeof(irqwait) )) + return -EFAULT; + + return i830_wait_irq( dev, irqwait.irq_seq ); +} + + +/* drm_dma.h hooks +*/ +void i830_driver_irq_preinstall( drm_device_t *dev ) { + drm_i830_private_t *dev_priv = + (drm_i830_private_t *)dev->dev_private; + + I830_WRITE16( I830REG_HWSTAM, 0xffff ); + I830_WRITE16( I830REG_INT_MASK_R, 0x0 ); + I830_WRITE16( I830REG_INT_ENABLE_R, 0x0 ); + atomic_set(&dev_priv->irq_received, 0); + atomic_set(&dev_priv->irq_emitted, 0); + init_waitqueue_head(&dev_priv->irq_queue); +} + +void i830_driver_irq_postinstall( drm_device_t *dev ) { + drm_i830_private_t *dev_priv = + (drm_i830_private_t *)dev->dev_private; + + I830_WRITE16( I830REG_INT_ENABLE_R, 0x2 ); +} + +void i830_driver_irq_uninstall( drm_device_t *dev ) { + drm_i830_private_t *dev_priv = + (drm_i830_private_t *)dev->dev_private; + if (!dev_priv) + return; + + I830_WRITE16( I830REG_INT_MASK_R, 0xffff ); + I830_WRITE16( I830REG_INT_ENABLE_R, 0x0 ); +} diff --git a/drivers/char/drm/i915_dma.c b/drivers/char/drm/i915_dma.c new file mode 100644 index 000000000000..7300a09dbd5c --- /dev/null +++ b/drivers/char/drm/i915_dma.c @@ -0,0 +1,725 @@ +/* i915_dma.c -- DMA support for the I915 -*- linux-c -*- + */ +/************************************************************************** + * + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + **************************************************************************/ + +#include "drmP.h" +#include "drm.h" +#include "i915_drm.h" +#include "i915_drv.h" + +drm_ioctl_desc_t i915_ioctls[] = { + [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, 1, 1}, + [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, 1, 1}, + [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, 1, 1}, + [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, 1, 0} +}; + +int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); + +/* Really want an OS-independent resettable timer. Would like to have + * this loop run for (eg) 3 sec, but have the timer reset every time + * the head pointer changes, so that EBUSY only happens if the ring + * actually stalls for (eg) 3 seconds. + */ +int i915_wait_ring(drm_device_t * dev, int n, const char *caller) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + drm_i915_ring_buffer_t *ring = &(dev_priv->ring); + u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + int i; + + for (i = 0; i < 10000; i++) { + ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->space = ring->head - (ring->tail + 8); + if (ring->space < 0) + ring->space += ring->Size; + if (ring->space >= n) + return 0; + + dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; + + if (ring->head != last_head) + i = 0; + + last_head = ring->head; + } + + return DRM_ERR(EBUSY); +} + +void i915_kernel_lost_context(drm_device_t * dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + drm_i915_ring_buffer_t *ring = &(dev_priv->ring); + + ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR; + ring->space = ring->head - (ring->tail + 8); + if (ring->space < 0) + ring->space += ring->Size; + + if (ring->head == ring->tail) + dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; +} + +int i915_dma_cleanup(drm_device_t * dev) +{ + /* Make sure interrupts are disabled here because the uninstall ioctl + * may not have been called from userspace and after dev_private + * is freed, it's too late. + */ + if (dev->irq) + drm_irq_uninstall (dev); + + if (dev->dev_private) { + drm_i915_private_t *dev_priv = + (drm_i915_private_t *) dev->dev_private; + + if (dev_priv->ring.virtual_start) { + drm_core_ioremapfree( &dev_priv->ring.map, dev); + } + + if (dev_priv->hw_status_page) { + drm_pci_free(dev, PAGE_SIZE, dev_priv->hw_status_page, + dev_priv->dma_status_page); + /* Need to rewrite hardware status page */ + I915_WRITE(0x02080, 0x1ffff000); + } + + drm_free (dev->dev_private, sizeof(drm_i915_private_t), + DRM_MEM_DRIVER); + + dev->dev_private = NULL; + } + + return 0; +} + +static int i915_initialize(drm_device_t * dev, + drm_i915_private_t * dev_priv, + drm_i915_init_t * init) +{ + memset(dev_priv, 0, sizeof(drm_i915_private_t)); + + DRM_GETSAREA(); + if (!dev_priv->sarea) { + DRM_ERROR("can not find sarea!\n"); + dev->dev_private = (void *)dev_priv; + i915_dma_cleanup(dev); + return DRM_ERR(EINVAL); + } + + dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); + if (!dev_priv->mmio_map) { + dev->dev_private = (void *)dev_priv; + i915_dma_cleanup(dev); + DRM_ERROR("can not find mmio map!\n"); + return DRM_ERR(EINVAL); + } + + dev_priv->sarea_priv = (drm_i915_sarea_t *) + ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); + + dev_priv->ring.Start = init->ring_start; + dev_priv->ring.End = init->ring_end; + dev_priv->ring.Size = init->ring_size; + dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; + + dev_priv->ring.map.offset = init->ring_start; + dev_priv->ring.map.size = init->ring_size; + dev_priv->ring.map.type = 0; + dev_priv->ring.map.flags = 0; + dev_priv->ring.map.mtrr = 0; + + drm_core_ioremap( &dev_priv->ring.map, dev ); + + if (dev_priv->ring.map.handle == NULL) { + dev->dev_private = (void *)dev_priv; + i915_dma_cleanup(dev); + DRM_ERROR("can not ioremap virtual address for" + " ring buffer\n"); + return DRM_ERR(ENOMEM); + } + + dev_priv->ring.virtual_start = dev_priv->ring.map.handle; + + dev_priv->back_offset = init->back_offset; + dev_priv->front_offset = init->front_offset; + dev_priv->current_page = 0; + dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; + + /* We are using separate values as placeholders for mechanisms for + * private backbuffer/depthbuffer usage. + */ + dev_priv->use_mi_batchbuffer_start = 0; + + /* Allow hardware batchbuffers unless told otherwise. + */ + dev_priv->allow_batchbuffer = 1; + + /* Program Hardware Status Page */ + dev_priv->hw_status_page = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, + 0xffffffff, + &dev_priv->dma_status_page); + + if (!dev_priv->hw_status_page) { + dev->dev_private = (void *)dev_priv; + i915_dma_cleanup(dev); + DRM_ERROR("Can not allocate hardware status page\n"); + return DRM_ERR(ENOMEM); + } + memset(dev_priv->hw_status_page, 0, PAGE_SIZE); + DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); + + I915_WRITE(0x02080, dev_priv->dma_status_page); + DRM_DEBUG("Enabled hardware status page\n"); + + dev->dev_private = (void *)dev_priv; + + return 0; +} + +static int i915_resume(drm_device_t * dev) +{ + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; + + DRM_DEBUG("%s\n", __FUNCTION__); + + if (!dev_priv->sarea) { + DRM_ERROR("can not find sarea!\n"); + return DRM_ERR(EINVAL); + } + + if (!dev_priv->mmio_map) { + DRM_ERROR("can not find mmio map!\n"); + return DRM_ERR(EINVAL); + } + + if (dev_priv->ring.map.handle == NULL) { + DRM_ERROR("can not ioremap virtual address for" + " ring buffer\n"); + return DRM_ERR(ENOMEM); + } + + /* Program Hardware Status Page */ + if (!dev_priv->hw_status_page) { + DRM_ERROR("Can not find hardware status page\n"); + return DRM_ERR(EINVAL); + } + DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); + + I915_WRITE(0x02080, dev_priv->dma_status_page); + DRM_DEBUG("Enabled hardware status page\n"); + + return 0; +} + +int i915_dma_init(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_i915_private_t *dev_priv; + drm_i915_init_t init; + int retcode = 0; + + DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data, + sizeof(init)); + + switch (init.func) { + case I915_INIT_DMA: + dev_priv = drm_alloc (sizeof(drm_i915_private_t), + DRM_MEM_DRIVER); + if (dev_priv == NULL) + return DRM_ERR(ENOMEM); + retcode = i915_initialize(dev, dev_priv, &init); + break; + case I915_CLEANUP_DMA: + retcode = i915_dma_cleanup(dev); + break; + case I915_RESUME_DMA: + retcode = i915_resume(dev); + break; + default: + retcode = -EINVAL; + break; + } + + return retcode; +} + +/* Implement basically the same security restrictions as hardware does + * for MI_BATCH_NON_SECURE. These can be made stricter at any time. + * + * Most of the calculations below involve calculating the size of a + * particular instruction. It's important to get the size right as + * that tells us where the next instruction to check is. Any illegal + * instruction detected will be given a size of zero, which is a + * signal to abort the rest of the buffer. + */ +static int do_validate_cmd(int cmd) +{ + switch (((cmd >> 29) & 0x7)) { + case 0x0: + switch ((cmd >> 23) & 0x3f) { + case 0x0: + return 1; /* MI_NOOP */ + case 0x4: + return 1; /* MI_FLUSH */ + default: + return 0; /* disallow everything else */ + } + break; + case 0x1: + return 0; /* reserved */ + case 0x2: + return (cmd & 0xff) + 2; /* 2d commands */ + case 0x3: + if (((cmd >> 24) & 0x1f) <= 0x18) + return 1; + + switch ((cmd >> 24) & 0x1f) { + case 0x1c: + return 1; + case 0x1d: + switch ((cmd>>16)&0xff) { + case 0x3: + return (cmd & 0x1f) + 2; + case 0x4: + return (cmd & 0xf) + 2; + default: + return (cmd & 0xffff) + 2; + } + case 0x1e: + if (cmd & (1 << 23)) + return (cmd & 0xffff) + 1; + else + return 1; + case 0x1f: + if ((cmd & (1 << 23)) == 0) /* inline vertices */ + return (cmd & 0x1ffff) + 2; + else if (cmd & (1 << 17)) /* indirect random */ + if ((cmd & 0xffff) == 0) + return 0; /* unknown length, too hard */ + else + return (((cmd & 0xffff) + 1) / 2) + 1; + else + return 2; /* indirect sequential */ + default: + return 0; + } + default: + return 0; + } + + return 0; +} + +static int validate_cmd(int cmd) +{ + int ret = do_validate_cmd(cmd); + +/* printk("validate_cmd( %x ): %d\n", cmd, ret); */ + + return ret; +} + +static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + int i; + RING_LOCALS; + + for (i = 0; i < dwords;) { + int cmd, sz; + + if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) + return DRM_ERR(EINVAL); + +/* printk("%d/%d ", i, dwords); */ + + if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) + return DRM_ERR(EINVAL); + + BEGIN_LP_RING(sz); + OUT_RING(cmd); + + while (++i, --sz) { + if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], + sizeof(cmd))) { + return DRM_ERR(EINVAL); + } + OUT_RING(cmd); + } + ADVANCE_LP_RING(); + } + + return 0; +} + +static int i915_emit_box(drm_device_t * dev, + drm_clip_rect_t __user * boxes, + int i, int DR1, int DR4) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + drm_clip_rect_t box; + RING_LOCALS; + + if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { + return EFAULT; + } + + if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { + DRM_ERROR("Bad box %d,%d..%d,%d\n", + box.x1, box.y1, box.x2, box.y2); + return DRM_ERR(EINVAL); + } + + BEGIN_LP_RING(6); + OUT_RING(GFX_OP_DRAWRECT_INFO); + OUT_RING(DR1); + OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); + OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); + OUT_RING(DR4); + OUT_RING(0); + ADVANCE_LP_RING(); + + return 0; +} + +static int i915_dispatch_cmdbuffer(drm_device_t * dev, + drm_i915_cmdbuffer_t * cmd) +{ + int nbox = cmd->num_cliprects; + int i = 0, count, ret; + + if (cmd->sz & 0x3) { + DRM_ERROR("alignment"); + return DRM_ERR(EINVAL); + } + + i915_kernel_lost_context(dev); + + count = nbox ? nbox : 1; + + for (i = 0; i < count; i++) { + if (i < nbox) { + ret = i915_emit_box(dev, cmd->cliprects, i, + cmd->DR1, cmd->DR4); + if (ret) + return ret; + } + + ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4); + if (ret) + return ret; + } + + return 0; +} + +static int i915_dispatch_batchbuffer(drm_device_t * dev, + drm_i915_batchbuffer_t * batch) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + drm_clip_rect_t __user *boxes = batch->cliprects; + int nbox = batch->num_cliprects; + int i = 0, count; + RING_LOCALS; + + if ((batch->start | batch->used) & 0x7) { + DRM_ERROR("alignment"); + return DRM_ERR(EINVAL); + } + + i915_kernel_lost_context(dev); + + count = nbox ? nbox : 1; + + for (i = 0; i < count; i++) { + if (i < nbox) { + int ret = i915_emit_box(dev, boxes, i, + batch->DR1, batch->DR4); + if (ret) + return ret; + } + + if (dev_priv->use_mi_batchbuffer_start) { + BEGIN_LP_RING(2); + OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); + OUT_RING(batch->start | MI_BATCH_NON_SECURE); + ADVANCE_LP_RING(); + } else { + BEGIN_LP_RING(4); + OUT_RING(MI_BATCH_BUFFER); + OUT_RING(batch->start | MI_BATCH_NON_SECURE); + OUT_RING(batch->start + batch->used - 4); + OUT_RING(0); + ADVANCE_LP_RING(); + } + } + + dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; + + BEGIN_LP_RING(4); + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(20); + OUT_RING(dev_priv->counter); + OUT_RING(0); + ADVANCE_LP_RING(); + + return 0; +} + +static int i915_dispatch_flip(drm_device_t * dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + + DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, + dev_priv->sarea_priv->pf_current_page); + + i915_kernel_lost_context(dev); + + BEGIN_LP_RING(2); + OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); + OUT_RING(0); + ADVANCE_LP_RING(); + + BEGIN_LP_RING(6); + OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); + OUT_RING(0); + if (dev_priv->current_page == 0) { + OUT_RING(dev_priv->back_offset); + dev_priv->current_page = 1; + } else { + OUT_RING(dev_priv->front_offset); + dev_priv->current_page = 0; + } + OUT_RING(0); + ADVANCE_LP_RING(); + + BEGIN_LP_RING(2); + OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); + OUT_RING(0); + ADVANCE_LP_RING(); + + dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; + + BEGIN_LP_RING(4); + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(20); + OUT_RING(dev_priv->counter); + OUT_RING(0); + ADVANCE_LP_RING(); + + dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; + return 0; +} + +static int i915_quiescent(drm_device_t * dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + + i915_kernel_lost_context(dev); + return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__); +} + +int i915_flush_ioctl(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + + LOCK_TEST_WITH_RETURN(dev, filp); + + return i915_quiescent(dev); +} + +int i915_batchbuffer(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) + dev_priv->sarea_priv; + drm_i915_batchbuffer_t batch; + int ret; + + if (!dev_priv->allow_batchbuffer) { + DRM_ERROR("Batchbuffer ioctl disabled\n"); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data, + sizeof(batch)); + + DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", + batch.start, batch.used, batch.num_cliprects); + + LOCK_TEST_WITH_RETURN(dev, filp); + + if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects, + batch.num_cliprects * + sizeof(drm_clip_rect_t))) + return DRM_ERR(EFAULT); + + ret = i915_dispatch_batchbuffer(dev, &batch); + + sarea_priv->last_dispatch = (int)hw_status[5]; + return ret; +} + +int i915_cmdbuffer(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) + dev_priv->sarea_priv; + drm_i915_cmdbuffer_t cmdbuf; + int ret; + + DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data, + sizeof(cmdbuf)); + + DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", + cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects); + + LOCK_TEST_WITH_RETURN(dev, filp); + + if (cmdbuf.num_cliprects && + DRM_VERIFYAREA_READ(cmdbuf.cliprects, + cmdbuf.num_cliprects * + sizeof(drm_clip_rect_t))) { + DRM_ERROR("Fault accessing cliprects\n"); + return DRM_ERR(EFAULT); + } + + ret = i915_dispatch_cmdbuffer(dev, &cmdbuf); + if (ret) { + DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); + return ret; + } + + sarea_priv->last_dispatch = (int)hw_status[5]; + return 0; +} + +int i915_do_cleanup_pageflip(drm_device_t * dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("%s\n", __FUNCTION__); + if (dev_priv->current_page != 0) + i915_dispatch_flip(dev); + + return 0; +} + +int i915_flip_bufs(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + + DRM_DEBUG("%s\n", __FUNCTION__); + + LOCK_TEST_WITH_RETURN(dev, filp); + + return i915_dispatch_flip(dev); +} + +int i915_getparam(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_i915_private_t *dev_priv = dev->dev_private; + drm_i915_getparam_t param; + int value; + + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data, + sizeof(param)); + + switch (param.param) { + case I915_PARAM_IRQ_ACTIVE: + value = dev->irq ? 1 : 0; + break; + case I915_PARAM_ALLOW_BATCHBUFFER: + value = dev_priv->allow_batchbuffer ? 1 : 0; + break; + default: + DRM_ERROR("Unkown parameter %d\n", param.param); + return DRM_ERR(EINVAL); + } + + if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + DRM_ERROR("DRM_COPY_TO_USER failed\n"); + return DRM_ERR(EFAULT); + } + + return 0; +} + +int i915_setparam(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_i915_private_t *dev_priv = dev->dev_private; + drm_i915_setparam_t param; + + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data, + sizeof(param)); + + switch (param.param) { + case I915_SETPARAM_USE_MI_BATCHBUFFER_START: + dev_priv->use_mi_batchbuffer_start = param.value; + break; + case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: + dev_priv->tex_lru_log_granularity = param.value; + break; + case I915_SETPARAM_ALLOW_BATCHBUFFER: + dev_priv->allow_batchbuffer = param.value; + break; + default: + DRM_ERROR("unknown parameter %d\n", param.param); + return DRM_ERR(EINVAL); + } + + return 0; +} + +void i915_driver_pretakedown(drm_device_t *dev) +{ + if ( dev->dev_private ) { + drm_i915_private_t *dev_priv = dev->dev_private; + i915_mem_takedown( &(dev_priv->agp_heap) ); + } + i915_dma_cleanup( dev ); +} + +void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp) +{ + if ( dev->dev_private ) { + drm_i915_private_t *dev_priv = dev->dev_private; + i915_mem_release( dev, filp, dev_priv->agp_heap ); + } +} + diff --git a/drivers/char/drm/i915_drm.h b/drivers/char/drm/i915_drm.h new file mode 100644 index 000000000000..7e55edf45c4f --- /dev/null +++ b/drivers/char/drm/i915_drm.h @@ -0,0 +1,167 @@ +#ifndef _I915_DRM_H_ +#define _I915_DRM_H_ + +/* Please note that modifications to all structs defined here are + * subject to backwards-compatibility constraints. + */ + +#include "drm.h" + +/* Each region is a minimum of 16k, and there are at most 255 of them. + */ +#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use + * of chars for next/prev indices */ +#define I915_LOG_MIN_TEX_REGION_SIZE 14 + +typedef struct _drm_i915_init { + enum { + I915_INIT_DMA = 0x01, + I915_CLEANUP_DMA = 0x02, + I915_RESUME_DMA = 0x03 + } func; + unsigned int mmio_offset; + int sarea_priv_offset; + unsigned int ring_start; + unsigned int ring_end; + unsigned int ring_size; + unsigned int front_offset; + unsigned int back_offset; + unsigned int depth_offset; + unsigned int w; + unsigned int h; + unsigned int pitch; + unsigned int pitch_bits; + unsigned int back_pitch; + unsigned int depth_pitch; + unsigned int cpp; + unsigned int chipset; +} drm_i915_init_t; + +typedef struct _drm_i915_sarea { + drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1]; + int last_upload; /* last time texture was uploaded */ + int last_enqueue; /* last time a buffer was enqueued */ + int last_dispatch; /* age of the most recently dispatched buffer */ + int ctxOwner; /* last context to upload state */ + int texAge; + int pf_enabled; /* is pageflipping allowed? */ + int pf_active; + int pf_current_page; /* which buffer is being displayed? */ + int perf_boxes; /* performance boxes to be displayed */ +} drm_i915_sarea_t; + +/* Flags for perf_boxes + */ +#define I915_BOX_RING_EMPTY 0x1 +#define I915_BOX_FLIP 0x2 +#define I915_BOX_WAIT 0x4 +#define I915_BOX_TEXTURE_LOAD 0x8 +#define I915_BOX_LOST_CONTEXT 0x10 + +/* I915 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_I915_INIT 0x00 +#define DRM_I915_FLUSH 0x01 +#define DRM_I915_FLIP 0x02 +#define DRM_I915_BATCHBUFFER 0x03 +#define DRM_I915_IRQ_EMIT 0x04 +#define DRM_I915_IRQ_WAIT 0x05 +#define DRM_I915_GETPARAM 0x06 +#define DRM_I915_SETPARAM 0x07 +#define DRM_I915_ALLOC 0x08 +#define DRM_I915_FREE 0x09 +#define DRM_I915_INIT_HEAP 0x0a +#define DRM_I915_CMDBUFFER 0x0b + +#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) +#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) +#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) +#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) +#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) +#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) +#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) +#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) +#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) +#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) +#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) +#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) + +/* Allow drivers to submit batchbuffers directly to hardware, relying + * on the security mechanisms provided by hardware. + */ +typedef struct _drm_i915_batchbuffer { + int start; /* agp offset */ + int used; /* nr bytes in use */ + int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ + int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ + int num_cliprects; /* mulitpass with multiple cliprects? */ + drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ +} drm_i915_batchbuffer_t; + +/* As above, but pass a pointer to userspace buffer which can be + * validated by the kernel prior to sending to hardware. + */ +typedef struct _drm_i915_cmdbuffer { + char __user *buf; /* pointer to userspace command buffer */ + int sz; /* nr bytes in buf */ + int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ + int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ + int num_cliprects; /* mulitpass with multiple cliprects? */ + drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ +} drm_i915_cmdbuffer_t; + +/* Userspace can request & wait on irq's: + */ +typedef struct drm_i915_irq_emit { + int __user *irq_seq; +} drm_i915_irq_emit_t; + +typedef struct drm_i915_irq_wait { + int irq_seq; +} drm_i915_irq_wait_t; + +/* Ioctl to query kernel params: + */ +#define I915_PARAM_IRQ_ACTIVE 1 +#define I915_PARAM_ALLOW_BATCHBUFFER 2 + +typedef struct drm_i915_getparam { + int param; + int __user *value; +} drm_i915_getparam_t; + +/* Ioctl to set kernel params: + */ +#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 +#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 +#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 + +typedef struct drm_i915_setparam { + int param; + int value; +} drm_i915_setparam_t; + +/* A memory manager for regions of shared memory: + */ +#define I915_MEM_REGION_AGP 1 + +typedef struct drm_i915_mem_alloc { + int region; + int alignment; + int size; + int __user *region_offset; /* offset from start of fb or agp */ +} drm_i915_mem_alloc_t; + +typedef struct drm_i915_mem_free { + int region; + int region_offset; +} drm_i915_mem_free_t; + +typedef struct drm_i915_mem_init_heap { + int region; + int size; + int start; +} drm_i915_mem_init_heap_t; + +#endif /* _I915_DRM_H_ */ diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c new file mode 100644 index 000000000000..002b7082e21b --- /dev/null +++ b/drivers/char/drm/i915_drv.c @@ -0,0 +1,104 @@ +/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- + */ + +/************************************************************************** + * + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + **************************************************************************/ + +#include "drmP.h" +#include "drm.h" +#include "i915_drm.h" +#include "i915_drv.h" + +#include "drm_pciids.h" + +int postinit( struct drm_device *dev, unsigned long flags ) +{ + dev->counters += 4; + dev->types[6] = _DRM_STAT_IRQ; + dev->types[7] = _DRM_STAT_PRIMARY; + dev->types[8] = _DRM_STAT_SECONDARY; + dev->types[9] = _DRM_STAT_DMA; + + DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, + dev->primary.minor, + pci_pretty_name(dev->pdev) + ); + return 0; +} + +static int version( drm_version_t *version ) +{ + int len; + + version->version_major = DRIVER_MAJOR; + version->version_minor = DRIVER_MINOR; + version->version_patchlevel = DRIVER_PATCHLEVEL; + DRM_COPY( version->name, DRIVER_NAME ); + DRM_COPY( version->date, DRIVER_DATE ); + DRM_COPY( version->desc, DRIVER_DESC ); + return 0; +} + +static struct pci_device_id pciidlist[] = { + i915_PCI_IDS +}; + +extern drm_ioctl_desc_t i915_ioctls[]; +extern int i915_max_ioctl; + +static struct drm_driver driver = { + .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | + DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, + .pretakedown = i915_driver_pretakedown, + .prerelease = i915_driver_prerelease, + .irq_preinstall = i915_driver_irq_preinstall, + .irq_postinstall = i915_driver_irq_postinstall, + .irq_uninstall = i915_driver_irq_uninstall, + .irq_handler = i915_driver_irq_handler, + .reclaim_buffers = drm_core_reclaim_buffers, + .get_map_ofs = drm_core_get_map_ofs, + .get_reg_ofs = drm_core_get_reg_ofs, + .postinit = postinit, + .version = version, + .ioctls = i915_ioctls, + .fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + }, + .pci_driver = { + .name = DRIVER_NAME, + .id_table = pciidlist, + } +}; + +static int __init i915_init(void) +{ + driver.num_ioctls = i915_max_ioctl; + return drm_init(&driver); +} + +static void __exit i915_exit(void) +{ + drm_exit(&driver); +} + +module_init(i915_init); +module_exit(i915_exit); + +MODULE_AUTHOR( DRIVER_AUTHOR ); +MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h new file mode 100644 index 000000000000..f6ca92a565db --- /dev/null +++ b/drivers/char/drm/i915_drv.h @@ -0,0 +1,243 @@ +/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- + */ +/************************************************************************** + * + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + **************************************************************************/ + +#ifndef _I915_DRV_H_ +#define _I915_DRV_H_ + +/* General customization: + */ + +#define DRIVER_AUTHOR "Tungsten Graphics, Inc." + +#define DRIVER_NAME "i915" +#define DRIVER_DESC "Intel Graphics" +#define DRIVER_DATE "20040405" + +/* Interface history: + * + * 1.1: Original. + */ +#define DRIVER_MAJOR 1 +#define DRIVER_MINOR 1 +#define DRIVER_PATCHLEVEL 0 + +/* We use our own dma mechanisms, not the drm template code. However, + * the shared IRQ code is useful to us: + */ +#define __HAVE_PM 1 + +typedef struct _drm_i915_ring_buffer { + int tail_mask; + unsigned long Start; + unsigned long End; + unsigned long Size; + u8 *virtual_start; + int head; + int tail; + int space; + drm_local_map_t map; +} drm_i915_ring_buffer_t; + +struct mem_block { + struct mem_block *next; + struct mem_block *prev; + int start; + int size; + DRMFILE filp; /* 0: free, -1: heap, other: real files */ +}; + +typedef struct drm_i915_private { + drm_local_map_t *sarea; + drm_local_map_t *mmio_map; + + drm_i915_sarea_t *sarea_priv; + drm_i915_ring_buffer_t ring; + + void *hw_status_page; + unsigned long counter; + dma_addr_t dma_status_page; + + int back_offset; + int front_offset; + int current_page; + int page_flipping; + int use_mi_batchbuffer_start; + + wait_queue_head_t irq_queue; + atomic_t irq_received; + atomic_t irq_emitted; + + int tex_lru_log_granularity; + int allow_batchbuffer; + struct mem_block *agp_heap; +} drm_i915_private_t; + + /* i915_dma.c */ +extern int i915_dma_init(DRM_IOCTL_ARGS); +extern int i915_dma_cleanup(drm_device_t * dev); +extern int i915_flush_ioctl(DRM_IOCTL_ARGS); +extern int i915_batchbuffer(DRM_IOCTL_ARGS); +extern int i915_flip_bufs(DRM_IOCTL_ARGS); +extern int i915_getparam(DRM_IOCTL_ARGS); +extern int i915_setparam(DRM_IOCTL_ARGS); +extern int i915_cmdbuffer(DRM_IOCTL_ARGS); +extern void i915_kernel_lost_context(drm_device_t * dev); +extern void i915_driver_pretakedown(drm_device_t *dev); +extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp); + +/* i915_irq.c */ +extern int i915_irq_emit(DRM_IOCTL_ARGS); +extern int i915_irq_wait(DRM_IOCTL_ARGS); +extern int i915_wait_irq(drm_device_t * dev, int irq_nr); +extern int i915_emit_irq(drm_device_t * dev); + +extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); +extern void i915_driver_irq_preinstall(drm_device_t *dev); +extern void i915_driver_irq_postinstall(drm_device_t *dev); +extern void i915_driver_irq_uninstall(drm_device_t *dev); + +/* i915_mem.c */ +extern int i915_mem_alloc(DRM_IOCTL_ARGS); +extern int i915_mem_free(DRM_IOCTL_ARGS); +extern int i915_mem_init_heap(DRM_IOCTL_ARGS); +extern void i915_mem_takedown(struct mem_block **heap); +extern void i915_mem_release(drm_device_t * dev, + DRMFILE filp, struct mem_block *heap); + +#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, reg) +#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val) +#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg) +#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, reg, val) + +#define I915_VERBOSE 0 + +#define RING_LOCALS unsigned int outring, ringmask, outcount; \ + volatile char *virt; + +#define BEGIN_LP_RING(n) do { \ + if (I915_VERBOSE) \ + DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \ + n, __FUNCTION__); \ + if (dev_priv->ring.space < n*4) \ + i915_wait_ring(dev, n*4, __FUNCTION__); \ + outcount = 0; \ + outring = dev_priv->ring.tail; \ + ringmask = dev_priv->ring.tail_mask; \ + virt = dev_priv->ring.virtual_start; \ +} while (0) + +#define OUT_RING(n) do { \ + if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ + *(volatile unsigned int *)(virt + outring) = n; \ + outcount++; \ + outring += 4; \ + outring &= ringmask; \ +} while (0) + +#define ADVANCE_LP_RING() do { \ + if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ + dev_priv->ring.tail = outring; \ + dev_priv->ring.space -= outcount * 4; \ + I915_WRITE(LP_RING + RING_TAIL, outring); \ +} while(0) + +extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); + +#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) +#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) +#define CMD_REPORT_HEAD (7<<23) +#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) +#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) + +#define INST_PARSER_CLIENT 0x00000000 +#define INST_OP_FLUSH 0x02000000 +#define INST_FLUSH_MAP_CACHE 0x00000001 + +#define BB1_START_ADDR_MASK (~0x7) +#define BB1_PROTECTED (1<<0) +#define BB1_UNPROTECTED (0<<0) +#define BB2_END_ADDR_MASK (~0x7) + +#define I915REG_HWSTAM 0x02098 +#define I915REG_INT_IDENTITY_R 0x020a4 +#define I915REG_INT_MASK_R 0x020a8 +#define I915REG_INT_ENABLE_R 0x020a0 + +#define SRX_INDEX 0x3c4 +#define SRX_DATA 0x3c5 +#define SR01 1 +#define SR01_SCREEN_OFF (1<<5) + +#define PPCR 0x61204 +#define PPCR_ON (1<<0) + +#define ADPA 0x61100 +#define ADPA_DPMS_MASK (~(3<<10)) +#define ADPA_DPMS_ON (0<<10) +#define ADPA_DPMS_SUSPEND (1<<10) +#define ADPA_DPMS_STANDBY (2<<10) +#define ADPA_DPMS_OFF (3<<10) + +#define NOPID 0x2094 +#define LP_RING 0x2030 +#define HP_RING 0x2040 +#define RING_TAIL 0x00 +#define TAIL_ADDR 0x001FFFF8 +#define RING_HEAD 0x04 +#define HEAD_WRAP_COUNT 0xFFE00000 +#define HEAD_WRAP_ONE 0x00200000 +#define HEAD_ADDR 0x001FFFFC +#define RING_START 0x08 +#define START_ADDR 0x0xFFFFF000 +#define RING_LEN 0x0C +#define RING_NR_PAGES 0x001FF000 +#define RING_REPORT_MASK 0x00000006 +#define RING_REPORT_64K 0x00000002 +#define RING_REPORT_128K 0x00000004 +#define RING_NO_REPORT 0x00000000 +#define RING_VALID_MASK 0x00000001 +#define RING_VALID 0x00000001 +#define RING_INVALID 0x00000000 + +#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) +#define SC_UPDATE_SCISSOR (0x1<<1) +#define SC_ENABLE_MASK (0x1<<0) +#define SC_ENABLE (0x1<<0) + +#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) +#define SCI_YMIN_MASK (0xffff<<16) +#define SCI_XMIN_MASK (0xffff<<0) +#define SCI_YMAX_MASK (0xffff<<16) +#define SCI_XMAX_MASK (0xffff<<0) + +#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) +#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) +#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) +#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) +#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) +#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) +#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) + +#define MI_BATCH_BUFFER ((0x30<<23)|1) +#define MI_BATCH_BUFFER_START (0x31<<23) +#define MI_BATCH_BUFFER_END (0xA<<23) +#define MI_BATCH_NON_SECURE (1) + +#define MI_WAIT_FOR_EVENT ((0x3<<23)) +#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) +#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) + +#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) + +#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) +#define ASYNC_FLIP (1<<22) + +#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) + +#endif diff --git a/drivers/char/drm/i915_irq.c b/drivers/char/drm/i915_irq.c new file mode 100644 index 000000000000..b0239262a84a --- /dev/null +++ b/drivers/char/drm/i915_irq.c @@ -0,0 +1,161 @@ +/* i915_dma.c -- DMA support for the I915 -*- linux-c -*- + */ +/************************************************************************** + * + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + **************************************************************************/ + +#include "drmP.h" +#include "drm.h" +#include "i915_drm.h" +#include "i915_drv.h" + +#define USER_INT_FLAG 0x2 +#define MAX_NOPID ((u32)~0) +#define READ_BREADCRUMB(dev_priv) (((u32*)(dev_priv->hw_status_page))[5]) + +irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) +{ + drm_device_t *dev = (drm_device_t *) arg; + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; + u16 temp; + + temp = I915_READ16(I915REG_INT_IDENTITY_R); + temp &= USER_INT_FLAG; + + DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp); + + if (temp == 0) + return IRQ_NONE; + + I915_WRITE16(I915REG_INT_IDENTITY_R, temp); + DRM_WAKEUP(&dev_priv->irq_queue); + + return IRQ_HANDLED; +} + +int i915_emit_irq(drm_device_t * dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + u32 ret; + RING_LOCALS; + + i915_kernel_lost_context(dev); + + DRM_DEBUG("%s\n", __FUNCTION__); + + ret = dev_priv->counter; + + BEGIN_LP_RING(2); + OUT_RING(0); + OUT_RING(GFX_OP_USER_INTERRUPT); + ADVANCE_LP_RING(); + + return ret; +} + +int i915_wait_irq(drm_device_t * dev, int irq_nr) +{ + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; + int ret = 0; + + DRM_DEBUG("%s irq_nr=%d breadcrumb=%d\n", __FUNCTION__, irq_nr, + READ_BREADCRUMB(dev_priv)); + + if (READ_BREADCRUMB(dev_priv) >= irq_nr) + return 0; + + dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; + + DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, + READ_BREADCRUMB(dev_priv) >= irq_nr); + + if (ret == DRM_ERR(EBUSY)) { + DRM_ERROR("%s: EBUSY -- rec: %d emitted: %d\n", + __FUNCTION__, + READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); + } + + dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); + return ret; +} + +/* Needs the lock as it touches the ring. + */ +int i915_irq_emit(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_i915_private_t *dev_priv = dev->dev_private; + drm_i915_irq_emit_t emit; + int result; + + LOCK_TEST_WITH_RETURN(dev, filp); + + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL(emit, (drm_i915_irq_emit_t __user *) data, + sizeof(emit)); + + result = i915_emit_irq(dev); + + if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); + return DRM_ERR(EFAULT); + } + + return 0; +} + +/* Doesn't need the hardware lock. + */ +int i915_irq_wait(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_i915_private_t *dev_priv = dev->dev_private; + drm_i915_irq_wait_t irqwait; + + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_i915_irq_wait_t __user *) data, + sizeof(irqwait)); + + return i915_wait_irq(dev, irqwait.irq_seq); +} + +/* drm_dma.h hooks +*/ +void i915_driver_irq_preinstall(drm_device_t * dev) +{ + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; + + I915_WRITE16(I915REG_HWSTAM, 0xfffe); + I915_WRITE16(I915REG_INT_MASK_R, 0x0); + I915_WRITE16(I915REG_INT_ENABLE_R, 0x0); +} + +void i915_driver_irq_postinstall(drm_device_t * dev) +{ + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; + + I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG); + DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); +} + +void i915_driver_irq_uninstall(drm_device_t * dev) +{ + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; + if (!dev_priv) + return; + + I915_WRITE16(I915REG_HWSTAM, 0xffff); + I915_WRITE16(I915REG_INT_MASK_R, 0xffff); + I915_WRITE16(I915REG_INT_ENABLE_R, 0x0); +} diff --git a/drivers/char/drm/i915_mem.c b/drivers/char/drm/i915_mem.c new file mode 100644 index 000000000000..d54a3005946b --- /dev/null +++ b/drivers/char/drm/i915_mem.c @@ -0,0 +1,346 @@ +/* i915_mem.c -- Simple agp/fb memory manager for i915 -*- linux-c -*- + */ +/************************************************************************** + * + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + **************************************************************************/ + +#include "drmP.h" +#include "drm.h" +#include "i915_drm.h" +#include "i915_drv.h" + +/* This memory manager is integrated into the global/local lru + * mechanisms used by the clients. Specifically, it operates by + * setting the 'in_use' fields of the global LRU to indicate whether + * this region is privately allocated to a client. + * + * This does require the client to actually respect that field. + * + * Currently no effort is made to allocate 'private' memory in any + * clever way - the LRU information isn't used to determine which + * block to allocate, and the ring is drained prior to allocations -- + * in other words allocation is expensive. + */ +static void mark_block(drm_device_t * dev, struct mem_block *p, int in_use) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_tex_region_t *list; + unsigned shift, nr; + unsigned start; + unsigned end; + unsigned i; + int age; + + shift = dev_priv->tex_lru_log_granularity; + nr = I915_NR_TEX_REGIONS; + + start = p->start >> shift; + end = (p->start + p->size - 1) >> shift; + + age = ++sarea_priv->texAge; + list = sarea_priv->texList; + + /* Mark the regions with the new flag and update their age. Move + * them to head of list to preserve LRU semantics. + */ + for (i = start; i <= end; i++) { + list[i].in_use = in_use; + list[i].age = age; + + /* remove_from_list(i) + */ + list[(unsigned)list[i].next].prev = list[i].prev; + list[(unsigned)list[i].prev].next = list[i].next; + + /* insert_at_head(list, i) + */ + list[i].prev = nr; + list[i].next = list[nr].next; + list[(unsigned)list[nr].next].prev = i; + list[nr].next = i; + } +} + +/* Very simple allocator for agp memory, working on a static range + * already mapped into each client's address space. + */ + +static struct mem_block *split_block(struct mem_block *p, int start, int size, + DRMFILE filp) +{ + /* Maybe cut off the start of an existing block */ + if (start > p->start) { + struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); + if (!newblock) + goto out; + newblock->start = start; + newblock->size = p->size - (start - p->start); + newblock->filp = NULL; + newblock->next = p->next; + newblock->prev = p; + p->next->prev = newblock; + p->next = newblock; + p->size -= newblock->size; + p = newblock; + } + + /* Maybe cut off the end of an existing block */ + if (size < p->size) { + struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); + if (!newblock) + goto out; + newblock->start = start + size; + newblock->size = p->size - size; + newblock->filp = NULL; + newblock->next = p->next; + newblock->prev = p; + p->next->prev = newblock; + p->next = newblock; + p->size = size; + } + + out: + /* Our block is in the middle */ + p->filp = filp; + return p; +} + +static struct mem_block *alloc_block(struct mem_block *heap, int size, + int align2, DRMFILE filp) +{ + struct mem_block *p; + int mask = (1 << align2) - 1; + + for (p = heap->next; p != heap; p = p->next) { + int start = (p->start + mask) & ~mask; + if (p->filp == NULL && start + size <= p->start + p->size) + return split_block(p, start, size, filp); + } + + return NULL; +} + +static struct mem_block *find_block(struct mem_block *heap, int start) +{ + struct mem_block *p; + + for (p = heap->next; p != heap; p = p->next) + if (p->start == start) + return p; + + return NULL; +} + +static void free_block(struct mem_block *p) +{ + p->filp = NULL; + + /* Assumes a single contiguous range. Needs a special filp in + * 'heap' to stop it being subsumed. + */ + if (p->next->filp == NULL) { + struct mem_block *q = p->next; + p->size += q->size; + p->next = q->next; + p->next->prev = p; + drm_free(q, sizeof(*q), DRM_MEM_BUFLISTS); + } + + if (p->prev->filp == NULL) { + struct mem_block *q = p->prev; + q->size += p->size; + q->next = p->next; + q->next->prev = q; + drm_free(p, sizeof(*q), DRM_MEM_BUFLISTS); + } +} + +/* Initialize. How to check for an uninitialized heap? + */ +static int init_heap(struct mem_block **heap, int start, int size) +{ + struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFLISTS); + + if (!blocks) + return -ENOMEM; + + *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFLISTS); + if (!*heap) { + drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFLISTS); + return -ENOMEM; + } + + blocks->start = start; + blocks->size = size; + blocks->filp = NULL; + blocks->next = blocks->prev = *heap; + + memset(*heap, 0, sizeof(**heap)); + (*heap)->filp = (DRMFILE) - 1; + (*heap)->next = (*heap)->prev = blocks; + return 0; +} + +/* Free all blocks associated with the releasing file. + */ +void i915_mem_release(drm_device_t * dev, DRMFILE filp, struct mem_block *heap) +{ + struct mem_block *p; + + if (!heap || !heap->next) + return; + + for (p = heap->next; p != heap; p = p->next) { + if (p->filp == filp) { + p->filp = NULL; + mark_block(dev, p, 0); + } + } + + /* Assumes a single contiguous range. Needs a special filp in + * 'heap' to stop it being subsumed. + */ + for (p = heap->next; p != heap; p = p->next) { + while (p->filp == NULL && p->next->filp == NULL) { + struct mem_block *q = p->next; + p->size += q->size; + p->next = q->next; + p->next->prev = p; + drm_free(q, sizeof(*q), DRM_MEM_BUFLISTS); + } + } +} + +/* Shutdown. + */ +void i915_mem_takedown(struct mem_block **heap) +{ + struct mem_block *p; + + if (!*heap) + return; + + for (p = (*heap)->next; p != *heap;) { + struct mem_block *q = p; + p = p->next; + drm_free(q, sizeof(*q), DRM_MEM_BUFLISTS); + } + + drm_free(*heap, sizeof(**heap), DRM_MEM_BUFLISTS); + *heap = NULL; +} + +static struct mem_block **get_heap(drm_i915_private_t * dev_priv, int region) +{ + switch (region) { + case I915_MEM_REGION_AGP: + return &dev_priv->agp_heap; + default: + return NULL; + } +} + +/* IOCTL HANDLERS */ + +int i915_mem_alloc(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_i915_private_t *dev_priv = dev->dev_private; + drm_i915_mem_alloc_t alloc; + struct mem_block *block, **heap; + + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL(alloc, (drm_i915_mem_alloc_t __user *) data, + sizeof(alloc)); + + heap = get_heap(dev_priv, alloc.region); + if (!heap || !*heap) + return DRM_ERR(EFAULT); + + /* Make things easier on ourselves: all allocations at least + * 4k aligned. + */ + if (alloc.alignment < 12) + alloc.alignment = 12; + + block = alloc_block(*heap, alloc.size, alloc.alignment, filp); + + if (!block) + return DRM_ERR(ENOMEM); + + mark_block(dev, block, 1); + + if (DRM_COPY_TO_USER(alloc.region_offset, &block->start, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); + return DRM_ERR(EFAULT); + } + + return 0; +} + +int i915_mem_free(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_i915_private_t *dev_priv = dev->dev_private; + drm_i915_mem_free_t memfree; + struct mem_block *block, **heap; + + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL(memfree, (drm_i915_mem_free_t __user *) data, + sizeof(memfree)); + + heap = get_heap(dev_priv, memfree.region); + if (!heap || !*heap) + return DRM_ERR(EFAULT); + + block = find_block(*heap, memfree.region_offset); + if (!block) + return DRM_ERR(EFAULT); + + if (block->filp != filp) + return DRM_ERR(EPERM); + + mark_block(dev, block, 0); + free_block(block); + return 0; +} + +int i915_mem_init_heap(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_i915_private_t *dev_priv = dev->dev_private; + drm_i915_mem_init_heap_t initheap; + struct mem_block **heap; + + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL(initheap, + (drm_i915_mem_init_heap_t __user *) data, + sizeof(initheap)); + + heap = get_heap(dev_priv, initheap.region); + if (!heap) + return DRM_ERR(EFAULT); + + if (*heap) { + DRM_ERROR("heap already initialized?"); + return DRM_ERR(EFAULT); + } + + return init_heap(heap, initheap.start, initheap.size); +} diff --git a/drivers/char/drm/mga_dma.c b/drivers/char/drm/mga_dma.c new file mode 100644 index 000000000000..832eaf8a5068 --- /dev/null +++ b/drivers/char/drm/mga_dma.c @@ -0,0 +1,754 @@ +/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*- + * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Jeff Hartmann + * Keith Whitwell + * + * Rewritten by: + * Gareth Hughes + */ + +#include "drmP.h" +#include "drm.h" +#include "mga_drm.h" +#include "mga_drv.h" + +#define MGA_DEFAULT_USEC_TIMEOUT 10000 +#define MGA_FREELIST_DEBUG 0 + +static int mga_do_cleanup_dma( drm_device_t *dev ); + +/* ================================================================ + * Engine control + */ + +int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ) +{ + u32 status = 0; + int i; + DRM_DEBUG( "\n" ); + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; + if ( status == MGA_ENDPRDMASTS ) { + MGA_WRITE8( MGA_CRTC_INDEX, 0 ); + return 0; + } + DRM_UDELAY( 1 ); + } + +#if MGA_DMA_DEBUG + DRM_ERROR( "failed!\n" ); + DRM_INFO( " status=0x%08x\n", status ); +#endif + return DRM_ERR(EBUSY); +} + +static int mga_do_dma_reset( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_primary_buffer_t *primary = &dev_priv->prim; + + DRM_DEBUG( "\n" ); + + /* The primary DMA stream should look like new right about now. + */ + primary->tail = 0; + primary->space = primary->size; + primary->last_flush = 0; + + sarea_priv->last_wrap = 0; + + /* FIXME: Reset counters, buffer ages etc... + */ + + /* FIXME: What else do we need to reinitialize? WARP stuff? + */ + + return 0; +} + +/* ================================================================ + * Primary DMA stream + */ + +void mga_do_dma_flush( drm_mga_private_t *dev_priv ) +{ + drm_mga_primary_buffer_t *primary = &dev_priv->prim; + u32 head, tail; + u32 status = 0; + int i; + DMA_LOCALS; + DRM_DEBUG( "\n" ); + + /* We need to wait so that we can do an safe flush */ + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; + if ( status == MGA_ENDPRDMASTS ) break; + DRM_UDELAY( 1 ); + } + + if ( primary->tail == primary->last_flush ) { + DRM_DEBUG( " bailing out...\n" ); + return; + } + + tail = primary->tail + dev_priv->primary->offset; + + /* We need to pad the stream between flushes, as the card + * actually (partially?) reads the first of these commands. + * See page 4-16 in the G400 manual, middle of the page or so. + */ + BEGIN_DMA( 1 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); + + ADVANCE_DMA(); + + primary->last_flush = primary->tail; + + head = MGA_READ( MGA_PRIMADDRESS ); + + if ( head <= tail ) { + primary->space = primary->size - primary->tail; + } else { + primary->space = head - tail; + } + + DRM_DEBUG( " head = 0x%06lx\n", head - dev_priv->primary->offset ); + DRM_DEBUG( " tail = 0x%06lx\n", tail - dev_priv->primary->offset ); + DRM_DEBUG( " space = 0x%06x\n", primary->space ); + + mga_flush_write_combine(); + MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER ); + + DRM_DEBUG( "done.\n" ); +} + +void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ) +{ + drm_mga_primary_buffer_t *primary = &dev_priv->prim; + u32 head, tail; + DMA_LOCALS; + DRM_DEBUG( "\n" ); + + BEGIN_DMA_WRAP(); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); + + ADVANCE_DMA(); + + tail = primary->tail + dev_priv->primary->offset; + + primary->tail = 0; + primary->last_flush = 0; + primary->last_wrap++; + + head = MGA_READ( MGA_PRIMADDRESS ); + + if ( head == dev_priv->primary->offset ) { + primary->space = primary->size; + } else { + primary->space = head - dev_priv->primary->offset; + } + + DRM_DEBUG( " head = 0x%06lx\n", + head - dev_priv->primary->offset ); + DRM_DEBUG( " tail = 0x%06x\n", primary->tail ); + DRM_DEBUG( " wrap = %d\n", primary->last_wrap ); + DRM_DEBUG( " space = 0x%06x\n", primary->space ); + + mga_flush_write_combine(); + MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER ); + + set_bit( 0, &primary->wrapped ); + DRM_DEBUG( "done.\n" ); +} + +void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ) +{ + drm_mga_primary_buffer_t *primary = &dev_priv->prim; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + u32 head = dev_priv->primary->offset; + DRM_DEBUG( "\n" ); + + sarea_priv->last_wrap++; + DRM_DEBUG( " wrap = %d\n", sarea_priv->last_wrap ); + + mga_flush_write_combine(); + MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL ); + + clear_bit( 0, &primary->wrapped ); + DRM_DEBUG( "done.\n" ); +} + + +/* ================================================================ + * Freelist management + */ + +#define MGA_BUFFER_USED ~0 +#define MGA_BUFFER_FREE 0 + +#if MGA_FREELIST_DEBUG +static void mga_freelist_print( drm_device_t *dev ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_freelist_t *entry; + + DRM_INFO( "\n" ); + DRM_INFO( "current dispatch: last=0x%x done=0x%x\n", + dev_priv->sarea_priv->last_dispatch, + (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) - + dev_priv->primary->offset) ); + DRM_INFO( "current freelist:\n" ); + + for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) { + DRM_INFO( " %p idx=%2d age=0x%x 0x%06lx\n", + entry, entry->buf->idx, entry->age.head, + entry->age.head - dev_priv->primary->offset ); + } + DRM_INFO( "\n" ); +} +#endif + +static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv ) +{ + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_mga_freelist_t *entry; + int i; + DRM_DEBUG( "count=%d\n", dma->buf_count ); + + dev_priv->head = drm_alloc( sizeof(drm_mga_freelist_t), + DRM_MEM_DRIVER ); + if ( dev_priv->head == NULL ) + return DRM_ERR(ENOMEM); + + memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) ); + SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 ); + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + + entry = drm_alloc( sizeof(drm_mga_freelist_t), + DRM_MEM_DRIVER ); + if ( entry == NULL ) + return DRM_ERR(ENOMEM); + + memset( entry, 0, sizeof(drm_mga_freelist_t) ); + + entry->next = dev_priv->head->next; + entry->prev = dev_priv->head; + SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); + entry->buf = buf; + + if ( dev_priv->head->next != NULL ) + dev_priv->head->next->prev = entry; + if ( entry->next == NULL ) + dev_priv->tail = entry; + + buf_priv->list_entry = entry; + buf_priv->discard = 0; + buf_priv->dispatched = 0; + + dev_priv->head->next = entry; + } + + return 0; +} + +static void mga_freelist_cleanup( drm_device_t *dev ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_freelist_t *entry; + drm_mga_freelist_t *next; + DRM_DEBUG( "\n" ); + + entry = dev_priv->head; + while ( entry ) { + next = entry->next; + drm_free( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER ); + entry = next; + } + + dev_priv->head = dev_priv->tail = NULL; +} + +#if 0 +/* FIXME: Still needed? + */ +static void mga_freelist_reset( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + int i; + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + SET_AGE( &buf_priv->list_entry->age, + MGA_BUFFER_FREE, 0 ); + } +} +#endif + +static drm_buf_t *mga_freelist_get( drm_device_t *dev ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_freelist_t *next; + drm_mga_freelist_t *prev; + drm_mga_freelist_t *tail = dev_priv->tail; + u32 head, wrap; + DRM_DEBUG( "\n" ); + + head = MGA_READ( MGA_PRIMADDRESS ); + wrap = dev_priv->sarea_priv->last_wrap; + + DRM_DEBUG( " tail=0x%06lx %d\n", + tail->age.head ? + tail->age.head - dev_priv->primary->offset : 0, + tail->age.wrap ); + DRM_DEBUG( " head=0x%06lx %d\n", + head - dev_priv->primary->offset, wrap ); + + if ( TEST_AGE( &tail->age, head, wrap ) ) { + prev = dev_priv->tail->prev; + next = dev_priv->tail; + prev->next = NULL; + next->prev = next->next = NULL; + dev_priv->tail = prev; + SET_AGE( &next->age, MGA_BUFFER_USED, 0 ); + return next->buf; + } + + DRM_DEBUG( "returning NULL!\n" ); + return NULL; +} + +int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + drm_mga_freelist_t *head, *entry, *prev; + + DRM_DEBUG( "age=0x%06lx wrap=%d\n", + buf_priv->list_entry->age.head - + dev_priv->primary->offset, + buf_priv->list_entry->age.wrap ); + + entry = buf_priv->list_entry; + head = dev_priv->head; + + if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) { + SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); + prev = dev_priv->tail; + prev->next = entry; + entry->prev = prev; + entry->next = NULL; + } else { + prev = head->next; + head->next = entry; + prev->prev = entry; + entry->prev = head; + entry->next = prev; + } + + return 0; +} + + +/* ================================================================ + * DMA initialization, cleanup + */ + +static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) +{ + drm_mga_private_t *dev_priv; + int ret; + DRM_DEBUG( "\n" ); + + dev_priv = drm_alloc( sizeof(drm_mga_private_t), DRM_MEM_DRIVER ); + if ( !dev_priv ) + return DRM_ERR(ENOMEM); + + memset( dev_priv, 0, sizeof(drm_mga_private_t) ); + + dev_priv->chipset = init->chipset; + + dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT; + + if ( init->sgram ) { + dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK; + } else { + dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; + } + dev_priv->maccess = init->maccess; + + dev_priv->fb_cpp = init->fb_cpp; + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; + + dev_priv->depth_cpp = init->depth_cpp; + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; + + /* FIXME: Need to support AGP textures... + */ + dev_priv->texture_offset = init->texture_offset[0]; + dev_priv->texture_size = init->texture_size[0]; + + DRM_GETSAREA(); + + if(!dev_priv->sarea) { + DRM_ERROR( "failed to find sarea!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + return DRM_ERR(EINVAL); + } + + dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); + if(!dev_priv->mmio) { + DRM_ERROR( "failed to find mmio region!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + return DRM_ERR(EINVAL); + } + dev_priv->status = drm_core_findmap(dev, init->status_offset); + if(!dev_priv->status) { + DRM_ERROR( "failed to find status page!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + return DRM_ERR(EINVAL); + } + dev_priv->warp = drm_core_findmap(dev, init->warp_offset); + if(!dev_priv->warp) { + DRM_ERROR( "failed to find warp microcode region!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + return DRM_ERR(EINVAL); + } + dev_priv->primary = drm_core_findmap(dev, init->primary_offset); + if(!dev_priv->primary) { + DRM_ERROR( "failed to find primary dma region!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + return DRM_ERR(EINVAL); + } + dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); + if(!dev->agp_buffer_map) { + DRM_ERROR( "failed to find dma buffer region!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + return DRM_ERR(EINVAL); + } + + dev_priv->sarea_priv = + (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle + + init->sarea_priv_offset); + + drm_core_ioremap( dev_priv->warp, dev ); + drm_core_ioremap( dev_priv->primary, dev ); + drm_core_ioremap( dev->agp_buffer_map, dev ); + + if(!dev_priv->warp->handle || + !dev_priv->primary->handle || + !dev->agp_buffer_map->handle ) { + DRM_ERROR( "failed to ioremap agp regions!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + return DRM_ERR(ENOMEM); + } + + ret = mga_warp_install_microcode( dev_priv ); + if ( ret < 0 ) { + DRM_ERROR( "failed to install WARP ucode!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + return ret; + } + + ret = mga_warp_init( dev_priv ); + if ( ret < 0 ) { + DRM_ERROR( "failed to init WARP engine!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + return ret; + } + + dev_priv->prim.status = (u32 *)dev_priv->status->handle; + + mga_do_wait_for_idle( dev_priv ); + + /* Init the primary DMA registers. + */ + MGA_WRITE( MGA_PRIMADDRESS, + dev_priv->primary->offset | MGA_DMA_GENERAL ); +#if 0 + MGA_WRITE( MGA_PRIMPTR, + virt_to_bus((void *)dev_priv->prim.status) | + MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */ + MGA_PRIMPTREN1 ); /* DWGSYNC */ +#endif + + dev_priv->prim.start = (u8 *)dev_priv->primary->handle; + dev_priv->prim.end = ((u8 *)dev_priv->primary->handle + + dev_priv->primary->size); + dev_priv->prim.size = dev_priv->primary->size; + + dev_priv->prim.tail = 0; + dev_priv->prim.space = dev_priv->prim.size; + dev_priv->prim.wrapped = 0; + + dev_priv->prim.last_flush = 0; + dev_priv->prim.last_wrap = 0; + + dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE; + + dev_priv->prim.status[0] = dev_priv->primary->offset; + dev_priv->prim.status[1] = 0; + + dev_priv->sarea_priv->last_wrap = 0; + dev_priv->sarea_priv->last_frame.head = 0; + dev_priv->sarea_priv->last_frame.wrap = 0; + + if ( mga_freelist_init( dev, dev_priv ) < 0 ) { + DRM_ERROR( "could not initialize freelist\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + return DRM_ERR(ENOMEM); + } + + /* Make dev_private visable to others. */ + dev->dev_private = (void *)dev_priv; + return 0; +} + +static int mga_do_cleanup_dma( drm_device_t *dev ) +{ + DRM_DEBUG( "\n" ); + + /* Make sure interrupts are disabled here because the uninstall ioctl + * may not have been called from userspace and after dev_private + * is freed, it's too late. + */ + if ( dev->irq_enabled ) drm_irq_uninstall(dev); + + if ( dev->dev_private ) { + drm_mga_private_t *dev_priv = dev->dev_private; + + if ( dev_priv->warp != NULL ) + drm_core_ioremapfree( dev_priv->warp, dev ); + if ( dev_priv->primary != NULL ) + drm_core_ioremapfree( dev_priv->primary, dev ); + if ( dev->agp_buffer_map != NULL ) + drm_core_ioremapfree( dev->agp_buffer_map, dev ); + + if ( dev_priv->head != NULL ) { + mga_freelist_cleanup( dev ); + } + + drm_free( dev->dev_private, sizeof(drm_mga_private_t), + DRM_MEM_DRIVER ); + dev->dev_private = NULL; + } + + return 0; +} + +int mga_dma_init( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_mga_init_t init; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( init, (drm_mga_init_t __user *)data, sizeof(init) ); + + switch ( init.func ) { + case MGA_INIT_DMA: + return mga_do_init_dma( dev, &init ); + case MGA_CLEANUP_DMA: + return mga_do_cleanup_dma( dev ); + } + + return DRM_ERR(EINVAL); +} + + +/* ================================================================ + * Primary DMA stream management + */ + +int mga_dma_flush( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_lock_t lock; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( lock, (drm_lock_t __user *)data, sizeof(lock) ); + + DRM_DEBUG( "%s%s%s\n", + (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", + (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", + (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" ); + + WRAP_WAIT_WITH_RETURN( dev_priv ); + + if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) { + mga_do_dma_flush( dev_priv ); + } + + if ( lock.flags & _DRM_LOCK_QUIESCENT ) { +#if MGA_DMA_DEBUG + int ret = mga_do_wait_for_idle( dev_priv ); + if ( ret < 0 ) + DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); + return ret; +#else + return mga_do_wait_for_idle( dev_priv ); +#endif + } else { + return 0; + } +} + +int mga_dma_reset( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + return mga_do_dma_reset( dev_priv ); +} + + +/* ================================================================ + * DMA buffer management + */ + +static int mga_dma_get_buffers( DRMFILE filp, + drm_device_t *dev, drm_dma_t *d ) +{ + drm_buf_t *buf; + int i; + + for ( i = d->granted_count ; i < d->request_count ; i++ ) { + buf = mga_freelist_get( dev ); + if ( !buf ) return DRM_ERR(EAGAIN); + + buf->filp = filp; + + if ( DRM_COPY_TO_USER( &d->request_indices[i], + &buf->idx, sizeof(buf->idx) ) ) + return DRM_ERR(EFAULT); + if ( DRM_COPY_TO_USER( &d->request_sizes[i], + &buf->total, sizeof(buf->total) ) ) + return DRM_ERR(EFAULT); + + d->granted_count++; + } + return 0; +} + +int mga_dma_buffers( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_device_dma_t *dma = dev->dma; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_dma_t __user *argp = (void __user *)data; + drm_dma_t d; + int ret = 0; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); + + /* Please don't send us buffers. + */ + if ( d.send_count != 0 ) { + DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", + DRM_CURRENTPID, d.send_count ); + return DRM_ERR(EINVAL); + } + + /* We'll send you buffers. + */ + if ( d.request_count < 0 || d.request_count > dma->buf_count ) { + DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", + DRM_CURRENTPID, d.request_count, dma->buf_count ); + return DRM_ERR(EINVAL); + } + + WRAP_TEST_WITH_RETURN( dev_priv ); + + d.granted_count = 0; + + if ( d.request_count ) { + ret = mga_dma_get_buffers( filp, dev, &d ); + } + + DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); + + return ret; +} + +void mga_driver_pretakedown(drm_device_t *dev) +{ + mga_do_cleanup_dma( dev ); +} + +int mga_driver_dma_quiescent(drm_device_t *dev) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + return mga_do_wait_for_idle( dev_priv ); +} diff --git a/drivers/char/drm/mga_drm.h b/drivers/char/drm/mga_drm.h new file mode 100644 index 000000000000..521d4451d012 --- /dev/null +++ b/drivers/char/drm/mga_drm.h @@ -0,0 +1,349 @@ +/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- + * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jeff Hartmann + * Keith Whitwell + * + * Rewritten by: + * Gareth Hughes + */ + +#ifndef __MGA_DRM_H__ +#define __MGA_DRM_H__ + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (mga_sarea.h) + */ + +#ifndef __MGA_SAREA_DEFINES__ +#define __MGA_SAREA_DEFINES__ + +/* WARP pipe flags + */ +#define MGA_F 0x1 /* fog */ +#define MGA_A 0x2 /* alpha */ +#define MGA_S 0x4 /* specular */ +#define MGA_T2 0x8 /* multitexture */ + +#define MGA_WARP_TGZ 0 +#define MGA_WARP_TGZF (MGA_F) +#define MGA_WARP_TGZA (MGA_A) +#define MGA_WARP_TGZAF (MGA_F|MGA_A) +#define MGA_WARP_TGZS (MGA_S) +#define MGA_WARP_TGZSF (MGA_S|MGA_F) +#define MGA_WARP_TGZSA (MGA_S|MGA_A) +#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) +#define MGA_WARP_T2GZ (MGA_T2) +#define MGA_WARP_T2GZF (MGA_T2|MGA_F) +#define MGA_WARP_T2GZA (MGA_T2|MGA_A) +#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) +#define MGA_WARP_T2GZS (MGA_T2|MGA_S) +#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) +#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) +#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) + +#define MGA_MAX_G200_PIPES 8 /* no multitex */ +#define MGA_MAX_G400_PIPES 16 +#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES +#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ + +#define MGA_CARD_TYPE_G200 1 +#define MGA_CARD_TYPE_G400 2 + + +#define MGA_FRONT 0x1 +#define MGA_BACK 0x2 +#define MGA_DEPTH 0x4 + +/* What needs to be changed for the current vertex dma buffer? + */ +#define MGA_UPLOAD_CONTEXT 0x1 +#define MGA_UPLOAD_TEX0 0x2 +#define MGA_UPLOAD_TEX1 0x4 +#define MGA_UPLOAD_PIPE 0x8 +#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ +#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ +#define MGA_UPLOAD_2D 0x40 +#define MGA_WAIT_AGE 0x80 /* handled client-side */ +#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ +#if 0 +#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock + quiescent */ +#endif + +/* 32 buffers of 64k each, total 2 meg. + */ +#define MGA_BUFFER_SIZE (1 << 16) +#define MGA_NUM_BUFFERS 128 + +/* Keep these small for testing. + */ +#define MGA_NR_SAREA_CLIPRECTS 8 + +/* 2 heaps (1 for card, 1 for agp), each divided into upto 128 + * regions, subject to a minimum region size of (1<<16) == 64k. + * + * Clients may subdivide regions internally, but when sharing between + * clients, the region size is the minimum granularity. + */ + +#define MGA_CARD_HEAP 0 +#define MGA_AGP_HEAP 1 +#define MGA_NR_TEX_HEAPS 2 +#define MGA_NR_TEX_REGIONS 16 +#define MGA_LOG_MIN_TEX_REGION_SIZE 16 + +#define DRM_MGA_IDLE_RETRY 2048 + +#endif /* __MGA_SAREA_DEFINES__ */ + + +/* Setup registers for 3D context + */ +typedef struct { + unsigned int dstorg; + unsigned int maccess; + unsigned int plnwt; + unsigned int dwgctl; + unsigned int alphactrl; + unsigned int fogcolor; + unsigned int wflag; + unsigned int tdualstage0; + unsigned int tdualstage1; + unsigned int fcol; + unsigned int stencil; + unsigned int stencilctl; +} drm_mga_context_regs_t; + +/* Setup registers for 2D, X server + */ +typedef struct { + unsigned int pitch; +} drm_mga_server_regs_t; + +/* Setup registers for each texture unit + */ +typedef struct { + unsigned int texctl; + unsigned int texctl2; + unsigned int texfilter; + unsigned int texbordercol; + unsigned int texorg; + unsigned int texwidth; + unsigned int texheight; + unsigned int texorg1; + unsigned int texorg2; + unsigned int texorg3; + unsigned int texorg4; +} drm_mga_texture_regs_t; + +/* General aging mechanism + */ +typedef struct { + unsigned int head; /* Position of head pointer */ + unsigned int wrap; /* Primary DMA wrap count */ +} drm_mga_age_t; + +typedef struct _drm_mga_sarea { + /* The channel for communication of state information to the kernel + * on firing a vertex dma buffer. + */ + drm_mga_context_regs_t context_state; + drm_mga_server_regs_t server_state; + drm_mga_texture_regs_t tex_state[2]; + unsigned int warp_pipe; + unsigned int dirty; + unsigned int vertsize; + + /* The current cliprects, or a subset thereof. + */ + drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS]; + unsigned int nbox; + + /* Information about the most recently used 3d drawable. The + * client fills in the req_* fields, the server fills in the + * exported_ fields and puts the cliprects into boxes, above. + * + * The client clears the exported_drawable field before + * clobbering the boxes data. + */ + unsigned int req_drawable; /* the X drawable id */ + unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ + + unsigned int exported_drawable; + unsigned int exported_index; + unsigned int exported_stamp; + unsigned int exported_buffers; + unsigned int exported_nfront; + unsigned int exported_nback; + int exported_back_x, exported_front_x, exported_w; + int exported_back_y, exported_front_y, exported_h; + drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS]; + + /* Counters for aging textures and for client-side throttling. + */ + unsigned int status[4]; + unsigned int last_wrap; + + drm_mga_age_t last_frame; + unsigned int last_enqueue; /* last time a buffer was enqueued */ + unsigned int last_dispatch; /* age of the most recently dispatched buffer */ + unsigned int last_quiescent; /* */ + + /* LRU lists for texture memory in agp space and on the card. + */ + drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1]; + unsigned int texAge[MGA_NR_TEX_HEAPS]; + + /* Mechanism to validate card state. + */ + int ctxOwner; +} drm_mga_sarea_t; + + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmMga.h) + */ + +/* MGA specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_MGA_INIT 0x00 +#define DRM_MGA_FLUSH 0x01 +#define DRM_MGA_RESET 0x02 +#define DRM_MGA_SWAP 0x03 +#define DRM_MGA_CLEAR 0x04 +#define DRM_MGA_VERTEX 0x05 +#define DRM_MGA_INDICES 0x06 +#define DRM_MGA_ILOAD 0x07 +#define DRM_MGA_BLIT 0x08 +#define DRM_MGA_GETPARAM 0x09 + +#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) +#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) +#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) +#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) +#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) +#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) +#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) +#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) +#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) +#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) + +typedef struct _drm_mga_warp_index { + int installed; + unsigned long phys_addr; + int size; +} drm_mga_warp_index_t; + +typedef struct drm_mga_init { + enum { + MGA_INIT_DMA = 0x01, + MGA_CLEANUP_DMA = 0x02 + } func; + + unsigned long sarea_priv_offset; + + int chipset; + int sgram; + + unsigned int maccess; + + unsigned int fb_cpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + + unsigned int depth_cpp; + unsigned int depth_offset, depth_pitch; + + unsigned int texture_offset[MGA_NR_TEX_HEAPS]; + unsigned int texture_size[MGA_NR_TEX_HEAPS]; + + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long status_offset; + unsigned long warp_offset; + unsigned long primary_offset; + unsigned long buffers_offset; +} drm_mga_init_t; + +typedef struct drm_mga_fullscreen { + enum { + MGA_INIT_FULLSCREEN = 0x01, + MGA_CLEANUP_FULLSCREEN = 0x02 + } func; +} drm_mga_fullscreen_t; + +typedef struct drm_mga_clear { + unsigned int flags; + unsigned int clear_color; + unsigned int clear_depth; + unsigned int color_mask; + unsigned int depth_mask; +} drm_mga_clear_t; + +typedef struct drm_mga_vertex { + int idx; /* buffer to queue */ + int used; /* bytes in use */ + int discard; /* client finished with buffer? */ +} drm_mga_vertex_t; + +typedef struct drm_mga_indices { + int idx; /* buffer to queue */ + unsigned int start; + unsigned int end; + int discard; /* client finished with buffer? */ +} drm_mga_indices_t; + +typedef struct drm_mga_iload { + int idx; + unsigned int dstorg; + unsigned int length; +} drm_mga_iload_t; + +typedef struct _drm_mga_blit { + unsigned int planemask; + unsigned int srcorg; + unsigned int dstorg; + int src_pitch, dst_pitch; + int delta_sx, delta_sy; + int delta_dx, delta_dy; + int height, ydir; /* flip image vertically */ + int source_pitch, dest_pitch; +} drm_mga_blit_t; + +/* 3.1: An ioctl to get parameters that aren't available to the 3d + * client any other way. + */ +#define MGA_PARAM_IRQ_NR 1 + +typedef struct drm_mga_getparam { + int param; + void __user *value; +} drm_mga_getparam_t; + +#endif diff --git a/drivers/char/drm/mga_drv.c b/drivers/char/drm/mga_drv.c new file mode 100644 index 000000000000..22dab3e9d92a --- /dev/null +++ b/drivers/char/drm/mga_drv.c @@ -0,0 +1,127 @@ +/* mga_drv.c -- Matrox G200/G400 driver -*- linux-c -*- + * Created: Mon Dec 13 01:56:22 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Gareth Hughes + */ + +#include +#include "drmP.h" +#include "drm.h" +#include "mga_drm.h" +#include "mga_drv.h" + + +#include "drm_pciids.h" + +static int postinit( struct drm_device *dev, unsigned long flags ) +{ + dev->counters += 3; + dev->types[6] = _DRM_STAT_IRQ; + dev->types[7] = _DRM_STAT_PRIMARY; + dev->types[8] = _DRM_STAT_SECONDARY; + + DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, + dev->primary.minor, + pci_pretty_name(dev->pdev) + ); + return 0; +} + +static int version( drm_version_t *version ) +{ + int len; + + version->version_major = DRIVER_MAJOR; + version->version_minor = DRIVER_MINOR; + version->version_patchlevel = DRIVER_PATCHLEVEL; + DRM_COPY( version->name, DRIVER_NAME ); + DRM_COPY( version->date, DRIVER_DATE ); + DRM_COPY( version->desc, DRIVER_DESC ); + return 0; +} + +static struct pci_device_id pciidlist[] = { + mga_PCI_IDS +}; + +extern drm_ioctl_desc_t mga_ioctls[]; +extern int mga_max_ioctl; + +static struct drm_driver driver = { + .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, + .pretakedown = mga_driver_pretakedown, + .dma_quiescent = mga_driver_dma_quiescent, + .vblank_wait = mga_driver_vblank_wait, + .irq_preinstall = mga_driver_irq_preinstall, + .irq_postinstall = mga_driver_irq_postinstall, + .irq_uninstall = mga_driver_irq_uninstall, + .irq_handler = mga_driver_irq_handler, + .reclaim_buffers = drm_core_reclaim_buffers, + .get_map_ofs = drm_core_get_map_ofs, + .get_reg_ofs = drm_core_get_reg_ofs, + .postinit = postinit, + .version = version, + .ioctls = mga_ioctls, + .dma_ioctl = mga_dma_buffers, + .fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + }, + .pci_driver = { + .name = DRIVER_NAME, + .id_table = pciidlist, + } +}; + +static int __init mga_init(void) +{ + driver.num_ioctls = mga_max_ioctl; + return drm_init(&driver); +} + +static void __exit mga_exit(void) +{ + drm_exit(&driver); +} + +module_init(mga_init); +module_exit(mga_exit); + +MODULE_AUTHOR( DRIVER_AUTHOR ); +MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/mga_drv.h b/drivers/char/drm/mga_drv.h new file mode 100644 index 000000000000..1d84a1eb34db --- /dev/null +++ b/drivers/char/drm/mga_drv.h @@ -0,0 +1,638 @@ +/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*- + * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Gareth Hughes + */ + +#ifndef __MGA_DRV_H__ +#define __MGA_DRV_H__ + +/* General customization: + */ + +#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." + +#define DRIVER_NAME "mga" +#define DRIVER_DESC "Matrox G200/G400" +#define DRIVER_DATE "20021029" + +#define DRIVER_MAJOR 3 +#define DRIVER_MINOR 1 +#define DRIVER_PATCHLEVEL 0 + +typedef struct drm_mga_primary_buffer { + u8 *start; + u8 *end; + int size; + + u32 tail; + int space; + volatile long wrapped; + + volatile u32 *status; + + u32 last_flush; + u32 last_wrap; + + u32 high_mark; +} drm_mga_primary_buffer_t; + +typedef struct drm_mga_freelist { + struct drm_mga_freelist *next; + struct drm_mga_freelist *prev; + drm_mga_age_t age; + drm_buf_t *buf; +} drm_mga_freelist_t; + +typedef struct { + drm_mga_freelist_t *list_entry; + int discard; + int dispatched; +} drm_mga_buf_priv_t; + +typedef struct drm_mga_private { + drm_mga_primary_buffer_t prim; + drm_mga_sarea_t *sarea_priv; + + drm_mga_freelist_t *head; + drm_mga_freelist_t *tail; + + unsigned int warp_pipe; + unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; + + int chipset; + int usec_timeout; + + u32 clear_cmd; + u32 maccess; + + unsigned int fb_cpp; + unsigned int front_offset; + unsigned int front_pitch; + unsigned int back_offset; + unsigned int back_pitch; + + unsigned int depth_cpp; + unsigned int depth_offset; + unsigned int depth_pitch; + + unsigned int texture_offset; + unsigned int texture_size; + + drm_local_map_t *sarea; + drm_local_map_t *mmio; + drm_local_map_t *status; + drm_local_map_t *warp; + drm_local_map_t *primary; + drm_local_map_t *buffers; + drm_local_map_t *agp_textures; +} drm_mga_private_t; + + /* mga_dma.c */ +extern int mga_dma_init( DRM_IOCTL_ARGS ); +extern int mga_dma_flush( DRM_IOCTL_ARGS ); +extern int mga_dma_reset( DRM_IOCTL_ARGS ); +extern int mga_dma_buffers( DRM_IOCTL_ARGS ); +extern void mga_driver_pretakedown(drm_device_t *dev); +extern int mga_driver_dma_quiescent(drm_device_t *dev); + +extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ); + +extern void mga_do_dma_flush( drm_mga_private_t *dev_priv ); +extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ); +extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ); + +extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ); + + /* mga_warp.c */ +extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); +extern int mga_warp_init( drm_mga_private_t *dev_priv ); + +extern int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); +extern irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS ); +extern void mga_driver_irq_preinstall( drm_device_t *dev ); +extern void mga_driver_irq_postinstall( drm_device_t *dev ); +extern void mga_driver_irq_uninstall( drm_device_t *dev ); + +#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() + +#if defined(__linux__) && defined(__alpha__) +#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) +#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) + +#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) +#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) + +#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) +#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) +#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) +#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) + +static inline u32 _MGA_READ(u32 *addr) +{ + DRM_MEMORYBARRIER(); + return *(volatile u32 *)addr; +} +#else +#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) +#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) +#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) +#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) +#endif + +#define DWGREG0 0x1c00 +#define DWGREG0_END 0x1dff +#define DWGREG1 0x2c00 +#define DWGREG1_END 0x2dff + +#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) +#define DMAREG0(r) (u8)((r - DWGREG0) >> 2) +#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) +#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) + + + +/* ================================================================ + * Helper macross... + */ + +#define MGA_EMIT_STATE( dev_priv, dirty ) \ +do { \ + if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ + if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \ + mga_g400_emit_state( dev_priv ); \ + } else { \ + mga_g200_emit_state( dev_priv ); \ + } \ + } \ +} while (0) + +#define WRAP_TEST_WITH_RETURN( dev_priv ) \ +do { \ + if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ + if ( mga_is_idle( dev_priv ) ) { \ + mga_do_dma_wrap_end( dev_priv ); \ + } else if ( dev_priv->prim.space < \ + dev_priv->prim.high_mark ) { \ + if ( MGA_DMA_DEBUG ) \ + DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ + return DRM_ERR(EBUSY); \ + } \ + } \ +} while (0) + +#define WRAP_WAIT_WITH_RETURN( dev_priv ) \ +do { \ + if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ + if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \ + if ( MGA_DMA_DEBUG ) \ + DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ + return DRM_ERR(EBUSY); \ + } \ + mga_do_dma_wrap_end( dev_priv ); \ + } \ +} while (0) + + +/* ================================================================ + * Primary DMA command stream + */ + +#define MGA_VERBOSE 0 + +#define DMA_LOCALS unsigned int write; volatile u8 *prim; + +#define DMA_BLOCK_SIZE (5 * sizeof(u32)) + +#define BEGIN_DMA( n ) \ +do { \ + if ( MGA_VERBOSE ) { \ + DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \ + (n), __FUNCTION__ ); \ + DRM_INFO( " space=0x%x req=0x%Zx\n", \ + dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ + } \ + prim = dev_priv->prim.start; \ + write = dev_priv->prim.tail; \ +} while (0) + +#define BEGIN_DMA_WRAP() \ +do { \ + if ( MGA_VERBOSE ) { \ + DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \ + DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ + } \ + prim = dev_priv->prim.start; \ + write = dev_priv->prim.tail; \ +} while (0) + +#define ADVANCE_DMA() \ +do { \ + dev_priv->prim.tail = write; \ + if ( MGA_VERBOSE ) { \ + DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ + write, dev_priv->prim.space ); \ + } \ +} while (0) + +#define FLUSH_DMA() \ +do { \ + if ( 0 ) { \ + DRM_INFO( "%s:\n", __FUNCTION__ ); \ + DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ + dev_priv->prim.tail, \ + MGA_READ( MGA_PRIMADDRESS ) - \ + dev_priv->primary->offset ); \ + } \ + if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ + if ( dev_priv->prim.space < \ + dev_priv->prim.high_mark ) { \ + mga_do_dma_wrap_start( dev_priv ); \ + } else { \ + mga_do_dma_flush( dev_priv ); \ + } \ + } \ +} while (0) + +/* Never use this, always use DMA_BLOCK(...) for primary DMA output. + */ +#define DMA_WRITE( offset, val ) \ +do { \ + if ( MGA_VERBOSE ) { \ + DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \ + (u32)(val), write + (offset) * sizeof(u32) ); \ + } \ + *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ +} while (0) + +#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ +do { \ + DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ + (DMAREG( reg1 ) << 8) | \ + (DMAREG( reg2 ) << 16) | \ + (DMAREG( reg3 ) << 24)) ); \ + DMA_WRITE( 1, val0 ); \ + DMA_WRITE( 2, val1 ); \ + DMA_WRITE( 3, val2 ); \ + DMA_WRITE( 4, val3 ); \ + write += DMA_BLOCK_SIZE; \ +} while (0) + + +/* Buffer aging via primary DMA stream head pointer. + */ + +#define SET_AGE( age, h, w ) \ +do { \ + (age)->head = h; \ + (age)->wrap = w; \ +} while (0) + +#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ + ( (age)->wrap == w && \ + (age)->head < h ) ) + +#define AGE_BUFFER( buf_priv ) \ +do { \ + drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ + if ( (buf_priv)->dispatched ) { \ + entry->age.head = (dev_priv->prim.tail + \ + dev_priv->primary->offset); \ + entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ + } else { \ + entry->age.head = 0; \ + entry->age.wrap = 0; \ + } \ +} while (0) + + +#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ + MGA_DWGENGSTS | \ + MGA_ENDPRDMASTS) +#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ + MGA_ENDPRDMASTS) + +#define MGA_DMA_DEBUG 0 + + + +/* A reduced set of the mga registers. + */ +#define MGA_CRTC_INDEX 0x1fd4 +#define MGA_CRTC_DATA 0x1fd5 + +/* CRTC11 */ +#define MGA_VINTCLR (1 << 4) +#define MGA_VINTEN (1 << 5) + +#define MGA_ALPHACTRL 0x2c7c +#define MGA_AR0 0x1c60 +#define MGA_AR1 0x1c64 +#define MGA_AR2 0x1c68 +#define MGA_AR3 0x1c6c +#define MGA_AR4 0x1c70 +#define MGA_AR5 0x1c74 +#define MGA_AR6 0x1c78 + +#define MGA_CXBNDRY 0x1c80 +#define MGA_CXLEFT 0x1ca0 +#define MGA_CXRIGHT 0x1ca4 + +#define MGA_DMAPAD 0x1c54 +#define MGA_DSTORG 0x2cb8 +#define MGA_DWGCTL 0x1c00 +# define MGA_OPCOD_MASK (15 << 0) +# define MGA_OPCOD_TRAP (4 << 0) +# define MGA_OPCOD_TEXTURE_TRAP (6 << 0) +# define MGA_OPCOD_BITBLT (8 << 0) +# define MGA_OPCOD_ILOAD (9 << 0) +# define MGA_ATYPE_MASK (7 << 4) +# define MGA_ATYPE_RPL (0 << 4) +# define MGA_ATYPE_RSTR (1 << 4) +# define MGA_ATYPE_ZI (3 << 4) +# define MGA_ATYPE_BLK (4 << 4) +# define MGA_ATYPE_I (7 << 4) +# define MGA_LINEAR (1 << 7) +# define MGA_ZMODE_MASK (7 << 8) +# define MGA_ZMODE_NOZCMP (0 << 8) +# define MGA_ZMODE_ZE (2 << 8) +# define MGA_ZMODE_ZNE (3 << 8) +# define MGA_ZMODE_ZLT (4 << 8) +# define MGA_ZMODE_ZLTE (5 << 8) +# define MGA_ZMODE_ZGT (6 << 8) +# define MGA_ZMODE_ZGTE (7 << 8) +# define MGA_SOLID (1 << 11) +# define MGA_ARZERO (1 << 12) +# define MGA_SGNZERO (1 << 13) +# define MGA_SHIFTZERO (1 << 14) +# define MGA_BOP_MASK (15 << 16) +# define MGA_BOP_ZERO (0 << 16) +# define MGA_BOP_DST (10 << 16) +# define MGA_BOP_SRC (12 << 16) +# define MGA_BOP_ONE (15 << 16) +# define MGA_TRANS_SHIFT 20 +# define MGA_TRANS_MASK (15 << 20) +# define MGA_BLTMOD_MASK (15 << 25) +# define MGA_BLTMOD_BMONOLEF (0 << 25) +# define MGA_BLTMOD_BMONOWF (4 << 25) +# define MGA_BLTMOD_PLAN (1 << 25) +# define MGA_BLTMOD_BFCOL (2 << 25) +# define MGA_BLTMOD_BU32BGR (3 << 25) +# define MGA_BLTMOD_BU32RGB (7 << 25) +# define MGA_BLTMOD_BU24BGR (11 << 25) +# define MGA_BLTMOD_BU24RGB (15 << 25) +# define MGA_PATTERN (1 << 29) +# define MGA_TRANSC (1 << 30) +# define MGA_CLIPDIS (1 << 31) +#define MGA_DWGSYNC 0x2c4c + +#define MGA_FCOL 0x1c24 +#define MGA_FIFOSTATUS 0x1e10 +#define MGA_FOGCOL 0x1cf4 +#define MGA_FXBNDRY 0x1c84 +#define MGA_FXLEFT 0x1ca8 +#define MGA_FXRIGHT 0x1cac + +#define MGA_ICLEAR 0x1e18 +# define MGA_SOFTRAPICLR (1 << 0) +# define MGA_VLINEICLR (1 << 5) +#define MGA_IEN 0x1e1c +# define MGA_SOFTRAPIEN (1 << 0) +# define MGA_VLINEIEN (1 << 5) + +#define MGA_LEN 0x1c5c + +#define MGA_MACCESS 0x1c04 + +#define MGA_PITCH 0x1c8c +#define MGA_PLNWT 0x1c1c +#define MGA_PRIMADDRESS 0x1e58 +# define MGA_DMA_GENERAL (0 << 0) +# define MGA_DMA_BLIT (1 << 0) +# define MGA_DMA_VECTOR (2 << 0) +# define MGA_DMA_VERTEX (3 << 0) +#define MGA_PRIMEND 0x1e5c +# define MGA_PRIMNOSTART (1 << 0) +# define MGA_PAGPXFER (1 << 1) +#define MGA_PRIMPTR 0x1e50 +# define MGA_PRIMPTREN0 (1 << 0) +# define MGA_PRIMPTREN1 (1 << 1) + +#define MGA_RST 0x1e40 +# define MGA_SOFTRESET (1 << 0) +# define MGA_SOFTEXTRST (1 << 1) + +#define MGA_SECADDRESS 0x2c40 +#define MGA_SECEND 0x2c44 +#define MGA_SETUPADDRESS 0x2cd0 +#define MGA_SETUPEND 0x2cd4 +#define MGA_SGN 0x1c58 +#define MGA_SOFTRAP 0x2c48 +#define MGA_SRCORG 0x2cb4 +# define MGA_SRMMAP_MASK (1 << 0) +# define MGA_SRCMAP_FB (0 << 0) +# define MGA_SRCMAP_SYSMEM (1 << 0) +# define MGA_SRCACC_MASK (1 << 1) +# define MGA_SRCACC_PCI (0 << 1) +# define MGA_SRCACC_AGP (1 << 1) +#define MGA_STATUS 0x1e14 +# define MGA_SOFTRAPEN (1 << 0) +# define MGA_VSYNCPEN (1 << 4) +# define MGA_VLINEPEN (1 << 5) +# define MGA_DWGENGSTS (1 << 16) +# define MGA_ENDPRDMASTS (1 << 17) +#define MGA_STENCIL 0x2cc8 +#define MGA_STENCILCTL 0x2ccc + +#define MGA_TDUALSTAGE0 0x2cf8 +#define MGA_TDUALSTAGE1 0x2cfc +#define MGA_TEXBORDERCOL 0x2c5c +#define MGA_TEXCTL 0x2c30 +#define MGA_TEXCTL2 0x2c3c +# define MGA_DUALTEX (1 << 7) +# define MGA_G400_TC2_MAGIC (1 << 15) +# define MGA_MAP1_ENABLE (1 << 31) +#define MGA_TEXFILTER 0x2c58 +#define MGA_TEXHEIGHT 0x2c2c +#define MGA_TEXORG 0x2c24 +# define MGA_TEXORGMAP_MASK (1 << 0) +# define MGA_TEXORGMAP_FB (0 << 0) +# define MGA_TEXORGMAP_SYSMEM (1 << 0) +# define MGA_TEXORGACC_MASK (1 << 1) +# define MGA_TEXORGACC_PCI (0 << 1) +# define MGA_TEXORGACC_AGP (1 << 1) +#define MGA_TEXORG1 0x2ca4 +#define MGA_TEXORG2 0x2ca8 +#define MGA_TEXORG3 0x2cac +#define MGA_TEXORG4 0x2cb0 +#define MGA_TEXTRANS 0x2c34 +#define MGA_TEXTRANSHIGH 0x2c38 +#define MGA_TEXWIDTH 0x2c28 + +#define MGA_WACCEPTSEQ 0x1dd4 +#define MGA_WCODEADDR 0x1e6c +#define MGA_WFLAG 0x1dc4 +#define MGA_WFLAG1 0x1de0 +#define MGA_WFLAGNB 0x1e64 +#define MGA_WFLAGNB1 0x1e08 +#define MGA_WGETMSB 0x1dc8 +#define MGA_WIADDR 0x1dc0 +#define MGA_WIADDR2 0x1dd8 +# define MGA_WMODE_SUSPEND (0 << 0) +# define MGA_WMODE_RESUME (1 << 0) +# define MGA_WMODE_JUMP (2 << 0) +# define MGA_WMODE_START (3 << 0) +# define MGA_WAGP_ENABLE (1 << 2) +#define MGA_WMISC 0x1e70 +# define MGA_WUCODECACHE_ENABLE (1 << 0) +# define MGA_WMASTER_ENABLE (1 << 1) +# define MGA_WCACHEFLUSH_ENABLE (1 << 3) +#define MGA_WVRTXSZ 0x1dcc + +#define MGA_YBOT 0x1c9c +#define MGA_YDST 0x1c90 +#define MGA_YDSTLEN 0x1c88 +#define MGA_YDSTORG 0x1c94 +#define MGA_YTOP 0x1c98 + +#define MGA_ZORG 0x1c0c + +/* This finishes the current batch of commands + */ +#define MGA_EXEC 0x0100 + +/* Warp registers + */ +#define MGA_WR0 0x2d00 +#define MGA_WR1 0x2d04 +#define MGA_WR2 0x2d08 +#define MGA_WR3 0x2d0c +#define MGA_WR4 0x2d10 +#define MGA_WR5 0x2d14 +#define MGA_WR6 0x2d18 +#define MGA_WR7 0x2d1c +#define MGA_WR8 0x2d20 +#define MGA_WR9 0x2d24 +#define MGA_WR10 0x2d28 +#define MGA_WR11 0x2d2c +#define MGA_WR12 0x2d30 +#define MGA_WR13 0x2d34 +#define MGA_WR14 0x2d38 +#define MGA_WR15 0x2d3c +#define MGA_WR16 0x2d40 +#define MGA_WR17 0x2d44 +#define MGA_WR18 0x2d48 +#define MGA_WR19 0x2d4c +#define MGA_WR20 0x2d50 +#define MGA_WR21 0x2d54 +#define MGA_WR22 0x2d58 +#define MGA_WR23 0x2d5c +#define MGA_WR24 0x2d60 +#define MGA_WR25 0x2d64 +#define MGA_WR26 0x2d68 +#define MGA_WR27 0x2d6c +#define MGA_WR28 0x2d70 +#define MGA_WR29 0x2d74 +#define MGA_WR30 0x2d78 +#define MGA_WR31 0x2d7c +#define MGA_WR32 0x2d80 +#define MGA_WR33 0x2d84 +#define MGA_WR34 0x2d88 +#define MGA_WR35 0x2d8c +#define MGA_WR36 0x2d90 +#define MGA_WR37 0x2d94 +#define MGA_WR38 0x2d98 +#define MGA_WR39 0x2d9c +#define MGA_WR40 0x2da0 +#define MGA_WR41 0x2da4 +#define MGA_WR42 0x2da8 +#define MGA_WR43 0x2dac +#define MGA_WR44 0x2db0 +#define MGA_WR45 0x2db4 +#define MGA_WR46 0x2db8 +#define MGA_WR47 0x2dbc +#define MGA_WR48 0x2dc0 +#define MGA_WR49 0x2dc4 +#define MGA_WR50 0x2dc8 +#define MGA_WR51 0x2dcc +#define MGA_WR52 0x2dd0 +#define MGA_WR53 0x2dd4 +#define MGA_WR54 0x2dd8 +#define MGA_WR55 0x2ddc +#define MGA_WR56 0x2de0 +#define MGA_WR57 0x2de4 +#define MGA_WR58 0x2de8 +#define MGA_WR59 0x2dec +#define MGA_WR60 0x2df0 +#define MGA_WR61 0x2df4 +#define MGA_WR62 0x2df8 +#define MGA_WR63 0x2dfc +# define MGA_G400_WR_MAGIC (1 << 6) +# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ + + +#define MGA_ILOAD_ALIGN 64 +#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) + +#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \ + MGA_ATYPE_I | \ + MGA_ZMODE_NOZCMP | \ + MGA_ARZERO | \ + MGA_SGNZERO | \ + MGA_BOP_SRC | \ + (15 << MGA_TRANS_SHIFT)) + +#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \ + MGA_ZMODE_NOZCMP | \ + MGA_SOLID | \ + MGA_ARZERO | \ + MGA_SGNZERO | \ + MGA_SHIFTZERO | \ + MGA_BOP_SRC | \ + (0 << MGA_TRANS_SHIFT) | \ + MGA_BLTMOD_BMONOLEF | \ + MGA_TRANSC | \ + MGA_CLIPDIS) + +#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \ + MGA_ATYPE_RPL | \ + MGA_SGNZERO | \ + MGA_SHIFTZERO | \ + MGA_BOP_SRC | \ + (0 << MGA_TRANS_SHIFT) | \ + MGA_BLTMOD_BFCOL | \ + MGA_CLIPDIS) + +/* Simple idle test. + */ +static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv ) +{ + u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; + return ( status == MGA_ENDPRDMASTS ); +} + +#endif diff --git a/drivers/char/drm/mga_irq.c b/drivers/char/drm/mga_irq.c new file mode 100644 index 000000000000..bc0b6b5d43a6 --- /dev/null +++ b/drivers/char/drm/mga_irq.c @@ -0,0 +1,102 @@ +/* mga_irq.c -- IRQ handling for radeon -*- linux-c -*- + * + * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + * + * The Weather Channel (TM) funded Tungsten Graphics to develop the + * initial release of the Radeon 8500 driver under the XFree86 license. + * This notice must be preserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Keith Whitwell + * Eric Anholt + */ + +#include "drmP.h" +#include "drm.h" +#include "mga_drm.h" +#include "mga_drv.h" + +irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS ) +{ + drm_device_t *dev = (drm_device_t *) arg; + drm_mga_private_t *dev_priv = + (drm_mga_private_t *)dev->dev_private; + int status; + + status = MGA_READ( MGA_STATUS ); + + /* VBLANK interrupt */ + if ( status & MGA_VLINEPEN ) { + MGA_WRITE( MGA_ICLEAR, MGA_VLINEICLR ); + atomic_inc(&dev->vbl_received); + DRM_WAKEUP(&dev->vbl_queue); + drm_vbl_send_signals( dev ); + return IRQ_HANDLED; + } + return IRQ_NONE; +} + +int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) +{ + unsigned int cur_vblank; + int ret = 0; + + /* Assume that the user has missed the current sequence number + * by about a day rather than she wants to wait for years + * using vertical blanks... + */ + DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, + ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) + - *sequence ) <= (1<<23) ) ); + + *sequence = cur_vblank; + + return ret; +} + +void mga_driver_irq_preinstall( drm_device_t *dev ) { + drm_mga_private_t *dev_priv = + (drm_mga_private_t *)dev->dev_private; + + /* Disable *all* interrupts */ + MGA_WRITE( MGA_IEN, 0 ); + /* Clear bits if they're already high */ + MGA_WRITE( MGA_ICLEAR, ~0 ); +} + +void mga_driver_irq_postinstall( drm_device_t *dev ) { + drm_mga_private_t *dev_priv = + (drm_mga_private_t *)dev->dev_private; + + /* Turn on VBL interrupt */ + MGA_WRITE( MGA_IEN, MGA_VLINEIEN ); +} + +void mga_driver_irq_uninstall( drm_device_t *dev ) { + drm_mga_private_t *dev_priv = + (drm_mga_private_t *)dev->dev_private; + if (!dev_priv) + return; + + /* Disable *all* interrupts */ + MGA_WRITE( MGA_IEN, 0 ); +} diff --git a/drivers/char/drm/mga_state.c b/drivers/char/drm/mga_state.c new file mode 100644 index 000000000000..3c7a8f5ba501 --- /dev/null +++ b/drivers/char/drm/mga_state.c @@ -0,0 +1,1123 @@ +/* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*- + * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jeff Hartmann + * Keith Whitwell + * + * Rewritten by: + * Gareth Hughes + */ + +#include "drmP.h" +#include "drm.h" +#include "mga_drm.h" +#include "mga_drv.h" + +/* ================================================================ + * DMA hardware state programming functions + */ + +static void mga_emit_clip_rect( drm_mga_private_t *dev_priv, + drm_clip_rect_t *box ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + unsigned int pitch = dev_priv->front_pitch; + DMA_LOCALS; + + BEGIN_DMA( 2 ); + + /* Force reset of DWGCTL on G400 (eliminates clip disable bit). + */ + if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { + DMA_BLOCK( MGA_DWGCTL, ctx->dwgctl, + MGA_LEN + MGA_EXEC, 0x80000000, + MGA_DWGCTL, ctx->dwgctl, + MGA_LEN + MGA_EXEC, 0x80000000 ); + } + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_CXBNDRY, (box->x2 << 16) | box->x1, + MGA_YTOP, box->y1 * pitch, + MGA_YBOT, box->y2 * pitch ); + + ADVANCE_DMA(); +} + +static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + DMA_LOCALS; + + BEGIN_DMA( 3 ); + + DMA_BLOCK( MGA_DSTORG, ctx->dstorg, + MGA_MACCESS, ctx->maccess, + MGA_PLNWT, ctx->plnwt, + MGA_DWGCTL, ctx->dwgctl ); + + DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, + MGA_FOGCOL, ctx->fogcolor, + MGA_WFLAG, ctx->wflag, + MGA_ZORG, dev_priv->depth_offset ); + + DMA_BLOCK( MGA_FCOL, ctx->fcol, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); + + ADVANCE_DMA(); +} + +static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + DMA_LOCALS; + + BEGIN_DMA( 4 ); + + DMA_BLOCK( MGA_DSTORG, ctx->dstorg, + MGA_MACCESS, ctx->maccess, + MGA_PLNWT, ctx->plnwt, + MGA_DWGCTL, ctx->dwgctl ); + + DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, + MGA_FOGCOL, ctx->fogcolor, + MGA_WFLAG, ctx->wflag, + MGA_ZORG, dev_priv->depth_offset ); + + DMA_BLOCK( MGA_WFLAG1, ctx->wflag, + MGA_TDUALSTAGE0, ctx->tdualstage0, + MGA_TDUALSTAGE1, ctx->tdualstage1, + MGA_FCOL, ctx->fcol ); + + DMA_BLOCK( MGA_STENCIL, ctx->stencil, + MGA_STENCILCTL, ctx->stencilctl, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); + + ADVANCE_DMA(); +} + +static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; + DMA_LOCALS; + + BEGIN_DMA( 4 ); + + DMA_BLOCK( MGA_TEXCTL2, tex->texctl2, + MGA_TEXCTL, tex->texctl, + MGA_TEXFILTER, tex->texfilter, + MGA_TEXBORDERCOL, tex->texbordercol ); + + DMA_BLOCK( MGA_TEXORG, tex->texorg, + MGA_TEXORG1, tex->texorg1, + MGA_TEXORG2, tex->texorg2, + MGA_TEXORG3, tex->texorg3 ); + + DMA_BLOCK( MGA_TEXORG4, tex->texorg4, + MGA_TEXWIDTH, tex->texwidth, + MGA_TEXHEIGHT, tex->texheight, + MGA_WR24, tex->texwidth ); + + DMA_BLOCK( MGA_WR34, tex->texheight, + MGA_TEXTRANS, 0x0000ffff, + MGA_TEXTRANSHIGH, 0x0000ffff, + MGA_DMAPAD, 0x00000000 ); + + ADVANCE_DMA(); +} + +static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; + DMA_LOCALS; + +/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */ +/* tex->texctl, tex->texctl2); */ + + BEGIN_DMA( 6 ); + + DMA_BLOCK( MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC, + MGA_TEXCTL, tex->texctl, + MGA_TEXFILTER, tex->texfilter, + MGA_TEXBORDERCOL, tex->texbordercol ); + + DMA_BLOCK( MGA_TEXORG, tex->texorg, + MGA_TEXORG1, tex->texorg1, + MGA_TEXORG2, tex->texorg2, + MGA_TEXORG3, tex->texorg3 ); + + DMA_BLOCK( MGA_TEXORG4, tex->texorg4, + MGA_TEXWIDTH, tex->texwidth, + MGA_TEXHEIGHT, tex->texheight, + MGA_WR49, 0x00000000 ); + + DMA_BLOCK( MGA_WR57, 0x00000000, + MGA_WR53, 0x00000000, + MGA_WR61, 0x00000000, + MGA_WR52, MGA_G400_WR_MAGIC ); + + DMA_BLOCK( MGA_WR60, MGA_G400_WR_MAGIC, + MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC, + MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC, + MGA_DMAPAD, 0x00000000 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_TEXTRANS, 0x0000ffff, + MGA_TEXTRANSHIGH, 0x0000ffff ); + + ADVANCE_DMA(); +} + +static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1]; + DMA_LOCALS; + +/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */ +/* tex->texctl, tex->texctl2); */ + + BEGIN_DMA( 5 ); + + DMA_BLOCK( MGA_TEXCTL2, (tex->texctl2 | + MGA_MAP1_ENABLE | + MGA_G400_TC2_MAGIC), + MGA_TEXCTL, tex->texctl, + MGA_TEXFILTER, tex->texfilter, + MGA_TEXBORDERCOL, tex->texbordercol ); + + DMA_BLOCK( MGA_TEXORG, tex->texorg, + MGA_TEXORG1, tex->texorg1, + MGA_TEXORG2, tex->texorg2, + MGA_TEXORG3, tex->texorg3 ); + + DMA_BLOCK( MGA_TEXORG4, tex->texorg4, + MGA_TEXWIDTH, tex->texwidth, + MGA_TEXHEIGHT, tex->texheight, + MGA_WR49, 0x00000000 ); + + DMA_BLOCK( MGA_WR57, 0x00000000, + MGA_WR53, 0x00000000, + MGA_WR61, 0x00000000, + MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC ); + + DMA_BLOCK( MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC, + MGA_TEXTRANS, 0x0000ffff, + MGA_TEXTRANSHIGH, 0x0000ffff, + MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC ); + + ADVANCE_DMA(); +} + +static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int pipe = sarea_priv->warp_pipe; + DMA_LOCALS; + + BEGIN_DMA( 3 ); + + DMA_BLOCK( MGA_WIADDR, MGA_WMODE_SUSPEND, + MGA_WVRTXSZ, 0x00000007, + MGA_WFLAG, 0x00000000, + MGA_WR24, 0x00000000 ); + + DMA_BLOCK( MGA_WR25, 0x00000100, + MGA_WR34, 0x00000000, + MGA_WR42, 0x0000ffff, + MGA_WR60, 0x0000ffff ); + + /* Padding required to to hardware bug. + */ + DMA_BLOCK( MGA_DMAPAD, 0xffffffff, + MGA_DMAPAD, 0xffffffff, + MGA_DMAPAD, 0xffffffff, + MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] | + MGA_WMODE_START | + MGA_WAGP_ENABLE) ); + + ADVANCE_DMA(); +} + +static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int pipe = sarea_priv->warp_pipe; + DMA_LOCALS; + +/* printk("mga_g400_emit_pipe %x\n", pipe); */ + + BEGIN_DMA( 10 ); + + DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); + + if ( pipe & MGA_T2 ) { + DMA_BLOCK( MGA_WVRTXSZ, 0x00001e09, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); + + DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x1e000000 ); + } else { + if ( dev_priv->warp_pipe & MGA_T2 ) { + /* Flush the WARP pipe */ + DMA_BLOCK( MGA_YDST, 0x00000000, + MGA_FXLEFT, 0x00000000, + MGA_FXRIGHT, 0x00000001, + MGA_DWGCTL, MGA_DWGCTL_FLUSH ); + + DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001, + MGA_DWGSYNC, 0x00007000, + MGA_TEXCTL2, MGA_G400_TC2_MAGIC, + MGA_LEN + MGA_EXEC, 0x00000000 ); + + DMA_BLOCK( MGA_TEXCTL2, (MGA_DUALTEX | + MGA_G400_TC2_MAGIC), + MGA_LEN + MGA_EXEC, 0x00000000, + MGA_TEXCTL2, MGA_G400_TC2_MAGIC, + MGA_DMAPAD, 0x00000000 ); + } + + DMA_BLOCK( MGA_WVRTXSZ, 0x00001807, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); + + DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x18000000 ); + } + + DMA_BLOCK( MGA_WFLAG, 0x00000000, + MGA_WFLAG1, 0x00000000, + MGA_WR56, MGA_G400_WR56_MAGIC, + MGA_DMAPAD, 0x00000000 ); + + DMA_BLOCK( MGA_WR49, 0x00000000, /* tex0 */ + MGA_WR57, 0x00000000, /* tex0 */ + MGA_WR53, 0x00000000, /* tex1 */ + MGA_WR61, 0x00000000 ); /* tex1 */ + + DMA_BLOCK( MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */ + MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */ + MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */ + MGA_WR60, MGA_G400_WR_MAGIC ); /* tex1 height */ + + /* Padding required to to hardware bug */ + DMA_BLOCK( MGA_DMAPAD, 0xffffffff, + MGA_DMAPAD, 0xffffffff, + MGA_DMAPAD, 0xffffffff, + MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] | + MGA_WMODE_START | + MGA_WAGP_ENABLE) ); + + ADVANCE_DMA(); +} + +static void mga_g200_emit_state( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int dirty = sarea_priv->dirty; + + if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { + mga_g200_emit_pipe( dev_priv ); + dev_priv->warp_pipe = sarea_priv->warp_pipe; + } + + if ( dirty & MGA_UPLOAD_CONTEXT ) { + mga_g200_emit_context( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; + } + + if ( dirty & MGA_UPLOAD_TEX0 ) { + mga_g200_emit_tex0( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; + } +} + +static void mga_g400_emit_state( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int dirty = sarea_priv->dirty; + int multitex = sarea_priv->warp_pipe & MGA_T2; + + if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { + mga_g400_emit_pipe( dev_priv ); + dev_priv->warp_pipe = sarea_priv->warp_pipe; + } + + if ( dirty & MGA_UPLOAD_CONTEXT ) { + mga_g400_emit_context( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; + } + + if ( dirty & MGA_UPLOAD_TEX0 ) { + mga_g400_emit_tex0( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; + } + + if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) { + mga_g400_emit_tex1( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_TEX1; + } +} + + +/* ================================================================ + * SAREA state verification + */ + +/* Disallow all write destinations except the front and backbuffer. + */ +static int mga_verify_context( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + + if ( ctx->dstorg != dev_priv->front_offset && + ctx->dstorg != dev_priv->back_offset ) { + DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n", + ctx->dstorg, dev_priv->front_offset, + dev_priv->back_offset ); + ctx->dstorg = 0; + return DRM_ERR(EINVAL); + } + + return 0; +} + +/* Disallow texture reads from PCI space. + */ +static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit]; + unsigned int org; + + org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK); + + if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) { + DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n", + tex->texorg, unit ); + tex->texorg = 0; + return DRM_ERR(EINVAL); + } + + return 0; +} + +static int mga_verify_state( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int dirty = sarea_priv->dirty; + int ret = 0; + + if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; + + if ( dirty & MGA_UPLOAD_CONTEXT ) + ret |= mga_verify_context( dev_priv ); + + if ( dirty & MGA_UPLOAD_TEX0 ) + ret |= mga_verify_tex( dev_priv, 0 ); + + if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { + if ( dirty & MGA_UPLOAD_TEX1 ) + ret |= mga_verify_tex( dev_priv, 1 ); + + if ( dirty & MGA_UPLOAD_PIPE ) + ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES ); + } else { + if ( dirty & MGA_UPLOAD_PIPE ) + ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES ); + } + + return ( ret == 0 ); +} + +static int mga_verify_iload( drm_mga_private_t *dev_priv, + unsigned int dstorg, unsigned int length ) +{ + if ( dstorg < dev_priv->texture_offset || + dstorg + length > (dev_priv->texture_offset + + dev_priv->texture_size) ) { + DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg ); + return DRM_ERR(EINVAL); + } + + if ( length & MGA_ILOAD_MASK ) { + DRM_ERROR( "*** bad iload length: 0x%x\n", + length & MGA_ILOAD_MASK ); + return DRM_ERR(EINVAL); + } + + return 0; +} + +static int mga_verify_blit( drm_mga_private_t *dev_priv, + unsigned int srcorg, unsigned int dstorg ) +{ + if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) || + (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) { + DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n", + srcorg, dstorg ); + return DRM_ERR(EINVAL); + } + return 0; +} + + +/* ================================================================ + * + */ + +static void mga_dma_dispatch_clear( drm_device_t *dev, + drm_mga_clear_t *clear ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int nbox = sarea_priv->nbox; + int i; + DMA_LOCALS; + DRM_DEBUG( "\n" ); + + BEGIN_DMA( 1 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, + MGA_DWGSYNC, 0x00007000 ); + + ADVANCE_DMA(); + + for ( i = 0 ; i < nbox ; i++ ) { + drm_clip_rect_t *box = &pbox[i]; + u32 height = box->y2 - box->y1; + + DRM_DEBUG( " from=%d,%d to=%d,%d\n", + box->x1, box->y1, box->x2, box->y2 ); + + if ( clear->flags & MGA_FRONT ) { + BEGIN_DMA( 2 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_PLNWT, clear->color_mask, + MGA_YDSTLEN, (box->y1 << 16) | height, + MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_FCOL, clear->clear_color, + MGA_DSTORG, dev_priv->front_offset, + MGA_DWGCTL + MGA_EXEC, + dev_priv->clear_cmd ); + + ADVANCE_DMA(); + } + + + if ( clear->flags & MGA_BACK ) { + BEGIN_DMA( 2 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_PLNWT, clear->color_mask, + MGA_YDSTLEN, (box->y1 << 16) | height, + MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_FCOL, clear->clear_color, + MGA_DSTORG, dev_priv->back_offset, + MGA_DWGCTL + MGA_EXEC, + dev_priv->clear_cmd ); + + ADVANCE_DMA(); + } + + if ( clear->flags & MGA_DEPTH ) { + BEGIN_DMA( 2 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_PLNWT, clear->depth_mask, + MGA_YDSTLEN, (box->y1 << 16) | height, + MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_FCOL, clear->clear_depth, + MGA_DSTORG, dev_priv->depth_offset, + MGA_DWGCTL + MGA_EXEC, + dev_priv->clear_cmd ); + + ADVANCE_DMA(); + } + + } + + BEGIN_DMA( 1 ); + + /* Force reset of DWGCTL */ + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_PLNWT, ctx->plnwt, + MGA_DWGCTL, ctx->dwgctl ); + + ADVANCE_DMA(); + + FLUSH_DMA(); +} + +static void mga_dma_dispatch_swap( drm_device_t *dev ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int nbox = sarea_priv->nbox; + int i; + DMA_LOCALS; + DRM_DEBUG( "\n" ); + + sarea_priv->last_frame.head = dev_priv->prim.tail; + sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap; + + BEGIN_DMA( 4 + nbox ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, + MGA_DWGSYNC, 0x00007000 ); + + DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset, + MGA_MACCESS, dev_priv->maccess, + MGA_SRCORG, dev_priv->back_offset, + MGA_AR5, dev_priv->front_pitch ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_PLNWT, 0xffffffff, + MGA_DWGCTL, MGA_DWGCTL_COPY ); + + for ( i = 0 ; i < nbox ; i++ ) { + drm_clip_rect_t *box = &pbox[i]; + u32 height = box->y2 - box->y1; + u32 start = box->y1 * dev_priv->front_pitch; + + DRM_DEBUG( " from=%d,%d to=%d,%d\n", + box->x1, box->y1, box->x2, box->y2 ); + + DMA_BLOCK( MGA_AR0, start + box->x2 - 1, + MGA_AR3, start + box->x1, + MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1, + MGA_YDSTLEN + MGA_EXEC, + (box->y1 << 16) | height ); + } + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_PLNWT, ctx->plnwt, + MGA_SRCORG, dev_priv->front_offset, + MGA_DWGCTL, ctx->dwgctl ); + + ADVANCE_DMA(); + + FLUSH_DMA(); + + DRM_DEBUG( "%s... done.\n", __FUNCTION__ ); +} + +static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + u32 address = (u32) buf->bus_address; + u32 length = (u32) buf->used; + int i = 0; + DMA_LOCALS; + DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used ); + + if ( buf->used ) { + buf_priv->dispatched = 1; + + MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); + + do { + if ( i < sarea_priv->nbox ) { + mga_emit_clip_rect( dev_priv, + &sarea_priv->boxes[i] ); + } + + BEGIN_DMA( 1 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_SECADDRESS, (address | + MGA_DMA_VERTEX), + MGA_SECEND, ((address + length) | + MGA_PAGPXFER) ); + + ADVANCE_DMA(); + } while ( ++i < sarea_priv->nbox ); + } + + if ( buf_priv->discard ) { + AGE_BUFFER( buf_priv ); + buf->pending = 0; + buf->used = 0; + buf_priv->dispatched = 0; + + mga_freelist_put( dev, buf ); + } + + FLUSH_DMA(); +} + +static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, + unsigned int start, unsigned int end ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + u32 address = (u32) buf->bus_address; + int i = 0; + DMA_LOCALS; + DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end ); + + if ( start != end ) { + buf_priv->dispatched = 1; + + MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); + + do { + if ( i < sarea_priv->nbox ) { + mga_emit_clip_rect( dev_priv, + &sarea_priv->boxes[i] ); + } + + BEGIN_DMA( 1 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_SETUPADDRESS, address + start, + MGA_SETUPEND, ((address + end) | + MGA_PAGPXFER) ); + + ADVANCE_DMA(); + } while ( ++i < sarea_priv->nbox ); + } + + if ( buf_priv->discard ) { + AGE_BUFFER( buf_priv ); + buf->pending = 0; + buf->used = 0; + buf_priv->dispatched = 0; + + mga_freelist_put( dev, buf ); + } + + FLUSH_DMA(); +} + +/* This copies a 64 byte aligned agp region to the frambuffer with a + * standard blit, the ioctl needs to do checking. + */ +static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf, + unsigned int dstorg, unsigned int length ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state; + u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM; + u32 y2; + DMA_LOCALS; + DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used ); + + y2 = length / 64; + + BEGIN_DMA( 5 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, + MGA_DWGSYNC, 0x00007000 ); + + DMA_BLOCK( MGA_DSTORG, dstorg, + MGA_MACCESS, 0x00000000, + MGA_SRCORG, srcorg, + MGA_AR5, 64 ); + + DMA_BLOCK( MGA_PITCH, 64, + MGA_PLNWT, 0xffffffff, + MGA_DMAPAD, 0x00000000, + MGA_DWGCTL, MGA_DWGCTL_COPY ); + + DMA_BLOCK( MGA_AR0, 63, + MGA_AR3, 0, + MGA_FXBNDRY, (63 << 16) | 0, + MGA_YDSTLEN + MGA_EXEC, y2 ); + + DMA_BLOCK( MGA_PLNWT, ctx->plnwt, + MGA_SRCORG, dev_priv->front_offset, + MGA_PITCH, dev_priv->front_pitch, + MGA_DWGSYNC, 0x00007000 ); + + ADVANCE_DMA(); + + AGE_BUFFER( buf_priv ); + + buf->pending = 0; + buf->used = 0; + buf_priv->dispatched = 0; + + mga_freelist_put( dev, buf ); + + FLUSH_DMA(); +} + +static void mga_dma_dispatch_blit( drm_device_t *dev, + drm_mga_blit_t *blit ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int nbox = sarea_priv->nbox; + u32 scandir = 0, i; + DMA_LOCALS; + DRM_DEBUG( "\n" ); + + BEGIN_DMA( 4 + nbox ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, + MGA_DWGSYNC, 0x00007000 ); + + DMA_BLOCK( MGA_DWGCTL, MGA_DWGCTL_COPY, + MGA_PLNWT, blit->planemask, + MGA_SRCORG, blit->srcorg, + MGA_DSTORG, blit->dstorg ); + + DMA_BLOCK( MGA_SGN, scandir, + MGA_MACCESS, dev_priv->maccess, + MGA_AR5, blit->ydir * blit->src_pitch, + MGA_PITCH, blit->dst_pitch ); + + for ( i = 0 ; i < nbox ; i++ ) { + int srcx = pbox[i].x1 + blit->delta_sx; + int srcy = pbox[i].y1 + blit->delta_sy; + int dstx = pbox[i].x1 + blit->delta_dx; + int dsty = pbox[i].y1 + blit->delta_dy; + int h = pbox[i].y2 - pbox[i].y1; + int w = pbox[i].x2 - pbox[i].x1 - 1; + int start; + + if ( blit->ydir == -1 ) { + srcy = blit->height - srcy - 1; + } + + start = srcy * blit->src_pitch + srcx; + + DMA_BLOCK( MGA_AR0, start + w, + MGA_AR3, start, + MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff), + MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h ); + } + + /* Do something to flush AGP? + */ + + /* Force reset of DWGCTL */ + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_PLNWT, ctx->plnwt, + MGA_PITCH, dev_priv->front_pitch, + MGA_DWGCTL, ctx->dwgctl ); + + ADVANCE_DMA(); +} + + +/* ================================================================ + * + */ + +static int mga_dma_clear( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_clear_t clear; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t __user *)data, sizeof(clear) ); + + if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; + + WRAP_TEST_WITH_RETURN( dev_priv ); + + mga_dma_dispatch_clear( dev, &clear ); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; + + return 0; +} + +static int mga_dma_swap( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; + + WRAP_TEST_WITH_RETURN( dev_priv ); + + mga_dma_dispatch_swap( dev ); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; + + return 0; +} + +static int mga_dma_vertex( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_mga_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_mga_vertex_t vertex; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( vertex, + (drm_mga_vertex_t __user *)data, + sizeof(vertex) ); + + if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL); + buf = dma->buflist[vertex.idx]; + buf_priv = buf->dev_private; + + buf->used = vertex.used; + buf_priv->discard = vertex.discard; + + if ( !mga_verify_state( dev_priv ) ) { + if ( vertex.discard ) { + if ( buf_priv->dispatched == 1 ) + AGE_BUFFER( buf_priv ); + buf_priv->dispatched = 0; + mga_freelist_put( dev, buf ); + } + return DRM_ERR(EINVAL); + } + + WRAP_TEST_WITH_RETURN( dev_priv ); + + mga_dma_dispatch_vertex( dev, buf ); + + return 0; +} + +static int mga_dma_indices( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_mga_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_mga_indices_t indices; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( indices, + (drm_mga_indices_t __user *)data, + sizeof(indices) ); + + if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL); + + buf = dma->buflist[indices.idx]; + buf_priv = buf->dev_private; + + buf_priv->discard = indices.discard; + + if ( !mga_verify_state( dev_priv ) ) { + if ( indices.discard ) { + if ( buf_priv->dispatched == 1 ) + AGE_BUFFER( buf_priv ); + buf_priv->dispatched = 0; + mga_freelist_put( dev, buf ); + } + return DRM_ERR(EINVAL); + } + + WRAP_TEST_WITH_RETURN( dev_priv ); + + mga_dma_dispatch_indices( dev, buf, indices.start, indices.end ); + + return 0; +} + +static int mga_dma_iload( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_device_dma_t *dma = dev->dma; + drm_mga_private_t *dev_priv = dev->dev_private; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_mga_iload_t iload; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t __user *)data, sizeof(iload) ); + +#if 0 + if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { + if ( MGA_DMA_DEBUG ) + DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); + return DRM_ERR(EBUSY); + } +#endif + if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL); + + buf = dma->buflist[iload.idx]; + buf_priv = buf->dev_private; + + if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) { + mga_freelist_put( dev, buf ); + return DRM_ERR(EINVAL); + } + + WRAP_TEST_WITH_RETURN( dev_priv ); + + mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length ); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; + + return 0; +} + +static int mga_dma_blit( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_blit_t blit; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t __user *)data, sizeof(blit) ); + + if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; + + if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) ) + return DRM_ERR(EINVAL); + + WRAP_TEST_WITH_RETURN( dev_priv ); + + mga_dma_dispatch_blit( dev, &blit ); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; + + return 0; +} + +static int mga_getparam( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_getparam_t param; + int value; + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t __user *)data, + sizeof(param) ); + + DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); + + switch( param.param ) { + case MGA_PARAM_IRQ_NR: + value = dev->irq; + break; + default: + return DRM_ERR(EINVAL); + } + + if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { + DRM_ERROR( "copy_to_user\n" ); + return DRM_ERR(EFAULT); + } + + return 0; +} + +drm_ioctl_desc_t mga_ioctls[] = { + [DRM_IOCTL_NR(DRM_MGA_INIT)] = { mga_dma_init, 1, 1 }, + [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = { mga_dma_flush, 1, 0 }, + [DRM_IOCTL_NR(DRM_MGA_RESET)] = { mga_dma_reset, 1, 0 }, + [DRM_IOCTL_NR(DRM_MGA_SWAP)] = { mga_dma_swap, 1, 0 }, + [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = { mga_dma_clear, 1, 0 }, + [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = { mga_dma_vertex, 1, 0 }, + [DRM_IOCTL_NR(DRM_MGA_INDICES)] = { mga_dma_indices, 1, 0 }, + [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = { mga_dma_iload, 1, 0 }, + [DRM_IOCTL_NR(DRM_MGA_BLIT)] = { mga_dma_blit, 1, 0 }, + [DRM_IOCTL_NR(DRM_MGA_GETPARAM)]= { mga_getparam, 1, 0 }, +}; + +int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls); diff --git a/drivers/char/drm/mga_ucode.h b/drivers/char/drm/mga_ucode.h new file mode 100644 index 000000000000..fa0f82ec9fa0 --- /dev/null +++ b/drivers/char/drm/mga_ucode.h @@ -0,0 +1,11645 @@ +/* mga_ucode.h -- Matrox G200/G400 WARP engine microcode -*- linux-c -*- + * Created: Thu Jan 11 21:20:43 2001 by gareth@valinux.com + * + * Copyright 1999 Matrox Graphics Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Kernel-based WARP engine management: + * Gareth Hughes + */ + +/* + * WARP pipes are named according to the functions they perform, where: + * + * - T stands for computation of texture stage 0 + * - T2 stands for computation of both texture stage 0 and texture stage 1 + * - G stands for computation of triangle intensity (Gouraud interpolation) + * - Z stands for computation of Z buffer interpolation + * - S stands for computation of specular highlight + * - A stands for computation of the alpha channel + * - F stands for computation of vertex fog interpolation + */ + +static unsigned char warp_g200_tgz[] = { + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x98, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x81, 0x04, +0x89, 0x04, +0x01, 0x04, +0x09, 0x04, + +0xC9, 0x41, 0xC0, 0xEC, +0x11, 0x04, +0x00, 0xE0, + +0x41, 0xCC, 0x41, 0xCD, +0x49, 0xCC, 0x49, 0xCD, + +0xD1, 0x41, 0xC0, 0xEC, +0x51, 0xCC, 0x51, 0xCD, + +0x80, 0x04, +0x10, 0x04, +0x08, 0x04, +0x00, 0xE0, + +0x00, 0xCC, 0xC0, 0xCD, +0xD1, 0x49, 0xC0, 0xEC, + +0x8A, 0x1F, 0x20, 0xE9, +0x8B, 0x3F, 0x20, 0xE9, + +0x41, 0x3C, 0x41, 0xAD, +0x49, 0x3C, 0x49, 0xAD, + +0x10, 0xCC, 0x10, 0xCD, +0x08, 0xCC, 0x08, 0xCD, + +0xB9, 0x41, 0x49, 0xBB, +0x1F, 0xF0, 0x41, 0xCD, + +0x51, 0x3C, 0x51, 0xAD, +0x00, 0x98, 0x80, 0xE9, + +0x72, 0x80, 0x07, 0xEA, +0x24, 0x1F, 0x20, 0xE9, + +0x15, 0x41, 0x49, 0xBD, +0x1D, 0x41, 0x51, 0xBD, + +0x2E, 0x41, 0x2A, 0xB8, +0x34, 0x53, 0xA0, 0xE8, + +0x15, 0x30, +0x1D, 0x30, +0x58, 0xE3, +0x00, 0xE0, + +0xB5, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x24, 0x43, 0xA0, 0xE8, +0x2C, 0x4B, 0xA0, 0xE8, + +0x15, 0x72, +0x09, 0xE3, +0x00, 0xE0, +0x1D, 0x72, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0x97, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x6C, 0x64, 0xC8, 0xEC, +0x98, 0xE1, +0xB5, 0x05, + +0xBD, 0x05, +0x2E, 0x30, +0x32, 0xC0, 0xA0, 0xE8, + +0x33, 0xC0, 0xA0, 0xE8, +0x74, 0x64, 0xC8, 0xEC, + +0x40, 0x3C, 0x40, 0xAD, +0x32, 0x6A, +0x2A, 0x30, + +0x20, 0x73, +0x33, 0x6A, +0x00, 0xE0, +0x28, 0x73, + +0x1C, 0x72, +0x83, 0xE2, +0x60, 0x80, 0x15, 0xEA, + +0xB8, 0x3D, 0x28, 0xDF, +0x30, 0x35, 0x20, 0xDF, + +0x40, 0x30, +0x00, 0xE0, +0xCC, 0xE2, +0x64, 0x72, + +0x25, 0x42, 0x52, 0xBF, +0x2D, 0x42, 0x4A, 0xBF, + +0x30, 0x2E, 0x30, 0xDF, +0x38, 0x2E, 0x38, 0xDF, + +0x18, 0x1D, 0x45, 0xE9, +0x1E, 0x15, 0x45, 0xE9, + +0x2B, 0x49, 0x51, 0xBD, +0x00, 0xE0, +0x1F, 0x73, + +0x38, 0x38, 0x40, 0xAF, +0x30, 0x30, 0x40, 0xAF, + +0x24, 0x1F, 0x24, 0xDF, +0x1D, 0x32, 0x20, 0xE9, + +0x2C, 0x1F, 0x2C, 0xDF, +0x1A, 0x33, 0x20, 0xE9, + +0xB0, 0x10, +0x08, 0xE3, +0x40, 0x10, +0xB8, 0x10, + +0x26, 0xF0, 0x30, 0xCD, +0x2F, 0xF0, 0x38, 0xCD, + +0x2B, 0x80, 0x20, 0xE9, +0x2A, 0x80, 0x20, 0xE9, + +0xA6, 0x20, +0x88, 0xE2, +0x00, 0xE0, +0xAF, 0x20, + +0x28, 0x2A, 0x26, 0xAF, +0x20, 0x2A, 0xC0, 0xAF, + +0x34, 0x1F, 0x34, 0xDF, +0x46, 0x24, 0x46, 0xDF, + +0x28, 0x30, 0x80, 0xBF, +0x20, 0x38, 0x80, 0xBF, + +0x47, 0x24, 0x47, 0xDF, +0x4E, 0x2C, 0x4E, 0xDF, + +0x4F, 0x2C, 0x4F, 0xDF, +0x56, 0x34, 0x56, 0xDF, + +0x28, 0x15, 0x28, 0xDF, +0x20, 0x1D, 0x20, 0xDF, + +0x57, 0x34, 0x57, 0xDF, +0x00, 0xE0, +0x1D, 0x05, + +0x04, 0x80, 0x10, 0xEA, +0x89, 0xE2, +0x2B, 0x30, + +0x3F, 0xC1, 0x1D, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA0, 0x68, +0xBF, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x20, 0xC0, 0x20, 0xAF, +0x28, 0x05, +0x97, 0x74, + +0x00, 0xE0, +0x2A, 0x10, +0x16, 0xC0, 0x20, 0xE9, + +0x04, 0x80, 0x10, 0xEA, +0x8C, 0xE2, +0x95, 0x05, + +0x28, 0xC1, 0x28, 0xAD, +0x1F, 0xC1, 0x15, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA8, 0x67, +0x9F, 0x6B, +0x00, 0x80, 0x00, 0xE8, + +0x28, 0xC0, 0x28, 0xAD, +0x1D, 0x25, +0x20, 0x05, + +0x28, 0x32, 0x80, 0xAD, +0x40, 0x2A, 0x40, 0xBD, + +0x1C, 0x80, 0x20, 0xE9, +0x20, 0x33, 0x20, 0xAD, + +0x20, 0x73, +0x00, 0xE0, +0xB6, 0x49, 0x51, 0xBB, + +0x26, 0x2F, 0xB0, 0xE8, +0x19, 0x20, 0x20, 0xE9, + +0x35, 0x20, 0x35, 0xDF, +0x3D, 0x20, 0x3D, 0xDF, + +0x15, 0x20, 0x15, 0xDF, +0x1D, 0x20, 0x1D, 0xDF, + +0x26, 0xD0, 0x26, 0xCD, +0x29, 0x49, 0x2A, 0xB8, + +0x26, 0x40, 0x80, 0xBD, +0x3B, 0x48, 0x50, 0xBD, + +0x3E, 0x54, 0x57, 0x9F, +0x00, 0xE0, +0x82, 0xE1, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x26, 0x30, +0x29, 0x30, +0x48, 0x3C, 0x48, 0xAD, + +0x2B, 0x72, +0xC2, 0xE1, +0x2C, 0xC0, 0x44, 0xC2, + +0x05, 0x24, 0x34, 0xBF, +0x0D, 0x24, 0x2C, 0xBF, + +0x2D, 0x46, 0x4E, 0xBF, +0x25, 0x46, 0x56, 0xBF, + +0x20, 0x1D, 0x6F, 0x8F, +0x32, 0x3E, 0x5F, 0xE9, + +0x3E, 0x50, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x30, + +0x1E, 0x8F, 0x51, 0x9F, +0x33, 0x1E, 0x5F, 0xE9, + +0x05, 0x44, 0x54, 0xB2, +0x0D, 0x44, 0x4C, 0xB2, + +0x19, 0xC0, 0xB0, 0xE8, +0x34, 0xC0, 0x44, 0xC4, + +0x33, 0x73, +0x00, 0xE0, +0x3E, 0x62, 0x57, 0x9F, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0xE0, +0x0D, 0x20, + +0x84, 0x3E, 0x58, 0xE9, +0x28, 0x1D, 0x6F, 0x8F, + +0x05, 0x20, +0x00, 0xE0, +0x85, 0x1E, 0x58, 0xE9, + +0x9B, 0x3B, 0x33, 0xDF, +0x20, 0x20, 0x42, 0xAF, + +0x30, 0x42, 0x56, 0x9F, +0x80, 0x3E, 0x57, 0xE9, + +0x3F, 0x8F, 0x51, 0x9F, +0x30, 0x80, 0x5F, 0xE9, + +0x28, 0x28, 0x24, 0xAF, +0x81, 0x1E, 0x57, 0xE9, + +0x05, 0x47, 0x57, 0xBF, +0x0D, 0x47, 0x4F, 0xBF, + +0x88, 0x80, 0x58, 0xE9, +0x1B, 0x29, 0x1B, 0xDF, + +0x30, 0x1D, 0x6F, 0x8F, +0x3A, 0x30, 0x4F, 0xE9, + +0x1C, 0x30, 0x26, 0xDF, +0x09, 0xE3, +0x3B, 0x05, + +0x3E, 0x50, 0x56, 0x9F, +0x3B, 0x3F, 0x4F, 0xE9, + +0x1E, 0x8F, 0x51, 0x9F, +0x00, 0xE0, +0xAC, 0x20, + +0x2D, 0x44, 0x4C, 0xB4, +0x2C, 0x1C, 0xC0, 0xAF, + +0x25, 0x44, 0x54, 0xB4, +0x00, 0xE0, +0xC8, 0x30, + +0x30, 0x46, 0x30, 0xAF, +0x1B, 0x1B, 0x48, 0xAF, + +0x00, 0xE0, +0x25, 0x20, +0x38, 0x2C, 0x4F, 0xE9, + +0x86, 0x80, 0x57, 0xE9, +0x38, 0x1D, 0x6F, 0x8F, + +0x28, 0x74, +0x00, 0xE0, +0x0D, 0x44, 0x4C, 0xB0, + +0x05, 0x44, 0x54, 0xB0, +0x2D, 0x20, +0x9B, 0x10, + +0x82, 0x3E, 0x57, 0xE9, +0x32, 0xF0, 0x1B, 0xCD, + +0x1E, 0xBD, 0x59, 0x9F, +0x83, 0x1E, 0x57, 0xE9, + +0x38, 0x47, 0x38, 0xAF, +0x34, 0x20, +0x2A, 0x30, + +0x00, 0xE0, +0x0D, 0x20, +0x32, 0x20, +0x05, 0x20, + +0x87, 0x80, 0x57, 0xE9, +0x1F, 0x54, 0x57, 0x9F, + +0x17, 0x42, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x6A, + +0x3F, 0x8F, 0x51, 0x9F, +0x37, 0x1E, 0x4F, 0xE9, + +0x37, 0x32, 0x2A, 0xAF, +0x00, 0xE0, +0x32, 0x00, + +0x00, 0x80, 0x00, 0xE8, +0x27, 0xC0, 0x44, 0xC0, + +0x36, 0x1F, 0x4F, 0xE9, +0x1F, 0x1F, 0x26, 0xDF, + +0x37, 0x1B, 0x37, 0xBF, +0x17, 0x26, 0x17, 0xDF, + +0x3E, 0x17, 0x4F, 0xE9, +0x3F, 0x3F, 0x4F, 0xE9, + +0x34, 0x1F, 0x34, 0xAF, +0x2B, 0x05, +0xA7, 0x20, + +0x33, 0x2B, 0x37, 0xDF, +0x27, 0x17, 0xC0, 0xAF, + +0x34, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x03, 0x80, 0x0A, 0xEA, +0x17, 0xC1, 0x2B, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xB3, 0x68, +0x97, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x33, 0xC0, 0x33, 0xAF, +0x3C, 0x27, 0x4F, 0xE9, + +0x57, 0x39, 0x20, 0xE9, +0x28, 0x19, 0x60, 0xEC, + +0x2B, 0x32, 0x20, 0xE9, +0x1D, 0x3B, 0x20, 0xE9, + +0xB3, 0x05, +0x00, 0xE0, +0x16, 0x28, 0x20, 0xE9, + +0x23, 0x3B, 0x33, 0xAD, +0x1E, 0x2B, 0x20, 0xE9, + +0x1C, 0x80, 0x20, 0xE9, +0x57, 0x36, 0x20, 0xE9, + +0x00, 0x80, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x90, 0xE2, +0x00, 0xE0, + +0x85, 0xFF, 0x20, 0xEA, +0x19, 0xC8, 0xC1, 0xCD, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x9F, 0x41, 0x49, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x25, 0x41, 0x49, 0xBD, +0x2D, 0x41, 0x51, 0xBD, + +0x0D, 0x80, 0x07, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x35, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x25, 0x30, +0x2D, 0x30, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0xA7, 0x5B, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x84, 0xFF, 0x0A, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0xC9, 0x41, 0xC8, 0xEC, +0x42, 0xE1, +0x00, 0xE0, + +0x82, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xC8, 0x40, 0xC0, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x7F, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +}; + +static unsigned char warp_g200_tgza[] = { + +0x00, 0x98, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x81, 0x04, +0x89, 0x04, +0x01, 0x04, +0x09, 0x04, + +0xC9, 0x41, 0xC0, 0xEC, +0x11, 0x04, +0x00, 0xE0, + +0x41, 0xCC, 0x41, 0xCD, +0x49, 0xCC, 0x49, 0xCD, + +0xD1, 0x41, 0xC0, 0xEC, +0x51, 0xCC, 0x51, 0xCD, + +0x80, 0x04, +0x10, 0x04, +0x08, 0x04, +0x00, 0xE0, + +0x00, 0xCC, 0xC0, 0xCD, +0xD1, 0x49, 0xC0, 0xEC, + +0x8A, 0x1F, 0x20, 0xE9, +0x8B, 0x3F, 0x20, 0xE9, + +0x41, 0x3C, 0x41, 0xAD, +0x49, 0x3C, 0x49, 0xAD, + +0x10, 0xCC, 0x10, 0xCD, +0x08, 0xCC, 0x08, 0xCD, + +0xB9, 0x41, 0x49, 0xBB, +0x1F, 0xF0, 0x41, 0xCD, + +0x51, 0x3C, 0x51, 0xAD, +0x00, 0x98, 0x80, 0xE9, + +0x7D, 0x80, 0x07, 0xEA, +0x24, 0x1F, 0x20, 0xE9, + +0x15, 0x41, 0x49, 0xBD, +0x1D, 0x41, 0x51, 0xBD, + +0x2E, 0x41, 0x2A, 0xB8, +0x34, 0x53, 0xA0, 0xE8, + +0x15, 0x30, +0x1D, 0x30, +0x58, 0xE3, +0x00, 0xE0, + +0xB5, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x24, 0x43, 0xA0, 0xE8, +0x2C, 0x4B, 0xA0, 0xE8, + +0x15, 0x72, +0x09, 0xE3, +0x00, 0xE0, +0x1D, 0x72, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0x97, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x6C, 0x64, 0xC8, 0xEC, +0x98, 0xE1, +0xB5, 0x05, + +0xBD, 0x05, +0x2E, 0x30, +0x32, 0xC0, 0xA0, 0xE8, + +0x33, 0xC0, 0xA0, 0xE8, +0x74, 0x64, 0xC8, 0xEC, + +0x40, 0x3C, 0x40, 0xAD, +0x32, 0x6A, +0x2A, 0x30, + +0x20, 0x73, +0x33, 0x6A, +0x00, 0xE0, +0x28, 0x73, + +0x1C, 0x72, +0x83, 0xE2, +0x6B, 0x80, 0x15, 0xEA, + +0xB8, 0x3D, 0x28, 0xDF, +0x30, 0x35, 0x20, 0xDF, + +0x40, 0x30, +0x00, 0xE0, +0xCC, 0xE2, +0x64, 0x72, + +0x25, 0x42, 0x52, 0xBF, +0x2D, 0x42, 0x4A, 0xBF, + +0x30, 0x2E, 0x30, 0xDF, +0x38, 0x2E, 0x38, 0xDF, + +0x18, 0x1D, 0x45, 0xE9, +0x1E, 0x15, 0x45, 0xE9, + +0x2B, 0x49, 0x51, 0xBD, +0x00, 0xE0, +0x1F, 0x73, + +0x38, 0x38, 0x40, 0xAF, +0x30, 0x30, 0x40, 0xAF, + +0x24, 0x1F, 0x24, 0xDF, +0x1D, 0x32, 0x20, 0xE9, + +0x2C, 0x1F, 0x2C, 0xDF, +0x1A, 0x33, 0x20, 0xE9, + +0xB0, 0x10, +0x08, 0xE3, +0x40, 0x10, +0xB8, 0x10, + +0x26, 0xF0, 0x30, 0xCD, +0x2F, 0xF0, 0x38, 0xCD, + +0x2B, 0x80, 0x20, 0xE9, +0x2A, 0x80, 0x20, 0xE9, + +0xA6, 0x20, +0x88, 0xE2, +0x00, 0xE0, +0xAF, 0x20, + +0x28, 0x2A, 0x26, 0xAF, +0x20, 0x2A, 0xC0, 0xAF, + +0x34, 0x1F, 0x34, 0xDF, +0x46, 0x24, 0x46, 0xDF, + +0x28, 0x30, 0x80, 0xBF, +0x20, 0x38, 0x80, 0xBF, + +0x47, 0x24, 0x47, 0xDF, +0x4E, 0x2C, 0x4E, 0xDF, + +0x4F, 0x2C, 0x4F, 0xDF, +0x56, 0x34, 0x56, 0xDF, + +0x28, 0x15, 0x28, 0xDF, +0x20, 0x1D, 0x20, 0xDF, + +0x57, 0x34, 0x57, 0xDF, +0x00, 0xE0, +0x1D, 0x05, + +0x04, 0x80, 0x10, 0xEA, +0x89, 0xE2, +0x2B, 0x30, + +0x3F, 0xC1, 0x1D, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA0, 0x68, +0xBF, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x20, 0xC0, 0x20, 0xAF, +0x28, 0x05, +0x97, 0x74, + +0x00, 0xE0, +0x2A, 0x10, +0x16, 0xC0, 0x20, 0xE9, + +0x04, 0x80, 0x10, 0xEA, +0x8C, 0xE2, +0x95, 0x05, + +0x28, 0xC1, 0x28, 0xAD, +0x1F, 0xC1, 0x15, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA8, 0x67, +0x9F, 0x6B, +0x00, 0x80, 0x00, 0xE8, + +0x28, 0xC0, 0x28, 0xAD, +0x1D, 0x25, +0x20, 0x05, + +0x28, 0x32, 0x80, 0xAD, +0x40, 0x2A, 0x40, 0xBD, + +0x1C, 0x80, 0x20, 0xE9, +0x20, 0x33, 0x20, 0xAD, + +0x20, 0x73, +0x00, 0xE0, +0xB6, 0x49, 0x51, 0xBB, + +0x26, 0x2F, 0xB0, 0xE8, +0x19, 0x20, 0x20, 0xE9, + +0x35, 0x20, 0x35, 0xDF, +0x3D, 0x20, 0x3D, 0xDF, + +0x15, 0x20, 0x15, 0xDF, +0x1D, 0x20, 0x1D, 0xDF, + +0x26, 0xD0, 0x26, 0xCD, +0x29, 0x49, 0x2A, 0xB8, + +0x26, 0x40, 0x80, 0xBD, +0x3B, 0x48, 0x50, 0xBD, + +0x3E, 0x54, 0x57, 0x9F, +0x00, 0xE0, +0x82, 0xE1, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x26, 0x30, +0x29, 0x30, +0x48, 0x3C, 0x48, 0xAD, + +0x2B, 0x72, +0xC2, 0xE1, +0x2C, 0xC0, 0x44, 0xC2, + +0x05, 0x24, 0x34, 0xBF, +0x0D, 0x24, 0x2C, 0xBF, + +0x2D, 0x46, 0x4E, 0xBF, +0x25, 0x46, 0x56, 0xBF, + +0x20, 0x1D, 0x6F, 0x8F, +0x32, 0x3E, 0x5F, 0xE9, + +0x3E, 0x50, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x30, + +0x1E, 0x8F, 0x51, 0x9F, +0x33, 0x1E, 0x5F, 0xE9, + +0x05, 0x44, 0x54, 0xB2, +0x0D, 0x44, 0x4C, 0xB2, + +0x19, 0xC0, 0xB0, 0xE8, +0x34, 0xC0, 0x44, 0xC4, + +0x33, 0x73, +0x00, 0xE0, +0x3E, 0x62, 0x57, 0x9F, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0xE0, +0x0D, 0x20, + +0x84, 0x3E, 0x58, 0xE9, +0x28, 0x1D, 0x6F, 0x8F, + +0x05, 0x20, +0x00, 0xE0, +0x85, 0x1E, 0x58, 0xE9, + +0x9B, 0x3B, 0x33, 0xDF, +0x20, 0x20, 0x42, 0xAF, + +0x30, 0x42, 0x56, 0x9F, +0x80, 0x3E, 0x57, 0xE9, + +0x3F, 0x8F, 0x51, 0x9F, +0x30, 0x80, 0x5F, 0xE9, + +0x28, 0x28, 0x24, 0xAF, +0x81, 0x1E, 0x57, 0xE9, + +0x05, 0x47, 0x57, 0xBF, +0x0D, 0x47, 0x4F, 0xBF, + +0x88, 0x80, 0x58, 0xE9, +0x1B, 0x29, 0x1B, 0xDF, + +0x30, 0x1D, 0x6F, 0x8F, +0x3A, 0x30, 0x4F, 0xE9, + +0x1C, 0x30, 0x26, 0xDF, +0x09, 0xE3, +0x3B, 0x05, + +0x3E, 0x50, 0x56, 0x9F, +0x3B, 0x3F, 0x4F, 0xE9, + +0x1E, 0x8F, 0x51, 0x9F, +0x00, 0xE0, +0xAC, 0x20, + +0x2D, 0x44, 0x4C, 0xB4, +0x2C, 0x1C, 0xC0, 0xAF, + +0x25, 0x44, 0x54, 0xB4, +0x00, 0xE0, +0xC8, 0x30, + +0x30, 0x46, 0x30, 0xAF, +0x1B, 0x1B, 0x48, 0xAF, + +0x00, 0xE0, +0x25, 0x20, +0x38, 0x2C, 0x4F, 0xE9, + +0x86, 0x80, 0x57, 0xE9, +0x38, 0x1D, 0x6F, 0x8F, + +0x28, 0x74, +0x00, 0xE0, +0x0D, 0x44, 0x4C, 0xB0, + +0x05, 0x44, 0x54, 0xB0, +0x2D, 0x20, +0x9B, 0x10, + +0x82, 0x3E, 0x57, 0xE9, +0x32, 0xF0, 0x1B, 0xCD, + +0x1E, 0xBD, 0x59, 0x9F, +0x83, 0x1E, 0x57, 0xE9, + +0x38, 0x47, 0x38, 0xAF, +0x34, 0x20, +0x2A, 0x30, + +0x00, 0xE0, +0x0D, 0x20, +0x32, 0x20, +0x05, 0x20, + +0x87, 0x80, 0x57, 0xE9, +0x1F, 0x54, 0x57, 0x9F, + +0x17, 0x42, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x6A, + +0x3F, 0x8F, 0x51, 0x9F, +0x37, 0x1E, 0x4F, 0xE9, + +0x37, 0x32, 0x2A, 0xAF, +0x00, 0xE0, +0x32, 0x00, + +0x00, 0x80, 0x00, 0xE8, +0x27, 0xC0, 0x44, 0xC0, + +0x36, 0x1F, 0x4F, 0xE9, +0x1F, 0x1F, 0x26, 0xDF, + +0x37, 0x1B, 0x37, 0xBF, +0x17, 0x26, 0x17, 0xDF, + +0x3E, 0x17, 0x4F, 0xE9, +0x3F, 0x3F, 0x4F, 0xE9, + +0x34, 0x1F, 0x34, 0xAF, +0x2B, 0x05, +0xA7, 0x20, + +0x33, 0x2B, 0x37, 0xDF, +0x27, 0x17, 0xC0, 0xAF, + +0x34, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x2D, 0x44, 0x4C, 0xB6, +0x25, 0x44, 0x54, 0xB6, + +0x03, 0x80, 0x2A, 0xEA, +0x17, 0xC1, 0x2B, 0xBD, + +0x2D, 0x20, +0x25, 0x20, +0x07, 0xC0, 0x44, 0xC6, + +0xB3, 0x68, +0x97, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x33, 0xC0, 0x33, 0xAF, +0x3C, 0x27, 0x4F, 0xE9, + +0x1F, 0x62, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x3F, 0x3D, 0x5D, 0x9F, +0x00, 0xE0, +0x07, 0x20, + +0x00, 0x80, 0x00, 0xE8, +0x28, 0x19, 0x60, 0xEC, + +0xB3, 0x05, +0x00, 0xE0, +0x00, 0x80, 0x00, 0xE8, + +0x23, 0x3B, 0x33, 0xAD, +0x00, 0x80, 0x00, 0xE8, + +0x1F, 0x26, 0x1F, 0xDF, +0x9D, 0x1F, 0x4F, 0xE9, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x9E, 0x3F, 0x4F, 0xE9, + +0x07, 0x07, 0x1F, 0xAF, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x9C, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x57, 0x39, 0x20, 0xE9, + +0x16, 0x28, 0x20, 0xE9, +0x1D, 0x3B, 0x20, 0xE9, + +0x1E, 0x2B, 0x20, 0xE9, +0x2B, 0x32, 0x20, 0xE9, + +0x1C, 0x23, 0x20, 0xE9, +0x57, 0x36, 0x20, 0xE9, + +0x00, 0x80, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x90, 0xE2, +0x00, 0xE0, + +0x7A, 0xFF, 0x20, 0xEA, +0x19, 0xC8, 0xC1, 0xCD, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x9F, 0x41, 0x49, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x25, 0x41, 0x49, 0xBD, +0x2D, 0x41, 0x51, 0xBD, + +0x0D, 0x80, 0x07, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x35, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x25, 0x30, +0x2D, 0x30, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0xA7, 0x5B, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x79, 0xFF, 0x0A, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0xC9, 0x41, 0xC8, 0xEC, +0x42, 0xE1, +0x00, 0xE0, + +0x77, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xC8, 0x40, 0xC0, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x74, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +}; + +static unsigned char warp_g200_tgzaf[] = { + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x98, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x81, 0x04, +0x89, 0x04, +0x01, 0x04, +0x09, 0x04, + +0xC9, 0x41, 0xC0, 0xEC, +0x11, 0x04, +0x00, 0xE0, + +0x41, 0xCC, 0x41, 0xCD, +0x49, 0xCC, 0x49, 0xCD, + +0xD1, 0x41, 0xC0, 0xEC, +0x51, 0xCC, 0x51, 0xCD, + +0x80, 0x04, +0x10, 0x04, +0x08, 0x04, +0x00, 0xE0, + +0x00, 0xCC, 0xC0, 0xCD, +0xD1, 0x49, 0xC0, 0xEC, + +0x8A, 0x1F, 0x20, 0xE9, +0x8B, 0x3F, 0x20, 0xE9, + +0x41, 0x3C, 0x41, 0xAD, +0x49, 0x3C, 0x49, 0xAD, + +0x10, 0xCC, 0x10, 0xCD, +0x08, 0xCC, 0x08, 0xCD, + +0xB9, 0x41, 0x49, 0xBB, +0x1F, 0xF0, 0x41, 0xCD, + +0x51, 0x3C, 0x51, 0xAD, +0x00, 0x98, 0x80, 0xE9, + +0x83, 0x80, 0x07, 0xEA, +0x24, 0x1F, 0x20, 0xE9, + +0x21, 0x45, 0x80, 0xE8, +0x1A, 0x4D, 0x80, 0xE8, + +0x31, 0x55, 0x80, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0x41, 0x49, 0xBD, +0x1D, 0x41, 0x51, 0xBD, + +0x2E, 0x41, 0x2A, 0xB8, +0x34, 0x53, 0xA0, 0xE8, + +0x15, 0x30, +0x1D, 0x30, +0x58, 0xE3, +0x00, 0xE0, + +0xB5, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x24, 0x43, 0xA0, 0xE8, +0x2C, 0x4B, 0xA0, 0xE8, + +0x15, 0x72, +0x09, 0xE3, +0x00, 0xE0, +0x1D, 0x72, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0x97, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x6C, 0x64, 0xC8, 0xEC, +0x98, 0xE1, +0xB5, 0x05, + +0xBD, 0x05, +0x2E, 0x30, +0x32, 0xC0, 0xA0, 0xE8, + +0x33, 0xC0, 0xA0, 0xE8, +0x74, 0x64, 0xC8, 0xEC, + +0x40, 0x3C, 0x40, 0xAD, +0x32, 0x6A, +0x2A, 0x30, + +0x20, 0x73, +0x33, 0x6A, +0x00, 0xE0, +0x28, 0x73, + +0x1C, 0x72, +0x83, 0xE2, +0x6F, 0x80, 0x15, 0xEA, + +0xB8, 0x3D, 0x28, 0xDF, +0x30, 0x35, 0x20, 0xDF, + +0x40, 0x30, +0x00, 0xE0, +0xCC, 0xE2, +0x64, 0x72, + +0x25, 0x42, 0x52, 0xBF, +0x2D, 0x42, 0x4A, 0xBF, + +0x30, 0x2E, 0x30, 0xDF, +0x38, 0x2E, 0x38, 0xDF, + +0x18, 0x1D, 0x45, 0xE9, +0x1E, 0x15, 0x45, 0xE9, + +0x2B, 0x49, 0x51, 0xBD, +0x00, 0xE0, +0x1F, 0x73, + +0x38, 0x38, 0x40, 0xAF, +0x30, 0x30, 0x40, 0xAF, + +0x24, 0x1F, 0x24, 0xDF, +0x1D, 0x32, 0x20, 0xE9, + +0x2C, 0x1F, 0x2C, 0xDF, +0x1A, 0x33, 0x20, 0xE9, + +0xB0, 0x10, +0x08, 0xE3, +0x40, 0x10, +0xB8, 0x10, + +0x26, 0xF0, 0x30, 0xCD, +0x2F, 0xF0, 0x38, 0xCD, + +0x2B, 0x80, 0x20, 0xE9, +0x2A, 0x80, 0x20, 0xE9, + +0xA6, 0x20, +0x88, 0xE2, +0x00, 0xE0, +0xAF, 0x20, + +0x28, 0x2A, 0x26, 0xAF, +0x20, 0x2A, 0xC0, 0xAF, + +0x34, 0x1F, 0x34, 0xDF, +0x46, 0x24, 0x46, 0xDF, + +0x28, 0x30, 0x80, 0xBF, +0x20, 0x38, 0x80, 0xBF, + +0x47, 0x24, 0x47, 0xDF, +0x4E, 0x2C, 0x4E, 0xDF, + +0x4F, 0x2C, 0x4F, 0xDF, +0x56, 0x34, 0x56, 0xDF, + +0x28, 0x15, 0x28, 0xDF, +0x20, 0x1D, 0x20, 0xDF, + +0x57, 0x34, 0x57, 0xDF, +0x00, 0xE0, +0x1D, 0x05, + +0x04, 0x80, 0x10, 0xEA, +0x89, 0xE2, +0x2B, 0x30, + +0x3F, 0xC1, 0x1D, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA0, 0x68, +0xBF, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x20, 0xC0, 0x20, 0xAF, +0x28, 0x05, +0x97, 0x74, + +0x00, 0xE0, +0x2A, 0x10, +0x16, 0xC0, 0x20, 0xE9, + +0x04, 0x80, 0x10, 0xEA, +0x8C, 0xE2, +0x95, 0x05, + +0x28, 0xC1, 0x28, 0xAD, +0x1F, 0xC1, 0x15, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA8, 0x67, +0x9F, 0x6B, +0x00, 0x80, 0x00, 0xE8, + +0x28, 0xC0, 0x28, 0xAD, +0x1D, 0x25, +0x20, 0x05, + +0x28, 0x32, 0x80, 0xAD, +0x40, 0x2A, 0x40, 0xBD, + +0x1C, 0x80, 0x20, 0xE9, +0x20, 0x33, 0x20, 0xAD, + +0x20, 0x73, +0x00, 0xE0, +0xB6, 0x49, 0x51, 0xBB, + +0x26, 0x2F, 0xB0, 0xE8, +0x19, 0x20, 0x20, 0xE9, + +0x35, 0x20, 0x35, 0xDF, +0x3D, 0x20, 0x3D, 0xDF, + +0x15, 0x20, 0x15, 0xDF, +0x1D, 0x20, 0x1D, 0xDF, + +0x26, 0xD0, 0x26, 0xCD, +0x29, 0x49, 0x2A, 0xB8, + +0x26, 0x40, 0x80, 0xBD, +0x3B, 0x48, 0x50, 0xBD, + +0x3E, 0x54, 0x57, 0x9F, +0x00, 0xE0, +0x82, 0xE1, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x26, 0x30, +0x29, 0x30, +0x48, 0x3C, 0x48, 0xAD, + +0x2B, 0x72, +0xC2, 0xE1, +0x2C, 0xC0, 0x44, 0xC2, + +0x05, 0x24, 0x34, 0xBF, +0x0D, 0x24, 0x2C, 0xBF, + +0x2D, 0x46, 0x4E, 0xBF, +0x25, 0x46, 0x56, 0xBF, + +0x20, 0x1D, 0x6F, 0x8F, +0x32, 0x3E, 0x5F, 0xE9, + +0x3E, 0x50, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x30, + +0x1E, 0x8F, 0x51, 0x9F, +0x33, 0x1E, 0x5F, 0xE9, + +0x05, 0x44, 0x54, 0xB2, +0x0D, 0x44, 0x4C, 0xB2, + +0x19, 0xC0, 0xB0, 0xE8, +0x34, 0xC0, 0x44, 0xC4, + +0x33, 0x73, +0x00, 0xE0, +0x3E, 0x62, 0x57, 0x9F, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0xE0, +0x0D, 0x20, + +0x84, 0x3E, 0x58, 0xE9, +0x28, 0x1D, 0x6F, 0x8F, + +0x05, 0x20, +0x00, 0xE0, +0x85, 0x1E, 0x58, 0xE9, + +0x9B, 0x3B, 0x33, 0xDF, +0x20, 0x20, 0x42, 0xAF, + +0x30, 0x42, 0x56, 0x9F, +0x80, 0x3E, 0x57, 0xE9, + +0x3F, 0x8F, 0x51, 0x9F, +0x30, 0x80, 0x5F, 0xE9, + +0x28, 0x28, 0x24, 0xAF, +0x81, 0x1E, 0x57, 0xE9, + +0x05, 0x47, 0x57, 0xBF, +0x0D, 0x47, 0x4F, 0xBF, + +0x88, 0x80, 0x58, 0xE9, +0x1B, 0x29, 0x1B, 0xDF, + +0x30, 0x1D, 0x6F, 0x8F, +0x3A, 0x30, 0x4F, 0xE9, + +0x1C, 0x30, 0x26, 0xDF, +0x09, 0xE3, +0x3B, 0x05, + +0x3E, 0x50, 0x56, 0x9F, +0x3B, 0x3F, 0x4F, 0xE9, + +0x1E, 0x8F, 0x51, 0x9F, +0x00, 0xE0, +0xAC, 0x20, + +0x2D, 0x44, 0x4C, 0xB4, +0x2C, 0x1C, 0xC0, 0xAF, + +0x25, 0x44, 0x54, 0xB4, +0x00, 0xE0, +0xC8, 0x30, + +0x30, 0x46, 0x30, 0xAF, +0x1B, 0x1B, 0x48, 0xAF, + +0x00, 0xE0, +0x25, 0x20, +0x38, 0x2C, 0x4F, 0xE9, + +0x86, 0x80, 0x57, 0xE9, +0x38, 0x1D, 0x6F, 0x8F, + +0x28, 0x74, +0x00, 0xE0, +0x0D, 0x44, 0x4C, 0xB0, + +0x05, 0x44, 0x54, 0xB0, +0x2D, 0x20, +0x9B, 0x10, + +0x82, 0x3E, 0x57, 0xE9, +0x32, 0xF0, 0x1B, 0xCD, + +0x1E, 0xBD, 0x59, 0x9F, +0x83, 0x1E, 0x57, 0xE9, + +0x38, 0x47, 0x38, 0xAF, +0x34, 0x20, +0x2A, 0x30, + +0x00, 0xE0, +0x0D, 0x20, +0x32, 0x20, +0x05, 0x20, + +0x87, 0x80, 0x57, 0xE9, +0x1F, 0x54, 0x57, 0x9F, + +0x17, 0x42, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x6A, + +0x3F, 0x8F, 0x51, 0x9F, +0x37, 0x1E, 0x4F, 0xE9, + +0x37, 0x32, 0x2A, 0xAF, +0x00, 0xE0, +0x32, 0x00, + +0x00, 0x80, 0x00, 0xE8, +0x27, 0xC0, 0x44, 0xC0, + +0x36, 0x1F, 0x4F, 0xE9, +0x1F, 0x1F, 0x26, 0xDF, + +0x37, 0x1B, 0x37, 0xBF, +0x17, 0x26, 0x17, 0xDF, + +0x3E, 0x17, 0x4F, 0xE9, +0x3F, 0x3F, 0x4F, 0xE9, + +0x34, 0x1F, 0x34, 0xAF, +0x2B, 0x05, +0xA7, 0x20, + +0x33, 0x2B, 0x37, 0xDF, +0x27, 0x17, 0xC0, 0xAF, + +0x34, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x0D, 0x21, 0x1A, 0xB6, +0x05, 0x21, 0x31, 0xB6, + +0x2D, 0x44, 0x4C, 0xB6, +0x25, 0x44, 0x54, 0xB6, + +0x03, 0x80, 0x2A, 0xEA, +0x17, 0xC1, 0x2B, 0xBD, + +0x0D, 0x20, +0x05, 0x20, +0x2F, 0xC0, 0x21, 0xC6, + +0xB3, 0x68, +0x97, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x33, 0xC0, 0x33, 0xAF, +0x3C, 0x27, 0x4F, 0xE9, + +0x00, 0xE0, +0x25, 0x20, +0x07, 0xC0, 0x44, 0xC6, + +0x17, 0x50, 0x56, 0x9F, +0x00, 0xE0, +0x2D, 0x20, + +0x37, 0x0F, 0x5C, 0x9F, +0x00, 0xE0, +0x2F, 0x20, + +0x1F, 0x62, 0x57, 0x9F, +0x00, 0xE0, +0x07, 0x20, + +0x3F, 0x3D, 0x5D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x28, 0x19, 0x60, 0xEC, + +0xB3, 0x05, +0x00, 0xE0, +0x17, 0x26, 0x17, 0xDF, + +0x23, 0x3B, 0x33, 0xAD, +0x35, 0x17, 0x4F, 0xE9, + +0x1F, 0x26, 0x1F, 0xDF, +0x9D, 0x1F, 0x4F, 0xE9, + +0x9E, 0x3F, 0x4F, 0xE9, +0x39, 0x37, 0x4F, 0xE9, + +0x2F, 0x2F, 0x17, 0xAF, +0x00, 0x80, 0x00, 0xE8, + +0x07, 0x07, 0x1F, 0xAF, +0x00, 0x80, 0x00, 0xE8, + +0x31, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x9C, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x57, 0x39, 0x20, 0xE9, + +0x16, 0x28, 0x20, 0xE9, +0x1D, 0x3B, 0x20, 0xE9, + +0x1E, 0x2B, 0x20, 0xE9, +0x2B, 0x32, 0x20, 0xE9, + +0x1C, 0x23, 0x20, 0xE9, +0x57, 0x36, 0x20, 0xE9, + +0x00, 0x80, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x90, 0xE2, +0x00, 0xE0, + +0x74, 0xFF, 0x20, 0xEA, +0x19, 0xC8, 0xC1, 0xCD, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x9F, 0x41, 0x49, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x25, 0x41, 0x49, 0xBD, +0x2D, 0x41, 0x51, 0xBD, + +0x0D, 0x80, 0x07, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x35, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x25, 0x30, +0x2D, 0x30, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0xA7, 0x5B, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x73, 0xFF, 0x0A, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0xC9, 0x41, 0xC8, 0xEC, +0x42, 0xE1, +0x00, 0xE0, + +0x71, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xC8, 0x40, 0xC0, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x6E, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +}; + +static unsigned char warp_g200_tgzf[] = { + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x98, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x81, 0x04, +0x89, 0x04, +0x01, 0x04, +0x09, 0x04, + +0xC9, 0x41, 0xC0, 0xEC, +0x11, 0x04, +0x00, 0xE0, + +0x41, 0xCC, 0x41, 0xCD, +0x49, 0xCC, 0x49, 0xCD, + +0xD1, 0x41, 0xC0, 0xEC, +0x51, 0xCC, 0x51, 0xCD, + +0x80, 0x04, +0x10, 0x04, +0x08, 0x04, +0x00, 0xE0, + +0x00, 0xCC, 0xC0, 0xCD, +0xD1, 0x49, 0xC0, 0xEC, + +0x8A, 0x1F, 0x20, 0xE9, +0x8B, 0x3F, 0x20, 0xE9, + +0x41, 0x3C, 0x41, 0xAD, +0x49, 0x3C, 0x49, 0xAD, + +0x10, 0xCC, 0x10, 0xCD, +0x08, 0xCC, 0x08, 0xCD, + +0xB9, 0x41, 0x49, 0xBB, +0x1F, 0xF0, 0x41, 0xCD, + +0x51, 0x3C, 0x51, 0xAD, +0x00, 0x98, 0x80, 0xE9, + +0x7F, 0x80, 0x07, 0xEA, +0x24, 0x1F, 0x20, 0xE9, + +0x21, 0x45, 0x80, 0xE8, +0x1A, 0x4D, 0x80, 0xE8, + +0x31, 0x55, 0x80, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0x41, 0x49, 0xBD, +0x1D, 0x41, 0x51, 0xBD, + +0x2E, 0x41, 0x2A, 0xB8, +0x34, 0x53, 0xA0, 0xE8, + +0x15, 0x30, +0x1D, 0x30, +0x58, 0xE3, +0x00, 0xE0, + +0xB5, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x24, 0x43, 0xA0, 0xE8, +0x2C, 0x4B, 0xA0, 0xE8, + +0x15, 0x72, +0x09, 0xE3, +0x00, 0xE0, +0x1D, 0x72, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0x97, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x6C, 0x64, 0xC8, 0xEC, +0x98, 0xE1, +0xB5, 0x05, + +0xBD, 0x05, +0x2E, 0x30, +0x32, 0xC0, 0xA0, 0xE8, + +0x33, 0xC0, 0xA0, 0xE8, +0x74, 0x64, 0xC8, 0xEC, + +0x40, 0x3C, 0x40, 0xAD, +0x32, 0x6A, +0x2A, 0x30, + +0x20, 0x73, +0x33, 0x6A, +0x00, 0xE0, +0x28, 0x73, + +0x1C, 0x72, +0x83, 0xE2, +0x6B, 0x80, 0x15, 0xEA, + +0xB8, 0x3D, 0x28, 0xDF, +0x30, 0x35, 0x20, 0xDF, + +0x40, 0x30, +0x00, 0xE0, +0xCC, 0xE2, +0x64, 0x72, + +0x25, 0x42, 0x52, 0xBF, +0x2D, 0x42, 0x4A, 0xBF, + +0x30, 0x2E, 0x30, 0xDF, +0x38, 0x2E, 0x38, 0xDF, + +0x18, 0x1D, 0x45, 0xE9, +0x1E, 0x15, 0x45, 0xE9, + +0x2B, 0x49, 0x51, 0xBD, +0x00, 0xE0, +0x1F, 0x73, + +0x38, 0x38, 0x40, 0xAF, +0x30, 0x30, 0x40, 0xAF, + +0x24, 0x1F, 0x24, 0xDF, +0x1D, 0x32, 0x20, 0xE9, + +0x2C, 0x1F, 0x2C, 0xDF, +0x1A, 0x33, 0x20, 0xE9, + +0xB0, 0x10, +0x08, 0xE3, +0x40, 0x10, +0xB8, 0x10, + +0x26, 0xF0, 0x30, 0xCD, +0x2F, 0xF0, 0x38, 0xCD, + +0x2B, 0x80, 0x20, 0xE9, +0x2A, 0x80, 0x20, 0xE9, + +0xA6, 0x20, +0x88, 0xE2, +0x00, 0xE0, +0xAF, 0x20, + +0x28, 0x2A, 0x26, 0xAF, +0x20, 0x2A, 0xC0, 0xAF, + +0x34, 0x1F, 0x34, 0xDF, +0x46, 0x24, 0x46, 0xDF, + +0x28, 0x30, 0x80, 0xBF, +0x20, 0x38, 0x80, 0xBF, + +0x47, 0x24, 0x47, 0xDF, +0x4E, 0x2C, 0x4E, 0xDF, + +0x4F, 0x2C, 0x4F, 0xDF, +0x56, 0x34, 0x56, 0xDF, + +0x28, 0x15, 0x28, 0xDF, +0x20, 0x1D, 0x20, 0xDF, + +0x57, 0x34, 0x57, 0xDF, +0x00, 0xE0, +0x1D, 0x05, + +0x04, 0x80, 0x10, 0xEA, +0x89, 0xE2, +0x2B, 0x30, + +0x3F, 0xC1, 0x1D, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA0, 0x68, +0xBF, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x20, 0xC0, 0x20, 0xAF, +0x28, 0x05, +0x97, 0x74, + +0x00, 0xE0, +0x2A, 0x10, +0x16, 0xC0, 0x20, 0xE9, + +0x04, 0x80, 0x10, 0xEA, +0x8C, 0xE2, +0x95, 0x05, + +0x28, 0xC1, 0x28, 0xAD, +0x1F, 0xC1, 0x15, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA8, 0x67, +0x9F, 0x6B, +0x00, 0x80, 0x00, 0xE8, + +0x28, 0xC0, 0x28, 0xAD, +0x1D, 0x25, +0x20, 0x05, + +0x28, 0x32, 0x80, 0xAD, +0x40, 0x2A, 0x40, 0xBD, + +0x1C, 0x80, 0x20, 0xE9, +0x20, 0x33, 0x20, 0xAD, + +0x20, 0x73, +0x00, 0xE0, +0xB6, 0x49, 0x51, 0xBB, + +0x26, 0x2F, 0xB0, 0xE8, +0x19, 0x20, 0x20, 0xE9, + +0x35, 0x20, 0x35, 0xDF, +0x3D, 0x20, 0x3D, 0xDF, + +0x15, 0x20, 0x15, 0xDF, +0x1D, 0x20, 0x1D, 0xDF, + +0x26, 0xD0, 0x26, 0xCD, +0x29, 0x49, 0x2A, 0xB8, + +0x26, 0x40, 0x80, 0xBD, +0x3B, 0x48, 0x50, 0xBD, + +0x3E, 0x54, 0x57, 0x9F, +0x00, 0xE0, +0x82, 0xE1, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x26, 0x30, +0x29, 0x30, +0x48, 0x3C, 0x48, 0xAD, + +0x2B, 0x72, +0xC2, 0xE1, +0x2C, 0xC0, 0x44, 0xC2, + +0x05, 0x24, 0x34, 0xBF, +0x0D, 0x24, 0x2C, 0xBF, + +0x2D, 0x46, 0x4E, 0xBF, +0x25, 0x46, 0x56, 0xBF, + +0x20, 0x1D, 0x6F, 0x8F, +0x32, 0x3E, 0x5F, 0xE9, + +0x3E, 0x50, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x30, + +0x1E, 0x8F, 0x51, 0x9F, +0x33, 0x1E, 0x5F, 0xE9, + +0x05, 0x44, 0x54, 0xB2, +0x0D, 0x44, 0x4C, 0xB2, + +0x19, 0xC0, 0xB0, 0xE8, +0x34, 0xC0, 0x44, 0xC4, + +0x33, 0x73, +0x00, 0xE0, +0x3E, 0x62, 0x57, 0x9F, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0xE0, +0x0D, 0x20, + +0x84, 0x3E, 0x58, 0xE9, +0x28, 0x1D, 0x6F, 0x8F, + +0x05, 0x20, +0x00, 0xE0, +0x85, 0x1E, 0x58, 0xE9, + +0x9B, 0x3B, 0x33, 0xDF, +0x20, 0x20, 0x42, 0xAF, + +0x30, 0x42, 0x56, 0x9F, +0x80, 0x3E, 0x57, 0xE9, + +0x3F, 0x8F, 0x51, 0x9F, +0x30, 0x80, 0x5F, 0xE9, + +0x28, 0x28, 0x24, 0xAF, +0x81, 0x1E, 0x57, 0xE9, + +0x05, 0x47, 0x57, 0xBF, +0x0D, 0x47, 0x4F, 0xBF, + +0x88, 0x80, 0x58, 0xE9, +0x1B, 0x29, 0x1B, 0xDF, + +0x30, 0x1D, 0x6F, 0x8F, +0x3A, 0x30, 0x4F, 0xE9, + +0x1C, 0x30, 0x26, 0xDF, +0x09, 0xE3, +0x3B, 0x05, + +0x3E, 0x50, 0x56, 0x9F, +0x3B, 0x3F, 0x4F, 0xE9, + +0x1E, 0x8F, 0x51, 0x9F, +0x00, 0xE0, +0xAC, 0x20, + +0x2D, 0x44, 0x4C, 0xB4, +0x2C, 0x1C, 0xC0, 0xAF, + +0x25, 0x44, 0x54, 0xB4, +0x00, 0xE0, +0xC8, 0x30, + +0x30, 0x46, 0x30, 0xAF, +0x1B, 0x1B, 0x48, 0xAF, + +0x00, 0xE0, +0x25, 0x20, +0x38, 0x2C, 0x4F, 0xE9, + +0x86, 0x80, 0x57, 0xE9, +0x38, 0x1D, 0x6F, 0x8F, + +0x28, 0x74, +0x00, 0xE0, +0x0D, 0x44, 0x4C, 0xB0, + +0x05, 0x44, 0x54, 0xB0, +0x2D, 0x20, +0x9B, 0x10, + +0x82, 0x3E, 0x57, 0xE9, +0x32, 0xF0, 0x1B, 0xCD, + +0x1E, 0xBD, 0x59, 0x9F, +0x83, 0x1E, 0x57, 0xE9, + +0x38, 0x47, 0x38, 0xAF, +0x34, 0x20, +0x2A, 0x30, + +0x00, 0xE0, +0x0D, 0x20, +0x32, 0x20, +0x05, 0x20, + +0x87, 0x80, 0x57, 0xE9, +0x1F, 0x54, 0x57, 0x9F, + +0x17, 0x42, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x6A, + +0x3F, 0x8F, 0x51, 0x9F, +0x37, 0x1E, 0x4F, 0xE9, + +0x37, 0x32, 0x2A, 0xAF, +0x00, 0xE0, +0x32, 0x00, + +0x00, 0x80, 0x00, 0xE8, +0x27, 0xC0, 0x44, 0xC0, + +0x36, 0x1F, 0x4F, 0xE9, +0x1F, 0x1F, 0x26, 0xDF, + +0x37, 0x1B, 0x37, 0xBF, +0x17, 0x26, 0x17, 0xDF, + +0x3E, 0x17, 0x4F, 0xE9, +0x3F, 0x3F, 0x4F, 0xE9, + +0x34, 0x1F, 0x34, 0xAF, +0x2B, 0x05, +0xA7, 0x20, + +0x33, 0x2B, 0x37, 0xDF, +0x27, 0x17, 0xC0, 0xAF, + +0x34, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x0D, 0x21, 0x1A, 0xB6, +0x05, 0x21, 0x31, 0xB6, + +0x03, 0x80, 0x2A, 0xEA, +0x17, 0xC1, 0x2B, 0xBD, + +0x0D, 0x20, +0x05, 0x20, +0x2F, 0xC0, 0x21, 0xC6, + +0xB3, 0x68, +0x97, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x33, 0xC0, 0x33, 0xAF, +0x3C, 0x27, 0x4F, 0xE9, + +0x17, 0x50, 0x56, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x37, 0x0F, 0x5C, 0x9F, +0x00, 0xE0, +0x2F, 0x20, + +0x00, 0x80, 0x00, 0xE8, +0x28, 0x19, 0x60, 0xEC, + +0xB3, 0x05, +0x00, 0xE0, +0x00, 0x80, 0x00, 0xE8, + +0x23, 0x3B, 0x33, 0xAD, +0x00, 0x80, 0x00, 0xE8, + +0x17, 0x26, 0x17, 0xDF, +0x35, 0x17, 0x4F, 0xE9, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x39, 0x37, 0x4F, 0xE9, + +0x2F, 0x2F, 0x17, 0xAF, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x31, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x57, 0x39, 0x20, 0xE9, + +0x16, 0x28, 0x20, 0xE9, +0x1D, 0x3B, 0x20, 0xE9, + +0x1E, 0x2B, 0x20, 0xE9, +0x2B, 0x32, 0x20, 0xE9, + +0x1C, 0x23, 0x20, 0xE9, +0x57, 0x36, 0x20, 0xE9, + +0x00, 0x80, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x90, 0xE2, +0x00, 0xE0, + +0x78, 0xFF, 0x20, 0xEA, +0x19, 0xC8, 0xC1, 0xCD, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x9F, 0x41, 0x49, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x25, 0x41, 0x49, 0xBD, +0x2D, 0x41, 0x51, 0xBD, + +0x0D, 0x80, 0x07, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x35, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x25, 0x30, +0x2D, 0x30, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0xA7, 0x5B, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x77, 0xFF, 0x0A, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0xC9, 0x41, 0xC8, 0xEC, +0x42, 0xE1, +0x00, 0xE0, + +0x75, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xC8, 0x40, 0xC0, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x72, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +}; + +static unsigned char warp_g200_tgzs[] = { + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x98, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x81, 0x04, +0x89, 0x04, +0x01, 0x04, +0x09, 0x04, + +0xC9, 0x41, 0xC0, 0xEC, +0x11, 0x04, +0x00, 0xE0, + +0x41, 0xCC, 0x41, 0xCD, +0x49, 0xCC, 0x49, 0xCD, + +0xD1, 0x41, 0xC0, 0xEC, +0x51, 0xCC, 0x51, 0xCD, + +0x80, 0x04, +0x10, 0x04, +0x08, 0x04, +0x00, 0xE0, + +0x00, 0xCC, 0xC0, 0xCD, +0xD1, 0x49, 0xC0, 0xEC, + +0x8A, 0x1F, 0x20, 0xE9, +0x8B, 0x3F, 0x20, 0xE9, + +0x41, 0x3C, 0x41, 0xAD, +0x49, 0x3C, 0x49, 0xAD, + +0x10, 0xCC, 0x10, 0xCD, +0x08, 0xCC, 0x08, 0xCD, + +0xB9, 0x41, 0x49, 0xBB, +0x1F, 0xF0, 0x41, 0xCD, + +0x51, 0x3C, 0x51, 0xAD, +0x00, 0x98, 0x80, 0xE9, + +0x8B, 0x80, 0x07, 0xEA, +0x24, 0x1F, 0x20, 0xE9, + +0x21, 0x45, 0x80, 0xE8, +0x1A, 0x4D, 0x80, 0xE8, + +0x31, 0x55, 0x80, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0x41, 0x49, 0xBD, +0x1D, 0x41, 0x51, 0xBD, + +0x2E, 0x41, 0x2A, 0xB8, +0x34, 0x53, 0xA0, 0xE8, + +0x15, 0x30, +0x1D, 0x30, +0x58, 0xE3, +0x00, 0xE0, + +0xB5, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x24, 0x43, 0xA0, 0xE8, +0x2C, 0x4B, 0xA0, 0xE8, + +0x15, 0x72, +0x09, 0xE3, +0x00, 0xE0, +0x1D, 0x72, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0x97, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x6C, 0x64, 0xC8, 0xEC, +0x98, 0xE1, +0xB5, 0x05, + +0xBD, 0x05, +0x2E, 0x30, +0x32, 0xC0, 0xA0, 0xE8, + +0x33, 0xC0, 0xA0, 0xE8, +0x74, 0x64, 0xC8, 0xEC, + +0x40, 0x3C, 0x40, 0xAD, +0x32, 0x6A, +0x2A, 0x30, + +0x20, 0x73, +0x33, 0x6A, +0x00, 0xE0, +0x28, 0x73, + +0x1C, 0x72, +0x83, 0xE2, +0x77, 0x80, 0x15, 0xEA, + +0xB8, 0x3D, 0x28, 0xDF, +0x30, 0x35, 0x20, 0xDF, + +0x40, 0x30, +0x00, 0xE0, +0xCC, 0xE2, +0x64, 0x72, + +0x25, 0x42, 0x52, 0xBF, +0x2D, 0x42, 0x4A, 0xBF, + +0x30, 0x2E, 0x30, 0xDF, +0x38, 0x2E, 0x38, 0xDF, + +0x18, 0x1D, 0x45, 0xE9, +0x1E, 0x15, 0x45, 0xE9, + +0x2B, 0x49, 0x51, 0xBD, +0x00, 0xE0, +0x1F, 0x73, + +0x38, 0x38, 0x40, 0xAF, +0x30, 0x30, 0x40, 0xAF, + +0x24, 0x1F, 0x24, 0xDF, +0x1D, 0x32, 0x20, 0xE9, + +0x2C, 0x1F, 0x2C, 0xDF, +0x1A, 0x33, 0x20, 0xE9, + +0xB0, 0x10, +0x08, 0xE3, +0x40, 0x10, +0xB8, 0x10, + +0x26, 0xF0, 0x30, 0xCD, +0x2F, 0xF0, 0x38, 0xCD, + +0x2B, 0x80, 0x20, 0xE9, +0x2A, 0x80, 0x20, 0xE9, + +0xA6, 0x20, +0x88, 0xE2, +0x00, 0xE0, +0xAF, 0x20, + +0x28, 0x2A, 0x26, 0xAF, +0x20, 0x2A, 0xC0, 0xAF, + +0x34, 0x1F, 0x34, 0xDF, +0x46, 0x24, 0x46, 0xDF, + +0x28, 0x30, 0x80, 0xBF, +0x20, 0x38, 0x80, 0xBF, + +0x47, 0x24, 0x47, 0xDF, +0x4E, 0x2C, 0x4E, 0xDF, + +0x4F, 0x2C, 0x4F, 0xDF, +0x56, 0x34, 0x56, 0xDF, + +0x28, 0x15, 0x28, 0xDF, +0x20, 0x1D, 0x20, 0xDF, + +0x57, 0x34, 0x57, 0xDF, +0x00, 0xE0, +0x1D, 0x05, + +0x04, 0x80, 0x10, 0xEA, +0x89, 0xE2, +0x2B, 0x30, + +0x3F, 0xC1, 0x1D, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA0, 0x68, +0xBF, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x20, 0xC0, 0x20, 0xAF, +0x28, 0x05, +0x97, 0x74, + +0x00, 0xE0, +0x2A, 0x10, +0x16, 0xC0, 0x20, 0xE9, + +0x04, 0x80, 0x10, 0xEA, +0x8C, 0xE2, +0x95, 0x05, + +0x28, 0xC1, 0x28, 0xAD, +0x1F, 0xC1, 0x15, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA8, 0x67, +0x9F, 0x6B, +0x00, 0x80, 0x00, 0xE8, + +0x28, 0xC0, 0x28, 0xAD, +0x1D, 0x25, +0x20, 0x05, + +0x28, 0x32, 0x80, 0xAD, +0x40, 0x2A, 0x40, 0xBD, + +0x1C, 0x80, 0x20, 0xE9, +0x20, 0x33, 0x20, 0xAD, + +0x20, 0x73, +0x00, 0xE0, +0xB6, 0x49, 0x51, 0xBB, + +0x26, 0x2F, 0xB0, 0xE8, +0x19, 0x20, 0x20, 0xE9, + +0x35, 0x20, 0x35, 0xDF, +0x3D, 0x20, 0x3D, 0xDF, + +0x15, 0x20, 0x15, 0xDF, +0x1D, 0x20, 0x1D, 0xDF, + +0x26, 0xD0, 0x26, 0xCD, +0x29, 0x49, 0x2A, 0xB8, + +0x26, 0x40, 0x80, 0xBD, +0x3B, 0x48, 0x50, 0xBD, + +0x3E, 0x54, 0x57, 0x9F, +0x00, 0xE0, +0x82, 0xE1, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x26, 0x30, +0x29, 0x30, +0x48, 0x3C, 0x48, 0xAD, + +0x2B, 0x72, +0xC2, 0xE1, +0x2C, 0xC0, 0x44, 0xC2, + +0x05, 0x24, 0x34, 0xBF, +0x0D, 0x24, 0x2C, 0xBF, + +0x2D, 0x46, 0x4E, 0xBF, +0x25, 0x46, 0x56, 0xBF, + +0x20, 0x1D, 0x6F, 0x8F, +0x32, 0x3E, 0x5F, 0xE9, + +0x3E, 0x50, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x30, + +0x1E, 0x8F, 0x51, 0x9F, +0x33, 0x1E, 0x5F, 0xE9, + +0x05, 0x44, 0x54, 0xB2, +0x0D, 0x44, 0x4C, 0xB2, + +0x19, 0xC0, 0xB0, 0xE8, +0x34, 0xC0, 0x44, 0xC4, + +0x33, 0x73, +0x00, 0xE0, +0x3E, 0x62, 0x57, 0x9F, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0xE0, +0x0D, 0x20, + +0x84, 0x3E, 0x58, 0xE9, +0x28, 0x1D, 0x6F, 0x8F, + +0x05, 0x20, +0x00, 0xE0, +0x85, 0x1E, 0x58, 0xE9, + +0x9B, 0x3B, 0x33, 0xDF, +0x20, 0x20, 0x42, 0xAF, + +0x30, 0x42, 0x56, 0x9F, +0x80, 0x3E, 0x57, 0xE9, + +0x3F, 0x8F, 0x51, 0x9F, +0x30, 0x80, 0x5F, 0xE9, + +0x28, 0x28, 0x24, 0xAF, +0x81, 0x1E, 0x57, 0xE9, + +0x05, 0x47, 0x57, 0xBF, +0x0D, 0x47, 0x4F, 0xBF, + +0x88, 0x80, 0x58, 0xE9, +0x1B, 0x29, 0x1B, 0xDF, + +0x30, 0x1D, 0x6F, 0x8F, +0x3A, 0x30, 0x4F, 0xE9, + +0x1C, 0x30, 0x26, 0xDF, +0x09, 0xE3, +0x3B, 0x05, + +0x3E, 0x50, 0x56, 0x9F, +0x3B, 0x3F, 0x4F, 0xE9, + +0x1E, 0x8F, 0x51, 0x9F, +0x00, 0xE0, +0xAC, 0x20, + +0x2D, 0x44, 0x4C, 0xB4, +0x2C, 0x1C, 0xC0, 0xAF, + +0x25, 0x44, 0x54, 0xB4, +0x00, 0xE0, +0xC8, 0x30, + +0x30, 0x46, 0x30, 0xAF, +0x1B, 0x1B, 0x48, 0xAF, + +0x00, 0xE0, +0x25, 0x20, +0x38, 0x2C, 0x4F, 0xE9, + +0x86, 0x80, 0x57, 0xE9, +0x38, 0x1D, 0x6F, 0x8F, + +0x28, 0x74, +0x00, 0xE0, +0x0D, 0x44, 0x4C, 0xB0, + +0x05, 0x44, 0x54, 0xB0, +0x2D, 0x20, +0x9B, 0x10, + +0x82, 0x3E, 0x57, 0xE9, +0x32, 0xF0, 0x1B, 0xCD, + +0x1E, 0xBD, 0x59, 0x9F, +0x83, 0x1E, 0x57, 0xE9, + +0x38, 0x47, 0x38, 0xAF, +0x34, 0x20, +0x2A, 0x30, + +0x00, 0xE0, +0x0D, 0x20, +0x32, 0x20, +0x05, 0x20, + +0x87, 0x80, 0x57, 0xE9, +0x1F, 0x54, 0x57, 0x9F, + +0x17, 0x42, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x6A, + +0x3F, 0x8F, 0x51, 0x9F, +0x37, 0x1E, 0x4F, 0xE9, + +0x37, 0x32, 0x2A, 0xAF, +0x00, 0xE0, +0x32, 0x00, + +0x00, 0x80, 0x00, 0xE8, +0x27, 0xC0, 0x44, 0xC0, + +0x36, 0x1F, 0x4F, 0xE9, +0x1F, 0x1F, 0x26, 0xDF, + +0x37, 0x1B, 0x37, 0xBF, +0x17, 0x26, 0x17, 0xDF, + +0x3E, 0x17, 0x4F, 0xE9, +0x3F, 0x3F, 0x4F, 0xE9, + +0x34, 0x1F, 0x34, 0xAF, +0x2B, 0x05, +0xA7, 0x20, + +0x33, 0x2B, 0x37, 0xDF, +0x27, 0x17, 0xC0, 0xAF, + +0x34, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x2D, 0x21, 0x1A, 0xB0, +0x25, 0x21, 0x31, 0xB0, + +0x0D, 0x21, 0x1A, 0xB2, +0x05, 0x21, 0x31, 0xB2, + +0x03, 0x80, 0x2A, 0xEA, +0x17, 0xC1, 0x2B, 0xBD, + +0x2D, 0x20, +0x25, 0x20, +0x05, 0x20, +0x0D, 0x20, + +0xB3, 0x68, +0x97, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x33, 0xC0, 0x33, 0xAF, +0x2F, 0xC0, 0x21, 0xC0, + +0x16, 0x42, 0x56, 0x9F, +0x3C, 0x27, 0x4F, 0xE9, + +0x1E, 0x62, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x25, 0x21, 0x31, 0xB4, +0x2D, 0x21, 0x1A, 0xB4, + +0x3F, 0x2F, 0x5D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x33, 0x05, +0x00, 0xE0, +0x28, 0x19, 0x60, 0xEC, + +0x37, 0x0F, 0x5C, 0x9F, +0x00, 0xE0, +0x2F, 0x20, + +0x23, 0x3B, 0x33, 0xAD, +0x1E, 0x26, 0x1E, 0xDF, + +0xA7, 0x1E, 0x4F, 0xE9, +0x17, 0x26, 0x16, 0xDF, + +0x2D, 0x20, +0x00, 0xE0, +0xA8, 0x3F, 0x4F, 0xE9, + +0x2F, 0x2F, 0x1E, 0xAF, +0x25, 0x20, +0x00, 0xE0, + +0xA4, 0x16, 0x4F, 0xE9, +0x0F, 0xC0, 0x21, 0xC2, + +0xA6, 0x80, 0x4F, 0xE9, +0x1F, 0x62, 0x57, 0x9F, + +0x3F, 0x2F, 0x5D, 0x9F, +0x00, 0xE0, +0x8F, 0x20, + +0xA5, 0x37, 0x4F, 0xE9, +0x0F, 0x17, 0x0F, 0xAF, + +0x06, 0xC0, 0x21, 0xC4, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0xA3, 0x80, 0x4F, 0xE9, + +0x06, 0x20, +0x00, 0xE0, +0x1F, 0x26, 0x1F, 0xDF, + +0xA1, 0x1F, 0x4F, 0xE9, +0xA2, 0x3F, 0x4F, 0xE9, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x06, 0x06, 0x1F, 0xAF, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA0, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x57, 0x39, 0x20, 0xE9, + +0x16, 0x28, 0x20, 0xE9, +0x1D, 0x3B, 0x20, 0xE9, + +0x1E, 0x2B, 0x20, 0xE9, +0x2B, 0x32, 0x20, 0xE9, + +0x1C, 0x23, 0x20, 0xE9, +0x57, 0x36, 0x20, 0xE9, + +0x00, 0x80, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x90, 0xE2, +0x00, 0xE0, + +0x6C, 0xFF, 0x20, 0xEA, +0x19, 0xC8, 0xC1, 0xCD, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x9F, 0x41, 0x49, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x25, 0x41, 0x49, 0xBD, +0x2D, 0x41, 0x51, 0xBD, + +0x0D, 0x80, 0x07, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x35, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x25, 0x30, +0x2D, 0x30, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0xA7, 0x5B, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x6B, 0xFF, 0x0A, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0xC9, 0x41, 0xC8, 0xEC, +0x42, 0xE1, +0x00, 0xE0, + +0x69, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xC8, 0x40, 0xC0, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x66, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +}; + +static unsigned char warp_g200_tgzsa[] = { + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x98, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x81, 0x04, +0x89, 0x04, +0x01, 0x04, +0x09, 0x04, + +0xC9, 0x41, 0xC0, 0xEC, +0x11, 0x04, +0x00, 0xE0, + +0x41, 0xCC, 0x41, 0xCD, +0x49, 0xCC, 0x49, 0xCD, + +0xD1, 0x41, 0xC0, 0xEC, +0x51, 0xCC, 0x51, 0xCD, + +0x80, 0x04, +0x10, 0x04, +0x08, 0x04, +0x00, 0xE0, + +0x00, 0xCC, 0xC0, 0xCD, +0xD1, 0x49, 0xC0, 0xEC, + +0x8A, 0x1F, 0x20, 0xE9, +0x8B, 0x3F, 0x20, 0xE9, + +0x41, 0x3C, 0x41, 0xAD, +0x49, 0x3C, 0x49, 0xAD, + +0x10, 0xCC, 0x10, 0xCD, +0x08, 0xCC, 0x08, 0xCD, + +0xB9, 0x41, 0x49, 0xBB, +0x1F, 0xF0, 0x41, 0xCD, + +0x51, 0x3C, 0x51, 0xAD, +0x00, 0x98, 0x80, 0xE9, + +0x8F, 0x80, 0x07, 0xEA, +0x24, 0x1F, 0x20, 0xE9, + +0x21, 0x45, 0x80, 0xE8, +0x1A, 0x4D, 0x80, 0xE8, + +0x31, 0x55, 0x80, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0x41, 0x49, 0xBD, +0x1D, 0x41, 0x51, 0xBD, + +0x2E, 0x41, 0x2A, 0xB8, +0x34, 0x53, 0xA0, 0xE8, + +0x15, 0x30, +0x1D, 0x30, +0x58, 0xE3, +0x00, 0xE0, + +0xB5, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x24, 0x43, 0xA0, 0xE8, +0x2C, 0x4B, 0xA0, 0xE8, + +0x15, 0x72, +0x09, 0xE3, +0x00, 0xE0, +0x1D, 0x72, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0x97, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x6C, 0x64, 0xC8, 0xEC, +0x98, 0xE1, +0xB5, 0x05, + +0xBD, 0x05, +0x2E, 0x30, +0x32, 0xC0, 0xA0, 0xE8, + +0x33, 0xC0, 0xA0, 0xE8, +0x74, 0x64, 0xC8, 0xEC, + +0x40, 0x3C, 0x40, 0xAD, +0x32, 0x6A, +0x2A, 0x30, + +0x20, 0x73, +0x33, 0x6A, +0x00, 0xE0, +0x28, 0x73, + +0x1C, 0x72, +0x83, 0xE2, +0x7B, 0x80, 0x15, 0xEA, + +0xB8, 0x3D, 0x28, 0xDF, +0x30, 0x35, 0x20, 0xDF, + +0x40, 0x30, +0x00, 0xE0, +0xCC, 0xE2, +0x64, 0x72, + +0x25, 0x42, 0x52, 0xBF, +0x2D, 0x42, 0x4A, 0xBF, + +0x30, 0x2E, 0x30, 0xDF, +0x38, 0x2E, 0x38, 0xDF, + +0x18, 0x1D, 0x45, 0xE9, +0x1E, 0x15, 0x45, 0xE9, + +0x2B, 0x49, 0x51, 0xBD, +0x00, 0xE0, +0x1F, 0x73, + +0x38, 0x38, 0x40, 0xAF, +0x30, 0x30, 0x40, 0xAF, + +0x24, 0x1F, 0x24, 0xDF, +0x1D, 0x32, 0x20, 0xE9, + +0x2C, 0x1F, 0x2C, 0xDF, +0x1A, 0x33, 0x20, 0xE9, + +0xB0, 0x10, +0x08, 0xE3, +0x40, 0x10, +0xB8, 0x10, + +0x26, 0xF0, 0x30, 0xCD, +0x2F, 0xF0, 0x38, 0xCD, + +0x2B, 0x80, 0x20, 0xE9, +0x2A, 0x80, 0x20, 0xE9, + +0xA6, 0x20, +0x88, 0xE2, +0x00, 0xE0, +0xAF, 0x20, + +0x28, 0x2A, 0x26, 0xAF, +0x20, 0x2A, 0xC0, 0xAF, + +0x34, 0x1F, 0x34, 0xDF, +0x46, 0x24, 0x46, 0xDF, + +0x28, 0x30, 0x80, 0xBF, +0x20, 0x38, 0x80, 0xBF, + +0x47, 0x24, 0x47, 0xDF, +0x4E, 0x2C, 0x4E, 0xDF, + +0x4F, 0x2C, 0x4F, 0xDF, +0x56, 0x34, 0x56, 0xDF, + +0x28, 0x15, 0x28, 0xDF, +0x20, 0x1D, 0x20, 0xDF, + +0x57, 0x34, 0x57, 0xDF, +0x00, 0xE0, +0x1D, 0x05, + +0x04, 0x80, 0x10, 0xEA, +0x89, 0xE2, +0x2B, 0x30, + +0x3F, 0xC1, 0x1D, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA0, 0x68, +0xBF, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x20, 0xC0, 0x20, 0xAF, +0x28, 0x05, +0x97, 0x74, + +0x00, 0xE0, +0x2A, 0x10, +0x16, 0xC0, 0x20, 0xE9, + +0x04, 0x80, 0x10, 0xEA, +0x8C, 0xE2, +0x95, 0x05, + +0x28, 0xC1, 0x28, 0xAD, +0x1F, 0xC1, 0x15, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA8, 0x67, +0x9F, 0x6B, +0x00, 0x80, 0x00, 0xE8, + +0x28, 0xC0, 0x28, 0xAD, +0x1D, 0x25, +0x20, 0x05, + +0x28, 0x32, 0x80, 0xAD, +0x40, 0x2A, 0x40, 0xBD, + +0x1C, 0x80, 0x20, 0xE9, +0x20, 0x33, 0x20, 0xAD, + +0x20, 0x73, +0x00, 0xE0, +0xB6, 0x49, 0x51, 0xBB, + +0x26, 0x2F, 0xB0, 0xE8, +0x19, 0x20, 0x20, 0xE9, + +0x35, 0x20, 0x35, 0xDF, +0x3D, 0x20, 0x3D, 0xDF, + +0x15, 0x20, 0x15, 0xDF, +0x1D, 0x20, 0x1D, 0xDF, + +0x26, 0xD0, 0x26, 0xCD, +0x29, 0x49, 0x2A, 0xB8, + +0x26, 0x40, 0x80, 0xBD, +0x3B, 0x48, 0x50, 0xBD, + +0x3E, 0x54, 0x57, 0x9F, +0x00, 0xE0, +0x82, 0xE1, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x26, 0x30, +0x29, 0x30, +0x48, 0x3C, 0x48, 0xAD, + +0x2B, 0x72, +0xC2, 0xE1, +0x2C, 0xC0, 0x44, 0xC2, + +0x05, 0x24, 0x34, 0xBF, +0x0D, 0x24, 0x2C, 0xBF, + +0x2D, 0x46, 0x4E, 0xBF, +0x25, 0x46, 0x56, 0xBF, + +0x20, 0x1D, 0x6F, 0x8F, +0x32, 0x3E, 0x5F, 0xE9, + +0x3E, 0x50, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x30, + +0x1E, 0x8F, 0x51, 0x9F, +0x33, 0x1E, 0x5F, 0xE9, + +0x05, 0x44, 0x54, 0xB2, +0x0D, 0x44, 0x4C, 0xB2, + +0x19, 0xC0, 0xB0, 0xE8, +0x34, 0xC0, 0x44, 0xC4, + +0x33, 0x73, +0x00, 0xE0, +0x3E, 0x62, 0x57, 0x9F, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0xE0, +0x0D, 0x20, + +0x84, 0x3E, 0x58, 0xE9, +0x28, 0x1D, 0x6F, 0x8F, + +0x05, 0x20, +0x00, 0xE0, +0x85, 0x1E, 0x58, 0xE9, + +0x9B, 0x3B, 0x33, 0xDF, +0x20, 0x20, 0x42, 0xAF, + +0x30, 0x42, 0x56, 0x9F, +0x80, 0x3E, 0x57, 0xE9, + +0x3F, 0x8F, 0x51, 0x9F, +0x30, 0x80, 0x5F, 0xE9, + +0x28, 0x28, 0x24, 0xAF, +0x81, 0x1E, 0x57, 0xE9, + +0x05, 0x47, 0x57, 0xBF, +0x0D, 0x47, 0x4F, 0xBF, + +0x88, 0x80, 0x58, 0xE9, +0x1B, 0x29, 0x1B, 0xDF, + +0x30, 0x1D, 0x6F, 0x8F, +0x3A, 0x30, 0x4F, 0xE9, + +0x1C, 0x30, 0x26, 0xDF, +0x09, 0xE3, +0x3B, 0x05, + +0x3E, 0x50, 0x56, 0x9F, +0x3B, 0x3F, 0x4F, 0xE9, + +0x1E, 0x8F, 0x51, 0x9F, +0x00, 0xE0, +0xAC, 0x20, + +0x2D, 0x44, 0x4C, 0xB4, +0x2C, 0x1C, 0xC0, 0xAF, + +0x25, 0x44, 0x54, 0xB4, +0x00, 0xE0, +0xC8, 0x30, + +0x30, 0x46, 0x30, 0xAF, +0x1B, 0x1B, 0x48, 0xAF, + +0x00, 0xE0, +0x25, 0x20, +0x38, 0x2C, 0x4F, 0xE9, + +0x86, 0x80, 0x57, 0xE9, +0x38, 0x1D, 0x6F, 0x8F, + +0x28, 0x74, +0x00, 0xE0, +0x0D, 0x44, 0x4C, 0xB0, + +0x05, 0x44, 0x54, 0xB0, +0x2D, 0x20, +0x9B, 0x10, + +0x82, 0x3E, 0x57, 0xE9, +0x32, 0xF0, 0x1B, 0xCD, + +0x1E, 0xBD, 0x59, 0x9F, +0x83, 0x1E, 0x57, 0xE9, + +0x38, 0x47, 0x38, 0xAF, +0x34, 0x20, +0x2A, 0x30, + +0x00, 0xE0, +0x0D, 0x20, +0x32, 0x20, +0x05, 0x20, + +0x87, 0x80, 0x57, 0xE9, +0x1F, 0x54, 0x57, 0x9F, + +0x17, 0x42, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x6A, + +0x3F, 0x8F, 0x51, 0x9F, +0x37, 0x1E, 0x4F, 0xE9, + +0x37, 0x32, 0x2A, 0xAF, +0x00, 0xE0, +0x32, 0x00, + +0x00, 0x80, 0x00, 0xE8, +0x27, 0xC0, 0x44, 0xC0, + +0x36, 0x1F, 0x4F, 0xE9, +0x1F, 0x1F, 0x26, 0xDF, + +0x37, 0x1B, 0x37, 0xBF, +0x17, 0x26, 0x17, 0xDF, + +0x3E, 0x17, 0x4F, 0xE9, +0x3F, 0x3F, 0x4F, 0xE9, + +0x34, 0x1F, 0x34, 0xAF, +0x2B, 0x05, +0xA7, 0x20, + +0x33, 0x2B, 0x37, 0xDF, +0x27, 0x17, 0xC0, 0xAF, + +0x34, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x2D, 0x21, 0x1A, 0xB0, +0x25, 0x21, 0x31, 0xB0, + +0x0D, 0x21, 0x1A, 0xB2, +0x05, 0x21, 0x31, 0xB2, + +0x03, 0x80, 0x2A, 0xEA, +0x17, 0xC1, 0x2B, 0xBD, + +0x2D, 0x20, +0x25, 0x20, +0x05, 0x20, +0x0D, 0x20, + +0xB3, 0x68, +0x97, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x33, 0xC0, 0x33, 0xAF, +0x2F, 0xC0, 0x21, 0xC0, + +0x16, 0x42, 0x56, 0x9F, +0x3C, 0x27, 0x4F, 0xE9, + +0x1E, 0x62, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x25, 0x21, 0x31, 0xB4, +0x2D, 0x21, 0x1A, 0xB4, + +0x3F, 0x2F, 0x5D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x33, 0x05, +0x00, 0xE0, +0x28, 0x19, 0x60, 0xEC, + +0x0D, 0x44, 0x4C, 0xB6, +0x05, 0x44, 0x54, 0xB6, + +0x37, 0x0F, 0x5C, 0x9F, +0x00, 0xE0, +0x2F, 0x20, + +0x23, 0x3B, 0x33, 0xAD, +0x1E, 0x26, 0x1E, 0xDF, + +0xA7, 0x1E, 0x4F, 0xE9, +0x17, 0x26, 0x16, 0xDF, + +0x2D, 0x20, +0x00, 0xE0, +0xA8, 0x3F, 0x4F, 0xE9, + +0x2F, 0x2F, 0x1E, 0xAF, +0x25, 0x20, +0x00, 0xE0, + +0xA4, 0x16, 0x4F, 0xE9, +0x0F, 0xC0, 0x21, 0xC2, + +0xA6, 0x80, 0x4F, 0xE9, +0x1F, 0x62, 0x57, 0x9F, + +0x0D, 0x20, +0x05, 0x20, +0x00, 0x80, 0x00, 0xE8, + +0x3F, 0x2F, 0x5D, 0x9F, +0x00, 0xE0, +0x0F, 0x20, + +0x17, 0x50, 0x56, 0x9F, +0xA5, 0x37, 0x4F, 0xE9, + +0x06, 0xC0, 0x21, 0xC4, +0x0F, 0x17, 0x0F, 0xAF, + +0x37, 0x0F, 0x5C, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x2F, 0xC0, 0x44, 0xC6, +0xA3, 0x80, 0x4F, 0xE9, + +0x06, 0x20, +0x00, 0xE0, +0x1F, 0x26, 0x1F, 0xDF, + +0x17, 0x26, 0x17, 0xDF, +0x9D, 0x17, 0x4F, 0xE9, + +0xA1, 0x1F, 0x4F, 0xE9, +0xA2, 0x3F, 0x4F, 0xE9, + +0x06, 0x06, 0x1F, 0xAF, +0x00, 0xE0, +0xAF, 0x20, + +0x9E, 0x37, 0x4F, 0xE9, +0x2F, 0x17, 0x2F, 0xAF, + +0xA0, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x9C, 0x80, 0x4F, 0xE9, + +0x00, 0x80, 0x00, 0xE8, +0x57, 0x39, 0x20, 0xE9, + +0x16, 0x28, 0x20, 0xE9, +0x1D, 0x3B, 0x20, 0xE9, + +0x1E, 0x2B, 0x20, 0xE9, +0x2B, 0x32, 0x20, 0xE9, + +0x1C, 0x23, 0x20, 0xE9, +0x57, 0x36, 0x20, 0xE9, + +0x00, 0x80, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x90, 0xE2, +0x00, 0xE0, + +0x68, 0xFF, 0x20, 0xEA, +0x19, 0xC8, 0xC1, 0xCD, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x9F, 0x41, 0x49, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x25, 0x41, 0x49, 0xBD, +0x2D, 0x41, 0x51, 0xBD, + +0x0D, 0x80, 0x07, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x35, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x25, 0x30, +0x2D, 0x30, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0xA7, 0x5B, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x67, 0xFF, 0x0A, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0xC9, 0x41, 0xC8, 0xEC, +0x42, 0xE1, +0x00, 0xE0, + +0x65, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xC8, 0x40, 0xC0, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x62, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +}; + +static unsigned char warp_g200_tgzsaf[] = { + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x98, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x81, 0x04, +0x89, 0x04, +0x01, 0x04, +0x09, 0x04, + +0xC9, 0x41, 0xC0, 0xEC, +0x11, 0x04, +0x00, 0xE0, + +0x41, 0xCC, 0x41, 0xCD, +0x49, 0xCC, 0x49, 0xCD, + +0xD1, 0x41, 0xC0, 0xEC, +0x51, 0xCC, 0x51, 0xCD, + +0x80, 0x04, +0x10, 0x04, +0x08, 0x04, +0x00, 0xE0, + +0x00, 0xCC, 0xC0, 0xCD, +0xD1, 0x49, 0xC0, 0xEC, + +0x8A, 0x1F, 0x20, 0xE9, +0x8B, 0x3F, 0x20, 0xE9, + +0x41, 0x3C, 0x41, 0xAD, +0x49, 0x3C, 0x49, 0xAD, + +0x10, 0xCC, 0x10, 0xCD, +0x08, 0xCC, 0x08, 0xCD, + +0xB9, 0x41, 0x49, 0xBB, +0x1F, 0xF0, 0x41, 0xCD, + +0x51, 0x3C, 0x51, 0xAD, +0x00, 0x98, 0x80, 0xE9, + +0x94, 0x80, 0x07, 0xEA, +0x24, 0x1F, 0x20, 0xE9, + +0x21, 0x45, 0x80, 0xE8, +0x1A, 0x4D, 0x80, 0xE8, + +0x31, 0x55, 0x80, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0x41, 0x49, 0xBD, +0x1D, 0x41, 0x51, 0xBD, + +0x2E, 0x41, 0x2A, 0xB8, +0x34, 0x53, 0xA0, 0xE8, + +0x15, 0x30, +0x1D, 0x30, +0x58, 0xE3, +0x00, 0xE0, + +0xB5, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x24, 0x43, 0xA0, 0xE8, +0x2C, 0x4B, 0xA0, 0xE8, + +0x15, 0x72, +0x09, 0xE3, +0x00, 0xE0, +0x1D, 0x72, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0x97, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x6C, 0x64, 0xC8, 0xEC, +0x98, 0xE1, +0xB5, 0x05, + +0xBD, 0x05, +0x2E, 0x30, +0x32, 0xC0, 0xA0, 0xE8, + +0x33, 0xC0, 0xA0, 0xE8, +0x74, 0x64, 0xC8, 0xEC, + +0x40, 0x3C, 0x40, 0xAD, +0x32, 0x6A, +0x2A, 0x30, + +0x20, 0x73, +0x33, 0x6A, +0x00, 0xE0, +0x28, 0x73, + +0x1C, 0x72, +0x83, 0xE2, +0x80, 0x80, 0x15, 0xEA, + +0xB8, 0x3D, 0x28, 0xDF, +0x30, 0x35, 0x20, 0xDF, + +0x40, 0x30, +0x00, 0xE0, +0xCC, 0xE2, +0x64, 0x72, + +0x25, 0x42, 0x52, 0xBF, +0x2D, 0x42, 0x4A, 0xBF, + +0x30, 0x2E, 0x30, 0xDF, +0x38, 0x2E, 0x38, 0xDF, + +0x18, 0x1D, 0x45, 0xE9, +0x1E, 0x15, 0x45, 0xE9, + +0x2B, 0x49, 0x51, 0xBD, +0x00, 0xE0, +0x1F, 0x73, + +0x38, 0x38, 0x40, 0xAF, +0x30, 0x30, 0x40, 0xAF, + +0x24, 0x1F, 0x24, 0xDF, +0x1D, 0x32, 0x20, 0xE9, + +0x2C, 0x1F, 0x2C, 0xDF, +0x1A, 0x33, 0x20, 0xE9, + +0xB0, 0x10, +0x08, 0xE3, +0x40, 0x10, +0xB8, 0x10, + +0x26, 0xF0, 0x30, 0xCD, +0x2F, 0xF0, 0x38, 0xCD, + +0x2B, 0x80, 0x20, 0xE9, +0x2A, 0x80, 0x20, 0xE9, + +0xA6, 0x20, +0x88, 0xE2, +0x00, 0xE0, +0xAF, 0x20, + +0x28, 0x2A, 0x26, 0xAF, +0x20, 0x2A, 0xC0, 0xAF, + +0x34, 0x1F, 0x34, 0xDF, +0x46, 0x24, 0x46, 0xDF, + +0x28, 0x30, 0x80, 0xBF, +0x20, 0x38, 0x80, 0xBF, + +0x47, 0x24, 0x47, 0xDF, +0x4E, 0x2C, 0x4E, 0xDF, + +0x4F, 0x2C, 0x4F, 0xDF, +0x56, 0x34, 0x56, 0xDF, + +0x28, 0x15, 0x28, 0xDF, +0x20, 0x1D, 0x20, 0xDF, + +0x57, 0x34, 0x57, 0xDF, +0x00, 0xE0, +0x1D, 0x05, + +0x04, 0x80, 0x10, 0xEA, +0x89, 0xE2, +0x2B, 0x30, + +0x3F, 0xC1, 0x1D, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA0, 0x68, +0xBF, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x20, 0xC0, 0x20, 0xAF, +0x28, 0x05, +0x97, 0x74, + +0x00, 0xE0, +0x2A, 0x10, +0x16, 0xC0, 0x20, 0xE9, + +0x04, 0x80, 0x10, 0xEA, +0x8C, 0xE2, +0x95, 0x05, + +0x28, 0xC1, 0x28, 0xAD, +0x1F, 0xC1, 0x15, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA8, 0x67, +0x9F, 0x6B, +0x00, 0x80, 0x00, 0xE8, + +0x28, 0xC0, 0x28, 0xAD, +0x1D, 0x25, +0x20, 0x05, + +0x28, 0x32, 0x80, 0xAD, +0x40, 0x2A, 0x40, 0xBD, + +0x1C, 0x80, 0x20, 0xE9, +0x20, 0x33, 0x20, 0xAD, + +0x20, 0x73, +0x00, 0xE0, +0xB6, 0x49, 0x51, 0xBB, + +0x26, 0x2F, 0xB0, 0xE8, +0x19, 0x20, 0x20, 0xE9, + +0x35, 0x20, 0x35, 0xDF, +0x3D, 0x20, 0x3D, 0xDF, + +0x15, 0x20, 0x15, 0xDF, +0x1D, 0x20, 0x1D, 0xDF, + +0x26, 0xD0, 0x26, 0xCD, +0x29, 0x49, 0x2A, 0xB8, + +0x26, 0x40, 0x80, 0xBD, +0x3B, 0x48, 0x50, 0xBD, + +0x3E, 0x54, 0x57, 0x9F, +0x00, 0xE0, +0x82, 0xE1, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x26, 0x30, +0x29, 0x30, +0x48, 0x3C, 0x48, 0xAD, + +0x2B, 0x72, +0xC2, 0xE1, +0x2C, 0xC0, 0x44, 0xC2, + +0x05, 0x24, 0x34, 0xBF, +0x0D, 0x24, 0x2C, 0xBF, + +0x2D, 0x46, 0x4E, 0xBF, +0x25, 0x46, 0x56, 0xBF, + +0x20, 0x1D, 0x6F, 0x8F, +0x32, 0x3E, 0x5F, 0xE9, + +0x3E, 0x50, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x30, + +0x1E, 0x8F, 0x51, 0x9F, +0x33, 0x1E, 0x5F, 0xE9, + +0x05, 0x44, 0x54, 0xB2, +0x0D, 0x44, 0x4C, 0xB2, + +0x19, 0xC0, 0xB0, 0xE8, +0x34, 0xC0, 0x44, 0xC4, + +0x33, 0x73, +0x00, 0xE0, +0x3E, 0x62, 0x57, 0x9F, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0xE0, +0x0D, 0x20, + +0x84, 0x3E, 0x58, 0xE9, +0x28, 0x1D, 0x6F, 0x8F, + +0x05, 0x20, +0x00, 0xE0, +0x85, 0x1E, 0x58, 0xE9, + +0x9B, 0x3B, 0x33, 0xDF, +0x20, 0x20, 0x42, 0xAF, + +0x30, 0x42, 0x56, 0x9F, +0x80, 0x3E, 0x57, 0xE9, + +0x3F, 0x8F, 0x51, 0x9F, +0x30, 0x80, 0x5F, 0xE9, + +0x28, 0x28, 0x24, 0xAF, +0x81, 0x1E, 0x57, 0xE9, + +0x05, 0x47, 0x57, 0xBF, +0x0D, 0x47, 0x4F, 0xBF, + +0x88, 0x80, 0x58, 0xE9, +0x1B, 0x29, 0x1B, 0xDF, + +0x30, 0x1D, 0x6F, 0x8F, +0x3A, 0x30, 0x4F, 0xE9, + +0x1C, 0x30, 0x26, 0xDF, +0x09, 0xE3, +0x3B, 0x05, + +0x3E, 0x50, 0x56, 0x9F, +0x3B, 0x3F, 0x4F, 0xE9, + +0x1E, 0x8F, 0x51, 0x9F, +0x00, 0xE0, +0xAC, 0x20, + +0x2D, 0x44, 0x4C, 0xB4, +0x2C, 0x1C, 0xC0, 0xAF, + +0x25, 0x44, 0x54, 0xB4, +0x00, 0xE0, +0xC8, 0x30, + +0x30, 0x46, 0x30, 0xAF, +0x1B, 0x1B, 0x48, 0xAF, + +0x00, 0xE0, +0x25, 0x20, +0x38, 0x2C, 0x4F, 0xE9, + +0x86, 0x80, 0x57, 0xE9, +0x38, 0x1D, 0x6F, 0x8F, + +0x28, 0x74, +0x00, 0xE0, +0x0D, 0x44, 0x4C, 0xB0, + +0x05, 0x44, 0x54, 0xB0, +0x2D, 0x20, +0x9B, 0x10, + +0x82, 0x3E, 0x57, 0xE9, +0x32, 0xF0, 0x1B, 0xCD, + +0x1E, 0xBD, 0x59, 0x9F, +0x83, 0x1E, 0x57, 0xE9, + +0x38, 0x47, 0x38, 0xAF, +0x34, 0x20, +0x2A, 0x30, + +0x00, 0xE0, +0x0D, 0x20, +0x32, 0x20, +0x05, 0x20, + +0x87, 0x80, 0x57, 0xE9, +0x1F, 0x54, 0x57, 0x9F, + +0x17, 0x42, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x6A, + +0x3F, 0x8F, 0x51, 0x9F, +0x37, 0x1E, 0x4F, 0xE9, + +0x37, 0x32, 0x2A, 0xAF, +0x00, 0xE0, +0x32, 0x00, + +0x00, 0x80, 0x00, 0xE8, +0x27, 0xC0, 0x44, 0xC0, + +0x36, 0x1F, 0x4F, 0xE9, +0x1F, 0x1F, 0x26, 0xDF, + +0x37, 0x1B, 0x37, 0xBF, +0x17, 0x26, 0x17, 0xDF, + +0x3E, 0x17, 0x4F, 0xE9, +0x3F, 0x3F, 0x4F, 0xE9, + +0x34, 0x1F, 0x34, 0xAF, +0x2B, 0x05, +0xA7, 0x20, + +0x33, 0x2B, 0x37, 0xDF, +0x27, 0x17, 0xC0, 0xAF, + +0x34, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x2D, 0x21, 0x1A, 0xB0, +0x25, 0x21, 0x31, 0xB0, + +0x0D, 0x21, 0x1A, 0xB2, +0x05, 0x21, 0x31, 0xB2, + +0x03, 0x80, 0x2A, 0xEA, +0x17, 0xC1, 0x2B, 0xBD, + +0x2D, 0x20, +0x25, 0x20, +0x05, 0x20, +0x0D, 0x20, + +0xB3, 0x68, +0x97, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x33, 0xC0, 0x33, 0xAF, +0x2F, 0xC0, 0x21, 0xC0, + +0x16, 0x42, 0x56, 0x9F, +0x3C, 0x27, 0x4F, 0xE9, + +0x1E, 0x62, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x25, 0x21, 0x31, 0xB4, +0x2D, 0x21, 0x1A, 0xB4, + +0x3F, 0x2F, 0x5D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x33, 0x05, +0x00, 0xE0, +0x28, 0x19, 0x60, 0xEC, + +0x0D, 0x21, 0x1A, 0xB6, +0x05, 0x21, 0x31, 0xB6, + +0x37, 0x0F, 0x5C, 0x9F, +0x00, 0xE0, +0x2F, 0x20, + +0x23, 0x3B, 0x33, 0xAD, +0x1E, 0x26, 0x1E, 0xDF, + +0xA7, 0x1E, 0x4F, 0xE9, +0x17, 0x26, 0x16, 0xDF, + +0x2D, 0x20, +0x00, 0xE0, +0xA8, 0x3F, 0x4F, 0xE9, + +0x2F, 0x2F, 0x1E, 0xAF, +0x25, 0x20, +0x00, 0xE0, + +0xA4, 0x16, 0x4F, 0xE9, +0x0F, 0xC0, 0x21, 0xC2, + +0xA6, 0x80, 0x4F, 0xE9, +0x1F, 0x62, 0x57, 0x9F, + +0x0D, 0x20, +0x05, 0x20, +0x2F, 0xC0, 0x21, 0xC6, + +0x2D, 0x44, 0x4C, 0xB6, +0x25, 0x44, 0x54, 0xB6, + +0x3F, 0x2F, 0x5D, 0x9F, +0x00, 0xE0, +0x0F, 0x20, + +0x2D, 0x20, +0x25, 0x20, +0x07, 0xC0, 0x44, 0xC6, + +0x17, 0x50, 0x56, 0x9F, +0xA5, 0x37, 0x4F, 0xE9, + +0x06, 0xC0, 0x21, 0xC4, +0x0F, 0x17, 0x0F, 0xAF, + +0x37, 0x0F, 0x5C, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x1E, 0x62, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x3E, 0x3D, 0x5D, 0x9F, +0x00, 0xE0, +0x07, 0x20, + +0x2F, 0x20, +0x00, 0xE0, +0xA3, 0x0F, 0x4F, 0xE9, + +0x06, 0x20, +0x00, 0xE0, +0x1F, 0x26, 0x1F, 0xDF, + +0x17, 0x26, 0x17, 0xDF, +0xA1, 0x1F, 0x4F, 0xE9, + +0x1E, 0x26, 0x1E, 0xDF, +0x9D, 0x1E, 0x4F, 0xE9, + +0x35, 0x17, 0x4F, 0xE9, +0xA2, 0x3F, 0x4F, 0xE9, + +0x06, 0x06, 0x1F, 0xAF, +0x39, 0x37, 0x4F, 0xE9, + +0x2F, 0x2F, 0x17, 0xAF, +0x07, 0x07, 0x1E, 0xAF, + +0xA0, 0x80, 0x4F, 0xE9, +0x9E, 0x3E, 0x4F, 0xE9, + +0x31, 0x80, 0x4F, 0xE9, +0x9C, 0x80, 0x4F, 0xE9, + +0x00, 0x80, 0x00, 0xE8, +0x57, 0x39, 0x20, 0xE9, + +0x16, 0x28, 0x20, 0xE9, +0x1D, 0x3B, 0x20, 0xE9, + +0x1E, 0x2B, 0x20, 0xE9, +0x2B, 0x32, 0x20, 0xE9, + +0x1C, 0x23, 0x20, 0xE9, +0x57, 0x36, 0x20, 0xE9, + +0x00, 0x80, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x90, 0xE2, +0x00, 0xE0, + +0x63, 0xFF, 0x20, 0xEA, +0x19, 0xC8, 0xC1, 0xCD, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x9F, 0x41, 0x49, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x25, 0x41, 0x49, 0xBD, +0x2D, 0x41, 0x51, 0xBD, + +0x0D, 0x80, 0x07, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x35, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x25, 0x30, +0x2D, 0x30, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0xA7, 0x5B, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x62, 0xFF, 0x0A, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0xC9, 0x41, 0xC8, 0xEC, +0x42, 0xE1, +0x00, 0xE0, + +0x60, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xC8, 0x40, 0xC0, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x5D, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +}; + +static unsigned char warp_g200_tgzsf[] = { + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x98, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x81, 0x04, +0x89, 0x04, +0x01, 0x04, +0x09, 0x04, + +0xC9, 0x41, 0xC0, 0xEC, +0x11, 0x04, +0x00, 0xE0, + +0x41, 0xCC, 0x41, 0xCD, +0x49, 0xCC, 0x49, 0xCD, + +0xD1, 0x41, 0xC0, 0xEC, +0x51, 0xCC, 0x51, 0xCD, + +0x80, 0x04, +0x10, 0x04, +0x08, 0x04, +0x00, 0xE0, + +0x00, 0xCC, 0xC0, 0xCD, +0xD1, 0x49, 0xC0, 0xEC, + +0x8A, 0x1F, 0x20, 0xE9, +0x8B, 0x3F, 0x20, 0xE9, + +0x41, 0x3C, 0x41, 0xAD, +0x49, 0x3C, 0x49, 0xAD, + +0x10, 0xCC, 0x10, 0xCD, +0x08, 0xCC, 0x08, 0xCD, + +0xB9, 0x41, 0x49, 0xBB, +0x1F, 0xF0, 0x41, 0xCD, + +0x51, 0x3C, 0x51, 0xAD, +0x00, 0x98, 0x80, 0xE9, + +0x8F, 0x80, 0x07, 0xEA, +0x24, 0x1F, 0x20, 0xE9, + +0x21, 0x45, 0x80, 0xE8, +0x1A, 0x4D, 0x80, 0xE8, + +0x31, 0x55, 0x80, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0x41, 0x49, 0xBD, +0x1D, 0x41, 0x51, 0xBD, + +0x2E, 0x41, 0x2A, 0xB8, +0x34, 0x53, 0xA0, 0xE8, + +0x15, 0x30, +0x1D, 0x30, +0x58, 0xE3, +0x00, 0xE0, + +0xB5, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x24, 0x43, 0xA0, 0xE8, +0x2C, 0x4B, 0xA0, 0xE8, + +0x15, 0x72, +0x09, 0xE3, +0x00, 0xE0, +0x1D, 0x72, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0x97, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x6C, 0x64, 0xC8, 0xEC, +0x98, 0xE1, +0xB5, 0x05, + +0xBD, 0x05, +0x2E, 0x30, +0x32, 0xC0, 0xA0, 0xE8, + +0x33, 0xC0, 0xA0, 0xE8, +0x74, 0x64, 0xC8, 0xEC, + +0x40, 0x3C, 0x40, 0xAD, +0x32, 0x6A, +0x2A, 0x30, + +0x20, 0x73, +0x33, 0x6A, +0x00, 0xE0, +0x28, 0x73, + +0x1C, 0x72, +0x83, 0xE2, +0x7B, 0x80, 0x15, 0xEA, + +0xB8, 0x3D, 0x28, 0xDF, +0x30, 0x35, 0x20, 0xDF, + +0x40, 0x30, +0x00, 0xE0, +0xCC, 0xE2, +0x64, 0x72, + +0x25, 0x42, 0x52, 0xBF, +0x2D, 0x42, 0x4A, 0xBF, + +0x30, 0x2E, 0x30, 0xDF, +0x38, 0x2E, 0x38, 0xDF, + +0x18, 0x1D, 0x45, 0xE9, +0x1E, 0x15, 0x45, 0xE9, + +0x2B, 0x49, 0x51, 0xBD, +0x00, 0xE0, +0x1F, 0x73, + +0x38, 0x38, 0x40, 0xAF, +0x30, 0x30, 0x40, 0xAF, + +0x24, 0x1F, 0x24, 0xDF, +0x1D, 0x32, 0x20, 0xE9, + +0x2C, 0x1F, 0x2C, 0xDF, +0x1A, 0x33, 0x20, 0xE9, + +0xB0, 0x10, +0x08, 0xE3, +0x40, 0x10, +0xB8, 0x10, + +0x26, 0xF0, 0x30, 0xCD, +0x2F, 0xF0, 0x38, 0xCD, + +0x2B, 0x80, 0x20, 0xE9, +0x2A, 0x80, 0x20, 0xE9, + +0xA6, 0x20, +0x88, 0xE2, +0x00, 0xE0, +0xAF, 0x20, + +0x28, 0x2A, 0x26, 0xAF, +0x20, 0x2A, 0xC0, 0xAF, + +0x34, 0x1F, 0x34, 0xDF, +0x46, 0x24, 0x46, 0xDF, + +0x28, 0x30, 0x80, 0xBF, +0x20, 0x38, 0x80, 0xBF, + +0x47, 0x24, 0x47, 0xDF, +0x4E, 0x2C, 0x4E, 0xDF, + +0x4F, 0x2C, 0x4F, 0xDF, +0x56, 0x34, 0x56, 0xDF, + +0x28, 0x15, 0x28, 0xDF, +0x20, 0x1D, 0x20, 0xDF, + +0x57, 0x34, 0x57, 0xDF, +0x00, 0xE0, +0x1D, 0x05, + +0x04, 0x80, 0x10, 0xEA, +0x89, 0xE2, +0x2B, 0x30, + +0x3F, 0xC1, 0x1D, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA0, 0x68, +0xBF, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x20, 0xC0, 0x20, 0xAF, +0x28, 0x05, +0x97, 0x74, + +0x00, 0xE0, +0x2A, 0x10, +0x16, 0xC0, 0x20, 0xE9, + +0x04, 0x80, 0x10, 0xEA, +0x8C, 0xE2, +0x95, 0x05, + +0x28, 0xC1, 0x28, 0xAD, +0x1F, 0xC1, 0x15, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xA8, 0x67, +0x9F, 0x6B, +0x00, 0x80, 0x00, 0xE8, + +0x28, 0xC0, 0x28, 0xAD, +0x1D, 0x25, +0x20, 0x05, + +0x28, 0x32, 0x80, 0xAD, +0x40, 0x2A, 0x40, 0xBD, + +0x1C, 0x80, 0x20, 0xE9, +0x20, 0x33, 0x20, 0xAD, + +0x20, 0x73, +0x00, 0xE0, +0xB6, 0x49, 0x51, 0xBB, + +0x26, 0x2F, 0xB0, 0xE8, +0x19, 0x20, 0x20, 0xE9, + +0x35, 0x20, 0x35, 0xDF, +0x3D, 0x20, 0x3D, 0xDF, + +0x15, 0x20, 0x15, 0xDF, +0x1D, 0x20, 0x1D, 0xDF, + +0x26, 0xD0, 0x26, 0xCD, +0x29, 0x49, 0x2A, 0xB8, + +0x26, 0x40, 0x80, 0xBD, +0x3B, 0x48, 0x50, 0xBD, + +0x3E, 0x54, 0x57, 0x9F, +0x00, 0xE0, +0x82, 0xE1, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x26, 0x30, +0x29, 0x30, +0x48, 0x3C, 0x48, 0xAD, + +0x2B, 0x72, +0xC2, 0xE1, +0x2C, 0xC0, 0x44, 0xC2, + +0x05, 0x24, 0x34, 0xBF, +0x0D, 0x24, 0x2C, 0xBF, + +0x2D, 0x46, 0x4E, 0xBF, +0x25, 0x46, 0x56, 0xBF, + +0x20, 0x1D, 0x6F, 0x8F, +0x32, 0x3E, 0x5F, 0xE9, + +0x3E, 0x50, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x30, + +0x1E, 0x8F, 0x51, 0x9F, +0x33, 0x1E, 0x5F, 0xE9, + +0x05, 0x44, 0x54, 0xB2, +0x0D, 0x44, 0x4C, 0xB2, + +0x19, 0xC0, 0xB0, 0xE8, +0x34, 0xC0, 0x44, 0xC4, + +0x33, 0x73, +0x00, 0xE0, +0x3E, 0x62, 0x57, 0x9F, + +0x1E, 0xAF, 0x59, 0x9F, +0x00, 0xE0, +0x0D, 0x20, + +0x84, 0x3E, 0x58, 0xE9, +0x28, 0x1D, 0x6F, 0x8F, + +0x05, 0x20, +0x00, 0xE0, +0x85, 0x1E, 0x58, 0xE9, + +0x9B, 0x3B, 0x33, 0xDF, +0x20, 0x20, 0x42, 0xAF, + +0x30, 0x42, 0x56, 0x9F, +0x80, 0x3E, 0x57, 0xE9, + +0x3F, 0x8F, 0x51, 0x9F, +0x30, 0x80, 0x5F, 0xE9, + +0x28, 0x28, 0x24, 0xAF, +0x81, 0x1E, 0x57, 0xE9, + +0x05, 0x47, 0x57, 0xBF, +0x0D, 0x47, 0x4F, 0xBF, + +0x88, 0x80, 0x58, 0xE9, +0x1B, 0x29, 0x1B, 0xDF, + +0x30, 0x1D, 0x6F, 0x8F, +0x3A, 0x30, 0x4F, 0xE9, + +0x1C, 0x30, 0x26, 0xDF, +0x09, 0xE3, +0x3B, 0x05, + +0x3E, 0x50, 0x56, 0x9F, +0x3B, 0x3F, 0x4F, 0xE9, + +0x1E, 0x8F, 0x51, 0x9F, +0x00, 0xE0, +0xAC, 0x20, + +0x2D, 0x44, 0x4C, 0xB4, +0x2C, 0x1C, 0xC0, 0xAF, + +0x25, 0x44, 0x54, 0xB4, +0x00, 0xE0, +0xC8, 0x30, + +0x30, 0x46, 0x30, 0xAF, +0x1B, 0x1B, 0x48, 0xAF, + +0x00, 0xE0, +0x25, 0x20, +0x38, 0x2C, 0x4F, 0xE9, + +0x86, 0x80, 0x57, 0xE9, +0x38, 0x1D, 0x6F, 0x8F, + +0x28, 0x74, +0x00, 0xE0, +0x0D, 0x44, 0x4C, 0xB0, + +0x05, 0x44, 0x54, 0xB0, +0x2D, 0x20, +0x9B, 0x10, + +0x82, 0x3E, 0x57, 0xE9, +0x32, 0xF0, 0x1B, 0xCD, + +0x1E, 0xBD, 0x59, 0x9F, +0x83, 0x1E, 0x57, 0xE9, + +0x38, 0x47, 0x38, 0xAF, +0x34, 0x20, +0x2A, 0x30, + +0x00, 0xE0, +0x0D, 0x20, +0x32, 0x20, +0x05, 0x20, + +0x87, 0x80, 0x57, 0xE9, +0x1F, 0x54, 0x57, 0x9F, + +0x17, 0x42, 0x56, 0x9F, +0x00, 0xE0, +0x3B, 0x6A, + +0x3F, 0x8F, 0x51, 0x9F, +0x37, 0x1E, 0x4F, 0xE9, + +0x37, 0x32, 0x2A, 0xAF, +0x00, 0xE0, +0x32, 0x00, + +0x00, 0x80, 0x00, 0xE8, +0x27, 0xC0, 0x44, 0xC0, + +0x36, 0x1F, 0x4F, 0xE9, +0x1F, 0x1F, 0x26, 0xDF, + +0x37, 0x1B, 0x37, 0xBF, +0x17, 0x26, 0x17, 0xDF, + +0x3E, 0x17, 0x4F, 0xE9, +0x3F, 0x3F, 0x4F, 0xE9, + +0x34, 0x1F, 0x34, 0xAF, +0x2B, 0x05, +0xA7, 0x20, + +0x33, 0x2B, 0x37, 0xDF, +0x27, 0x17, 0xC0, 0xAF, + +0x34, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x2D, 0x21, 0x1A, 0xB0, +0x25, 0x21, 0x31, 0xB0, + +0x0D, 0x21, 0x1A, 0xB2, +0x05, 0x21, 0x31, 0xB2, + +0x03, 0x80, 0x2A, 0xEA, +0x17, 0xC1, 0x2B, 0xBD, + +0x2D, 0x20, +0x25, 0x20, +0x05, 0x20, +0x0D, 0x20, + +0xB3, 0x68, +0x97, 0x25, +0x00, 0x80, 0x00, 0xE8, + +0x33, 0xC0, 0x33, 0xAF, +0x2F, 0xC0, 0x21, 0xC0, + +0x16, 0x42, 0x56, 0x9F, +0x3C, 0x27, 0x4F, 0xE9, + +0x1E, 0x62, 0x57, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x25, 0x21, 0x31, 0xB4, +0x2D, 0x21, 0x1A, 0xB4, + +0x3F, 0x2F, 0x5D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x33, 0x05, +0x00, 0xE0, +0x28, 0x19, 0x60, 0xEC, + +0x0D, 0x21, 0x1A, 0xB6, +0x05, 0x21, 0x31, 0xB6, + +0x37, 0x0F, 0x5C, 0x9F, +0x00, 0xE0, +0x2F, 0x20, + +0x23, 0x3B, 0x33, 0xAD, +0x1E, 0x26, 0x1E, 0xDF, + +0xA7, 0x1E, 0x4F, 0xE9, +0x17, 0x26, 0x16, 0xDF, + +0x2D, 0x20, +0x00, 0xE0, +0xA8, 0x3F, 0x4F, 0xE9, + +0x2F, 0x2F, 0x1E, 0xAF, +0x25, 0x20, +0x00, 0xE0, + +0xA4, 0x16, 0x4F, 0xE9, +0x0F, 0xC0, 0x21, 0xC2, + +0xA6, 0x80, 0x4F, 0xE9, +0x1F, 0x62, 0x57, 0x9F, + +0x0D, 0x20, +0x05, 0x20, +0x2F, 0xC0, 0x21, 0xC6, + +0x3F, 0x2F, 0x5D, 0x9F, +0x00, 0xE0, +0x0F, 0x20, + +0x17, 0x50, 0x56, 0x9F, +0xA5, 0x37, 0x4F, 0xE9, + +0x06, 0xC0, 0x21, 0xC4, +0x0F, 0x17, 0x0F, 0xAF, + +0x37, 0x0F, 0x5C, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x2F, 0x20, +0x00, 0xE0, +0xA3, 0x80, 0x4F, 0xE9, + +0x06, 0x20, +0x00, 0xE0, +0x1F, 0x26, 0x1F, 0xDF, + +0x17, 0x26, 0x17, 0xDF, +0x35, 0x17, 0x4F, 0xE9, + +0xA1, 0x1F, 0x4F, 0xE9, +0xA2, 0x3F, 0x4F, 0xE9, + +0x06, 0x06, 0x1F, 0xAF, +0x39, 0x37, 0x4F, 0xE9, + +0x2F, 0x2F, 0x17, 0xAF, +0x00, 0x80, 0x00, 0xE8, + +0xA0, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x31, 0x80, 0x4F, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x57, 0x39, 0x20, 0xE9, + +0x16, 0x28, 0x20, 0xE9, +0x1D, 0x3B, 0x20, 0xE9, + +0x1E, 0x2B, 0x20, 0xE9, +0x2B, 0x32, 0x20, 0xE9, + +0x1C, 0x23, 0x20, 0xE9, +0x57, 0x36, 0x20, 0xE9, + +0x00, 0x80, 0xA0, 0xE9, +0x40, 0x40, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x90, 0xE2, +0x00, 0xE0, + +0x68, 0xFF, 0x20, 0xEA, +0x19, 0xC8, 0xC1, 0xCD, + +0x1F, 0xD7, 0x18, 0xBD, +0x3F, 0xD7, 0x22, 0xBD, + +0x9F, 0x41, 0x49, 0xBD, +0x00, 0x80, 0x00, 0xE8, + +0x25, 0x41, 0x49, 0xBD, +0x2D, 0x41, 0x51, 0xBD, + +0x0D, 0x80, 0x07, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x35, 0x40, 0x48, 0xBD, +0x3D, 0x40, 0x50, 0xBD, + +0x00, 0x80, 0x00, 0xE8, +0x25, 0x30, +0x2D, 0x30, + +0x35, 0x30, +0xB5, 0x30, +0xBD, 0x30, +0x3D, 0x30, + +0x9C, 0xA7, 0x5B, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x67, 0xFF, 0x0A, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0xC9, 0x41, 0xC8, 0xEC, +0x42, 0xE1, +0x00, 0xE0, + +0x65, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0xC8, 0x40, 0xC0, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x62, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +}; + +static unsigned char warp_g400_t2gz[] = { + +0x00, 0x8A, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x0A, 0x40, 0x50, 0xBF, +0x2A, 0x40, 0x60, 0xBF, + +0x32, 0x41, 0x51, 0xBF, +0x3A, 0x41, 0x61, 0xBF, + +0xC3, 0x6B, +0xD3, 0x6B, +0x00, 0x8A, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x53, 0xA0, 0xE8, + +0xAD, 0xEE, 0x23, 0x9F, +0x00, 0xE0, +0x51, 0x04, + +0x90, 0xE2, +0x61, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x51, 0x41, 0xE0, 0xEC, +0x39, 0x67, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x63, 0xA0, 0xE8, + +0x61, 0x41, 0xE0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x78, 0x80, 0x15, 0xEA, +0x10, 0x04, +0x20, 0x04, + +0x61, 0x51, 0xE0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x52, 0xBF, +0x0F, 0x52, 0xA0, 0xE8, + +0x1A, 0x42, 0x62, 0xBF, +0x1E, 0x51, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x0E, 0x61, 0x60, 0xEA, + +0x32, 0x40, 0x50, 0xBD, +0x22, 0x40, 0x60, 0xBD, + +0x12, 0x41, 0x51, 0xBD, +0x3A, 0x41, 0x61, 0xBD, + +0xBF, 0x2F, 0x0E, 0xBD, +0x97, 0xE2, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x35, 0x48, 0xB1, 0xE8, +0x3D, 0x59, 0xB1, 0xE8, + +0x46, 0x31, 0x46, 0xBF, +0x56, 0x31, 0x56, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x66, 0x31, 0x66, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x57, 0x39, 0x57, 0xBF, +0x67, 0x39, 0x67, 0xBF, + +0x69, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x35, 0x00, +0x3D, 0x00, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0x8D, 0x2F, 0x1E, 0xBD, + +0x43, 0x75, 0xF8, 0xEC, +0x35, 0x20, +0x3D, 0x20, + +0x43, 0x43, 0x2D, 0xDF, +0x53, 0x53, 0x2D, 0xDF, + +0xAE, 0x1E, 0x0E, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x48, 0x35, 0x48, 0xBF, +0x58, 0x35, 0x58, 0xBF, + +0x68, 0x35, 0x68, 0xBF, +0x49, 0x3D, 0x49, 0xBF, + +0x59, 0x3D, 0x59, 0xBF, +0x69, 0x3D, 0x69, 0xBF, + +0x63, 0x63, 0x2D, 0xDF, +0x4D, 0x7D, 0xF8, 0xEC, + +0x59, 0xE3, +0x00, 0xE0, +0xB8, 0x38, 0x33, 0xBF, + +0x2D, 0x73, +0x30, 0x76, +0x18, 0x3A, 0x41, 0xE9, + +0x3F, 0x53, 0xA0, 0xE8, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x63, 0xA0, 0xE8, + +0x50, 0x70, 0xF8, 0xEC, +0x2B, 0x50, 0x3C, 0xE9, + +0x1F, 0x0F, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x59, 0x78, 0xF8, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x46, 0x37, 0x46, 0xDF, +0x56, 0x3F, 0x56, 0xDF, + +0x2B, 0x40, 0x3D, 0xE9, +0x66, 0x3D, 0x66, 0xDF, + +0x1D, 0x32, 0x41, 0xE9, +0x67, 0x3D, 0x67, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3F, 0x57, 0xDF, + +0x2A, 0x40, 0x20, 0xE9, +0x59, 0x3F, 0x59, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x69, 0x3D, 0x69, 0xDF, + +0x48, 0x37, 0x48, 0xDF, +0x58, 0x3F, 0x58, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x68, 0x3D, 0x68, 0xDF, +0x49, 0x37, 0x49, 0xDF, + +0x3D, 0xCF, 0x74, 0xC0, +0x37, 0xCF, 0x74, 0xC4, + +0x31, 0x53, 0x2F, 0x9F, +0x34, 0x80, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x0A, 0x44, 0x54, 0xB0, +0x02, 0x44, 0x64, 0xB0, + +0x2A, 0x44, 0x54, 0xB2, +0x1A, 0x44, 0x64, 0xB2, + +0x25, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x3D, 0xCF, 0x74, 0xC2, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x2A, 0x44, 0x54, 0xB4, +0x1A, 0x44, 0x64, 0xB4, + +0x39, 0xE5, 0x2C, 0x9F, +0x38, 0x3D, 0x20, 0xE9, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0x2A, 0x46, 0x56, 0xBF, +0x1A, 0x46, 0x66, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x0A, 0x47, 0x57, 0xBF, +0x02, 0x47, 0x67, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x2A, 0x43, 0x53, 0xBF, +0x1A, 0x43, 0x63, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x36, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x37, 0x39, 0x4F, 0xE9, + +0x0A, 0x48, 0x58, 0xBF, +0x02, 0x48, 0x68, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x2A, 0x49, 0x59, 0xBF, +0x1A, 0x49, 0x69, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x82, 0x30, 0x57, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x83, 0x38, 0x57, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x84, 0x31, 0x5E, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x85, 0x39, 0x5E, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8A, 0x36, 0x20, 0xE9, + +0x87, 0x77, 0x57, 0xE9, +0x8B, 0x3E, 0xBF, 0xEA, + +0x80, 0x30, 0x57, 0xE9, +0x81, 0x38, 0x57, 0xE9, + +0x82, 0x31, 0x57, 0xE9, +0x86, 0x78, 0x57, 0xE9, + +0x83, 0x39, 0x57, 0xE9, +0x87, 0x79, 0x57, 0xE9, + +0x30, 0x1F, 0x5F, 0xE9, +0x8A, 0x34, 0x20, 0xE9, + +0x8B, 0x3C, 0x20, 0xE9, +0x37, 0x50, 0x60, 0xBD, + +0x57, 0x0D, 0x20, 0xE9, +0x35, 0x51, 0x61, 0xBD, + +0x2B, 0x50, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x0E, 0x77, + +0x24, 0x51, 0x20, 0xE9, +0x9F, 0xFF, 0x20, 0xEA, + +0x16, 0x0E, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x0B, 0x46, 0xA0, 0xE8, +0x1B, 0x56, 0xA0, 0xE8, + +0x2B, 0x66, 0xA0, 0xE8, +0x0C, 0x47, 0xA0, 0xE8, + +0x1C, 0x57, 0xA0, 0xE8, +0x2C, 0x67, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x57, 0x80, 0x57, 0xCF, + +0x66, 0x33, 0x66, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x67, 0x3B, 0x67, 0xCF, + +0x0B, 0x48, 0xA0, 0xE8, +0x1B, 0x58, 0xA0, 0xE8, + +0x2B, 0x68, 0xA0, 0xE8, +0x0C, 0x49, 0xA0, 0xE8, + +0x1C, 0x59, 0xA0, 0xE8, +0x2C, 0x69, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x34, 0xD7, 0x34, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3C, 0xD7, 0x3C, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x34, 0x80, 0x34, 0xBD, +0x3C, 0x80, 0x3C, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x48, 0x80, 0x48, 0xCF, +0x59, 0x80, 0x59, 0xCF, + +0x68, 0x33, 0x68, 0xCF, +0x49, 0x3B, 0x49, 0xCF, + +0xBE, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x58, 0x33, 0x58, 0xCF, +0x69, 0x3B, 0x69, 0xCF, + +0x7D, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_t2gza[] = { + +0x00, 0x8A, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x0A, 0x40, 0x50, 0xBF, +0x2A, 0x40, 0x60, 0xBF, + +0x32, 0x41, 0x51, 0xBF, +0x3A, 0x41, 0x61, 0xBF, + +0xC3, 0x6B, +0xD3, 0x6B, +0x00, 0x8A, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x53, 0xA0, 0xE8, + +0xAD, 0xEE, 0x23, 0x9F, +0x00, 0xE0, +0x51, 0x04, + +0x90, 0xE2, +0x61, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x51, 0x41, 0xE0, 0xEC, +0x39, 0x67, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x63, 0xA0, 0xE8, + +0x61, 0x41, 0xE0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x7C, 0x80, 0x15, 0xEA, +0x10, 0x04, +0x20, 0x04, + +0x61, 0x51, 0xE0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x52, 0xBF, +0x0F, 0x52, 0xA0, 0xE8, + +0x1A, 0x42, 0x62, 0xBF, +0x1E, 0x51, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x0E, 0x61, 0x60, 0xEA, + +0x32, 0x40, 0x50, 0xBD, +0x22, 0x40, 0x60, 0xBD, + +0x12, 0x41, 0x51, 0xBD, +0x3A, 0x41, 0x61, 0xBD, + +0xBF, 0x2F, 0x0E, 0xBD, +0x97, 0xE2, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x35, 0x48, 0xB1, 0xE8, +0x3D, 0x59, 0xB1, 0xE8, + +0x46, 0x31, 0x46, 0xBF, +0x56, 0x31, 0x56, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x66, 0x31, 0x66, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x57, 0x39, 0x57, 0xBF, +0x67, 0x39, 0x67, 0xBF, + +0x6D, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x35, 0x00, +0x3D, 0x00, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0x8D, 0x2F, 0x1E, 0xBD, + +0x43, 0x75, 0xF8, 0xEC, +0x35, 0x20, +0x3D, 0x20, + +0x43, 0x43, 0x2D, 0xDF, +0x53, 0x53, 0x2D, 0xDF, + +0xAE, 0x1E, 0x0E, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x48, 0x35, 0x48, 0xBF, +0x58, 0x35, 0x58, 0xBF, + +0x68, 0x35, 0x68, 0xBF, +0x49, 0x3D, 0x49, 0xBF, + +0x59, 0x3D, 0x59, 0xBF, +0x69, 0x3D, 0x69, 0xBF, + +0x63, 0x63, 0x2D, 0xDF, +0x4D, 0x7D, 0xF8, 0xEC, + +0x59, 0xE3, +0x00, 0xE0, +0xB8, 0x38, 0x33, 0xBF, + +0x2D, 0x73, +0x30, 0x76, +0x18, 0x3A, 0x41, 0xE9, + +0x3F, 0x53, 0xA0, 0xE8, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x63, 0xA0, 0xE8, + +0x50, 0x70, 0xF8, 0xEC, +0x2B, 0x50, 0x3C, 0xE9, + +0x1F, 0x0F, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x59, 0x78, 0xF8, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x46, 0x37, 0x46, 0xDF, +0x56, 0x3F, 0x56, 0xDF, + +0x2B, 0x40, 0x3D, 0xE9, +0x66, 0x3D, 0x66, 0xDF, + +0x1D, 0x32, 0x41, 0xE9, +0x67, 0x3D, 0x67, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3F, 0x57, 0xDF, + +0x2A, 0x40, 0x20, 0xE9, +0x59, 0x3F, 0x59, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x69, 0x3D, 0x69, 0xDF, + +0x48, 0x37, 0x48, 0xDF, +0x58, 0x3F, 0x58, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x68, 0x3D, 0x68, 0xDF, +0x49, 0x37, 0x49, 0xDF, + +0x3D, 0xCF, 0x74, 0xC0, +0x37, 0xCF, 0x74, 0xC4, + +0x31, 0x53, 0x2F, 0x9F, +0x34, 0x80, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x0A, 0x44, 0x54, 0xB0, +0x02, 0x44, 0x64, 0xB0, + +0x2A, 0x44, 0x54, 0xB2, +0x1A, 0x44, 0x64, 0xB2, + +0x29, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x0F, 0xCF, 0x74, 0xC6, +0x3D, 0xCF, 0x74, 0xC2, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x9C, 0x0F, 0x20, 0xE9, + +0x0A, 0x44, 0x54, 0xB4, +0x02, 0x44, 0x64, 0xB4, + +0x2A, 0x44, 0x54, 0xB6, +0x1A, 0x44, 0x64, 0xB6, + +0x39, 0xE5, 0x2C, 0x9F, +0x38, 0x3D, 0x20, 0xE9, + +0x0A, 0x20, +0x02, 0x20, +0x2A, 0x20, +0x1A, 0x20, + +0x0A, 0x47, 0x57, 0xBF, +0x02, 0x47, 0x67, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x2A, 0x46, 0x56, 0xBF, +0x1A, 0x46, 0x66, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x36, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x37, 0x38, 0x4F, 0xE9, + +0x2A, 0x43, 0x53, 0xBF, +0x1A, 0x43, 0x63, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x9D, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x9E, 0x39, 0x4F, 0xE9, + +0x0A, 0x48, 0x58, 0xBF, +0x02, 0x48, 0x68, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x2A, 0x49, 0x59, 0xBF, +0x1A, 0x49, 0x69, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x82, 0x30, 0x57, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x83, 0x38, 0x57, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x84, 0x31, 0x5E, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x85, 0x39, 0x5E, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8A, 0x36, 0x20, 0xE9, + +0x87, 0x77, 0x57, 0xE9, +0x8B, 0x3E, 0xBF, 0xEA, + +0x80, 0x30, 0x57, 0xE9, +0x81, 0x38, 0x57, 0xE9, + +0x82, 0x31, 0x57, 0xE9, +0x86, 0x78, 0x57, 0xE9, + +0x83, 0x39, 0x57, 0xE9, +0x87, 0x79, 0x57, 0xE9, + +0x30, 0x1F, 0x5F, 0xE9, +0x8A, 0x34, 0x20, 0xE9, + +0x8B, 0x3C, 0x20, 0xE9, +0x37, 0x50, 0x60, 0xBD, + +0x57, 0x0D, 0x20, 0xE9, +0x35, 0x51, 0x61, 0xBD, + +0x2B, 0x50, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x0E, 0x77, + +0x24, 0x51, 0x20, 0xE9, +0x9B, 0xFF, 0x20, 0xEA, + +0x16, 0x0E, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x0B, 0x46, 0xA0, 0xE8, +0x1B, 0x56, 0xA0, 0xE8, + +0x2B, 0x66, 0xA0, 0xE8, +0x0C, 0x47, 0xA0, 0xE8, + +0x1C, 0x57, 0xA0, 0xE8, +0x2C, 0x67, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x57, 0x80, 0x57, 0xCF, + +0x66, 0x33, 0x66, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x67, 0x3B, 0x67, 0xCF, + +0x0B, 0x48, 0xA0, 0xE8, +0x1B, 0x58, 0xA0, 0xE8, + +0x2B, 0x68, 0xA0, 0xE8, +0x0C, 0x49, 0xA0, 0xE8, + +0x1C, 0x59, 0xA0, 0xE8, +0x2C, 0x69, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x34, 0xD7, 0x34, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3C, 0xD7, 0x3C, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x34, 0x80, 0x34, 0xBD, +0x3C, 0x80, 0x3C, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x48, 0x80, 0x48, 0xCF, +0x59, 0x80, 0x59, 0xCF, + +0x68, 0x33, 0x68, 0xCF, +0x49, 0x3B, 0x49, 0xCF, + +0xBA, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x58, 0x33, 0x58, 0xCF, +0x69, 0x3B, 0x69, 0xCF, + +0x79, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_t2gzaf[] = { + +0x00, 0x8A, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x0A, 0x40, 0x50, 0xBF, +0x2A, 0x40, 0x60, 0xBF, + +0x32, 0x41, 0x51, 0xBF, +0x3A, 0x41, 0x61, 0xBF, + +0xC3, 0x6B, +0xD3, 0x6B, +0x00, 0x8A, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x53, 0xA0, 0xE8, + +0xAD, 0xEE, 0x23, 0x9F, +0x00, 0xE0, +0x51, 0x04, + +0x90, 0xE2, +0x61, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x51, 0x41, 0xE0, 0xEC, +0x39, 0x67, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x63, 0xA0, 0xE8, + +0x61, 0x41, 0xE0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x81, 0x80, 0x15, 0xEA, +0x10, 0x04, +0x20, 0x04, + +0x61, 0x51, 0xE0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x52, 0xBF, +0x0F, 0x52, 0xA0, 0xE8, + +0x1A, 0x42, 0x62, 0xBF, +0x1E, 0x51, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x0E, 0x61, 0x60, 0xEA, + +0x32, 0x40, 0x50, 0xBD, +0x22, 0x40, 0x60, 0xBD, + +0x12, 0x41, 0x51, 0xBD, +0x3A, 0x41, 0x61, 0xBD, + +0xBF, 0x2F, 0x0E, 0xBD, +0x97, 0xE2, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x35, 0x48, 0xB1, 0xE8, +0x3D, 0x59, 0xB1, 0xE8, + +0x46, 0x31, 0x46, 0xBF, +0x56, 0x31, 0x56, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x66, 0x31, 0x66, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x57, 0x39, 0x57, 0xBF, +0x67, 0x39, 0x67, 0xBF, + +0x72, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x35, 0x00, +0x3D, 0x00, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0x8D, 0x2F, 0x1E, 0xBD, + +0x43, 0x75, 0xF8, 0xEC, +0x35, 0x20, +0x3D, 0x20, + +0x43, 0x43, 0x2D, 0xDF, +0x53, 0x53, 0x2D, 0xDF, + +0xAE, 0x1E, 0x0E, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x48, 0x35, 0x48, 0xBF, +0x58, 0x35, 0x58, 0xBF, + +0x68, 0x35, 0x68, 0xBF, +0x49, 0x3D, 0x49, 0xBF, + +0x59, 0x3D, 0x59, 0xBF, +0x69, 0x3D, 0x69, 0xBF, + +0x63, 0x63, 0x2D, 0xDF, +0x4D, 0x7D, 0xF8, 0xEC, + +0x59, 0xE3, +0x00, 0xE0, +0xB8, 0x38, 0x33, 0xBF, + +0x2D, 0x73, +0x30, 0x76, +0x18, 0x3A, 0x41, 0xE9, + +0x3F, 0x53, 0xA0, 0xE8, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x63, 0xA0, 0xE8, + +0x50, 0x70, 0xF8, 0xEC, +0x2B, 0x50, 0x3C, 0xE9, + +0x1F, 0x0F, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x59, 0x78, 0xF8, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x46, 0x37, 0x46, 0xDF, +0x56, 0x3F, 0x56, 0xDF, + +0x2B, 0x40, 0x3D, 0xE9, +0x66, 0x3D, 0x66, 0xDF, + +0x1D, 0x32, 0x41, 0xE9, +0x67, 0x3D, 0x67, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3F, 0x57, 0xDF, + +0x2A, 0x40, 0x20, 0xE9, +0x59, 0x3F, 0x59, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x69, 0x3D, 0x69, 0xDF, + +0x48, 0x37, 0x48, 0xDF, +0x58, 0x3F, 0x58, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x68, 0x3D, 0x68, 0xDF, +0x49, 0x37, 0x49, 0xDF, + +0x3D, 0xCF, 0x74, 0xC0, +0x37, 0xCF, 0x74, 0xC4, + +0x0A, 0x44, 0x54, 0xB0, +0x02, 0x44, 0x64, 0xB0, + +0x31, 0x53, 0x2F, 0x9F, +0x34, 0x37, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x54, 0xB2, +0x1A, 0x44, 0x64, 0xB2, + +0x2E, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0x3D, 0xCF, 0x74, 0xC2, +0x0F, 0xCF, 0x74, 0xC6, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x9C, 0x0F, 0x20, 0xE9, + +0x0A, 0x44, 0x54, 0xB4, +0x02, 0x44, 0x64, 0xB4, + +0x2A, 0x44, 0x54, 0xB6, +0x1A, 0x44, 0x64, 0xB6, + +0x39, 0xE5, 0x2C, 0x9F, +0x38, 0x3D, 0x20, 0xE9, + +0x0A, 0x20, +0x02, 0x20, +0x2A, 0x20, +0x1A, 0x20, + +0x3D, 0xCF, 0x75, 0xC6, +0x00, 0x80, 0x00, 0xE8, + +0x30, 0x50, 0x2E, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x0A, 0x45, 0x55, 0xB6, +0x02, 0x45, 0x65, 0xB6, + +0x31, 0x53, 0x2F, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x31, 0x3D, 0x20, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x2A, 0x46, 0x56, 0xBF, +0x1A, 0x46, 0x66, 0xBF, + +0x0A, 0x47, 0x57, 0xBF, +0x02, 0x47, 0x67, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x36, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x37, 0x38, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x9D, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x9E, 0x39, 0x4F, 0xE9, + +0x2A, 0x43, 0x53, 0xBF, +0x1A, 0x43, 0x63, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x35, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x39, 0x38, 0x4F, 0xE9, + +0x0A, 0x48, 0x58, 0xBF, +0x02, 0x48, 0x68, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x2A, 0x49, 0x59, 0xBF, +0x1A, 0x49, 0x69, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x82, 0x30, 0x57, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x83, 0x38, 0x57, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x84, 0x31, 0x5E, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x85, 0x39, 0x5E, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8A, 0x36, 0x20, 0xE9, + +0x87, 0x77, 0x57, 0xE9, +0x8B, 0x3E, 0xBF, 0xEA, + +0x80, 0x30, 0x57, 0xE9, +0x81, 0x38, 0x57, 0xE9, + +0x82, 0x31, 0x57, 0xE9, +0x86, 0x78, 0x57, 0xE9, + +0x83, 0x39, 0x57, 0xE9, +0x87, 0x79, 0x57, 0xE9, + +0x30, 0x1F, 0x5F, 0xE9, +0x8A, 0x34, 0x20, 0xE9, + +0x8B, 0x3C, 0x20, 0xE9, +0x37, 0x50, 0x60, 0xBD, + +0x57, 0x0D, 0x20, 0xE9, +0x35, 0x51, 0x61, 0xBD, + +0x2B, 0x50, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x0E, 0x77, + +0x24, 0x51, 0x20, 0xE9, +0x96, 0xFF, 0x20, 0xEA, + +0x16, 0x0E, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x0B, 0x46, 0xA0, 0xE8, +0x1B, 0x56, 0xA0, 0xE8, + +0x2B, 0x66, 0xA0, 0xE8, +0x0C, 0x47, 0xA0, 0xE8, + +0x1C, 0x57, 0xA0, 0xE8, +0x2C, 0x67, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x57, 0x80, 0x57, 0xCF, + +0x66, 0x33, 0x66, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x67, 0x3B, 0x67, 0xCF, + +0x0B, 0x48, 0xA0, 0xE8, +0x1B, 0x58, 0xA0, 0xE8, + +0x2B, 0x68, 0xA0, 0xE8, +0x0C, 0x49, 0xA0, 0xE8, + +0x1C, 0x59, 0xA0, 0xE8, +0x2C, 0x69, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x34, 0xD7, 0x34, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3C, 0xD7, 0x3C, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x34, 0x80, 0x34, 0xBD, +0x3C, 0x80, 0x3C, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x48, 0x80, 0x48, 0xCF, +0x59, 0x80, 0x59, 0xCF, + +0x68, 0x33, 0x68, 0xCF, +0x49, 0x3B, 0x49, 0xCF, + +0xB5, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x58, 0x33, 0x58, 0xCF, +0x69, 0x3B, 0x69, 0xCF, + +0x74, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_t2gzf[] = { + +0x00, 0x8A, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x0A, 0x40, 0x50, 0xBF, +0x2A, 0x40, 0x60, 0xBF, + +0x32, 0x41, 0x51, 0xBF, +0x3A, 0x41, 0x61, 0xBF, + +0xC3, 0x6B, +0xD3, 0x6B, +0x00, 0x8A, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x53, 0xA0, 0xE8, + +0xAD, 0xEE, 0x23, 0x9F, +0x00, 0xE0, +0x51, 0x04, + +0x90, 0xE2, +0x61, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x51, 0x41, 0xE0, 0xEC, +0x39, 0x67, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x63, 0xA0, 0xE8, + +0x61, 0x41, 0xE0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x7D, 0x80, 0x15, 0xEA, +0x10, 0x04, +0x20, 0x04, + +0x61, 0x51, 0xE0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x52, 0xBF, +0x0F, 0x52, 0xA0, 0xE8, + +0x1A, 0x42, 0x62, 0xBF, +0x1E, 0x51, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x0E, 0x61, 0x60, 0xEA, + +0x32, 0x40, 0x50, 0xBD, +0x22, 0x40, 0x60, 0xBD, + +0x12, 0x41, 0x51, 0xBD, +0x3A, 0x41, 0x61, 0xBD, + +0xBF, 0x2F, 0x0E, 0xBD, +0x97, 0xE2, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x35, 0x48, 0xB1, 0xE8, +0x3D, 0x59, 0xB1, 0xE8, + +0x46, 0x31, 0x46, 0xBF, +0x56, 0x31, 0x56, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x66, 0x31, 0x66, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x57, 0x39, 0x57, 0xBF, +0x67, 0x39, 0x67, 0xBF, + +0x6E, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x35, 0x00, +0x3D, 0x00, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0x8D, 0x2F, 0x1E, 0xBD, + +0x43, 0x75, 0xF8, 0xEC, +0x35, 0x20, +0x3D, 0x20, + +0x43, 0x43, 0x2D, 0xDF, +0x53, 0x53, 0x2D, 0xDF, + +0xAE, 0x1E, 0x0E, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x48, 0x35, 0x48, 0xBF, +0x58, 0x35, 0x58, 0xBF, + +0x68, 0x35, 0x68, 0xBF, +0x49, 0x3D, 0x49, 0xBF, + +0x59, 0x3D, 0x59, 0xBF, +0x69, 0x3D, 0x69, 0xBF, + +0x63, 0x63, 0x2D, 0xDF, +0x4D, 0x7D, 0xF8, 0xEC, + +0x59, 0xE3, +0x00, 0xE0, +0xB8, 0x38, 0x33, 0xBF, + +0x2D, 0x73, +0x30, 0x76, +0x18, 0x3A, 0x41, 0xE9, + +0x3F, 0x53, 0xA0, 0xE8, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x63, 0xA0, 0xE8, + +0x50, 0x70, 0xF8, 0xEC, +0x2B, 0x50, 0x3C, 0xE9, + +0x1F, 0x0F, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x59, 0x78, 0xF8, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x46, 0x37, 0x46, 0xDF, +0x56, 0x3F, 0x56, 0xDF, + +0x2B, 0x40, 0x3D, 0xE9, +0x66, 0x3D, 0x66, 0xDF, + +0x1D, 0x32, 0x41, 0xE9, +0x67, 0x3D, 0x67, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3F, 0x57, 0xDF, + +0x2A, 0x40, 0x20, 0xE9, +0x59, 0x3F, 0x59, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x69, 0x3D, 0x69, 0xDF, + +0x48, 0x37, 0x48, 0xDF, +0x58, 0x3F, 0x58, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x68, 0x3D, 0x68, 0xDF, +0x49, 0x37, 0x49, 0xDF, + +0x3D, 0xCF, 0x74, 0xC0, +0x37, 0xCF, 0x74, 0xC4, + +0x39, 0xE5, 0x2C, 0x9F, +0x34, 0x80, 0x20, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x88, 0x73, 0x5E, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x0F, 0xCF, 0x75, 0xC6, +0x3C, 0x3D, 0x20, 0xE9, + +0x0A, 0x44, 0x54, 0xB0, +0x02, 0x44, 0x64, 0xB0, + +0x2A, 0x44, 0x54, 0xB2, +0x1A, 0x44, 0x64, 0xB2, + +0x28, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x3D, 0xCF, 0x74, 0xC2, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x31, 0x0F, 0x20, 0xE9, + +0x0A, 0x44, 0x54, 0xB4, +0x02, 0x44, 0x64, 0xB4, + +0x2A, 0x45, 0x55, 0xB6, +0x1A, 0x45, 0x65, 0xB6, + +0x39, 0xE5, 0x2C, 0x9F, +0x38, 0x3D, 0x20, 0xE9, + +0x0A, 0x20, +0x02, 0x20, +0x2A, 0x20, +0x1A, 0x20, + +0x0A, 0x47, 0x57, 0xBF, +0x02, 0x47, 0x67, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x2A, 0x46, 0x56, 0xBF, +0x1A, 0x46, 0x66, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x36, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x37, 0x38, 0x4F, 0xE9, + +0x2A, 0x43, 0x53, 0xBF, +0x1A, 0x43, 0x63, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x35, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x39, 0x39, 0x4F, 0xE9, + +0x0A, 0x48, 0x58, 0xBF, +0x02, 0x48, 0x68, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x2A, 0x49, 0x59, 0xBF, +0x1A, 0x49, 0x69, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x82, 0x30, 0x57, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x83, 0x38, 0x57, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x84, 0x31, 0x5E, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x85, 0x39, 0x5E, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8A, 0x36, 0x20, 0xE9, + +0x87, 0x77, 0x57, 0xE9, +0x8B, 0x3E, 0xBF, 0xEA, + +0x80, 0x30, 0x57, 0xE9, +0x81, 0x38, 0x57, 0xE9, + +0x82, 0x31, 0x57, 0xE9, +0x86, 0x78, 0x57, 0xE9, + +0x83, 0x39, 0x57, 0xE9, +0x87, 0x79, 0x57, 0xE9, + +0x30, 0x1F, 0x5F, 0xE9, +0x8A, 0x34, 0x20, 0xE9, + +0x8B, 0x3C, 0x20, 0xE9, +0x37, 0x50, 0x60, 0xBD, + +0x57, 0x0D, 0x20, 0xE9, +0x35, 0x51, 0x61, 0xBD, + +0x2B, 0x50, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x0E, 0x77, + +0x24, 0x51, 0x20, 0xE9, +0x9A, 0xFF, 0x20, 0xEA, + +0x16, 0x0E, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x0B, 0x46, 0xA0, 0xE8, +0x1B, 0x56, 0xA0, 0xE8, + +0x2B, 0x66, 0xA0, 0xE8, +0x0C, 0x47, 0xA0, 0xE8, + +0x1C, 0x57, 0xA0, 0xE8, +0x2C, 0x67, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x57, 0x80, 0x57, 0xCF, + +0x66, 0x33, 0x66, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x67, 0x3B, 0x67, 0xCF, + +0x0B, 0x48, 0xA0, 0xE8, +0x1B, 0x58, 0xA0, 0xE8, + +0x2B, 0x68, 0xA0, 0xE8, +0x0C, 0x49, 0xA0, 0xE8, + +0x1C, 0x59, 0xA0, 0xE8, +0x2C, 0x69, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x34, 0xD7, 0x34, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3C, 0xD7, 0x3C, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x34, 0x80, 0x34, 0xBD, +0x3C, 0x80, 0x3C, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x48, 0x80, 0x48, 0xCF, +0x59, 0x80, 0x59, 0xCF, + +0x68, 0x33, 0x68, 0xCF, +0x49, 0x3B, 0x49, 0xCF, + +0xBB, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x58, 0x33, 0x58, 0xCF, +0x69, 0x3B, 0x69, 0xCF, + +0x78, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_t2gzs[] = { + +0x00, 0x8A, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x0A, 0x40, 0x50, 0xBF, +0x2A, 0x40, 0x60, 0xBF, + +0x32, 0x41, 0x51, 0xBF, +0x3A, 0x41, 0x61, 0xBF, + +0xC3, 0x6B, +0xD3, 0x6B, +0x00, 0x8A, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x53, 0xA0, 0xE8, + +0xAD, 0xEE, 0x23, 0x9F, +0x00, 0xE0, +0x51, 0x04, + +0x90, 0xE2, +0x61, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x51, 0x41, 0xE0, 0xEC, +0x39, 0x67, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x63, 0xA0, 0xE8, + +0x61, 0x41, 0xE0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x85, 0x80, 0x15, 0xEA, +0x10, 0x04, +0x20, 0x04, + +0x61, 0x51, 0xE0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x52, 0xBF, +0x0F, 0x52, 0xA0, 0xE8, + +0x1A, 0x42, 0x62, 0xBF, +0x1E, 0x51, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x0E, 0x61, 0x60, 0xEA, + +0x32, 0x40, 0x50, 0xBD, +0x22, 0x40, 0x60, 0xBD, + +0x12, 0x41, 0x51, 0xBD, +0x3A, 0x41, 0x61, 0xBD, + +0xBF, 0x2F, 0x0E, 0xBD, +0x97, 0xE2, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x35, 0x48, 0xB1, 0xE8, +0x3D, 0x59, 0xB1, 0xE8, + +0x46, 0x31, 0x46, 0xBF, +0x56, 0x31, 0x56, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x66, 0x31, 0x66, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x57, 0x39, 0x57, 0xBF, +0x67, 0x39, 0x67, 0xBF, + +0x76, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x35, 0x00, +0x3D, 0x00, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0x8D, 0x2F, 0x1E, 0xBD, + +0x43, 0x75, 0xF8, 0xEC, +0x35, 0x20, +0x3D, 0x20, + +0x43, 0x43, 0x2D, 0xDF, +0x53, 0x53, 0x2D, 0xDF, + +0xAE, 0x1E, 0x0E, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x48, 0x35, 0x48, 0xBF, +0x58, 0x35, 0x58, 0xBF, + +0x68, 0x35, 0x68, 0xBF, +0x49, 0x3D, 0x49, 0xBF, + +0x59, 0x3D, 0x59, 0xBF, +0x69, 0x3D, 0x69, 0xBF, + +0x63, 0x63, 0x2D, 0xDF, +0x4D, 0x7D, 0xF8, 0xEC, + +0x59, 0xE3, +0x00, 0xE0, +0xB8, 0x38, 0x33, 0xBF, + +0x2D, 0x73, +0x30, 0x76, +0x18, 0x3A, 0x41, 0xE9, + +0x3F, 0x53, 0xA0, 0xE8, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x63, 0xA0, 0xE8, + +0x50, 0x70, 0xF8, 0xEC, +0x2B, 0x50, 0x3C, 0xE9, + +0x1F, 0x0F, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x59, 0x78, 0xF8, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x46, 0x37, 0x46, 0xDF, +0x56, 0x3F, 0x56, 0xDF, + +0x2B, 0x40, 0x3D, 0xE9, +0x66, 0x3D, 0x66, 0xDF, + +0x1D, 0x32, 0x41, 0xE9, +0x67, 0x3D, 0x67, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3F, 0x57, 0xDF, + +0x2A, 0x40, 0x20, 0xE9, +0x59, 0x3F, 0x59, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x69, 0x3D, 0x69, 0xDF, + +0x48, 0x37, 0x48, 0xDF, +0x58, 0x3F, 0x58, 0xDF, + +0x68, 0x3D, 0x68, 0xDF, +0x49, 0x37, 0x49, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x0F, 0xCF, 0x74, 0xC2, +0x37, 0xCF, 0x74, 0xC4, + +0x0A, 0x44, 0x54, 0xB0, +0x02, 0x44, 0x64, 0xB0, + +0x3D, 0xCF, 0x74, 0xC0, +0x34, 0x37, 0x20, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x38, 0x0F, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x54, 0xB2, +0x1A, 0x44, 0x64, 0xB2, + +0x31, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x0F, 0xCF, 0x75, 0xC0, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x3D, 0xCF, 0x75, 0xC2, +0x37, 0xCF, 0x75, 0xC4, + +0x31, 0x53, 0x2F, 0x9F, +0xA6, 0x0F, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA3, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x54, 0xB4, +0x1A, 0x44, 0x64, 0xB4, + +0x0A, 0x45, 0x55, 0xB0, +0x02, 0x45, 0x65, 0xB0, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0xA0, 0x37, 0x20, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x30, 0x50, 0x2E, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x2A, 0x45, 0x55, 0xB2, +0x1A, 0x45, 0x65, 0xB2, + +0x0A, 0x45, 0x55, 0xB4, +0x02, 0x45, 0x65, 0xB4, + +0x38, 0x21, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x2A, 0x20, +0x1A, 0x20, +0x0A, 0x20, +0x02, 0x20, + +0x2A, 0x46, 0x56, 0xBF, +0x1A, 0x46, 0x66, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x36, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x37, 0x39, 0x4F, 0xE9, + +0x30, 0x50, 0x2E, 0x9F, +0xA7, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0xA8, 0x38, 0x4F, 0xE9, + +0x0A, 0x47, 0x57, 0xBF, +0x02, 0x47, 0x67, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0xA4, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA5, 0x39, 0x4F, 0xE9, + +0x2A, 0x43, 0x53, 0xBF, +0x1A, 0x43, 0x63, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0xA1, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0xA2, 0x38, 0x4F, 0xE9, + +0x0A, 0x48, 0x58, 0xBF, +0x02, 0x48, 0x68, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x2A, 0x49, 0x59, 0xBF, +0x1A, 0x49, 0x69, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x82, 0x30, 0x57, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x83, 0x38, 0x57, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x84, 0x31, 0x5E, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x85, 0x39, 0x5E, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8A, 0x36, 0x20, 0xE9, + +0x87, 0x77, 0x57, 0xE9, +0x8B, 0x3E, 0xBF, 0xEA, + +0x80, 0x30, 0x57, 0xE9, +0x81, 0x38, 0x57, 0xE9, + +0x82, 0x31, 0x57, 0xE9, +0x86, 0x78, 0x57, 0xE9, + +0x83, 0x39, 0x57, 0xE9, +0x87, 0x79, 0x57, 0xE9, + +0x30, 0x1F, 0x5F, 0xE9, +0x8A, 0x34, 0x20, 0xE9, + +0x8B, 0x3C, 0x20, 0xE9, +0x37, 0x50, 0x60, 0xBD, + +0x57, 0x0D, 0x20, 0xE9, +0x35, 0x51, 0x61, 0xBD, + +0x2B, 0x50, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x0E, 0x77, + +0x24, 0x51, 0x20, 0xE9, +0x92, 0xFF, 0x20, 0xEA, + +0x16, 0x0E, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x0B, 0x46, 0xA0, 0xE8, +0x1B, 0x56, 0xA0, 0xE8, + +0x2B, 0x66, 0xA0, 0xE8, +0x0C, 0x47, 0xA0, 0xE8, + +0x1C, 0x57, 0xA0, 0xE8, +0x2C, 0x67, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x57, 0x80, 0x57, 0xCF, + +0x66, 0x33, 0x66, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x67, 0x3B, 0x67, 0xCF, + +0x0B, 0x48, 0xA0, 0xE8, +0x1B, 0x58, 0xA0, 0xE8, + +0x2B, 0x68, 0xA0, 0xE8, +0x0C, 0x49, 0xA0, 0xE8, + +0x1C, 0x59, 0xA0, 0xE8, +0x2C, 0x69, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x34, 0xD7, 0x34, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3C, 0xD7, 0x3C, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x34, 0x80, 0x34, 0xBD, +0x3C, 0x80, 0x3C, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x48, 0x80, 0x48, 0xCF, +0x59, 0x80, 0x59, 0xCF, + +0x68, 0x33, 0x68, 0xCF, +0x49, 0x3B, 0x49, 0xCF, + +0xB2, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x58, 0x33, 0x58, 0xCF, +0x69, 0x3B, 0x69, 0xCF, + +0x70, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_t2gzsa[] = { + +0x00, 0x8A, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x0A, 0x40, 0x50, 0xBF, +0x2A, 0x40, 0x60, 0xBF, + +0x32, 0x41, 0x51, 0xBF, +0x3A, 0x41, 0x61, 0xBF, + +0xC3, 0x6B, +0xD3, 0x6B, +0x00, 0x8A, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x53, 0xA0, 0xE8, + +0xAD, 0xEE, 0x23, 0x9F, +0x00, 0xE0, +0x51, 0x04, + +0x90, 0xE2, +0x61, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x51, 0x41, 0xE0, 0xEC, +0x39, 0x67, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x63, 0xA0, 0xE8, + +0x61, 0x41, 0xE0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x8A, 0x80, 0x15, 0xEA, +0x10, 0x04, +0x20, 0x04, + +0x61, 0x51, 0xE0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x52, 0xBF, +0x0F, 0x52, 0xA0, 0xE8, + +0x1A, 0x42, 0x62, 0xBF, +0x1E, 0x51, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x0E, 0x61, 0x60, 0xEA, + +0x32, 0x40, 0x50, 0xBD, +0x22, 0x40, 0x60, 0xBD, + +0x12, 0x41, 0x51, 0xBD, +0x3A, 0x41, 0x61, 0xBD, + +0xBF, 0x2F, 0x0E, 0xBD, +0x97, 0xE2, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x35, 0x48, 0xB1, 0xE8, +0x3D, 0x59, 0xB1, 0xE8, + +0x46, 0x31, 0x46, 0xBF, +0x56, 0x31, 0x56, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x66, 0x31, 0x66, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x57, 0x39, 0x57, 0xBF, +0x67, 0x39, 0x67, 0xBF, + +0x7B, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x35, 0x00, +0x3D, 0x00, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0x8D, 0x2F, 0x1E, 0xBD, + +0x43, 0x75, 0xF8, 0xEC, +0x35, 0x20, +0x3D, 0x20, + +0x43, 0x43, 0x2D, 0xDF, +0x53, 0x53, 0x2D, 0xDF, + +0xAE, 0x1E, 0x0E, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x48, 0x35, 0x48, 0xBF, +0x58, 0x35, 0x58, 0xBF, + +0x68, 0x35, 0x68, 0xBF, +0x49, 0x3D, 0x49, 0xBF, + +0x59, 0x3D, 0x59, 0xBF, +0x69, 0x3D, 0x69, 0xBF, + +0x63, 0x63, 0x2D, 0xDF, +0x4D, 0x7D, 0xF8, 0xEC, + +0x59, 0xE3, +0x00, 0xE0, +0xB8, 0x38, 0x33, 0xBF, + +0x2D, 0x73, +0x30, 0x76, +0x18, 0x3A, 0x41, 0xE9, + +0x3F, 0x53, 0xA0, 0xE8, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x63, 0xA0, 0xE8, + +0x50, 0x70, 0xF8, 0xEC, +0x2B, 0x50, 0x3C, 0xE9, + +0x1F, 0x0F, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x59, 0x78, 0xF8, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x46, 0x37, 0x46, 0xDF, +0x56, 0x3F, 0x56, 0xDF, + +0x2B, 0x40, 0x3D, 0xE9, +0x66, 0x3D, 0x66, 0xDF, + +0x1D, 0x32, 0x41, 0xE9, +0x67, 0x3D, 0x67, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3F, 0x57, 0xDF, + +0x2A, 0x40, 0x20, 0xE9, +0x59, 0x3F, 0x59, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x69, 0x3D, 0x69, 0xDF, + +0x48, 0x37, 0x48, 0xDF, +0x58, 0x3F, 0x58, 0xDF, + +0x68, 0x3D, 0x68, 0xDF, +0x49, 0x37, 0x49, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x0F, 0xCF, 0x74, 0xC2, +0x37, 0xCF, 0x74, 0xC4, + +0x0A, 0x44, 0x54, 0xB0, +0x02, 0x44, 0x64, 0xB0, + +0x3D, 0xCF, 0x74, 0xC0, +0x34, 0x37, 0x20, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x38, 0x0F, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x54, 0xB2, +0x1A, 0x44, 0x64, 0xB2, + +0x36, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x0F, 0xCF, 0x75, 0xC0, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x3D, 0xCF, 0x75, 0xC2, +0x37, 0xCF, 0x75, 0xC4, + +0x31, 0x53, 0x2F, 0x9F, +0xA6, 0x0F, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA3, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x54, 0xB4, +0x1A, 0x44, 0x64, 0xB4, + +0x0A, 0x45, 0x55, 0xB0, +0x02, 0x45, 0x65, 0xB0, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0xA0, 0x37, 0x20, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x30, 0x50, 0x2E, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x2A, 0x45, 0x55, 0xB2, +0x1A, 0x45, 0x65, 0xB2, + +0x0A, 0x45, 0x55, 0xB4, +0x02, 0x45, 0x65, 0xB4, + +0x0F, 0xCF, 0x74, 0xC6, +0x2A, 0x20, +0x1A, 0x20, + +0xA7, 0x30, 0x4F, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x9C, 0x0F, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA8, 0x38, 0x4F, 0xE9, + +0x2A, 0x44, 0x54, 0xB6, +0x1A, 0x44, 0x64, 0xB6, + +0x30, 0x50, 0x2E, 0x9F, +0x36, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x37, 0x39, 0x4F, 0xE9, + +0x00, 0x80, 0x00, 0xE8, +0x2A, 0x20, +0x1A, 0x20, + +0x2A, 0x46, 0x56, 0xBF, +0x1A, 0x46, 0x66, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0xA4, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA5, 0x39, 0x4F, 0xE9, + +0x0A, 0x47, 0x57, 0xBF, +0x02, 0x47, 0x67, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0xA1, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA2, 0x38, 0x4F, 0xE9, + +0x2A, 0x43, 0x53, 0xBF, +0x1A, 0x43, 0x63, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x9D, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x9E, 0x39, 0x4F, 0xE9, + +0x0A, 0x48, 0x58, 0xBF, +0x02, 0x48, 0x68, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x2A, 0x49, 0x59, 0xBF, +0x1A, 0x49, 0x69, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x82, 0x30, 0x57, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x83, 0x38, 0x57, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x84, 0x31, 0x5E, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x85, 0x39, 0x5E, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8A, 0x36, 0x20, 0xE9, + +0x87, 0x77, 0x57, 0xE9, +0x8B, 0x3E, 0xBF, 0xEA, + +0x80, 0x30, 0x57, 0xE9, +0x81, 0x38, 0x57, 0xE9, + +0x82, 0x31, 0x57, 0xE9, +0x86, 0x78, 0x57, 0xE9, + +0x83, 0x39, 0x57, 0xE9, +0x87, 0x79, 0x57, 0xE9, + +0x30, 0x1F, 0x5F, 0xE9, +0x8A, 0x34, 0x20, 0xE9, + +0x8B, 0x3C, 0x20, 0xE9, +0x37, 0x50, 0x60, 0xBD, + +0x57, 0x0D, 0x20, 0xE9, +0x35, 0x51, 0x61, 0xBD, + +0x2B, 0x50, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x0E, 0x77, + +0x24, 0x51, 0x20, 0xE9, +0x8D, 0xFF, 0x20, 0xEA, + +0x16, 0x0E, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x0B, 0x46, 0xA0, 0xE8, +0x1B, 0x56, 0xA0, 0xE8, + +0x2B, 0x66, 0xA0, 0xE8, +0x0C, 0x47, 0xA0, 0xE8, + +0x1C, 0x57, 0xA0, 0xE8, +0x2C, 0x67, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x57, 0x80, 0x57, 0xCF, + +0x66, 0x33, 0x66, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x67, 0x3B, 0x67, 0xCF, + +0x0B, 0x48, 0xA0, 0xE8, +0x1B, 0x58, 0xA0, 0xE8, + +0x2B, 0x68, 0xA0, 0xE8, +0x0C, 0x49, 0xA0, 0xE8, + +0x1C, 0x59, 0xA0, 0xE8, +0x2C, 0x69, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x34, 0xD7, 0x34, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3C, 0xD7, 0x3C, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x34, 0x80, 0x34, 0xBD, +0x3C, 0x80, 0x3C, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x48, 0x80, 0x48, 0xCF, +0x59, 0x80, 0x59, 0xCF, + +0x68, 0x33, 0x68, 0xCF, +0x49, 0x3B, 0x49, 0xCF, + +0xAD, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x58, 0x33, 0x58, 0xCF, +0x69, 0x3B, 0x69, 0xCF, + +0x6B, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_t2gzsaf[] = { + +0x00, 0x8A, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x0A, 0x40, 0x50, 0xBF, +0x2A, 0x40, 0x60, 0xBF, + +0x32, 0x41, 0x51, 0xBF, +0x3A, 0x41, 0x61, 0xBF, + +0xC3, 0x6B, +0xD3, 0x6B, +0x00, 0x8A, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x53, 0xA0, 0xE8, + +0xAD, 0xEE, 0x23, 0x9F, +0x00, 0xE0, +0x51, 0x04, + +0x90, 0xE2, +0x61, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x51, 0x41, 0xE0, 0xEC, +0x39, 0x67, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x63, 0xA0, 0xE8, + +0x61, 0x41, 0xE0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x8E, 0x80, 0x15, 0xEA, +0x10, 0x04, +0x20, 0x04, + +0x61, 0x51, 0xE0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x52, 0xBF, +0x0F, 0x52, 0xA0, 0xE8, + +0x1A, 0x42, 0x62, 0xBF, +0x1E, 0x51, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x0E, 0x61, 0x60, 0xEA, + +0x32, 0x40, 0x50, 0xBD, +0x22, 0x40, 0x60, 0xBD, + +0x12, 0x41, 0x51, 0xBD, +0x3A, 0x41, 0x61, 0xBD, + +0xBF, 0x2F, 0x0E, 0xBD, +0x97, 0xE2, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x35, 0x48, 0xB1, 0xE8, +0x3D, 0x59, 0xB1, 0xE8, + +0x46, 0x31, 0x46, 0xBF, +0x56, 0x31, 0x56, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x66, 0x31, 0x66, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x57, 0x39, 0x57, 0xBF, +0x67, 0x39, 0x67, 0xBF, + +0x7F, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x35, 0x00, +0x3D, 0x00, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0x8D, 0x2F, 0x1E, 0xBD, + +0x43, 0x75, 0xF8, 0xEC, +0x35, 0x20, +0x3D, 0x20, + +0x43, 0x43, 0x2D, 0xDF, +0x53, 0x53, 0x2D, 0xDF, + +0xAE, 0x1E, 0x0E, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x48, 0x35, 0x48, 0xBF, +0x58, 0x35, 0x58, 0xBF, + +0x68, 0x35, 0x68, 0xBF, +0x49, 0x3D, 0x49, 0xBF, + +0x59, 0x3D, 0x59, 0xBF, +0x69, 0x3D, 0x69, 0xBF, + +0x63, 0x63, 0x2D, 0xDF, +0x4D, 0x7D, 0xF8, 0xEC, + +0x59, 0xE3, +0x00, 0xE0, +0xB8, 0x38, 0x33, 0xBF, + +0x2D, 0x73, +0x30, 0x76, +0x18, 0x3A, 0x41, 0xE9, + +0x3F, 0x53, 0xA0, 0xE8, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x63, 0xA0, 0xE8, + +0x50, 0x70, 0xF8, 0xEC, +0x2B, 0x50, 0x3C, 0xE9, + +0x1F, 0x0F, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x59, 0x78, 0xF8, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x46, 0x37, 0x46, 0xDF, +0x56, 0x3F, 0x56, 0xDF, + +0x2B, 0x40, 0x3D, 0xE9, +0x66, 0x3D, 0x66, 0xDF, + +0x1D, 0x32, 0x41, 0xE9, +0x67, 0x3D, 0x67, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3F, 0x57, 0xDF, + +0x2A, 0x40, 0x20, 0xE9, +0x59, 0x3F, 0x59, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x69, 0x3D, 0x69, 0xDF, + +0x48, 0x37, 0x48, 0xDF, +0x58, 0x3F, 0x58, 0xDF, + +0x68, 0x3D, 0x68, 0xDF, +0x49, 0x37, 0x49, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x0F, 0xCF, 0x74, 0xC2, +0x37, 0xCF, 0x74, 0xC4, + +0x0A, 0x44, 0x54, 0xB0, +0x02, 0x44, 0x64, 0xB0, + +0x3D, 0xCF, 0x74, 0xC0, +0x34, 0x37, 0x20, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x38, 0x0F, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x54, 0xB2, +0x1A, 0x44, 0x64, 0xB2, + +0x3A, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x0F, 0xCF, 0x75, 0xC0, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x3D, 0xCF, 0x75, 0xC2, +0x37, 0xCF, 0x75, 0xC4, + +0x31, 0x53, 0x2F, 0x9F, +0xA6, 0x0F, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA3, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x54, 0xB4, +0x1A, 0x44, 0x64, 0xB4, + +0x0A, 0x45, 0x55, 0xB0, +0x02, 0x45, 0x65, 0xB0, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0xA0, 0x37, 0x20, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x30, 0x50, 0x2E, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x2A, 0x45, 0x55, 0xB2, +0x1A, 0x45, 0x65, 0xB2, + +0x0A, 0x45, 0x55, 0xB4, +0x02, 0x45, 0x65, 0xB4, + +0x0F, 0xCF, 0x74, 0xC6, +0x2A, 0x20, +0x1A, 0x20, + +0xA7, 0x30, 0x4F, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x9C, 0x0F, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA8, 0x38, 0x4F, 0xE9, + +0x2A, 0x44, 0x54, 0xB6, +0x1A, 0x44, 0x64, 0xB6, + +0x30, 0x50, 0x2E, 0x9F, +0x36, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x37, 0x39, 0x4F, 0xE9, + +0x0A, 0x45, 0x55, 0xB6, +0x02, 0x45, 0x65, 0xB6, + +0x3D, 0xCF, 0x75, 0xC6, +0x2A, 0x20, +0x1A, 0x20, + +0x2A, 0x46, 0x56, 0xBF, +0x1A, 0x46, 0x66, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0xA4, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA5, 0x39, 0x4F, 0xE9, + +0x31, 0x3D, 0x20, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x0A, 0x47, 0x57, 0xBF, +0x02, 0x47, 0x67, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0xA1, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0xA2, 0x38, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x9D, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x9E, 0x39, 0x4F, 0xE9, + +0x2A, 0x43, 0x53, 0xBF, +0x1A, 0x43, 0x63, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x35, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x39, 0x38, 0x4F, 0xE9, + +0x0A, 0x48, 0x58, 0xBF, +0x02, 0x48, 0x68, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x2A, 0x49, 0x59, 0xBF, +0x1A, 0x49, 0x69, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x82, 0x30, 0x57, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x83, 0x38, 0x57, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x84, 0x31, 0x5E, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x85, 0x39, 0x5E, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8A, 0x36, 0x20, 0xE9, + +0x87, 0x77, 0x57, 0xE9, +0x8B, 0x3E, 0xBF, 0xEA, + +0x80, 0x30, 0x57, 0xE9, +0x81, 0x38, 0x57, 0xE9, + +0x82, 0x31, 0x57, 0xE9, +0x86, 0x78, 0x57, 0xE9, + +0x83, 0x39, 0x57, 0xE9, +0x87, 0x79, 0x57, 0xE9, + +0x30, 0x1F, 0x5F, 0xE9, +0x8A, 0x34, 0x20, 0xE9, + +0x8B, 0x3C, 0x20, 0xE9, +0x37, 0x50, 0x60, 0xBD, + +0x57, 0x0D, 0x20, 0xE9, +0x35, 0x51, 0x61, 0xBD, + +0x2B, 0x50, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x0E, 0x77, + +0x24, 0x51, 0x20, 0xE9, +0x89, 0xFF, 0x20, 0xEA, + +0x16, 0x0E, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x0B, 0x46, 0xA0, 0xE8, +0x1B, 0x56, 0xA0, 0xE8, + +0x2B, 0x66, 0xA0, 0xE8, +0x0C, 0x47, 0xA0, 0xE8, + +0x1C, 0x57, 0xA0, 0xE8, +0x2C, 0x67, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x57, 0x80, 0x57, 0xCF, + +0x66, 0x33, 0x66, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x67, 0x3B, 0x67, 0xCF, + +0x0B, 0x48, 0xA0, 0xE8, +0x1B, 0x58, 0xA0, 0xE8, + +0x2B, 0x68, 0xA0, 0xE8, +0x0C, 0x49, 0xA0, 0xE8, + +0x1C, 0x59, 0xA0, 0xE8, +0x2C, 0x69, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x34, 0xD7, 0x34, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3C, 0xD7, 0x3C, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x34, 0x80, 0x34, 0xBD, +0x3C, 0x80, 0x3C, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x48, 0x80, 0x48, 0xCF, +0x59, 0x80, 0x59, 0xCF, + +0x68, 0x33, 0x68, 0xCF, +0x49, 0x3B, 0x49, 0xCF, + +0xA9, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x58, 0x33, 0x58, 0xCF, +0x69, 0x3B, 0x69, 0xCF, + +0x67, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_t2gzsf[] = { + +0x00, 0x8A, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x0A, 0x40, 0x50, 0xBF, +0x2A, 0x40, 0x60, 0xBF, + +0x32, 0x41, 0x51, 0xBF, +0x3A, 0x41, 0x61, 0xBF, + +0xC3, 0x6B, +0xD3, 0x6B, +0x00, 0x8A, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x53, 0xA0, 0xE8, + +0xAD, 0xEE, 0x23, 0x9F, +0x00, 0xE0, +0x51, 0x04, + +0x90, 0xE2, +0x61, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x51, 0x41, 0xE0, 0xEC, +0x39, 0x67, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x63, 0xA0, 0xE8, + +0x61, 0x41, 0xE0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x8A, 0x80, 0x15, 0xEA, +0x10, 0x04, +0x20, 0x04, + +0x61, 0x51, 0xE0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x52, 0xBF, +0x0F, 0x52, 0xA0, 0xE8, + +0x1A, 0x42, 0x62, 0xBF, +0x1E, 0x51, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x0E, 0x61, 0x60, 0xEA, + +0x32, 0x40, 0x50, 0xBD, +0x22, 0x40, 0x60, 0xBD, + +0x12, 0x41, 0x51, 0xBD, +0x3A, 0x41, 0x61, 0xBD, + +0xBF, 0x2F, 0x0E, 0xBD, +0x97, 0xE2, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x35, 0x48, 0xB1, 0xE8, +0x3D, 0x59, 0xB1, 0xE8, + +0x46, 0x31, 0x46, 0xBF, +0x56, 0x31, 0x56, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x66, 0x31, 0x66, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x57, 0x39, 0x57, 0xBF, +0x67, 0x39, 0x67, 0xBF, + +0x7B, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x35, 0x00, +0x3D, 0x00, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0x8D, 0x2F, 0x1E, 0xBD, + +0x43, 0x75, 0xF8, 0xEC, +0x35, 0x20, +0x3D, 0x20, + +0x43, 0x43, 0x2D, 0xDF, +0x53, 0x53, 0x2D, 0xDF, + +0xAE, 0x1E, 0x0E, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x48, 0x35, 0x48, 0xBF, +0x58, 0x35, 0x58, 0xBF, + +0x68, 0x35, 0x68, 0xBF, +0x49, 0x3D, 0x49, 0xBF, + +0x59, 0x3D, 0x59, 0xBF, +0x69, 0x3D, 0x69, 0xBF, + +0x63, 0x63, 0x2D, 0xDF, +0x4D, 0x7D, 0xF8, 0xEC, + +0x59, 0xE3, +0x00, 0xE0, +0xB8, 0x38, 0x33, 0xBF, + +0x2D, 0x73, +0x30, 0x76, +0x18, 0x3A, 0x41, 0xE9, + +0x3F, 0x53, 0xA0, 0xE8, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x63, 0xA0, 0xE8, + +0x50, 0x70, 0xF8, 0xEC, +0x2B, 0x50, 0x3C, 0xE9, + +0x1F, 0x0F, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x59, 0x78, 0xF8, 0xEC, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x46, 0x37, 0x46, 0xDF, +0x56, 0x3F, 0x56, 0xDF, + +0x2B, 0x40, 0x3D, 0xE9, +0x66, 0x3D, 0x66, 0xDF, + +0x1D, 0x32, 0x41, 0xE9, +0x67, 0x3D, 0x67, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3F, 0x57, 0xDF, + +0x2A, 0x40, 0x20, 0xE9, +0x59, 0x3F, 0x59, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x69, 0x3D, 0x69, 0xDF, + +0x48, 0x37, 0x48, 0xDF, +0x58, 0x3F, 0x58, 0xDF, + +0x68, 0x3D, 0x68, 0xDF, +0x49, 0x37, 0x49, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x0F, 0xCF, 0x74, 0xC2, +0x37, 0xCF, 0x74, 0xC4, + +0x0A, 0x44, 0x54, 0xB0, +0x02, 0x44, 0x64, 0xB0, + +0x3D, 0xCF, 0x74, 0xC0, +0x34, 0x37, 0x20, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x38, 0x0F, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x54, 0xB2, +0x1A, 0x44, 0x64, 0xB2, + +0x36, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x0F, 0xCF, 0x75, 0xC0, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x3D, 0xCF, 0x75, 0xC2, +0x37, 0xCF, 0x75, 0xC4, + +0x31, 0x53, 0x2F, 0x9F, +0xA6, 0x0F, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA3, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x54, 0xB4, +0x1A, 0x44, 0x64, 0xB4, + +0x0A, 0x45, 0x55, 0xB0, +0x02, 0x45, 0x65, 0xB0, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0xA0, 0x37, 0x20, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x30, 0x50, 0x2E, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x2A, 0x45, 0x55, 0xB2, +0x1A, 0x45, 0x65, 0xB2, + +0x0A, 0x45, 0x55, 0xB4, +0x02, 0x45, 0x65, 0xB4, + +0x0F, 0xCF, 0x75, 0xC6, +0x2A, 0x20, +0x1A, 0x20, + +0xA7, 0x30, 0x4F, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x31, 0x0F, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA8, 0x38, 0x4F, 0xE9, + +0x2A, 0x45, 0x55, 0xB6, +0x1A, 0x45, 0x65, 0xB6, + +0x30, 0x50, 0x2E, 0x9F, +0x36, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x37, 0x39, 0x4F, 0xE9, + +0x00, 0x80, 0x00, 0xE8, +0x2A, 0x20, +0x1A, 0x20, + +0x2A, 0x46, 0x56, 0xBF, +0x1A, 0x46, 0x66, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0xA4, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA5, 0x39, 0x4F, 0xE9, + +0x0A, 0x47, 0x57, 0xBF, +0x02, 0x47, 0x67, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0xA1, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA2, 0x38, 0x4F, 0xE9, + +0x2A, 0x43, 0x53, 0xBF, +0x1A, 0x43, 0x63, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x35, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x39, 0x39, 0x4F, 0xE9, + +0x0A, 0x48, 0x58, 0xBF, +0x02, 0x48, 0x68, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x2A, 0x49, 0x59, 0xBF, +0x1A, 0x49, 0x69, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x82, 0x30, 0x57, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x83, 0x38, 0x57, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x84, 0x31, 0x5E, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x85, 0x39, 0x5E, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8A, 0x36, 0x20, 0xE9, + +0x87, 0x77, 0x57, 0xE9, +0x8B, 0x3E, 0xBF, 0xEA, + +0x80, 0x30, 0x57, 0xE9, +0x81, 0x38, 0x57, 0xE9, + +0x82, 0x31, 0x57, 0xE9, +0x86, 0x78, 0x57, 0xE9, + +0x83, 0x39, 0x57, 0xE9, +0x87, 0x79, 0x57, 0xE9, + +0x30, 0x1F, 0x5F, 0xE9, +0x8A, 0x34, 0x20, 0xE9, + +0x8B, 0x3C, 0x20, 0xE9, +0x37, 0x50, 0x60, 0xBD, + +0x57, 0x0D, 0x20, 0xE9, +0x35, 0x51, 0x61, 0xBD, + +0x2B, 0x50, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x0E, 0x77, + +0x24, 0x51, 0x20, 0xE9, +0x8D, 0xFF, 0x20, 0xEA, + +0x16, 0x0E, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x0B, 0x46, 0xA0, 0xE8, +0x1B, 0x56, 0xA0, 0xE8, + +0x2B, 0x66, 0xA0, 0xE8, +0x0C, 0x47, 0xA0, 0xE8, + +0x1C, 0x57, 0xA0, 0xE8, +0x2C, 0x67, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x57, 0x80, 0x57, 0xCF, + +0x66, 0x33, 0x66, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x67, 0x3B, 0x67, 0xCF, + +0x0B, 0x48, 0xA0, 0xE8, +0x1B, 0x58, 0xA0, 0xE8, + +0x2B, 0x68, 0xA0, 0xE8, +0x0C, 0x49, 0xA0, 0xE8, + +0x1C, 0x59, 0xA0, 0xE8, +0x2C, 0x69, 0xA0, 0xE8, + +0x0B, 0x00, +0x1B, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x0C, 0x00, +0x1C, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x0B, 0x65, +0x1B, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x0C, 0x65, +0x1C, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x0B, 0x1B, 0x60, 0xEC, +0x34, 0xD7, 0x34, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x0C, 0x1C, 0x60, 0xEC, + +0x3C, 0xD7, 0x3C, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x0B, 0x2B, 0xDE, 0xE8, +0x1B, 0x80, 0xDE, 0xE8, + +0x34, 0x80, 0x34, 0xBD, +0x3C, 0x80, 0x3C, 0xBD, + +0x33, 0xD7, 0x0B, 0xBD, +0x3B, 0xD7, 0x1B, 0xBD, + +0x48, 0x80, 0x48, 0xCF, +0x59, 0x80, 0x59, 0xCF, + +0x68, 0x33, 0x68, 0xCF, +0x49, 0x3B, 0x49, 0xCF, + +0xAD, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x58, 0x33, 0x58, 0xCF, +0x69, 0x3B, 0x69, 0xCF, + +0x6B, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_tgz[] = { + +0x00, 0x88, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x22, 0x40, 0x48, 0xBF, +0x2A, 0x40, 0x50, 0xBF, + +0x32, 0x41, 0x49, 0xBF, +0x3A, 0x41, 0x51, 0xBF, + +0xC3, 0x6B, +0xCB, 0x6B, +0x00, 0x88, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x4B, 0xA0, 0xE8, + +0xAD, 0xEE, 0x29, 0x9F, +0x00, 0xE0, +0x49, 0x04, + +0x90, 0xE2, +0x51, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x49, 0x41, 0xC0, 0xEC, +0x39, 0x57, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x53, 0xA0, 0xE8, + +0x51, 0x41, 0xC0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x58, 0x80, 0x15, 0xEA, +0x08, 0x04, +0x10, 0x04, + +0x51, 0x49, 0xC0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x4A, 0xBF, +0x27, 0x4A, 0xA0, 0xE8, + +0x1A, 0x42, 0x52, 0xBF, +0x1E, 0x49, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x26, 0x51, 0x60, 0xEA, + +0x32, 0x40, 0x48, 0xBD, +0x22, 0x40, 0x50, 0xBD, + +0x12, 0x41, 0x49, 0xBD, +0x3A, 0x41, 0x51, 0xBD, + +0xBF, 0x2F, 0x26, 0xBD, +0x00, 0xE0, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x46, 0x31, 0x46, 0xBF, +0x4E, 0x31, 0x4E, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x56, 0x31, 0x56, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x4F, 0x39, 0x4F, 0xBF, +0x57, 0x39, 0x57, 0xBF, + +0x4A, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x42, 0x73, 0xF8, 0xEC, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0xA5, 0x2F, 0x1E, 0xBD, + +0x43, 0x43, 0x2D, 0xDF, +0x4B, 0x4B, 0x2D, 0xDF, + +0xAE, 0x1E, 0x26, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x53, 0x53, 0x2D, 0xDF, +0x00, 0x80, 0x00, 0xE8, + +0xB8, 0x38, 0x33, 0xBF, +0x00, 0xE0, +0x59, 0xE3, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x2B, 0x40, 0x3D, 0xE9, +0x3F, 0x4B, 0xA0, 0xE8, + +0x2D, 0x73, +0x30, 0x76, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x53, 0xA0, 0xE8, + +0x48, 0x70, 0xF8, 0xEC, +0x2B, 0x48, 0x3C, 0xE9, + +0x1F, 0x27, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x18, 0x3A, 0x41, 0xE9, +0x1D, 0x32, 0x41, 0xE9, + +0x2A, 0x40, 0x20, 0xE9, +0x56, 0x3D, 0x56, 0xDF, + +0x46, 0x37, 0x46, 0xDF, +0x4E, 0x3F, 0x4E, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x4F, 0x3F, 0x4F, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3D, 0x57, 0xDF, + +0x3D, 0xCF, 0x74, 0xC0, +0x37, 0xCF, 0x74, 0xC4, + +0x31, 0x53, 0x2F, 0x9F, +0x34, 0x80, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x0A, 0x44, 0x4C, 0xB0, +0x02, 0x44, 0x54, 0xB0, + +0x2A, 0x44, 0x4C, 0xB2, +0x1A, 0x44, 0x54, 0xB2, + +0x1D, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x3D, 0xCF, 0x74, 0xC2, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x2A, 0x44, 0x4C, 0xB4, +0x1A, 0x44, 0x54, 0xB4, + +0x39, 0xE5, 0x2C, 0x9F, +0x38, 0x3D, 0x20, 0xE9, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0x2A, 0x46, 0x4E, 0xBF, +0x1A, 0x46, 0x56, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x0A, 0x47, 0x4F, 0xBF, +0x02, 0x47, 0x57, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x2A, 0x43, 0x4B, 0xBF, +0x1A, 0x43, 0x53, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x36, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x37, 0x39, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x37, 0x48, 0x50, 0xBD, +0x8A, 0x36, 0x20, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8B, 0x3E, 0x20, 0xE9, + +0x82, 0x30, 0x57, 0xE9, +0x87, 0x77, 0x57, 0xE9, + +0x83, 0x38, 0x57, 0xE9, +0x35, 0x49, 0x51, 0xBD, + +0x84, 0x31, 0x5E, 0xE9, +0x30, 0x1F, 0x5F, 0xE9, + +0x85, 0x39, 0x5E, 0xE9, +0x57, 0x25, 0x20, 0xE9, + +0x2B, 0x48, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x26, 0x77, + +0x24, 0x49, 0x20, 0xE9, +0xAF, 0xFF, 0x20, 0xEA, + +0x16, 0x26, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x1C, 0x46, 0xA0, 0xE8, +0x23, 0x4E, 0xA0, 0xE8, + +0x2B, 0x56, 0xA0, 0xE8, +0x1D, 0x47, 0xA0, 0xE8, + +0x24, 0x4F, 0xA0, 0xE8, +0x2C, 0x57, 0xA0, 0xE8, + +0x1C, 0x00, +0x23, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x1D, 0x00, +0x24, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x1C, 0x65, +0x23, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x1D, 0x65, +0x24, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x1C, 0x23, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x1D, 0x24, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x1C, 0x2B, 0xDE, 0xE8, +0x23, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x1C, 0xBD, +0x3B, 0xD7, 0x23, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x4F, 0x80, 0x4F, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0xD6, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x4E, 0x33, 0x4E, 0xCF, +0x57, 0x3B, 0x57, 0xCF, + +0x9D, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_tgza[] = { + +0x00, 0x88, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x22, 0x40, 0x48, 0xBF, +0x2A, 0x40, 0x50, 0xBF, + +0x32, 0x41, 0x49, 0xBF, +0x3A, 0x41, 0x51, 0xBF, + +0xC3, 0x6B, +0xCB, 0x6B, +0x00, 0x88, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x4B, 0xA0, 0xE8, + +0xAD, 0xEE, 0x29, 0x9F, +0x00, 0xE0, +0x49, 0x04, + +0x90, 0xE2, +0x51, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x49, 0x41, 0xC0, 0xEC, +0x39, 0x57, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x53, 0xA0, 0xE8, + +0x51, 0x41, 0xC0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x5C, 0x80, 0x15, 0xEA, +0x08, 0x04, +0x10, 0x04, + +0x51, 0x49, 0xC0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x4A, 0xBF, +0x27, 0x4A, 0xA0, 0xE8, + +0x1A, 0x42, 0x52, 0xBF, +0x1E, 0x49, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x26, 0x51, 0x60, 0xEA, + +0x32, 0x40, 0x48, 0xBD, +0x22, 0x40, 0x50, 0xBD, + +0x12, 0x41, 0x49, 0xBD, +0x3A, 0x41, 0x51, 0xBD, + +0xBF, 0x2F, 0x26, 0xBD, +0x00, 0xE0, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x46, 0x31, 0x46, 0xBF, +0x4E, 0x31, 0x4E, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x56, 0x31, 0x56, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x4F, 0x39, 0x4F, 0xBF, +0x57, 0x39, 0x57, 0xBF, + +0x4E, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x42, 0x73, 0xF8, 0xEC, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0xA5, 0x2F, 0x1E, 0xBD, + +0x43, 0x43, 0x2D, 0xDF, +0x4B, 0x4B, 0x2D, 0xDF, + +0xAE, 0x1E, 0x26, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x53, 0x53, 0x2D, 0xDF, +0x00, 0x80, 0x00, 0xE8, + +0xB8, 0x38, 0x33, 0xBF, +0x00, 0xE0, +0x59, 0xE3, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x2B, 0x40, 0x3D, 0xE9, +0x3F, 0x4B, 0xA0, 0xE8, + +0x2D, 0x73, +0x30, 0x76, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x53, 0xA0, 0xE8, + +0x48, 0x70, 0xF8, 0xEC, +0x2B, 0x48, 0x3C, 0xE9, + +0x1F, 0x27, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x18, 0x3A, 0x41, 0xE9, +0x1D, 0x32, 0x41, 0xE9, + +0x2A, 0x40, 0x20, 0xE9, +0x56, 0x3D, 0x56, 0xDF, + +0x46, 0x37, 0x46, 0xDF, +0x4E, 0x3F, 0x4E, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x4F, 0x3F, 0x4F, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3D, 0x57, 0xDF, + +0x3D, 0xCF, 0x74, 0xC0, +0x37, 0xCF, 0x74, 0xC4, + +0x31, 0x53, 0x2F, 0x9F, +0x34, 0x80, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x27, 0xCF, 0x74, 0xC6, +0x3D, 0xCF, 0x74, 0xC2, + +0x0A, 0x44, 0x4C, 0xB0, +0x02, 0x44, 0x54, 0xB0, + +0x2A, 0x44, 0x4C, 0xB2, +0x1A, 0x44, 0x54, 0xB2, + +0x20, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x9C, 0x27, 0x20, 0xE9, + +0x0A, 0x44, 0x4C, 0xB4, +0x02, 0x44, 0x54, 0xB4, + +0x2A, 0x44, 0x4C, 0xB6, +0x1A, 0x44, 0x54, 0xB6, + +0x39, 0xE5, 0x2C, 0x9F, +0x38, 0x3D, 0x20, 0xE9, + +0x0A, 0x20, +0x02, 0x20, +0x2A, 0x20, +0x1A, 0x20, + +0x0A, 0x47, 0x4F, 0xBF, +0x02, 0x47, 0x57, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x2A, 0x46, 0x4E, 0xBF, +0x1A, 0x46, 0x56, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x36, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x37, 0x38, 0x4F, 0xE9, + +0x2A, 0x43, 0x4B, 0xBF, +0x1A, 0x43, 0x53, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x9D, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x9E, 0x39, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x37, 0x48, 0x50, 0xBD, +0x8A, 0x36, 0x20, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8B, 0x3E, 0x20, 0xE9, + +0x82, 0x30, 0x57, 0xE9, +0x87, 0x77, 0x57, 0xE9, + +0x83, 0x38, 0x57, 0xE9, +0x35, 0x49, 0x51, 0xBD, + +0x84, 0x31, 0x5E, 0xE9, +0x30, 0x1F, 0x5F, 0xE9, + +0x85, 0x39, 0x5E, 0xE9, +0x57, 0x25, 0x20, 0xE9, + +0x2B, 0x48, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x26, 0x77, + +0x24, 0x49, 0x20, 0xE9, +0xAB, 0xFF, 0x20, 0xEA, + +0x16, 0x26, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x1C, 0x46, 0xA0, 0xE8, +0x23, 0x4E, 0xA0, 0xE8, + +0x2B, 0x56, 0xA0, 0xE8, +0x1D, 0x47, 0xA0, 0xE8, + +0x24, 0x4F, 0xA0, 0xE8, +0x2C, 0x57, 0xA0, 0xE8, + +0x1C, 0x00, +0x23, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x1D, 0x00, +0x24, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x1C, 0x65, +0x23, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x1D, 0x65, +0x24, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x1C, 0x23, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x1D, 0x24, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x1C, 0x2B, 0xDE, 0xE8, +0x23, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x1C, 0xBD, +0x3B, 0xD7, 0x23, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x4F, 0x80, 0x4F, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0xD3, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x4E, 0x33, 0x4E, 0xCF, +0x57, 0x3B, 0x57, 0xCF, + +0x99, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_tgzaf[] = { + +0x00, 0x88, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x22, 0x40, 0x48, 0xBF, +0x2A, 0x40, 0x50, 0xBF, + +0x32, 0x41, 0x49, 0xBF, +0x3A, 0x41, 0x51, 0xBF, + +0xC3, 0x6B, +0xCB, 0x6B, +0x00, 0x88, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x4B, 0xA0, 0xE8, + +0xAD, 0xEE, 0x29, 0x9F, +0x00, 0xE0, +0x49, 0x04, + +0x90, 0xE2, +0x51, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x49, 0x41, 0xC0, 0xEC, +0x39, 0x57, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x53, 0xA0, 0xE8, + +0x51, 0x41, 0xC0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x61, 0x80, 0x15, 0xEA, +0x08, 0x04, +0x10, 0x04, + +0x51, 0x49, 0xC0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x4A, 0xBF, +0x27, 0x4A, 0xA0, 0xE8, + +0x1A, 0x42, 0x52, 0xBF, +0x1E, 0x49, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x26, 0x51, 0x60, 0xEA, + +0x32, 0x40, 0x48, 0xBD, +0x22, 0x40, 0x50, 0xBD, + +0x12, 0x41, 0x49, 0xBD, +0x3A, 0x41, 0x51, 0xBD, + +0xBF, 0x2F, 0x26, 0xBD, +0x00, 0xE0, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x46, 0x31, 0x46, 0xBF, +0x4E, 0x31, 0x4E, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x56, 0x31, 0x56, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x4F, 0x39, 0x4F, 0xBF, +0x57, 0x39, 0x57, 0xBF, + +0x53, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x42, 0x73, 0xF8, 0xEC, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0xA5, 0x2F, 0x1E, 0xBD, + +0x43, 0x43, 0x2D, 0xDF, +0x4B, 0x4B, 0x2D, 0xDF, + +0xAE, 0x1E, 0x26, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x53, 0x53, 0x2D, 0xDF, +0x00, 0x80, 0x00, 0xE8, + +0xB8, 0x38, 0x33, 0xBF, +0x00, 0xE0, +0x59, 0xE3, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x2B, 0x40, 0x3D, 0xE9, +0x3F, 0x4B, 0xA0, 0xE8, + +0x2D, 0x73, +0x30, 0x76, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x53, 0xA0, 0xE8, + +0x48, 0x70, 0xF8, 0xEC, +0x2B, 0x48, 0x3C, 0xE9, + +0x1F, 0x27, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x18, 0x3A, 0x41, 0xE9, +0x1D, 0x32, 0x41, 0xE9, + +0x2A, 0x40, 0x20, 0xE9, +0x56, 0x3D, 0x56, 0xDF, + +0x46, 0x37, 0x46, 0xDF, +0x4E, 0x3F, 0x4E, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x4F, 0x3F, 0x4F, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3D, 0x57, 0xDF, + +0x3D, 0xCF, 0x74, 0xC0, +0x37, 0xCF, 0x74, 0xC4, + +0x0A, 0x44, 0x4C, 0xB0, +0x02, 0x44, 0x54, 0xB0, + +0x31, 0x53, 0x2F, 0x9F, +0x34, 0x37, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x4C, 0xB2, +0x1A, 0x44, 0x54, 0xB2, + +0x26, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0x3D, 0xCF, 0x74, 0xC2, +0x27, 0xCF, 0x74, 0xC6, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x9C, 0x27, 0x20, 0xE9, + +0x0A, 0x44, 0x4C, 0xB4, +0x02, 0x44, 0x54, 0xB4, + +0x2A, 0x44, 0x4C, 0xB6, +0x1A, 0x44, 0x54, 0xB6, + +0x39, 0xE5, 0x2C, 0x9F, +0x38, 0x3D, 0x20, 0xE9, + +0x0A, 0x20, +0x02, 0x20, +0x2A, 0x20, +0x1A, 0x20, + +0x3D, 0xCF, 0x75, 0xC6, +0x00, 0x80, 0x00, 0xE8, + +0x30, 0x50, 0x2E, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x0A, 0x45, 0x4D, 0xB6, +0x02, 0x45, 0x55, 0xB6, + +0x31, 0x53, 0x2F, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x31, 0x3D, 0x20, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x2A, 0x46, 0x4E, 0xBF, +0x1A, 0x46, 0x56, 0xBF, + +0x0A, 0x47, 0x4F, 0xBF, +0x02, 0x47, 0x57, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x36, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x37, 0x38, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x9D, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x9E, 0x39, 0x4F, 0xE9, + +0x2A, 0x43, 0x4B, 0xBF, +0x1A, 0x43, 0x53, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x35, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x39, 0x38, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x37, 0x48, 0x50, 0xBD, +0x8A, 0x36, 0x20, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8B, 0x3E, 0x20, 0xE9, + +0x82, 0x30, 0x57, 0xE9, +0x87, 0x77, 0x57, 0xE9, + +0x83, 0x38, 0x57, 0xE9, +0x35, 0x49, 0x51, 0xBD, + +0x84, 0x31, 0x5E, 0xE9, +0x30, 0x1F, 0x5F, 0xE9, + +0x85, 0x39, 0x5E, 0xE9, +0x57, 0x25, 0x20, 0xE9, + +0x2B, 0x48, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x26, 0x77, + +0x24, 0x49, 0x20, 0xE9, +0xA6, 0xFF, 0x20, 0xEA, + +0x16, 0x26, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x1C, 0x46, 0xA0, 0xE8, +0x23, 0x4E, 0xA0, 0xE8, + +0x2B, 0x56, 0xA0, 0xE8, +0x1D, 0x47, 0xA0, 0xE8, + +0x24, 0x4F, 0xA0, 0xE8, +0x2C, 0x57, 0xA0, 0xE8, + +0x1C, 0x00, +0x23, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x1D, 0x00, +0x24, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x1C, 0x65, +0x23, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x1D, 0x65, +0x24, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x1C, 0x23, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x1D, 0x24, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x1C, 0x2B, 0xDE, 0xE8, +0x23, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x1C, 0xBD, +0x3B, 0xD7, 0x23, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x4F, 0x80, 0x4F, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0xCD, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x4E, 0x33, 0x4E, 0xCF, +0x57, 0x3B, 0x57, 0xCF, + +0x94, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_tgzf[] = { + +0x00, 0x88, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x22, 0x40, 0x48, 0xBF, +0x2A, 0x40, 0x50, 0xBF, + +0x32, 0x41, 0x49, 0xBF, +0x3A, 0x41, 0x51, 0xBF, + +0xC3, 0x6B, +0xCB, 0x6B, +0x00, 0x88, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x4B, 0xA0, 0xE8, + +0xAD, 0xEE, 0x29, 0x9F, +0x00, 0xE0, +0x49, 0x04, + +0x90, 0xE2, +0x51, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x49, 0x41, 0xC0, 0xEC, +0x39, 0x57, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x53, 0xA0, 0xE8, + +0x51, 0x41, 0xC0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x5D, 0x80, 0x15, 0xEA, +0x08, 0x04, +0x10, 0x04, + +0x51, 0x49, 0xC0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x4A, 0xBF, +0x27, 0x4A, 0xA0, 0xE8, + +0x1A, 0x42, 0x52, 0xBF, +0x1E, 0x49, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x26, 0x51, 0x60, 0xEA, + +0x32, 0x40, 0x48, 0xBD, +0x22, 0x40, 0x50, 0xBD, + +0x12, 0x41, 0x49, 0xBD, +0x3A, 0x41, 0x51, 0xBD, + +0xBF, 0x2F, 0x26, 0xBD, +0x00, 0xE0, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x46, 0x31, 0x46, 0xBF, +0x4E, 0x31, 0x4E, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x56, 0x31, 0x56, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x4F, 0x39, 0x4F, 0xBF, +0x57, 0x39, 0x57, 0xBF, + +0x4F, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x42, 0x73, 0xF8, 0xEC, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0xA5, 0x2F, 0x1E, 0xBD, + +0x43, 0x43, 0x2D, 0xDF, +0x4B, 0x4B, 0x2D, 0xDF, + +0xAE, 0x1E, 0x26, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x53, 0x53, 0x2D, 0xDF, +0x00, 0x80, 0x00, 0xE8, + +0xB8, 0x38, 0x33, 0xBF, +0x00, 0xE0, +0x59, 0xE3, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x2B, 0x40, 0x3D, 0xE9, +0x3F, 0x4B, 0xA0, 0xE8, + +0x2D, 0x73, +0x30, 0x76, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x53, 0xA0, 0xE8, + +0x48, 0x70, 0xF8, 0xEC, +0x2B, 0x48, 0x3C, 0xE9, + +0x1F, 0x27, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x18, 0x3A, 0x41, 0xE9, +0x1D, 0x32, 0x41, 0xE9, + +0x2A, 0x40, 0x20, 0xE9, +0x56, 0x3D, 0x56, 0xDF, + +0x46, 0x37, 0x46, 0xDF, +0x4E, 0x3F, 0x4E, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x4F, 0x3F, 0x4F, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3D, 0x57, 0xDF, + +0x3D, 0xCF, 0x74, 0xC0, +0x37, 0xCF, 0x74, 0xC4, + +0x39, 0xE5, 0x2C, 0x9F, +0x34, 0x80, 0x20, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x88, 0x73, 0x5E, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x27, 0xCF, 0x75, 0xC6, +0x3C, 0x3D, 0x20, 0xE9, + +0x0A, 0x44, 0x4C, 0xB0, +0x02, 0x44, 0x54, 0xB0, + +0x2A, 0x44, 0x4C, 0xB2, +0x1A, 0x44, 0x54, 0xB2, + +0x20, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x3D, 0xCF, 0x74, 0xC2, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x31, 0x27, 0x20, 0xE9, + +0x0A, 0x44, 0x4C, 0xB4, +0x02, 0x44, 0x54, 0xB4, + +0x2A, 0x45, 0x4D, 0xB6, +0x1A, 0x45, 0x55, 0xB6, + +0x39, 0xE5, 0x2C, 0x9F, +0x38, 0x3D, 0x20, 0xE9, + +0x0A, 0x20, +0x02, 0x20, +0x2A, 0x20, +0x1A, 0x20, + +0x0A, 0x47, 0x4F, 0xBF, +0x02, 0x47, 0x57, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x2A, 0x46, 0x4E, 0xBF, +0x1A, 0x46, 0x56, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x36, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x37, 0x38, 0x4F, 0xE9, + +0x2A, 0x43, 0x4B, 0xBF, +0x1A, 0x43, 0x53, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x35, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x39, 0x39, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x37, 0x48, 0x50, 0xBD, +0x8A, 0x36, 0x20, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8B, 0x3E, 0x20, 0xE9, + +0x82, 0x30, 0x57, 0xE9, +0x87, 0x77, 0x57, 0xE9, + +0x83, 0x38, 0x57, 0xE9, +0x35, 0x49, 0x51, 0xBD, + +0x84, 0x31, 0x5E, 0xE9, +0x30, 0x1F, 0x5F, 0xE9, + +0x85, 0x39, 0x5E, 0xE9, +0x57, 0x25, 0x20, 0xE9, + +0x2B, 0x48, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x26, 0x77, + +0x24, 0x49, 0x20, 0xE9, +0xAA, 0xFF, 0x20, 0xEA, + +0x16, 0x26, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x1C, 0x46, 0xA0, 0xE8, +0x23, 0x4E, 0xA0, 0xE8, + +0x2B, 0x56, 0xA0, 0xE8, +0x1D, 0x47, 0xA0, 0xE8, + +0x24, 0x4F, 0xA0, 0xE8, +0x2C, 0x57, 0xA0, 0xE8, + +0x1C, 0x00, +0x23, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x1D, 0x00, +0x24, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x1C, 0x65, +0x23, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x1D, 0x65, +0x24, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x1C, 0x23, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x1D, 0x24, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x1C, 0x2B, 0xDE, 0xE8, +0x23, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x1C, 0xBD, +0x3B, 0xD7, 0x23, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x4F, 0x80, 0x4F, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0xD3, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x4E, 0x33, 0x4E, 0xCF, +0x57, 0x3B, 0x57, 0xCF, + +0x98, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_tgzs[] = { + +0x00, 0x88, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x22, 0x40, 0x48, 0xBF, +0x2A, 0x40, 0x50, 0xBF, + +0x32, 0x41, 0x49, 0xBF, +0x3A, 0x41, 0x51, 0xBF, + +0xC3, 0x6B, +0xCB, 0x6B, +0x00, 0x88, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x4B, 0xA0, 0xE8, + +0xAD, 0xEE, 0x29, 0x9F, +0x00, 0xE0, +0x49, 0x04, + +0x90, 0xE2, +0x51, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x49, 0x41, 0xC0, 0xEC, +0x39, 0x57, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x53, 0xA0, 0xE8, + +0x51, 0x41, 0xC0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x65, 0x80, 0x15, 0xEA, +0x08, 0x04, +0x10, 0x04, + +0x51, 0x49, 0xC0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x4A, 0xBF, +0x27, 0x4A, 0xA0, 0xE8, + +0x1A, 0x42, 0x52, 0xBF, +0x1E, 0x49, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x26, 0x51, 0x60, 0xEA, + +0x32, 0x40, 0x48, 0xBD, +0x22, 0x40, 0x50, 0xBD, + +0x12, 0x41, 0x49, 0xBD, +0x3A, 0x41, 0x51, 0xBD, + +0xBF, 0x2F, 0x26, 0xBD, +0x00, 0xE0, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x46, 0x31, 0x46, 0xBF, +0x4E, 0x31, 0x4E, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x56, 0x31, 0x56, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x4F, 0x39, 0x4F, 0xBF, +0x57, 0x39, 0x57, 0xBF, + +0x57, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x42, 0x73, 0xF8, 0xEC, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0xA5, 0x2F, 0x1E, 0xBD, + +0x43, 0x43, 0x2D, 0xDF, +0x4B, 0x4B, 0x2D, 0xDF, + +0xAE, 0x1E, 0x26, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x53, 0x53, 0x2D, 0xDF, +0x00, 0x80, 0x00, 0xE8, + +0xB8, 0x38, 0x33, 0xBF, +0x00, 0xE0, +0x59, 0xE3, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x2B, 0x40, 0x3D, 0xE9, +0x3F, 0x4B, 0xA0, 0xE8, + +0x2D, 0x73, +0x30, 0x76, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x53, 0xA0, 0xE8, + +0x48, 0x70, 0xF8, 0xEC, +0x2B, 0x48, 0x3C, 0xE9, + +0x1F, 0x27, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x18, 0x3A, 0x41, 0xE9, +0x1D, 0x32, 0x41, 0xE9, + +0x2A, 0x40, 0x20, 0xE9, +0x56, 0x3D, 0x56, 0xDF, + +0x46, 0x37, 0x46, 0xDF, +0x4E, 0x3F, 0x4E, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x4F, 0x3F, 0x4F, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3D, 0x57, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x27, 0xCF, 0x74, 0xC2, +0x37, 0xCF, 0x74, 0xC4, + +0x0A, 0x44, 0x4C, 0xB0, +0x02, 0x44, 0x54, 0xB0, + +0x3D, 0xCF, 0x74, 0xC0, +0x34, 0x37, 0x20, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x38, 0x27, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x4C, 0xB2, +0x1A, 0x44, 0x54, 0xB2, + +0x29, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x27, 0xCF, 0x75, 0xC0, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x3D, 0xCF, 0x75, 0xC2, +0x37, 0xCF, 0x75, 0xC4, + +0x31, 0x53, 0x2F, 0x9F, +0xA6, 0x27, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA3, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x4C, 0xB4, +0x1A, 0x44, 0x54, 0xB4, + +0x0A, 0x45, 0x4D, 0xB0, +0x02, 0x45, 0x55, 0xB0, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0xA0, 0x37, 0x20, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x30, 0x50, 0x2E, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x2A, 0x45, 0x4D, 0xB2, +0x1A, 0x45, 0x55, 0xB2, + +0x0A, 0x45, 0x4D, 0xB4, +0x02, 0x45, 0x55, 0xB4, + +0x38, 0x21, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x0A, 0x20, +0x02, 0x20, +0x2A, 0x20, +0x1A, 0x20, + +0x2A, 0x46, 0x4E, 0xBF, +0x1A, 0x46, 0x56, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0x36, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x37, 0x39, 0x4F, 0xE9, + +0x30, 0x50, 0x2E, 0x9F, +0xA7, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0xA8, 0x38, 0x4F, 0xE9, + +0x0A, 0x47, 0x4F, 0xBF, +0x02, 0x47, 0x57, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0xA4, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA5, 0x39, 0x4F, 0xE9, + +0x2A, 0x43, 0x4B, 0xBF, +0x1A, 0x43, 0x53, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0xA1, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0xA2, 0x38, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x37, 0x48, 0x50, 0xBD, +0x8A, 0x36, 0x20, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8B, 0x3E, 0x20, 0xE9, + +0x82, 0x30, 0x57, 0xE9, +0x87, 0x77, 0x57, 0xE9, + +0x83, 0x38, 0x57, 0xE9, +0x35, 0x49, 0x51, 0xBD, + +0x84, 0x31, 0x5E, 0xE9, +0x30, 0x1F, 0x5F, 0xE9, + +0x85, 0x39, 0x5E, 0xE9, +0x57, 0x25, 0x20, 0xE9, + +0x2B, 0x48, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x26, 0x77, + +0x24, 0x49, 0x20, 0xE9, +0xA2, 0xFF, 0x20, 0xEA, + +0x16, 0x26, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x1C, 0x46, 0xA0, 0xE8, +0x23, 0x4E, 0xA0, 0xE8, + +0x2B, 0x56, 0xA0, 0xE8, +0x1D, 0x47, 0xA0, 0xE8, + +0x24, 0x4F, 0xA0, 0xE8, +0x2C, 0x57, 0xA0, 0xE8, + +0x1C, 0x00, +0x23, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x1D, 0x00, +0x24, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x1C, 0x65, +0x23, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x1D, 0x65, +0x24, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x1C, 0x23, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x1D, 0x24, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x1C, 0x2B, 0xDE, 0xE8, +0x23, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x1C, 0xBD, +0x3B, 0xD7, 0x23, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x4F, 0x80, 0x4F, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0xCA, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x4E, 0x33, 0x4E, 0xCF, +0x57, 0x3B, 0x57, 0xCF, + +0x90, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_tgzsa[] = { + +0x00, 0x88, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x22, 0x40, 0x48, 0xBF, +0x2A, 0x40, 0x50, 0xBF, + +0x32, 0x41, 0x49, 0xBF, +0x3A, 0x41, 0x51, 0xBF, + +0xC3, 0x6B, +0xCB, 0x6B, +0x00, 0x88, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x4B, 0xA0, 0xE8, + +0xAD, 0xEE, 0x29, 0x9F, +0x00, 0xE0, +0x49, 0x04, + +0x90, 0xE2, +0x51, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x49, 0x41, 0xC0, 0xEC, +0x39, 0x57, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x53, 0xA0, 0xE8, + +0x51, 0x41, 0xC0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x6A, 0x80, 0x15, 0xEA, +0x08, 0x04, +0x10, 0x04, + +0x51, 0x49, 0xC0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x4A, 0xBF, +0x27, 0x4A, 0xA0, 0xE8, + +0x1A, 0x42, 0x52, 0xBF, +0x1E, 0x49, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x26, 0x51, 0x60, 0xEA, + +0x32, 0x40, 0x48, 0xBD, +0x22, 0x40, 0x50, 0xBD, + +0x12, 0x41, 0x49, 0xBD, +0x3A, 0x41, 0x51, 0xBD, + +0xBF, 0x2F, 0x26, 0xBD, +0x00, 0xE0, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x46, 0x31, 0x46, 0xBF, +0x4E, 0x31, 0x4E, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x56, 0x31, 0x56, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x4F, 0x39, 0x4F, 0xBF, +0x57, 0x39, 0x57, 0xBF, + +0x5C, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x42, 0x73, 0xF8, 0xEC, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0xA5, 0x2F, 0x1E, 0xBD, + +0x43, 0x43, 0x2D, 0xDF, +0x4B, 0x4B, 0x2D, 0xDF, + +0xAE, 0x1E, 0x26, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x53, 0x53, 0x2D, 0xDF, +0x00, 0x80, 0x00, 0xE8, + +0xB8, 0x38, 0x33, 0xBF, +0x00, 0xE0, +0x59, 0xE3, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x2B, 0x40, 0x3D, 0xE9, +0x3F, 0x4B, 0xA0, 0xE8, + +0x2D, 0x73, +0x30, 0x76, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x53, 0xA0, 0xE8, + +0x48, 0x70, 0xF8, 0xEC, +0x2B, 0x48, 0x3C, 0xE9, + +0x1F, 0x27, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x18, 0x3A, 0x41, 0xE9, +0x1D, 0x32, 0x41, 0xE9, + +0x2A, 0x40, 0x20, 0xE9, +0x56, 0x3D, 0x56, 0xDF, + +0x46, 0x37, 0x46, 0xDF, +0x4E, 0x3F, 0x4E, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x4F, 0x3F, 0x4F, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3D, 0x57, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x27, 0xCF, 0x74, 0xC2, +0x37, 0xCF, 0x74, 0xC4, + +0x0A, 0x44, 0x4C, 0xB0, +0x02, 0x44, 0x54, 0xB0, + +0x3D, 0xCF, 0x74, 0xC0, +0x34, 0x37, 0x20, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x38, 0x27, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x4C, 0xB2, +0x1A, 0x44, 0x54, 0xB2, + +0x2E, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x27, 0xCF, 0x75, 0xC0, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x3D, 0xCF, 0x75, 0xC2, +0x37, 0xCF, 0x75, 0xC4, + +0x31, 0x53, 0x2F, 0x9F, +0xA6, 0x27, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA3, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x4C, 0xB4, +0x1A, 0x44, 0x54, 0xB4, + +0x0A, 0x45, 0x4D, 0xB0, +0x02, 0x45, 0x55, 0xB0, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0xA0, 0x37, 0x20, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x30, 0x50, 0x2E, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x2A, 0x45, 0x4D, 0xB2, +0x1A, 0x45, 0x55, 0xB2, + +0x0A, 0x45, 0x4D, 0xB4, +0x02, 0x45, 0x55, 0xB4, + +0x27, 0xCF, 0x74, 0xC6, +0x2A, 0x20, +0x1A, 0x20, + +0xA7, 0x30, 0x4F, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x9C, 0x27, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA8, 0x38, 0x4F, 0xE9, + +0x2A, 0x44, 0x4C, 0xB6, +0x1A, 0x44, 0x54, 0xB6, + +0x30, 0x50, 0x2E, 0x9F, +0x36, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x37, 0x39, 0x4F, 0xE9, + +0x00, 0x80, 0x00, 0xE8, +0x2A, 0x20, +0x1A, 0x20, + +0x2A, 0x46, 0x4E, 0xBF, +0x1A, 0x46, 0x56, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0xA4, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA5, 0x39, 0x4F, 0xE9, + +0x0A, 0x47, 0x4F, 0xBF, +0x02, 0x47, 0x57, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0xA1, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA2, 0x38, 0x4F, 0xE9, + +0x2A, 0x43, 0x4B, 0xBF, +0x1A, 0x43, 0x53, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x9D, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x9E, 0x39, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x37, 0x48, 0x50, 0xBD, +0x8A, 0x36, 0x20, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8B, 0x3E, 0x20, 0xE9, + +0x82, 0x30, 0x57, 0xE9, +0x87, 0x77, 0x57, 0xE9, + +0x83, 0x38, 0x57, 0xE9, +0x35, 0x49, 0x51, 0xBD, + +0x84, 0x31, 0x5E, 0xE9, +0x30, 0x1F, 0x5F, 0xE9, + +0x85, 0x39, 0x5E, 0xE9, +0x57, 0x25, 0x20, 0xE9, + +0x2B, 0x48, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x26, 0x77, + +0x24, 0x49, 0x20, 0xE9, +0x9D, 0xFF, 0x20, 0xEA, + +0x16, 0x26, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x1C, 0x46, 0xA0, 0xE8, +0x23, 0x4E, 0xA0, 0xE8, + +0x2B, 0x56, 0xA0, 0xE8, +0x1D, 0x47, 0xA0, 0xE8, + +0x24, 0x4F, 0xA0, 0xE8, +0x2C, 0x57, 0xA0, 0xE8, + +0x1C, 0x00, +0x23, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x1D, 0x00, +0x24, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x1C, 0x65, +0x23, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x1D, 0x65, +0x24, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x1C, 0x23, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x1D, 0x24, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x1C, 0x2B, 0xDE, 0xE8, +0x23, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x1C, 0xBD, +0x3B, 0xD7, 0x23, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x4F, 0x80, 0x4F, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0xC5, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x4E, 0x33, 0x4E, 0xCF, +0x57, 0x3B, 0x57, 0xCF, + +0x8B, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_tgzsaf[] = { + +0x00, 0x88, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x22, 0x40, 0x48, 0xBF, +0x2A, 0x40, 0x50, 0xBF, + +0x32, 0x41, 0x49, 0xBF, +0x3A, 0x41, 0x51, 0xBF, + +0xC3, 0x6B, +0xCB, 0x6B, +0x00, 0x88, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x4B, 0xA0, 0xE8, + +0xAD, 0xEE, 0x29, 0x9F, +0x00, 0xE0, +0x49, 0x04, + +0x90, 0xE2, +0x51, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x49, 0x41, 0xC0, 0xEC, +0x39, 0x57, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x53, 0xA0, 0xE8, + +0x51, 0x41, 0xC0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x6E, 0x80, 0x15, 0xEA, +0x08, 0x04, +0x10, 0x04, + +0x51, 0x49, 0xC0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x4A, 0xBF, +0x27, 0x4A, 0xA0, 0xE8, + +0x1A, 0x42, 0x52, 0xBF, +0x1E, 0x49, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x26, 0x51, 0x60, 0xEA, + +0x32, 0x40, 0x48, 0xBD, +0x22, 0x40, 0x50, 0xBD, + +0x12, 0x41, 0x49, 0xBD, +0x3A, 0x41, 0x51, 0xBD, + +0xBF, 0x2F, 0x26, 0xBD, +0x00, 0xE0, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x46, 0x31, 0x46, 0xBF, +0x4E, 0x31, 0x4E, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x56, 0x31, 0x56, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x4F, 0x39, 0x4F, 0xBF, +0x57, 0x39, 0x57, 0xBF, + +0x60, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x42, 0x73, 0xF8, 0xEC, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0xA5, 0x2F, 0x1E, 0xBD, + +0x43, 0x43, 0x2D, 0xDF, +0x4B, 0x4B, 0x2D, 0xDF, + +0xAE, 0x1E, 0x26, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x53, 0x53, 0x2D, 0xDF, +0x00, 0x80, 0x00, 0xE8, + +0xB8, 0x38, 0x33, 0xBF, +0x00, 0xE0, +0x59, 0xE3, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x2B, 0x40, 0x3D, 0xE9, +0x3F, 0x4B, 0xA0, 0xE8, + +0x2D, 0x73, +0x30, 0x76, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x53, 0xA0, 0xE8, + +0x48, 0x70, 0xF8, 0xEC, +0x2B, 0x48, 0x3C, 0xE9, + +0x1F, 0x27, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x18, 0x3A, 0x41, 0xE9, +0x1D, 0x32, 0x41, 0xE9, + +0x2A, 0x40, 0x20, 0xE9, +0x56, 0x3D, 0x56, 0xDF, + +0x46, 0x37, 0x46, 0xDF, +0x4E, 0x3F, 0x4E, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x4F, 0x3F, 0x4F, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3D, 0x57, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x27, 0xCF, 0x74, 0xC2, +0x37, 0xCF, 0x74, 0xC4, + +0x0A, 0x44, 0x4C, 0xB0, +0x02, 0x44, 0x54, 0xB0, + +0x3D, 0xCF, 0x74, 0xC0, +0x34, 0x37, 0x20, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x38, 0x27, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x4C, 0xB2, +0x1A, 0x44, 0x54, 0xB2, + +0x32, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x27, 0xCF, 0x75, 0xC0, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x3D, 0xCF, 0x75, 0xC2, +0x37, 0xCF, 0x75, 0xC4, + +0x31, 0x53, 0x2F, 0x9F, +0xA6, 0x27, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA3, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x4C, 0xB4, +0x1A, 0x44, 0x54, 0xB4, + +0x0A, 0x45, 0x4D, 0xB0, +0x02, 0x45, 0x55, 0xB0, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0xA0, 0x37, 0x20, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x30, 0x50, 0x2E, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x2A, 0x45, 0x4D, 0xB2, +0x1A, 0x45, 0x55, 0xB2, + +0x0A, 0x45, 0x4D, 0xB4, +0x02, 0x45, 0x55, 0xB4, + +0x27, 0xCF, 0x74, 0xC6, +0x2A, 0x20, +0x1A, 0x20, + +0xA7, 0x30, 0x4F, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x9C, 0x27, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA8, 0x38, 0x4F, 0xE9, + +0x2A, 0x44, 0x4C, 0xB6, +0x1A, 0x44, 0x54, 0xB6, + +0x30, 0x50, 0x2E, 0x9F, +0x36, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x37, 0x39, 0x4F, 0xE9, + +0x0A, 0x45, 0x4D, 0xB6, +0x02, 0x45, 0x55, 0xB6, + +0x3D, 0xCF, 0x75, 0xC6, +0x2A, 0x20, +0x1A, 0x20, + +0x2A, 0x46, 0x4E, 0xBF, +0x1A, 0x46, 0x56, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0xA4, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA5, 0x39, 0x4F, 0xE9, + +0x31, 0x3D, 0x20, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x0A, 0x47, 0x4F, 0xBF, +0x02, 0x47, 0x57, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0xA1, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0xA2, 0x38, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x9D, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x9E, 0x39, 0x4F, 0xE9, + +0x2A, 0x43, 0x4B, 0xBF, +0x1A, 0x43, 0x53, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x35, 0x30, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x39, 0x38, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x37, 0x48, 0x50, 0xBD, +0x8A, 0x36, 0x20, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8B, 0x3E, 0x20, 0xE9, + +0x82, 0x30, 0x57, 0xE9, +0x87, 0x77, 0x57, 0xE9, + +0x83, 0x38, 0x57, 0xE9, +0x35, 0x49, 0x51, 0xBD, + +0x84, 0x31, 0x5E, 0xE9, +0x30, 0x1F, 0x5F, 0xE9, + +0x85, 0x39, 0x5E, 0xE9, +0x57, 0x25, 0x20, 0xE9, + +0x2B, 0x48, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x26, 0x77, + +0x24, 0x49, 0x20, 0xE9, +0x99, 0xFF, 0x20, 0xEA, + +0x16, 0x26, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x1C, 0x46, 0xA0, 0xE8, +0x23, 0x4E, 0xA0, 0xE8, + +0x2B, 0x56, 0xA0, 0xE8, +0x1D, 0x47, 0xA0, 0xE8, + +0x24, 0x4F, 0xA0, 0xE8, +0x2C, 0x57, 0xA0, 0xE8, + +0x1C, 0x00, +0x23, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x1D, 0x00, +0x24, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x1C, 0x65, +0x23, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x1D, 0x65, +0x24, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x1C, 0x23, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x1D, 0x24, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x1C, 0x2B, 0xDE, 0xE8, +0x23, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x1C, 0xBD, +0x3B, 0xD7, 0x23, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x4F, 0x80, 0x4F, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0xC1, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x4E, 0x33, 0x4E, 0xCF, +0x57, 0x3B, 0x57, 0xCF, + +0x87, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; + +static unsigned char warp_g400_tgzsf[] = { + +0x00, 0x88, 0x98, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +0xFF, 0x80, 0xC0, 0xE9, +0x00, 0x80, 0x00, 0xE8, + +0x22, 0x40, 0x48, 0xBF, +0x2A, 0x40, 0x50, 0xBF, + +0x32, 0x41, 0x49, 0xBF, +0x3A, 0x41, 0x51, 0xBF, + +0xC3, 0x6B, +0xCB, 0x6B, +0x00, 0x88, 0x98, 0xE9, + +0x73, 0x7B, 0xC8, 0xEC, +0x96, 0xE2, +0x41, 0x04, + +0x7B, 0x43, 0xA0, 0xE8, +0x73, 0x4B, 0xA0, 0xE8, + +0xAD, 0xEE, 0x29, 0x9F, +0x00, 0xE0, +0x49, 0x04, + +0x90, 0xE2, +0x51, 0x04, +0x31, 0x46, 0xB1, 0xE8, + +0x49, 0x41, 0xC0, 0xEC, +0x39, 0x57, 0xB1, 0xE8, + +0x00, 0x04, +0x46, 0xE2, +0x73, 0x53, 0xA0, 0xE8, + +0x51, 0x41, 0xC0, 0xEC, +0x31, 0x00, +0x39, 0x00, + +0x6A, 0x80, 0x15, 0xEA, +0x08, 0x04, +0x10, 0x04, + +0x51, 0x49, 0xC0, 0xEC, +0x2F, 0x41, 0x60, 0xEA, + +0x31, 0x20, +0x39, 0x20, +0x1F, 0x42, 0xA0, 0xE8, + +0x2A, 0x42, 0x4A, 0xBF, +0x27, 0x4A, 0xA0, 0xE8, + +0x1A, 0x42, 0x52, 0xBF, +0x1E, 0x49, 0x60, 0xEA, + +0x73, 0x7B, 0xC8, 0xEC, +0x26, 0x51, 0x60, 0xEA, + +0x32, 0x40, 0x48, 0xBD, +0x22, 0x40, 0x50, 0xBD, + +0x12, 0x41, 0x49, 0xBD, +0x3A, 0x41, 0x51, 0xBD, + +0xBF, 0x2F, 0x26, 0xBD, +0x00, 0xE0, +0x7B, 0x72, + +0x32, 0x20, +0x22, 0x20, +0x12, 0x20, +0x3A, 0x20, + +0x46, 0x31, 0x46, 0xBF, +0x4E, 0x31, 0x4E, 0xBF, + +0xB3, 0xE2, 0x2D, 0x9F, +0x00, 0x80, 0x00, 0xE8, + +0x56, 0x31, 0x56, 0xBF, +0x47, 0x39, 0x47, 0xBF, + +0x4F, 0x39, 0x4F, 0xBF, +0x57, 0x39, 0x57, 0xBF, + +0x5C, 0x80, 0x07, 0xEA, +0x24, 0x41, 0x20, 0xE9, + +0x42, 0x73, 0xF8, 0xEC, +0x00, 0xE0, +0x2D, 0x73, + +0x33, 0x72, +0x0C, 0xE3, +0xA5, 0x2F, 0x1E, 0xBD, + +0x43, 0x43, 0x2D, 0xDF, +0x4B, 0x4B, 0x2D, 0xDF, + +0xAE, 0x1E, 0x26, 0xBD, +0x58, 0xE3, +0x33, 0x66, + +0x53, 0x53, 0x2D, 0xDF, +0x00, 0x80, 0x00, 0xE8, + +0xB8, 0x38, 0x33, 0xBF, +0x00, 0xE0, +0x59, 0xE3, + +0x1E, 0x12, 0x41, 0xE9, +0x1A, 0x22, 0x41, 0xE9, + +0x2B, 0x40, 0x3D, 0xE9, +0x3F, 0x4B, 0xA0, 0xE8, + +0x2D, 0x73, +0x30, 0x76, +0x05, 0x80, 0x3D, 0xEA, + +0x37, 0x43, 0xA0, 0xE8, +0x3D, 0x53, 0xA0, 0xE8, + +0x48, 0x70, 0xF8, 0xEC, +0x2B, 0x48, 0x3C, 0xE9, + +0x1F, 0x27, 0xBC, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x00, 0x80, 0x00, 0xE8, +0x00, 0x80, 0x00, 0xE8, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x15, 0xC0, 0x20, 0xE9, +0x15, 0xC0, 0x20, 0xE9, + +0x18, 0x3A, 0x41, 0xE9, +0x1D, 0x32, 0x41, 0xE9, + +0x2A, 0x40, 0x20, 0xE9, +0x56, 0x3D, 0x56, 0xDF, + +0x46, 0x37, 0x46, 0xDF, +0x4E, 0x3F, 0x4E, 0xDF, + +0x16, 0x30, 0x20, 0xE9, +0x4F, 0x3F, 0x4F, 0xDF, + +0x47, 0x37, 0x47, 0xDF, +0x57, 0x3D, 0x57, 0xDF, + +0x32, 0x32, 0x2D, 0xDF, +0x22, 0x22, 0x2D, 0xDF, + +0x12, 0x12, 0x2D, 0xDF, +0x3A, 0x3A, 0x2D, 0xDF, + +0x27, 0xCF, 0x74, 0xC2, +0x37, 0xCF, 0x74, 0xC4, + +0x0A, 0x44, 0x4C, 0xB0, +0x02, 0x44, 0x54, 0xB0, + +0x3D, 0xCF, 0x74, 0xC0, +0x34, 0x37, 0x20, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x38, 0x27, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3C, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x4C, 0xB2, +0x1A, 0x44, 0x54, 0xB2, + +0x2E, 0x80, 0x3A, 0xEA, +0x0A, 0x20, +0x02, 0x20, + +0x27, 0xCF, 0x75, 0xC0, +0x2A, 0x20, +0x1A, 0x20, + +0x30, 0x50, 0x2E, 0x9F, +0x32, 0x31, 0x5F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x33, 0x39, 0x5F, 0xE9, + +0x3D, 0xCF, 0x75, 0xC2, +0x37, 0xCF, 0x75, 0xC4, + +0x31, 0x53, 0x2F, 0x9F, +0xA6, 0x27, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA3, 0x3D, 0x20, 0xE9, + +0x2A, 0x44, 0x4C, 0xB4, +0x1A, 0x44, 0x54, 0xB4, + +0x0A, 0x45, 0x4D, 0xB0, +0x02, 0x45, 0x55, 0xB0, + +0x88, 0x73, 0x5E, 0xE9, +0x2A, 0x20, +0x1A, 0x20, + +0xA0, 0x37, 0x20, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x3E, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x3F, 0x38, 0x4F, 0xE9, + +0x30, 0x50, 0x2E, 0x9F, +0x3A, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x3B, 0x39, 0x4F, 0xE9, + +0x2A, 0x45, 0x4D, 0xB2, +0x1A, 0x45, 0x55, 0xB2, + +0x0A, 0x45, 0x4D, 0xB4, +0x02, 0x45, 0x55, 0xB4, + +0x27, 0xCF, 0x75, 0xC6, +0x2A, 0x20, +0x1A, 0x20, + +0xA7, 0x30, 0x4F, 0xE9, +0x0A, 0x20, +0x02, 0x20, + +0x31, 0x53, 0x2F, 0x9F, +0x31, 0x27, 0x20, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA8, 0x38, 0x4F, 0xE9, + +0x2A, 0x45, 0x4D, 0xB6, +0x1A, 0x45, 0x55, 0xB6, + +0x30, 0x50, 0x2E, 0x9F, +0x36, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x37, 0x39, 0x4F, 0xE9, + +0x00, 0x80, 0x00, 0xE8, +0x2A, 0x20, +0x1A, 0x20, + +0x2A, 0x46, 0x4E, 0xBF, +0x1A, 0x46, 0x56, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0xA4, 0x31, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA5, 0x39, 0x4F, 0xE9, + +0x0A, 0x47, 0x4F, 0xBF, +0x02, 0x47, 0x57, 0xBF, + +0x31, 0x53, 0x2F, 0x9F, +0xA1, 0x30, 0x4F, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0xA2, 0x38, 0x4F, 0xE9, + +0x2A, 0x43, 0x4B, 0xBF, +0x1A, 0x43, 0x53, 0xBF, + +0x30, 0x50, 0x2E, 0x9F, +0x35, 0x31, 0x4F, 0xE9, + +0x38, 0x21, 0x2C, 0x9F, +0x39, 0x39, 0x4F, 0xE9, + +0x31, 0x53, 0x2F, 0x9F, +0x80, 0x31, 0x57, 0xE9, + +0x39, 0xE5, 0x2C, 0x9F, +0x81, 0x39, 0x57, 0xE9, + +0x37, 0x48, 0x50, 0xBD, +0x8A, 0x36, 0x20, 0xE9, + +0x86, 0x76, 0x57, 0xE9, +0x8B, 0x3E, 0x20, 0xE9, + +0x82, 0x30, 0x57, 0xE9, +0x87, 0x77, 0x57, 0xE9, + +0x83, 0x38, 0x57, 0xE9, +0x35, 0x49, 0x51, 0xBD, + +0x84, 0x31, 0x5E, 0xE9, +0x30, 0x1F, 0x5F, 0xE9, + +0x85, 0x39, 0x5E, 0xE9, +0x57, 0x25, 0x20, 0xE9, + +0x2B, 0x48, 0x20, 0xE9, +0x1D, 0x37, 0xE1, 0xEA, + +0x1E, 0x35, 0xE1, 0xEA, +0x00, 0xE0, +0x26, 0x77, + +0x24, 0x49, 0x20, 0xE9, +0x9D, 0xFF, 0x20, 0xEA, + +0x16, 0x26, 0x20, 0xE9, +0x57, 0x2E, 0xBF, 0xEA, + +0x1C, 0x46, 0xA0, 0xE8, +0x23, 0x4E, 0xA0, 0xE8, + +0x2B, 0x56, 0xA0, 0xE8, +0x1D, 0x47, 0xA0, 0xE8, + +0x24, 0x4F, 0xA0, 0xE8, +0x2C, 0x57, 0xA0, 0xE8, + +0x1C, 0x00, +0x23, 0x00, +0x2B, 0x00, +0x00, 0xE0, + +0x1D, 0x00, +0x24, 0x00, +0x2C, 0x00, +0x00, 0xE0, + +0x1C, 0x65, +0x23, 0x65, +0x2B, 0x65, +0x00, 0xE0, + +0x1D, 0x65, +0x24, 0x65, +0x2C, 0x65, +0x00, 0xE0, + +0x1C, 0x23, 0x60, 0xEC, +0x36, 0xD7, 0x36, 0xAD, + +0x2B, 0x80, 0x60, 0xEC, +0x1D, 0x24, 0x60, 0xEC, + +0x3E, 0xD7, 0x3E, 0xAD, +0x2C, 0x80, 0x60, 0xEC, + +0x1C, 0x2B, 0xDE, 0xE8, +0x23, 0x80, 0xDE, 0xE8, + +0x36, 0x80, 0x36, 0xBD, +0x3E, 0x80, 0x3E, 0xBD, + +0x33, 0xD7, 0x1C, 0xBD, +0x3B, 0xD7, 0x23, 0xBD, + +0x46, 0x80, 0x46, 0xCF, +0x4F, 0x80, 0x4F, 0xCF, + +0x56, 0x33, 0x56, 0xCF, +0x47, 0x3B, 0x47, 0xCF, + +0xC5, 0xFF, 0x20, 0xEA, +0x00, 0x80, 0x00, 0xE8, + +0x4E, 0x33, 0x4E, 0xCF, +0x57, 0x3B, 0x57, 0xCF, + +0x8B, 0xFF, 0x20, 0xEA, +0x57, 0xC0, 0xBF, 0xEA, + +0x00, 0x80, 0xA0, 0xE9, +0x00, 0x00, 0xD8, 0xEC, + +}; diff --git a/drivers/char/drm/mga_warp.c b/drivers/char/drm/mga_warp.c new file mode 100644 index 000000000000..0a3a0cc700dc --- /dev/null +++ b/drivers/char/drm/mga_warp.c @@ -0,0 +1,210 @@ +/* mga_warp.c -- Matrox G200/G400 WARP engine management -*- linux-c -*- + * Created: Thu Jan 11 21:29:32 2001 by gareth@valinux.com + * + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Gareth Hughes + */ + +#include "drmP.h" +#include "drm.h" +#include "mga_drm.h" +#include "mga_drv.h" +#include "mga_ucode.h" + + +#define MGA_WARP_CODE_ALIGN 256 /* in bytes */ + +#define WARP_UCODE_SIZE( which ) \ + ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN) + +#define WARP_UCODE_INSTALL( which, where ) \ +do { \ + DRM_DEBUG( " pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase );\ + dev_priv->warp_pipe_phys[where] = pcbase; \ + memcpy( vcbase, which, sizeof(which) ); \ + pcbase += WARP_UCODE_SIZE( which ); \ + vcbase += WARP_UCODE_SIZE( which ); \ +} while (0) + + +static unsigned int mga_warp_g400_microcode_size( drm_mga_private_t *dev_priv ) +{ + unsigned int size; + + size = ( WARP_UCODE_SIZE( warp_g400_tgz ) + + WARP_UCODE_SIZE( warp_g400_tgza ) + + WARP_UCODE_SIZE( warp_g400_tgzaf ) + + WARP_UCODE_SIZE( warp_g400_tgzf ) + + WARP_UCODE_SIZE( warp_g400_tgzs ) + + WARP_UCODE_SIZE( warp_g400_tgzsa ) + + WARP_UCODE_SIZE( warp_g400_tgzsaf ) + + WARP_UCODE_SIZE( warp_g400_tgzsf ) + + WARP_UCODE_SIZE( warp_g400_t2gz ) + + WARP_UCODE_SIZE( warp_g400_t2gza ) + + WARP_UCODE_SIZE( warp_g400_t2gzaf ) + + WARP_UCODE_SIZE( warp_g400_t2gzf ) + + WARP_UCODE_SIZE( warp_g400_t2gzs ) + + WARP_UCODE_SIZE( warp_g400_t2gzsa ) + + WARP_UCODE_SIZE( warp_g400_t2gzsaf ) + + WARP_UCODE_SIZE( warp_g400_t2gzsf ) ); + + size = PAGE_ALIGN( size ); + + DRM_DEBUG( "G400 ucode size = %d bytes\n", size ); + return size; +} + +static unsigned int mga_warp_g200_microcode_size( drm_mga_private_t *dev_priv ) +{ + unsigned int size; + + size = ( WARP_UCODE_SIZE( warp_g200_tgz ) + + WARP_UCODE_SIZE( warp_g200_tgza ) + + WARP_UCODE_SIZE( warp_g200_tgzaf ) + + WARP_UCODE_SIZE( warp_g200_tgzf ) + + WARP_UCODE_SIZE( warp_g200_tgzs ) + + WARP_UCODE_SIZE( warp_g200_tgzsa ) + + WARP_UCODE_SIZE( warp_g200_tgzsaf ) + + WARP_UCODE_SIZE( warp_g200_tgzsf ) ); + + size = PAGE_ALIGN( size ); + + DRM_DEBUG( "G200 ucode size = %d bytes\n", size ); + return size; +} + +static int mga_warp_install_g400_microcode( drm_mga_private_t *dev_priv ) +{ + unsigned char *vcbase = dev_priv->warp->handle; + unsigned long pcbase = dev_priv->warp->offset; + unsigned int size; + + size = mga_warp_g400_microcode_size( dev_priv ); + if ( size > dev_priv->warp->size ) { + DRM_ERROR( "microcode too large! (%u > %lu)\n", + size, dev_priv->warp->size ); + return DRM_ERR(ENOMEM); + } + + memset( dev_priv->warp_pipe_phys, 0, + sizeof(dev_priv->warp_pipe_phys) ); + + WARP_UCODE_INSTALL( warp_g400_tgz, MGA_WARP_TGZ ); + WARP_UCODE_INSTALL( warp_g400_tgzf, MGA_WARP_TGZF ); + WARP_UCODE_INSTALL( warp_g400_tgza, MGA_WARP_TGZA ); + WARP_UCODE_INSTALL( warp_g400_tgzaf, MGA_WARP_TGZAF ); + WARP_UCODE_INSTALL( warp_g400_tgzs, MGA_WARP_TGZS ); + WARP_UCODE_INSTALL( warp_g400_tgzsf, MGA_WARP_TGZSF ); + WARP_UCODE_INSTALL( warp_g400_tgzsa, MGA_WARP_TGZSA ); + WARP_UCODE_INSTALL( warp_g400_tgzsaf, MGA_WARP_TGZSAF ); + + WARP_UCODE_INSTALL( warp_g400_t2gz, MGA_WARP_T2GZ ); + WARP_UCODE_INSTALL( warp_g400_t2gzf, MGA_WARP_T2GZF ); + WARP_UCODE_INSTALL( warp_g400_t2gza, MGA_WARP_T2GZA ); + WARP_UCODE_INSTALL( warp_g400_t2gzaf, MGA_WARP_T2GZAF ); + WARP_UCODE_INSTALL( warp_g400_t2gzs, MGA_WARP_T2GZS ); + WARP_UCODE_INSTALL( warp_g400_t2gzsf, MGA_WARP_T2GZSF ); + WARP_UCODE_INSTALL( warp_g400_t2gzsa, MGA_WARP_T2GZSA ); + WARP_UCODE_INSTALL( warp_g400_t2gzsaf, MGA_WARP_T2GZSAF ); + + return 0; +} + +static int mga_warp_install_g200_microcode( drm_mga_private_t *dev_priv ) +{ + unsigned char *vcbase = dev_priv->warp->handle; + unsigned long pcbase = dev_priv->warp->offset; + unsigned int size; + + size = mga_warp_g200_microcode_size( dev_priv ); + if ( size > dev_priv->warp->size ) { + DRM_ERROR( "microcode too large! (%u > %lu)\n", + size, dev_priv->warp->size ); + return DRM_ERR(ENOMEM); + } + + memset( dev_priv->warp_pipe_phys, 0, + sizeof(dev_priv->warp_pipe_phys) ); + + WARP_UCODE_INSTALL( warp_g200_tgz, MGA_WARP_TGZ ); + WARP_UCODE_INSTALL( warp_g200_tgzf, MGA_WARP_TGZF ); + WARP_UCODE_INSTALL( warp_g200_tgza, MGA_WARP_TGZA ); + WARP_UCODE_INSTALL( warp_g200_tgzaf, MGA_WARP_TGZAF ); + WARP_UCODE_INSTALL( warp_g200_tgzs, MGA_WARP_TGZS ); + WARP_UCODE_INSTALL( warp_g200_tgzsf, MGA_WARP_TGZSF ); + WARP_UCODE_INSTALL( warp_g200_tgzsa, MGA_WARP_TGZSA ); + WARP_UCODE_INSTALL( warp_g200_tgzsaf, MGA_WARP_TGZSAF ); + + return 0; +} + +int mga_warp_install_microcode( drm_mga_private_t *dev_priv ) +{ + switch ( dev_priv->chipset ) { + case MGA_CARD_TYPE_G400: + return mga_warp_install_g400_microcode( dev_priv ); + case MGA_CARD_TYPE_G200: + return mga_warp_install_g200_microcode( dev_priv ); + default: + return DRM_ERR(EINVAL); + } +} + +#define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE) + +int mga_warp_init( drm_mga_private_t *dev_priv ) +{ + u32 wmisc; + + /* FIXME: Get rid of these damned magic numbers... + */ + switch ( dev_priv->chipset ) { + case MGA_CARD_TYPE_G400: + MGA_WRITE( MGA_WIADDR2, MGA_WMODE_SUSPEND ); + MGA_WRITE( MGA_WGETMSB, 0x00000E00 ); + MGA_WRITE( MGA_WVRTXSZ, 0x00001807 ); + MGA_WRITE( MGA_WACCEPTSEQ, 0x18000000 ); + break; + case MGA_CARD_TYPE_G200: + MGA_WRITE( MGA_WIADDR, MGA_WMODE_SUSPEND ); + MGA_WRITE( MGA_WGETMSB, 0x1606 ); + MGA_WRITE( MGA_WVRTXSZ, 7 ); + break; + default: + return DRM_ERR(EINVAL); + } + + MGA_WRITE( MGA_WMISC, (MGA_WUCODECACHE_ENABLE | + MGA_WMASTER_ENABLE | + MGA_WCACHEFLUSH_ENABLE) ); + wmisc = MGA_READ( MGA_WMISC ); + if ( wmisc != WMISC_EXPECTED ) { + DRM_ERROR( "WARP engine config failed! 0x%x != 0x%x\n", + wmisc, WMISC_EXPECTED ); + return DRM_ERR(EINVAL); + } + + return 0; +} diff --git a/drivers/char/drm/r128_cce.c b/drivers/char/drm/r128_cce.c new file mode 100644 index 000000000000..08ed8d01d9d9 --- /dev/null +++ b/drivers/char/drm/r128_cce.c @@ -0,0 +1,943 @@ +/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*- + * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Gareth Hughes + */ + +#include "drmP.h" +#include "drm.h" +#include "r128_drm.h" +#include "r128_drv.h" + +#define R128_FIFO_DEBUG 0 + +/* CCE microcode (from ATI) */ +static u32 r128_cce_microcode[] = { + 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, + 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, + 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, + 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, + 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, + 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, + 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, + 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, + 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, + 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, + 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, + 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, + 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, + 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, + 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, + 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, + 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, + 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, + 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, + 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, + 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, + 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, + 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, + 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, + 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, + 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, + 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, + 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, + 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, + 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, + 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, + 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, + 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, + 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, + 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static int R128_READ_PLL(drm_device_t *dev, int addr) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + + R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); + return R128_READ(R128_CLOCK_CNTL_DATA); +} + +#if R128_FIFO_DEBUG +static void r128_status( drm_r128_private_t *dev_priv ) +{ + printk( "GUI_STAT = 0x%08x\n", + (unsigned int)R128_READ( R128_GUI_STAT ) ); + printk( "PM4_STAT = 0x%08x\n", + (unsigned int)R128_READ( R128_PM4_STAT ) ); + printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n", + (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) ); + printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n", + (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) ); + printk( "PM4_MICRO_CNTL = 0x%08x\n", + (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) ); + printk( "PM4_BUFFER_CNTL = 0x%08x\n", + (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) ); +} +#endif + + +/* ================================================================ + * Engine, FIFO control + */ + +static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv ) +{ + u32 tmp; + int i; + + tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL; + R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp ); + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) { + return 0; + } + DRM_UDELAY( 1 ); + } + +#if R128_FIFO_DEBUG + DRM_ERROR( "failed!\n" ); +#endif + return DRM_ERR(EBUSY); +} + +static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries ) +{ + int i; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK; + if ( slots >= entries ) return 0; + DRM_UDELAY( 1 ); + } + +#if R128_FIFO_DEBUG + DRM_ERROR( "failed!\n" ); +#endif + return DRM_ERR(EBUSY); +} + +static int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ) +{ + int i, ret; + + ret = r128_do_wait_for_fifo( dev_priv, 64 ); + if ( ret ) return ret; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) { + r128_do_pixcache_flush( dev_priv ); + return 0; + } + DRM_UDELAY( 1 ); + } + +#if R128_FIFO_DEBUG + DRM_ERROR( "failed!\n" ); +#endif + return DRM_ERR(EBUSY); +} + + +/* ================================================================ + * CCE control, initialization + */ + +/* Load the microcode for the CCE */ +static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) +{ + int i; + + DRM_DEBUG( "\n" ); + + r128_do_wait_for_idle( dev_priv ); + + R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 ); + for ( i = 0 ; i < 256 ; i++ ) { + R128_WRITE( R128_PM4_MICROCODE_DATAH, + r128_cce_microcode[i * 2] ); + R128_WRITE( R128_PM4_MICROCODE_DATAL, + r128_cce_microcode[i * 2 + 1] ); + } +} + +/* Flush any pending commands to the CCE. This should only be used just + * prior to a wait for idle, as it informs the engine that the command + * stream is ending. + */ +static void r128_do_cce_flush( drm_r128_private_t *dev_priv ) +{ + u32 tmp; + + tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE; + R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp ); +} + +/* Wait for the CCE to go idle. + */ +int r128_do_cce_idle( drm_r128_private_t *dev_priv ) +{ + int i; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + if ( GET_RING_HEAD( dev_priv ) == dev_priv->ring.tail ) { + int pm4stat = R128_READ( R128_PM4_STAT ); + if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >= + dev_priv->cce_fifo_size ) && + !(pm4stat & (R128_PM4_BUSY | + R128_PM4_GUI_ACTIVE)) ) { + return r128_do_pixcache_flush( dev_priv ); + } + } + DRM_UDELAY( 1 ); + } + +#if R128_FIFO_DEBUG + DRM_ERROR( "failed!\n" ); + r128_status( dev_priv ); +#endif + return DRM_ERR(EBUSY); +} + +/* Start the Concurrent Command Engine. + */ +static void r128_do_cce_start( drm_r128_private_t *dev_priv ) +{ + r128_do_wait_for_idle( dev_priv ); + + R128_WRITE( R128_PM4_BUFFER_CNTL, + dev_priv->cce_mode | dev_priv->ring.size_l2qw + | R128_PM4_BUFFER_CNTL_NOUPDATE ); + R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */ + R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN ); + + dev_priv->cce_running = 1; +} + +/* Reset the Concurrent Command Engine. This will not flush any pending + * commands, so you must wait for the CCE command stream to complete + * before calling this routine. + */ +static void r128_do_cce_reset( drm_r128_private_t *dev_priv ) +{ + R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); + R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); + dev_priv->ring.tail = 0; +} + +/* Stop the Concurrent Command Engine. This will not flush any pending + * commands, so you must flush the command stream and wait for the CCE + * to go idle before calling this routine. + */ +static void r128_do_cce_stop( drm_r128_private_t *dev_priv ) +{ + R128_WRITE( R128_PM4_MICRO_CNTL, 0 ); + R128_WRITE( R128_PM4_BUFFER_CNTL, + R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE ); + + dev_priv->cce_running = 0; +} + +/* Reset the engine. This will stop the CCE if it is running. + */ +static int r128_do_engine_reset( drm_device_t *dev ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; + + r128_do_pixcache_flush( dev_priv ); + + clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX ); + mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL ); + + R128_WRITE_PLL( R128_MCLK_CNTL, + mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP ); + + gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL ); + + /* Taken from the sample code - do not change */ + R128_WRITE( R128_GEN_RESET_CNTL, + gen_reset_cntl | R128_SOFT_RESET_GUI ); + R128_READ( R128_GEN_RESET_CNTL ); + R128_WRITE( R128_GEN_RESET_CNTL, + gen_reset_cntl & ~R128_SOFT_RESET_GUI ); + R128_READ( R128_GEN_RESET_CNTL ); + + R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl ); + R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index ); + R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl ); + + /* Reset the CCE ring */ + r128_do_cce_reset( dev_priv ); + + /* The CCE is no longer running after an engine reset */ + dev_priv->cce_running = 0; + + /* Reset any pending vertex, indirect buffers */ + r128_freelist_reset( dev ); + + return 0; +} + +static void r128_cce_init_ring_buffer( drm_device_t *dev, + drm_r128_private_t *dev_priv ) +{ + u32 ring_start; + u32 tmp; + + DRM_DEBUG( "\n" ); + + /* The manual (p. 2) says this address is in "VM space". This + * means it's an offset from the start of AGP space. + */ +#if __OS_HAS_AGP + if ( !dev_priv->is_pci ) + ring_start = dev_priv->cce_ring->offset - dev->agp->base; + else +#endif + ring_start = dev_priv->cce_ring->offset - dev->sg->handle; + + R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET ); + + R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); + R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); + + /* Set watermark control */ + R128_WRITE( R128_PM4_BUFFER_WM_CNTL, + ((R128_WATERMARK_L/4) << R128_WMA_SHIFT) + | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT) + | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT) + | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) ); + + /* Force read. Why? Because it's in the examples... */ + R128_READ( R128_PM4_BUFFER_ADDR ); + + /* Turn on bus mastering */ + tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS; + R128_WRITE( R128_BUS_CNTL, tmp ); +} + +static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) +{ + drm_r128_private_t *dev_priv; + + DRM_DEBUG( "\n" ); + + dev_priv = drm_alloc( sizeof(drm_r128_private_t), DRM_MEM_DRIVER ); + if ( dev_priv == NULL ) + return DRM_ERR(ENOMEM); + + memset( dev_priv, 0, sizeof(drm_r128_private_t) ); + + dev_priv->is_pci = init->is_pci; + + if ( dev_priv->is_pci && !dev->sg ) { + DRM_ERROR( "PCI GART memory not allocated!\n" ); + dev->dev_private = (void *)dev_priv; + r128_do_cleanup_cce( dev ); + return DRM_ERR(EINVAL); + } + + dev_priv->usec_timeout = init->usec_timeout; + if ( dev_priv->usec_timeout < 1 || + dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) { + DRM_DEBUG( "TIMEOUT problem!\n" ); + dev->dev_private = (void *)dev_priv; + r128_do_cleanup_cce( dev ); + return DRM_ERR(EINVAL); + } + + dev_priv->cce_mode = init->cce_mode; + + /* GH: Simple idle check. + */ + atomic_set( &dev_priv->idle_count, 0 ); + + /* We don't support anything other than bus-mastering ring mode, + * but the ring can be in either AGP or PCI space for the ring + * read pointer. + */ + if ( ( init->cce_mode != R128_PM4_192BM ) && + ( init->cce_mode != R128_PM4_128BM_64INDBM ) && + ( init->cce_mode != R128_PM4_64BM_128INDBM ) && + ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) { + DRM_DEBUG( "Bad cce_mode!\n" ); + dev->dev_private = (void *)dev_priv; + r128_do_cleanup_cce( dev ); + return DRM_ERR(EINVAL); + } + + switch ( init->cce_mode ) { + case R128_PM4_NONPM4: + dev_priv->cce_fifo_size = 0; + break; + case R128_PM4_192PIO: + case R128_PM4_192BM: + dev_priv->cce_fifo_size = 192; + break; + case R128_PM4_128PIO_64INDBM: + case R128_PM4_128BM_64INDBM: + dev_priv->cce_fifo_size = 128; + break; + case R128_PM4_64PIO_128INDBM: + case R128_PM4_64BM_128INDBM: + case R128_PM4_64PIO_64VCBM_64INDBM: + case R128_PM4_64BM_64VCBM_64INDBM: + case R128_PM4_64PIO_64VCPIO_64INDPIO: + dev_priv->cce_fifo_size = 64; + break; + } + + switch ( init->fb_bpp ) { + case 16: + dev_priv->color_fmt = R128_DATATYPE_RGB565; + break; + case 32: + default: + dev_priv->color_fmt = R128_DATATYPE_ARGB8888; + break; + } + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; + + switch ( init->depth_bpp ) { + case 16: + dev_priv->depth_fmt = R128_DATATYPE_RGB565; + break; + case 24: + case 32: + default: + dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; + break; + } + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; + dev_priv->span_offset = init->span_offset; + + dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) | + (dev_priv->front_offset >> 5)); + dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) | + (dev_priv->back_offset >> 5)); + dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | + (dev_priv->depth_offset >> 5) | + R128_DST_TILE); + dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | + (dev_priv->span_offset >> 5)); + + DRM_GETSAREA(); + + if(!dev_priv->sarea) { + DRM_ERROR("could not find sarea!\n"); + dev->dev_private = (void *)dev_priv; + r128_do_cleanup_cce( dev ); + return DRM_ERR(EINVAL); + } + + dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); + if(!dev_priv->mmio) { + DRM_ERROR("could not find mmio region!\n"); + dev->dev_private = (void *)dev_priv; + r128_do_cleanup_cce( dev ); + return DRM_ERR(EINVAL); + } + dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset); + if(!dev_priv->cce_ring) { + DRM_ERROR("could not find cce ring region!\n"); + dev->dev_private = (void *)dev_priv; + r128_do_cleanup_cce( dev ); + return DRM_ERR(EINVAL); + } + dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); + if(!dev_priv->ring_rptr) { + DRM_ERROR("could not find ring read pointer!\n"); + dev->dev_private = (void *)dev_priv; + r128_do_cleanup_cce( dev ); + return DRM_ERR(EINVAL); + } + dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); + if(!dev->agp_buffer_map) { + DRM_ERROR("could not find dma buffer region!\n"); + dev->dev_private = (void *)dev_priv; + r128_do_cleanup_cce( dev ); + return DRM_ERR(EINVAL); + } + + if ( !dev_priv->is_pci ) { + dev_priv->agp_textures = drm_core_findmap(dev, init->agp_textures_offset); + if(!dev_priv->agp_textures) { + DRM_ERROR("could not find agp texture region!\n"); + dev->dev_private = (void *)dev_priv; + r128_do_cleanup_cce( dev ); + return DRM_ERR(EINVAL); + } + } + + dev_priv->sarea_priv = + (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle + + init->sarea_priv_offset); + +#if __OS_HAS_AGP + if ( !dev_priv->is_pci ) { + drm_core_ioremap( dev_priv->cce_ring, dev ); + drm_core_ioremap( dev_priv->ring_rptr, dev ); + drm_core_ioremap( dev->agp_buffer_map, dev ); + if(!dev_priv->cce_ring->handle || + !dev_priv->ring_rptr->handle || + !dev->agp_buffer_map->handle) { + DRM_ERROR("Could not ioremap agp regions!\n"); + dev->dev_private = (void *)dev_priv; + r128_do_cleanup_cce( dev ); + return DRM_ERR(ENOMEM); + } + } else +#endif + { + dev_priv->cce_ring->handle = + (void *)dev_priv->cce_ring->offset; + dev_priv->ring_rptr->handle = + (void *)dev_priv->ring_rptr->offset; + dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; + } + +#if __OS_HAS_AGP + if ( !dev_priv->is_pci ) + dev_priv->cce_buffers_offset = dev->agp->base; + else +#endif + dev_priv->cce_buffers_offset = dev->sg->handle; + + dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle; + dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle + + init->ring_size / sizeof(u32)); + dev_priv->ring.size = init->ring_size; + dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 ); + + dev_priv->ring.tail_mask = + (dev_priv->ring.size / sizeof(u32)) - 1; + + dev_priv->ring.high_mark = 128; + + dev_priv->sarea_priv->last_frame = 0; + R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); + + dev_priv->sarea_priv->last_dispatch = 0; + R128_WRITE( R128_LAST_DISPATCH_REG, + dev_priv->sarea_priv->last_dispatch ); + +#if __OS_HAS_AGP + if ( dev_priv->is_pci ) { +#endif + if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart, + &dev_priv->bus_pci_gart) ) { + DRM_ERROR( "failed to init PCI GART!\n" ); + dev->dev_private = (void *)dev_priv; + r128_do_cleanup_cce( dev ); + return DRM_ERR(ENOMEM); + } + R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart ); +#if __OS_HAS_AGP + } +#endif + + r128_cce_init_ring_buffer( dev, dev_priv ); + r128_cce_load_microcode( dev_priv ); + + dev->dev_private = (void *)dev_priv; + + r128_do_engine_reset( dev ); + + return 0; +} + +int r128_do_cleanup_cce( drm_device_t *dev ) +{ + + /* Make sure interrupts are disabled here because the uninstall ioctl + * may not have been called from userspace and after dev_private + * is freed, it's too late. + */ + if ( dev->irq_enabled ) drm_irq_uninstall(dev); + + if ( dev->dev_private ) { + drm_r128_private_t *dev_priv = dev->dev_private; + +#if __OS_HAS_AGP + if ( !dev_priv->is_pci ) { + if ( dev_priv->cce_ring != NULL ) + drm_core_ioremapfree( dev_priv->cce_ring, dev ); + if ( dev_priv->ring_rptr != NULL ) + drm_core_ioremapfree( dev_priv->ring_rptr, dev ); + if ( dev->agp_buffer_map != NULL ) + drm_core_ioremapfree( dev->agp_buffer_map, dev ); + } else +#endif + { + if (!drm_ati_pcigart_cleanup( dev, + dev_priv->phys_pci_gart, + dev_priv->bus_pci_gart )) + DRM_ERROR( "failed to cleanup PCI GART!\n" ); + } + + drm_free( dev->dev_private, sizeof(drm_r128_private_t), + DRM_MEM_DRIVER ); + dev->dev_private = NULL; + } + + return 0; +} + +int r128_cce_init( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_init_t init; + + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( init, (drm_r128_init_t __user *)data, sizeof(init) ); + + switch ( init.func ) { + case R128_INIT_CCE: + return r128_do_init_cce( dev, &init ); + case R128_CLEANUP_CCE: + return r128_do_cleanup_cce( dev ); + } + + return DRM_ERR(EINVAL); +} + +int r128_cce_start( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) { + DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ ); + return 0; + } + + r128_do_cce_start( dev_priv ); + + return 0; +} + +/* Stop the CCE. The engine must have been idled before calling this + * routine. + */ +int r128_cce_stop( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_cce_stop_t stop; + int ret; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *)data, sizeof(stop) ); + + /* Flush any pending CCE commands. This ensures any outstanding + * commands are exectuted by the engine before we turn it off. + */ + if ( stop.flush ) { + r128_do_cce_flush( dev_priv ); + } + + /* If we fail to make the engine go idle, we return an error + * code so that the DRM ioctl wrapper can try again. + */ + if ( stop.idle ) { + ret = r128_do_cce_idle( dev_priv ); + if ( ret ) return ret; + } + + /* Finally, we can turn off the CCE. If the engine isn't idle, + * we will get some dropped triangles as they won't be fully + * rendered before the CCE is shut down. + */ + r128_do_cce_stop( dev_priv ); + + /* Reset the engine */ + r128_do_engine_reset( dev ); + + return 0; +} + +/* Just reset the CCE ring. Called as part of an X Server engine reset. + */ +int r128_cce_reset( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( !dev_priv ) { + DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + r128_do_cce_reset( dev_priv ); + + /* The CCE is no longer running after an engine reset */ + dev_priv->cce_running = 0; + + return 0; +} + +int r128_cce_idle( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( dev_priv->cce_running ) { + r128_do_cce_flush( dev_priv ); + } + + return r128_do_cce_idle( dev_priv ); +} + +int r128_engine_reset( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + return r128_do_engine_reset( dev ); +} + +int r128_fullscreen( DRM_IOCTL_ARGS ) +{ + return DRM_ERR(EINVAL); +} + + +/* ================================================================ + * Freelist management + */ +#define R128_BUFFER_USED 0xffffffff +#define R128_BUFFER_FREE 0 + +#if 0 +static int r128_freelist_init( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_buf_t *buf; + drm_r128_buf_priv_t *buf_priv; + drm_r128_freelist_t *entry; + int i; + + dev_priv->head = drm_alloc( sizeof(drm_r128_freelist_t), + DRM_MEM_DRIVER ); + if ( dev_priv->head == NULL ) + return DRM_ERR(ENOMEM); + + memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) ); + dev_priv->head->age = R128_BUFFER_USED; + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + + entry = drm_alloc( sizeof(drm_r128_freelist_t), + DRM_MEM_DRIVER ); + if ( !entry ) return DRM_ERR(ENOMEM); + + entry->age = R128_BUFFER_FREE; + entry->buf = buf; + entry->prev = dev_priv->head; + entry->next = dev_priv->head->next; + if ( !entry->next ) + dev_priv->tail = entry; + + buf_priv->discard = 0; + buf_priv->dispatched = 0; + buf_priv->list_entry = entry; + + dev_priv->head->next = entry; + + if ( dev_priv->head->next ) + dev_priv->head->next->prev = entry; + } + + return 0; + +} +#endif + +static drm_buf_t *r128_freelist_get( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_buf_priv_t *buf_priv; + drm_buf_t *buf; + int i, t; + + /* FIXME: Optimize -- use freelist code */ + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + if ( buf->filp == 0 ) + return buf; + } + + for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { + u32 done_age = R128_READ( R128_LAST_DISPATCH_REG ); + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + if ( buf->pending && buf_priv->age <= done_age ) { + /* The buffer has been processed, so it + * can now be used. + */ + buf->pending = 0; + return buf; + } + } + DRM_UDELAY( 1 ); + } + + DRM_DEBUG( "returning NULL!\n" ); + return NULL; +} + +void r128_freelist_reset( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; + int i; + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + drm_buf_t *buf = dma->buflist[i]; + drm_r128_buf_priv_t *buf_priv = buf->dev_private; + buf_priv->age = 0; + } +} + + +/* ================================================================ + * CCE command submission + */ + +int r128_wait_ring( drm_r128_private_t *dev_priv, int n ) +{ + drm_r128_ring_buffer_t *ring = &dev_priv->ring; + int i; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + r128_update_ring_snapshot( dev_priv ); + if ( ring->space >= n ) + return 0; + DRM_UDELAY( 1 ); + } + + /* FIXME: This is being ignored... */ + DRM_ERROR( "failed!\n" ); + return DRM_ERR(EBUSY); +} + +static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) +{ + int i; + drm_buf_t *buf; + + for ( i = d->granted_count ; i < d->request_count ; i++ ) { + buf = r128_freelist_get( dev ); + if ( !buf ) return DRM_ERR(EAGAIN); + + buf->filp = filp; + + if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, + sizeof(buf->idx) ) ) + return DRM_ERR(EFAULT); + if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, + sizeof(buf->total) ) ) + return DRM_ERR(EFAULT); + + d->granted_count++; + } + return 0; +} + +int r128_cce_buffers( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_device_dma_t *dma = dev->dma; + int ret = 0; + drm_dma_t __user *argp = (void __user *)data; + drm_dma_t d; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); + + /* Please don't send us buffers. + */ + if ( d.send_count != 0 ) { + DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", + DRM_CURRENTPID, d.send_count ); + return DRM_ERR(EINVAL); + } + + /* We'll send you buffers. + */ + if ( d.request_count < 0 || d.request_count > dma->buf_count ) { + DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", + DRM_CURRENTPID, d.request_count, dma->buf_count ); + return DRM_ERR(EINVAL); + } + + d.granted_count = 0; + + if ( d.request_count ) { + ret = r128_cce_get_buffers( filp, dev, &d ); + } + + DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d) ); + + return ret; +} diff --git a/drivers/char/drm/r128_drm.h b/drivers/char/drm/r128_drm.h new file mode 100644 index 000000000000..0cba17d1e0ff --- /dev/null +++ b/drivers/char/drm/r128_drm.h @@ -0,0 +1,345 @@ +/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- + * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Gareth Hughes + * Kevin E. Martin + */ + +#ifndef __R128_DRM_H__ +#define __R128_DRM_H__ + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the X server file (r128_sarea.h) + */ +#ifndef __R128_SAREA_DEFINES__ +#define __R128_SAREA_DEFINES__ + +/* What needs to be changed for the current vertex buffer? + */ +#define R128_UPLOAD_CONTEXT 0x001 +#define R128_UPLOAD_SETUP 0x002 +#define R128_UPLOAD_TEX0 0x004 +#define R128_UPLOAD_TEX1 0x008 +#define R128_UPLOAD_TEX0IMAGES 0x010 +#define R128_UPLOAD_TEX1IMAGES 0x020 +#define R128_UPLOAD_CORE 0x040 +#define R128_UPLOAD_MASKS 0x080 +#define R128_UPLOAD_WINDOW 0x100 +#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ +#define R128_REQUIRE_QUIESCENCE 0x400 +#define R128_UPLOAD_ALL 0x7ff + +#define R128_FRONT 0x1 +#define R128_BACK 0x2 +#define R128_DEPTH 0x4 + +/* Primitive types + */ +#define R128_POINTS 0x1 +#define R128_LINES 0x2 +#define R128_LINE_STRIP 0x3 +#define R128_TRIANGLES 0x4 +#define R128_TRIANGLE_FAN 0x5 +#define R128_TRIANGLE_STRIP 0x6 + +/* Vertex/indirect buffer size + */ +#define R128_BUFFER_SIZE 16384 + +/* Byte offsets for indirect buffer data + */ +#define R128_INDEX_PRIM_OFFSET 20 +#define R128_HOSTDATA_BLIT_OFFSET 32 + +/* Keep these small for testing. + */ +#define R128_NR_SAREA_CLIPRECTS 12 + +/* There are 2 heaps (local/AGP). Each region within a heap is a + * minimum of 64k, and there are at most 64 of them per heap. + */ +#define R128_LOCAL_TEX_HEAP 0 +#define R128_AGP_TEX_HEAP 1 +#define R128_NR_TEX_HEAPS 2 +#define R128_NR_TEX_REGIONS 64 +#define R128_LOG_TEX_GRANULARITY 16 + +#define R128_NR_CONTEXT_REGS 12 + +#define R128_MAX_TEXTURE_LEVELS 11 +#define R128_MAX_TEXTURE_UNITS 2 + +#endif /* __R128_SAREA_DEFINES__ */ + +typedef struct { + /* Context state - can be written in one large chunk */ + unsigned int dst_pitch_offset_c; + unsigned int dp_gui_master_cntl_c; + unsigned int sc_top_left_c; + unsigned int sc_bottom_right_c; + unsigned int z_offset_c; + unsigned int z_pitch_c; + unsigned int z_sten_cntl_c; + unsigned int tex_cntl_c; + unsigned int misc_3d_state_cntl_reg; + unsigned int texture_clr_cmp_clr_c; + unsigned int texture_clr_cmp_msk_c; + unsigned int fog_color_c; + + /* Texture state */ + unsigned int tex_size_pitch_c; + unsigned int constant_color_c; + + /* Setup state */ + unsigned int pm4_vc_fpu_setup; + unsigned int setup_cntl; + + /* Mask state */ + unsigned int dp_write_mask; + unsigned int sten_ref_mask_c; + unsigned int plane_3d_mask_c; + + /* Window state */ + unsigned int window_xy_offset; + + /* Core state */ + unsigned int scale_3d_cntl; +} drm_r128_context_regs_t; + +/* Setup registers for each texture unit + */ +typedef struct { + unsigned int tex_cntl; + unsigned int tex_combine_cntl; + unsigned int tex_size_pitch; + unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; + unsigned int tex_border_color; +} drm_r128_texture_regs_t; + + +typedef struct drm_r128_sarea { + /* The channel for communication of state information to the kernel + * on firing a vertex buffer. + */ + drm_r128_context_regs_t context_state; + drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; + unsigned int dirty; + unsigned int vertsize; + unsigned int vc_format; + + /* The current cliprects, or a subset thereof. + */ + drm_clip_rect_t boxes[R128_NR_SAREA_CLIPRECTS]; + unsigned int nbox; + + /* Counters for client-side throttling of rendering clients. + */ + unsigned int last_frame; + unsigned int last_dispatch; + + drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1]; + unsigned int tex_age[R128_NR_TEX_HEAPS]; + int ctx_owner; + int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ + int pfCurrentPage; /* which buffer is being displayed? */ +} drm_r128_sarea_t; + + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmR128.h) + */ + +/* Rage 128 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_R128_INIT 0x00 +#define DRM_R128_CCE_START 0x01 +#define DRM_R128_CCE_STOP 0x02 +#define DRM_R128_CCE_RESET 0x03 +#define DRM_R128_CCE_IDLE 0x04 +/* 0x05 not used */ +#define DRM_R128_RESET 0x06 +#define DRM_R128_SWAP 0x07 +#define DRM_R128_CLEAR 0x08 +#define DRM_R128_VERTEX 0x09 +#define DRM_R128_INDICES 0x0a +#define DRM_R128_BLIT 0x0b +#define DRM_R128_DEPTH 0x0c +#define DRM_R128_STIPPLE 0x0d +/* 0x0e not used */ +#define DRM_R128_INDIRECT 0x0f +#define DRM_R128_FULLSCREEN 0x10 +#define DRM_R128_CLEAR2 0x11 +#define DRM_R128_GETPARAM 0x12 +#define DRM_R128_FLIP 0x13 + +#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t) +#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START) +#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t) +#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET) +#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE) +/* 0x05 not used */ +#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET) +#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP) +#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t) +#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t) +#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t) +#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t) +#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t) +#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t) +/* 0x0e not used */ +#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t) +#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t) +#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t) +#define DRM_IOCTL_R128_GETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t) +#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP) + +typedef struct drm_r128_init { + enum { + R128_INIT_CCE = 0x01, + R128_CLEANUP_CCE = 0x02 + } func; +#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) + int sarea_priv_offset; +#else + unsigned long sarea_priv_offset; +#endif + int is_pci; + int cce_mode; + int cce_secure; + int ring_size; + int usec_timeout; + + unsigned int fb_bpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + unsigned int depth_bpp; + unsigned int depth_offset, depth_pitch; + unsigned int span_offset; + +#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) + unsigned int fb_offset; + unsigned int mmio_offset; + unsigned int ring_offset; + unsigned int ring_rptr_offset; + unsigned int buffers_offset; + unsigned int agp_textures_offset; +#else + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long ring_offset; + unsigned long ring_rptr_offset; + unsigned long buffers_offset; + unsigned long agp_textures_offset; +#endif +} drm_r128_init_t; + +typedef struct drm_r128_cce_stop { + int flush; + int idle; +} drm_r128_cce_stop_t; + +typedef struct drm_r128_clear { + unsigned int flags; +#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) + int x, y, w, h; +#endif + unsigned int clear_color; + unsigned int clear_depth; +#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0) + unsigned int color_mask; + unsigned int depth_mask; +#endif +} drm_r128_clear_t; + +typedef struct drm_r128_vertex { + int prim; + int idx; /* Index of vertex buffer */ + int count; /* Number of vertices in buffer */ + int discard; /* Client finished with buffer? */ +} drm_r128_vertex_t; + +typedef struct drm_r128_indices { + int prim; + int idx; + int start; + int end; + int discard; /* Client finished with buffer? */ +} drm_r128_indices_t; + +typedef struct drm_r128_blit { + int idx; + int pitch; + int offset; + int format; + unsigned short x, y; + unsigned short width, height; +} drm_r128_blit_t; + +typedef struct drm_r128_depth { + enum { + R128_WRITE_SPAN = 0x01, + R128_WRITE_PIXELS = 0x02, + R128_READ_SPAN = 0x03, + R128_READ_PIXELS = 0x04 + } func; + int n; + int __user *x; + int __user *y; + unsigned int __user *buffer; + unsigned char __user *mask; +} drm_r128_depth_t; + +typedef struct drm_r128_stipple { + unsigned int __user *mask; +} drm_r128_stipple_t; + +typedef struct drm_r128_indirect { + int idx; + int start; + int end; + int discard; +} drm_r128_indirect_t; + +typedef struct drm_r128_fullscreen { + enum { + R128_INIT_FULLSCREEN = 0x01, + R128_CLEANUP_FULLSCREEN = 0x02 + } func; +} drm_r128_fullscreen_t; + +/* 2.3: An ioctl to get parameters that aren't available to the 3d + * client any other way. + */ +#define R128_PARAM_IRQ_NR 1 + +typedef struct drm_r128_getparam { + int param; + void __user *value; +} drm_r128_getparam_t; + +#endif diff --git a/drivers/char/drm/r128_drv.c b/drivers/char/drm/r128_drv.c new file mode 100644 index 000000000000..ced63810237b --- /dev/null +++ b/drivers/char/drm/r128_drv.c @@ -0,0 +1,122 @@ +/* r128_drv.c -- ATI Rage 128 driver -*- linux-c -*- + * Created: Mon Dec 13 09:47:27 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Gareth Hughes + */ + +#include +#include "drmP.h" +#include "drm.h" +#include "r128_drm.h" +#include "r128_drv.h" + +#include "drm_pciids.h" + +static int postinit( struct drm_device *dev, unsigned long flags ) +{ + DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, + dev->primary.minor, + pci_pretty_name(dev->pdev) + ); + return 0; +} + +static int version( drm_version_t *version ) +{ + int len; + + version->version_major = DRIVER_MAJOR; + version->version_minor = DRIVER_MINOR; + version->version_patchlevel = DRIVER_PATCHLEVEL; + DRM_COPY( version->name, DRIVER_NAME ); + DRM_COPY( version->date, DRIVER_DATE ); + DRM_COPY( version->desc, DRIVER_DESC ); + return 0; +} + +static struct pci_device_id pciidlist[] = { + r128_PCI_IDS +}; + +extern drm_ioctl_desc_t r128_ioctls[]; +extern int r128_max_ioctl; + +static struct drm_driver driver = { + .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, + .dev_priv_size = sizeof(drm_r128_buf_priv_t), + .prerelease = r128_driver_prerelease, + .pretakedown = r128_driver_pretakedown, + .vblank_wait = r128_driver_vblank_wait, + .irq_preinstall = r128_driver_irq_preinstall, + .irq_postinstall = r128_driver_irq_postinstall, + .irq_uninstall = r128_driver_irq_uninstall, + .irq_handler = r128_driver_irq_handler, + .reclaim_buffers = drm_core_reclaim_buffers, + .get_map_ofs = drm_core_get_map_ofs, + .get_reg_ofs = drm_core_get_reg_ofs, + .postinit = postinit, + .version = version, + .ioctls = r128_ioctls, + .dma_ioctl = r128_cce_buffers, + .fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + }, + .pci_driver = { + .name = DRIVER_NAME, + .id_table = pciidlist, + } +}; + +static int __init r128_init(void) +{ + driver.num_ioctls = r128_max_ioctl; + return drm_init(&driver); +} + +static void __exit r128_exit(void) +{ + drm_exit(&driver); +} + +module_init(r128_init); +module_exit(r128_exit); + +MODULE_AUTHOR( DRIVER_AUTHOR ); +MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/r128_drv.h b/drivers/char/drm/r128_drv.h new file mode 100644 index 000000000000..cf1aa5df459e --- /dev/null +++ b/drivers/char/drm/r128_drv.h @@ -0,0 +1,521 @@ +/* r128_drv.h -- Private header for r128 driver -*- linux-c -*- + * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rickard E. (Rik) Faith + * Kevin E. Martin + * Gareth Hughes + * Michel D�zer + */ + +#ifndef __R128_DRV_H__ +#define __R128_DRV_H__ + +/* General customization: + */ +#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." + +#define DRIVER_NAME "r128" +#define DRIVER_DESC "ATI Rage 128" +#define DRIVER_DATE "20030725" + +/* Interface history: + * + * ?? - ?? + * 2.4 - Add support for ycbcr textures (no new ioctls) + * 2.5 - Add FLIP ioctl, disable FULLSCREEN. + */ +#define DRIVER_MAJOR 2 +#define DRIVER_MINOR 5 +#define DRIVER_PATCHLEVEL 0 + + +#define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR ) + +typedef struct drm_r128_freelist { + unsigned int age; + drm_buf_t *buf; + struct drm_r128_freelist *next; + struct drm_r128_freelist *prev; +} drm_r128_freelist_t; + +typedef struct drm_r128_ring_buffer { + u32 *start; + u32 *end; + int size; + int size_l2qw; + + u32 tail; + u32 tail_mask; + int space; + + int high_mark; +} drm_r128_ring_buffer_t; + +typedef struct drm_r128_private { + drm_r128_ring_buffer_t ring; + drm_r128_sarea_t *sarea_priv; + + int cce_mode; + int cce_fifo_size; + int cce_running; + + drm_r128_freelist_t *head; + drm_r128_freelist_t *tail; + + int usec_timeout; + int is_pci; + unsigned long phys_pci_gart; + dma_addr_t bus_pci_gart; + unsigned long cce_buffers_offset; + + atomic_t idle_count; + + int page_flipping; + int current_page; + u32 crtc_offset; + u32 crtc_offset_cntl; + + u32 color_fmt; + unsigned int front_offset; + unsigned int front_pitch; + unsigned int back_offset; + unsigned int back_pitch; + + u32 depth_fmt; + unsigned int depth_offset; + unsigned int depth_pitch; + unsigned int span_offset; + + u32 front_pitch_offset_c; + u32 back_pitch_offset_c; + u32 depth_pitch_offset_c; + u32 span_pitch_offset_c; + + drm_local_map_t *sarea; + drm_local_map_t *mmio; + drm_local_map_t *cce_ring; + drm_local_map_t *ring_rptr; + drm_local_map_t *agp_textures; +} drm_r128_private_t; + +typedef struct drm_r128_buf_priv { + u32 age; + int prim; + int discard; + int dispatched; + drm_r128_freelist_t *list_entry; +} drm_r128_buf_priv_t; + + /* r128_cce.c */ +extern int r128_cce_init( DRM_IOCTL_ARGS ); +extern int r128_cce_start( DRM_IOCTL_ARGS ); +extern int r128_cce_stop( DRM_IOCTL_ARGS ); +extern int r128_cce_reset( DRM_IOCTL_ARGS ); +extern int r128_cce_idle( DRM_IOCTL_ARGS ); +extern int r128_engine_reset( DRM_IOCTL_ARGS ); +extern int r128_fullscreen( DRM_IOCTL_ARGS ); +extern int r128_cce_buffers( DRM_IOCTL_ARGS ); + +extern void r128_freelist_reset( drm_device_t *dev ); + +extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n ); + +extern int r128_do_cce_idle( drm_r128_private_t *dev_priv ); +extern int r128_do_cleanup_cce( drm_device_t *dev ); + +extern int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); + +extern irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS ); +extern void r128_driver_irq_preinstall( drm_device_t *dev ); +extern void r128_driver_irq_postinstall( drm_device_t *dev ); +extern void r128_driver_irq_uninstall( drm_device_t *dev ); +extern void r128_driver_pretakedown(drm_device_t *dev); +extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp); + +/* Register definitions, register access macros and drmAddMap constants + * for Rage 128 kernel driver. + */ + +#define R128_AUX_SC_CNTL 0x1660 +# define R128_AUX1_SC_EN (1 << 0) +# define R128_AUX1_SC_MODE_OR (0 << 1) +# define R128_AUX1_SC_MODE_NAND (1 << 1) +# define R128_AUX2_SC_EN (1 << 2) +# define R128_AUX2_SC_MODE_OR (0 << 3) +# define R128_AUX2_SC_MODE_NAND (1 << 3) +# define R128_AUX3_SC_EN (1 << 4) +# define R128_AUX3_SC_MODE_OR (0 << 5) +# define R128_AUX3_SC_MODE_NAND (1 << 5) +#define R128_AUX1_SC_LEFT 0x1664 +#define R128_AUX1_SC_RIGHT 0x1668 +#define R128_AUX1_SC_TOP 0x166c +#define R128_AUX1_SC_BOTTOM 0x1670 +#define R128_AUX2_SC_LEFT 0x1674 +#define R128_AUX2_SC_RIGHT 0x1678 +#define R128_AUX2_SC_TOP 0x167c +#define R128_AUX2_SC_BOTTOM 0x1680 +#define R128_AUX3_SC_LEFT 0x1684 +#define R128_AUX3_SC_RIGHT 0x1688 +#define R128_AUX3_SC_TOP 0x168c +#define R128_AUX3_SC_BOTTOM 0x1690 + +#define R128_BRUSH_DATA0 0x1480 +#define R128_BUS_CNTL 0x0030 +# define R128_BUS_MASTER_DIS (1 << 6) + +#define R128_CLOCK_CNTL_INDEX 0x0008 +#define R128_CLOCK_CNTL_DATA 0x000c +# define R128_PLL_WR_EN (1 << 7) +#define R128_CONSTANT_COLOR_C 0x1d34 +#define R128_CRTC_OFFSET 0x0224 +#define R128_CRTC_OFFSET_CNTL 0x0228 +# define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16) + +#define R128_DP_GUI_MASTER_CNTL 0x146c +# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) +# define R128_GMC_BRUSH_NONE (15 << 4) +# define R128_GMC_DST_16BPP (4 << 8) +# define R128_GMC_DST_24BPP (5 << 8) +# define R128_GMC_DST_32BPP (6 << 8) +# define R128_GMC_DST_DATATYPE_SHIFT 8 +# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) +# define R128_DP_SRC_SOURCE_MEMORY (2 << 24) +# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) +# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define R128_GMC_AUX_CLIP_DIS (1 << 29) +# define R128_GMC_WR_MSK_DIS (1 << 30) +# define R128_ROP3_S 0x00cc0000 +# define R128_ROP3_P 0x00f00000 +#define R128_DP_WRITE_MASK 0x16cc +#define R128_DST_PITCH_OFFSET_C 0x1c80 +# define R128_DST_TILE (1 << 31) + +#define R128_GEN_INT_CNTL 0x0040 +# define R128_CRTC_VBLANK_INT_EN (1 << 0) +#define R128_GEN_INT_STATUS 0x0044 +# define R128_CRTC_VBLANK_INT (1 << 0) +# define R128_CRTC_VBLANK_INT_AK (1 << 0) +#define R128_GEN_RESET_CNTL 0x00f0 +# define R128_SOFT_RESET_GUI (1 << 0) + +#define R128_GUI_SCRATCH_REG0 0x15e0 +#define R128_GUI_SCRATCH_REG1 0x15e4 +#define R128_GUI_SCRATCH_REG2 0x15e8 +#define R128_GUI_SCRATCH_REG3 0x15ec +#define R128_GUI_SCRATCH_REG4 0x15f0 +#define R128_GUI_SCRATCH_REG5 0x15f4 + +#define R128_GUI_STAT 0x1740 +# define R128_GUI_FIFOCNT_MASK 0x0fff +# define R128_GUI_ACTIVE (1 << 31) + +#define R128_MCLK_CNTL 0x000f +# define R128_FORCE_GCP (1 << 16) +# define R128_FORCE_PIPE3D_CP (1 << 17) +# define R128_FORCE_RCP (1 << 18) + +#define R128_PC_GUI_CTLSTAT 0x1748 +#define R128_PC_NGUI_CTLSTAT 0x0184 +# define R128_PC_FLUSH_GUI (3 << 0) +# define R128_PC_RI_GUI (1 << 2) +# define R128_PC_FLUSH_ALL 0x00ff +# define R128_PC_BUSY (1 << 31) + +#define R128_PCI_GART_PAGE 0x017c +#define R128_PRIM_TEX_CNTL_C 0x1cb0 + +#define R128_SCALE_3D_CNTL 0x1a00 +#define R128_SEC_TEX_CNTL_C 0x1d00 +#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c +#define R128_SETUP_CNTL 0x1bc4 +#define R128_STEN_REF_MASK_C 0x1d40 + +#define R128_TEX_CNTL_C 0x1c9c +# define R128_TEX_CACHE_FLUSH (1 << 23) + +#define R128_WAIT_UNTIL 0x1720 +# define R128_EVENT_CRTC_OFFSET (1 << 0) +#define R128_WINDOW_XY_OFFSET 0x1bcc + + +/* CCE registers + */ +#define R128_PM4_BUFFER_OFFSET 0x0700 +#define R128_PM4_BUFFER_CNTL 0x0704 +# define R128_PM4_MASK (15 << 28) +# define R128_PM4_NONPM4 (0 << 28) +# define R128_PM4_192PIO (1 << 28) +# define R128_PM4_192BM (2 << 28) +# define R128_PM4_128PIO_64INDBM (3 << 28) +# define R128_PM4_128BM_64INDBM (4 << 28) +# define R128_PM4_64PIO_128INDBM (5 << 28) +# define R128_PM4_64BM_128INDBM (6 << 28) +# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) +# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) +# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) +# define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27) + +#define R128_PM4_BUFFER_WM_CNTL 0x0708 +# define R128_WMA_SHIFT 0 +# define R128_WMB_SHIFT 8 +# define R128_WMC_SHIFT 16 +# define R128_WB_WM_SHIFT 24 + +#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c +#define R128_PM4_BUFFER_DL_RPTR 0x0710 +#define R128_PM4_BUFFER_DL_WPTR 0x0714 +# define R128_PM4_BUFFER_DL_DONE (1 << 31) + +#define R128_PM4_VC_FPU_SETUP 0x071c + +#define R128_PM4_IW_INDOFF 0x0738 +#define R128_PM4_IW_INDSIZE 0x073c + +#define R128_PM4_STAT 0x07b8 +# define R128_PM4_FIFOCNT_MASK 0x0fff +# define R128_PM4_BUSY (1 << 16) +# define R128_PM4_GUI_ACTIVE (1 << 31) + +#define R128_PM4_MICROCODE_ADDR 0x07d4 +#define R128_PM4_MICROCODE_RADDR 0x07d8 +#define R128_PM4_MICROCODE_DATAH 0x07dc +#define R128_PM4_MICROCODE_DATAL 0x07e0 + +#define R128_PM4_BUFFER_ADDR 0x07f0 +#define R128_PM4_MICRO_CNTL 0x07fc +# define R128_PM4_MICRO_FREERUN (1 << 30) + +#define R128_PM4_FIFO_DATA_EVEN 0x1000 +#define R128_PM4_FIFO_DATA_ODD 0x1004 + + +/* CCE command packets + */ +#define R128_CCE_PACKET0 0x00000000 +#define R128_CCE_PACKET1 0x40000000 +#define R128_CCE_PACKET2 0x80000000 +#define R128_CCE_PACKET3 0xC0000000 +# define R128_CNTL_HOSTDATA_BLT 0x00009400 +# define R128_CNTL_PAINT_MULTI 0x00009A00 +# define R128_CNTL_BITBLT_MULTI 0x00009B00 +# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 + +#define R128_CCE_PACKET_MASK 0xC0000000 +#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 +#define R128_CCE_PACKET0_REG_MASK 0x000007ff +#define R128_CCE_PACKET1_REG0_MASK 0x000007ff +#define R128_CCE_PACKET1_REG1_MASK 0x003ff800 + +#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 +#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 +#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 +#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 +#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 +#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 +#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 +#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 +#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 +#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 +#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 +#define R128_CCE_VC_CNTL_NUM_SHIFT 16 + +#define R128_DATATYPE_VQ 0 +#define R128_DATATYPE_CI4 1 +#define R128_DATATYPE_CI8 2 +#define R128_DATATYPE_ARGB1555 3 +#define R128_DATATYPE_RGB565 4 +#define R128_DATATYPE_RGB888 5 +#define R128_DATATYPE_ARGB8888 6 +#define R128_DATATYPE_RGB332 7 +#define R128_DATATYPE_Y8 8 +#define R128_DATATYPE_RGB8 9 +#define R128_DATATYPE_CI16 10 +#define R128_DATATYPE_YVYU422 11 +#define R128_DATATYPE_VYUY422 12 +#define R128_DATATYPE_AYUV444 14 +#define R128_DATATYPE_ARGB4444 15 + +/* Constants */ +#define R128_AGP_OFFSET 0x02000000 + +#define R128_WATERMARK_L 16 +#define R128_WATERMARK_M 8 +#define R128_WATERMARK_N 8 +#define R128_WATERMARK_K 128 + +#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ + +#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 +#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 +#define R128_MAX_VB_AGE 0x7fffffff +#define R128_MAX_VB_VERTS (0xffff) + +#define R128_RING_HIGH_MARK 128 + +#define R128_PERFORMANCE_BOXES 0 + +#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) +#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) +#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) +#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) + +#define R128_WRITE_PLL(addr,val) \ +do { \ + R128_WRITE8(R128_CLOCK_CNTL_INDEX, \ + ((addr) & 0x1f) | R128_PLL_WR_EN); \ + R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ +} while (0) + + +#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ + ((n) << 16) | ((reg) >> 2)) +#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ + (((reg1) >> 2) << 11) | ((reg0) >> 2)) +#define CCE_PACKET2() (R128_CCE_PACKET2) +#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ + (pkt) | ((n) << 16)) + + +static __inline__ void +r128_update_ring_snapshot( drm_r128_private_t *dev_priv ) +{ + drm_r128_ring_buffer_t *ring = &dev_priv->ring; + ring->space = (GET_RING_HEAD( dev_priv ) - ring->tail) * sizeof(u32); + if ( ring->space <= 0 ) + ring->space += ring->size; +} + +/* ================================================================ + * Misc helper macros + */ + +#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ +do { \ + drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ + if ( ring->space < ring->high_mark ) { \ + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \ + r128_update_ring_snapshot( dev_priv ); \ + if ( ring->space >= ring->high_mark ) \ + goto __ring_space_done; \ + DRM_UDELAY(1); \ + } \ + DRM_ERROR( "ring space check failed!\n" ); \ + return DRM_ERR(EBUSY); \ + } \ + __ring_space_done: \ + ; \ +} while (0) + +#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ +do { \ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \ + if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \ + int __ret = r128_do_cce_idle( dev_priv ); \ + if ( __ret ) return __ret; \ + sarea_priv->last_dispatch = 0; \ + r128_freelist_reset( dev ); \ + } \ +} while (0) + +#define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \ + OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \ + OUT_RING( R128_EVENT_CRTC_OFFSET ); \ +} while (0) + + +/* ================================================================ + * Ring control + */ + +#define R128_VERBOSE 0 + +#define RING_LOCALS \ + int write, _nr; unsigned int tail_mask; volatile u32 *ring; + +#define BEGIN_RING( n ) do { \ + if ( R128_VERBOSE ) { \ + DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ + (n), __FUNCTION__ ); \ + } \ + if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ + COMMIT_RING(); \ + r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \ + } \ + _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ + ring = dev_priv->ring.start; \ + write = dev_priv->ring.tail; \ + tail_mask = dev_priv->ring.tail_mask; \ +} while (0) + +/* You can set this to zero if you want. If the card locks up, you'll + * need to keep this set. It works around a bug in early revs of the + * Rage 128 chipset, where the CCE would read 32 dwords past the end of + * the ring buffer before wrapping around. + */ +#define R128_BROKEN_CCE 1 + +#define ADVANCE_RING() do { \ + if ( R128_VERBOSE ) { \ + DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ + write, dev_priv->ring.tail ); \ + } \ + if ( R128_BROKEN_CCE && write < 32 ) { \ + memcpy( dev_priv->ring.end, \ + dev_priv->ring.start, \ + write * sizeof(u32) ); \ + } \ + if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \ + DRM_ERROR( \ + "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ + ((dev_priv->ring.tail + _nr) & tail_mask), \ + write, __LINE__); \ + } else \ + dev_priv->ring.tail = write; \ +} while (0) + +#define COMMIT_RING() do { \ + if ( R128_VERBOSE ) { \ + DRM_INFO( "COMMIT_RING() tail=0x%06x\n", \ + dev_priv->ring.tail ); \ + } \ + DRM_MEMORYBARRIER(); \ + R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \ + R128_READ( R128_PM4_BUFFER_DL_WPTR ); \ +} while (0) + +#define OUT_RING( x ) do { \ + if ( R128_VERBOSE ) { \ + DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ + (unsigned int)(x), write ); \ + } \ + ring[write++] = cpu_to_le32( x ); \ + write &= tail_mask; \ +} while (0) + +#endif /* __R128_DRV_H__ */ diff --git a/drivers/char/drm/r128_irq.c b/drivers/char/drm/r128_irq.c new file mode 100644 index 000000000000..643a30785fe5 --- /dev/null +++ b/drivers/char/drm/r128_irq.c @@ -0,0 +1,102 @@ +/* r128_irq.c -- IRQ handling for radeon -*- linux-c -*- + * + * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + * + * The Weather Channel (TM) funded Tungsten Graphics to develop the + * initial release of the Radeon 8500 driver under the XFree86 license. + * This notice must be preserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Keith Whitwell + * Eric Anholt + */ + +#include "drmP.h" +#include "drm.h" +#include "r128_drm.h" +#include "r128_drv.h" + +irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS ) +{ + drm_device_t *dev = (drm_device_t *) arg; + drm_r128_private_t *dev_priv = + (drm_r128_private_t *)dev->dev_private; + int status; + + status = R128_READ( R128_GEN_INT_STATUS ); + + /* VBLANK interrupt */ + if ( status & R128_CRTC_VBLANK_INT ) { + R128_WRITE( R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK ); + atomic_inc(&dev->vbl_received); + DRM_WAKEUP(&dev->vbl_queue); + drm_vbl_send_signals( dev ); + return IRQ_HANDLED; + } + return IRQ_NONE; +} + +int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) +{ + unsigned int cur_vblank; + int ret = 0; + + /* Assume that the user has missed the current sequence number + * by about a day rather than she wants to wait for years + * using vertical blanks... + */ + DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, + ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) + - *sequence ) <= (1<<23) ) ); + + *sequence = cur_vblank; + + return ret; +} + +void r128_driver_irq_preinstall( drm_device_t *dev ) { + drm_r128_private_t *dev_priv = + (drm_r128_private_t *)dev->dev_private; + + /* Disable *all* interrupts */ + R128_WRITE( R128_GEN_INT_CNTL, 0 ); + /* Clear vblank bit if it's already high */ + R128_WRITE( R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK ); +} + +void r128_driver_irq_postinstall( drm_device_t *dev ) { + drm_r128_private_t *dev_priv = + (drm_r128_private_t *)dev->dev_private; + + /* Turn on VBL interrupt */ + R128_WRITE( R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN ); +} + +void r128_driver_irq_uninstall( drm_device_t *dev ) { + drm_r128_private_t *dev_priv = + (drm_r128_private_t *)dev->dev_private; + if (!dev_priv) + return; + + /* Disable *all* interrupts */ + R128_WRITE( R128_GEN_INT_CNTL, 0 ); +} diff --git a/drivers/char/drm/r128_state.c b/drivers/char/drm/r128_state.c new file mode 100644 index 000000000000..38b3cbd0bbba --- /dev/null +++ b/drivers/char/drm/r128_state.c @@ -0,0 +1,1732 @@ +/* r128_state.c -- State support for r128 -*- linux-c -*- + * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com + * + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Gareth Hughes + */ + +#include "drmP.h" +#include "drm.h" +#include "r128_drm.h" +#include "r128_drv.h" + + +/* ================================================================ + * CCE hardware state programming functions + */ + +static void r128_emit_clip_rects( drm_r128_private_t *dev_priv, + drm_clip_rect_t *boxes, int count ) +{ + u32 aux_sc_cntl = 0x00000000; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( (count < 3? count: 3) * 5 + 2 ); + + if ( count >= 1 ) { + OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) ); + OUT_RING( boxes[0].x1 ); + OUT_RING( boxes[0].x2 - 1 ); + OUT_RING( boxes[0].y1 ); + OUT_RING( boxes[0].y2 - 1 ); + + aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR); + } + if ( count >= 2 ) { + OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) ); + OUT_RING( boxes[1].x1 ); + OUT_RING( boxes[1].x2 - 1 ); + OUT_RING( boxes[1].y1 ); + OUT_RING( boxes[1].y2 - 1 ); + + aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR); + } + if ( count >= 3 ) { + OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) ); + OUT_RING( boxes[2].x1 ); + OUT_RING( boxes[2].x2 - 1 ); + OUT_RING( boxes[2].y1 ); + OUT_RING( boxes[2].y2 - 1 ); + + aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR); + } + + OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) ); + OUT_RING( aux_sc_cntl ); + + ADVANCE_RING(); +} + +static __inline__ void r128_emit_core( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) ); + OUT_RING( ctx->scale_3d_cntl ); + + ADVANCE_RING(); +} + +static __inline__ void r128_emit_context( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 13 ); + + OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) ); + OUT_RING( ctx->dst_pitch_offset_c ); + OUT_RING( ctx->dp_gui_master_cntl_c ); + OUT_RING( ctx->sc_top_left_c ); + OUT_RING( ctx->sc_bottom_right_c ); + OUT_RING( ctx->z_offset_c ); + OUT_RING( ctx->z_pitch_c ); + OUT_RING( ctx->z_sten_cntl_c ); + OUT_RING( ctx->tex_cntl_c ); + OUT_RING( ctx->misc_3d_state_cntl_reg ); + OUT_RING( ctx->texture_clr_cmp_clr_c ); + OUT_RING( ctx->texture_clr_cmp_msk_c ); + OUT_RING( ctx->fog_color_c ); + + ADVANCE_RING(); +} + +static __inline__ void r128_emit_setup( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 3 ); + + OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) ); + OUT_RING( ctx->setup_cntl ); + OUT_RING( ctx->pm4_vc_fpu_setup ); + + ADVANCE_RING(); +} + +static __inline__ void r128_emit_masks( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 5 ); + + OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); + OUT_RING( ctx->dp_write_mask ); + + OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) ); + OUT_RING( ctx->sten_ref_mask_c ); + OUT_RING( ctx->plane_3d_mask_c ); + + ADVANCE_RING(); +} + +static __inline__ void r128_emit_window( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) ); + OUT_RING( ctx->window_xy_offset ); + + ADVANCE_RING(); +} + +static __inline__ void r128_emit_tex0( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_context_regs_t *ctx = &sarea_priv->context_state; + drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0]; + int i; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS ); + + OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C, + 2 + R128_MAX_TEXTURE_LEVELS ) ); + OUT_RING( tex->tex_cntl ); + OUT_RING( tex->tex_combine_cntl ); + OUT_RING( ctx->tex_size_pitch_c ); + for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { + OUT_RING( tex->tex_offset[i] ); + } + + OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) ); + OUT_RING( ctx->constant_color_c ); + OUT_RING( tex->tex_border_color ); + + ADVANCE_RING(); +} + +static __inline__ void r128_emit_tex1( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1]; + int i; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS ); + + OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C, + 1 + R128_MAX_TEXTURE_LEVELS ) ); + OUT_RING( tex->tex_cntl ); + OUT_RING( tex->tex_combine_cntl ); + for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { + OUT_RING( tex->tex_offset[i] ); + } + + OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) ); + OUT_RING( tex->tex_border_color ); + + ADVANCE_RING(); +} + +static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv ) +{ + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int dirty = sarea_priv->dirty; + + DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); + + if ( dirty & R128_UPLOAD_CORE ) { + r128_emit_core( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_CORE; + } + + if ( dirty & R128_UPLOAD_CONTEXT ) { + r128_emit_context( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT; + } + + if ( dirty & R128_UPLOAD_SETUP ) { + r128_emit_setup( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_SETUP; + } + + if ( dirty & R128_UPLOAD_MASKS ) { + r128_emit_masks( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_MASKS; + } + + if ( dirty & R128_UPLOAD_WINDOW ) { + r128_emit_window( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_WINDOW; + } + + if ( dirty & R128_UPLOAD_TEX0 ) { + r128_emit_tex0( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_TEX0; + } + + if ( dirty & R128_UPLOAD_TEX1 ) { + r128_emit_tex1( dev_priv ); + sarea_priv->dirty &= ~R128_UPLOAD_TEX1; + } + + /* Turn off the texture cache flushing */ + sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH; + + sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE; +} + + +#if R128_PERFORMANCE_BOXES +/* ================================================================ + * Performance monitoring functions + */ + +static void r128_clear_box( drm_r128_private_t *dev_priv, + int x, int y, int w, int h, + int r, int g, int b ) +{ + u32 pitch, offset; + u32 fb_bpp, color; + RING_LOCALS; + + switch ( dev_priv->fb_bpp ) { + case 16: + fb_bpp = R128_GMC_DST_16BPP; + color = (((r & 0xf8) << 8) | + ((g & 0xfc) << 3) | + ((b & 0xf8) >> 3)); + break; + case 24: + fb_bpp = R128_GMC_DST_24BPP; + color = ((r << 16) | (g << 8) | b); + break; + case 32: + fb_bpp = R128_GMC_DST_32BPP; + color = (((0xff) << 24) | (r << 16) | (g << 8) | b); + break; + default: + return; + } + + offset = dev_priv->back_offset; + pitch = dev_priv->back_pitch >> 3; + + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + fb_bpp | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS ); + + OUT_RING( (pitch << 21) | (offset >> 5) ); + OUT_RING( color ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); +} + +static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv ) +{ + if ( atomic_read( &dev_priv->idle_count ) == 0 ) { + r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); + } else { + atomic_set( &dev_priv->idle_count, 0 ); + } +} + +#endif + + +/* ================================================================ + * CCE command dispatch functions + */ + +static void r128_print_dirty( const char *msg, unsigned int flags ) +{ + DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", + msg, + flags, + (flags & R128_UPLOAD_CORE) ? "core, " : "", + (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", + (flags & R128_UPLOAD_SETUP) ? "setup, " : "", + (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", + (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", + (flags & R128_UPLOAD_MASKS) ? "masks, " : "", + (flags & R128_UPLOAD_WINDOW) ? "window, " : "", + (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", + (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" ); +} + +static void r128_cce_dispatch_clear( drm_device_t *dev, + drm_r128_clear_t *clear ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + unsigned int flags = clear->flags; + int i; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { + unsigned int tmp = flags; + + flags &= ~(R128_FRONT | R128_BACK); + if ( tmp & R128_FRONT ) flags |= R128_BACK; + if ( tmp & R128_BACK ) flags |= R128_FRONT; + } + + for ( i = 0 ; i < nbox ; i++ ) { + int x = pbox[i].x1; + int y = pbox[i].y1; + int w = pbox[i].x2 - x; + int h = pbox[i].y2 - y; + + DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", + pbox[i].x1, pbox[i].y1, pbox[i].x2, + pbox[i].y2, flags ); + + if ( flags & (R128_FRONT | R128_BACK) ) { + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); + OUT_RING( clear->color_mask ); + + ADVANCE_RING(); + } + + if ( flags & R128_FRONT ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS ); + + OUT_RING( dev_priv->front_pitch_offset_c ); + OUT_RING( clear->clear_color ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + + if ( flags & R128_BACK ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS ); + + OUT_RING( dev_priv->back_pitch_offset_c ); + OUT_RING( clear->clear_color ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + + if ( flags & R128_DEPTH ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS | + R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( clear->clear_depth ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + } +} + +static void r128_cce_dispatch_swap( drm_device_t *dev ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int i; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + +#if R128_PERFORMANCE_BOXES + /* Do some trivial performance monitoring... + */ + r128_cce_performance_boxes( dev_priv ); +#endif + + for ( i = 0 ; i < nbox ; i++ ) { + int x = pbox[i].x1; + int y = pbox[i].y1; + int w = pbox[i].x2 - x; + int h = pbox[i].y2 - y; + + BEGIN_RING( 7 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); + OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | + R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_NONE | + (dev_priv->color_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_S | + R128_DP_SRC_SOURCE_MEMORY | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS | + R128_GMC_WR_MSK_DIS ); + + /* Make this work even if front & back are flipped: + */ + if (dev_priv->current_page == 0) { + OUT_RING( dev_priv->back_pitch_offset_c ); + OUT_RING( dev_priv->front_pitch_offset_c ); + } + else { + OUT_RING( dev_priv->front_pitch_offset_c ); + OUT_RING( dev_priv->back_pitch_offset_c ); + } + + OUT_RING( (x << 16) | y ); + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + + /* Increment the frame counter. The client-side 3D driver must + * throttle the framerate by waiting for this value before + * performing the swapbuffer ioctl. + */ + dev_priv->sarea_priv->last_frame++; + + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); + OUT_RING( dev_priv->sarea_priv->last_frame ); + + ADVANCE_RING(); +} + +static void r128_cce_dispatch_flip( drm_device_t *dev ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, + dev_priv->sarea_priv->pfCurrentPage); + +#if R128_PERFORMANCE_BOXES + /* Do some trivial performance monitoring... + */ + r128_cce_performance_boxes( dev_priv ); +#endif + + BEGIN_RING( 4 ); + + R128_WAIT_UNTIL_PAGE_FLIPPED(); + OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) ); + + if ( dev_priv->current_page == 0 ) { + OUT_RING( dev_priv->back_offset ); + } else { + OUT_RING( dev_priv->front_offset ); + } + + ADVANCE_RING(); + + /* Increment the frame counter. The client-side 3D driver must + * throttle the framerate by waiting for this value before + * performing the swapbuffer ioctl. + */ + dev_priv->sarea_priv->last_frame++; + dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = + 1 - dev_priv->current_page; + + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); + OUT_RING( dev_priv->sarea_priv->last_frame ); + + ADVANCE_RING(); +} + +static void r128_cce_dispatch_vertex( drm_device_t *dev, + drm_buf_t *buf ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_buf_priv_t *buf_priv = buf->dev_private; + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + int format = sarea_priv->vc_format; + int offset = buf->bus_address; + int size = buf->used; + int prim = buf_priv->prim; + int i = 0; + RING_LOCALS; + DRM_DEBUG( "buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox ); + + if ( 0 ) + r128_print_dirty( "dispatch_vertex", sarea_priv->dirty ); + + if ( buf->used ) { + buf_priv->dispatched = 1; + + if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { + r128_emit_state( dev_priv ); + } + + do { + /* Emit the next set of up to three cliprects */ + if ( i < sarea_priv->nbox ) { + r128_emit_clip_rects( dev_priv, + &sarea_priv->boxes[i], + sarea_priv->nbox - i ); + } + + /* Emit the vertex buffer rendering commands */ + BEGIN_RING( 5 ); + + OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) ); + OUT_RING( offset ); + OUT_RING( size ); + OUT_RING( format ); + OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | + (size << R128_CCE_VC_CNTL_NUM_SHIFT) ); + + ADVANCE_RING(); + + i += 3; + } while ( i < sarea_priv->nbox ); + } + + if ( buf_priv->discard ) { + buf_priv->age = dev_priv->sarea_priv->last_dispatch; + + /* Emit the vertex buffer age */ + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); + OUT_RING( buf_priv->age ); + + ADVANCE_RING(); + + buf->pending = 1; + buf->used = 0; + /* FIXME: Check dispatched field */ + buf_priv->dispatched = 0; + } + + dev_priv->sarea_priv->last_dispatch++; + + sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; + sarea_priv->nbox = 0; +} + +static void r128_cce_dispatch_indirect( drm_device_t *dev, + drm_buf_t *buf, + int start, int end ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_buf_priv_t *buf_priv = buf->dev_private; + RING_LOCALS; + DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", + buf->idx, start, end ); + + if ( start != end ) { + int offset = buf->bus_address + start; + int dwords = (end - start + 3) / sizeof(u32); + + /* Indirect buffer data must be an even number of + * dwords, so if we've been given an odd number we must + * pad the data with a Type-2 CCE packet. + */ + if ( dwords & 1 ) { + u32 *data = (u32 *) + ((char *)dev->agp_buffer_map->handle + + buf->offset + start); + data[dwords++] = cpu_to_le32( R128_CCE_PACKET2 ); + } + + buf_priv->dispatched = 1; + + /* Fire off the indirect buffer */ + BEGIN_RING( 3 ); + + OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) ); + OUT_RING( offset ); + OUT_RING( dwords ); + + ADVANCE_RING(); + } + + if ( buf_priv->discard ) { + buf_priv->age = dev_priv->sarea_priv->last_dispatch; + + /* Emit the indirect buffer age */ + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); + OUT_RING( buf_priv->age ); + + ADVANCE_RING(); + + buf->pending = 1; + buf->used = 0; + /* FIXME: Check dispatched field */ + buf_priv->dispatched = 0; + } + + dev_priv->sarea_priv->last_dispatch++; +} + +static void r128_cce_dispatch_indices( drm_device_t *dev, + drm_buf_t *buf, + int start, int end, + int count ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_buf_priv_t *buf_priv = buf->dev_private; + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + int format = sarea_priv->vc_format; + int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset; + int prim = buf_priv->prim; + u32 *data; + int dwords; + int i = 0; + RING_LOCALS; + DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count ); + + if ( 0 ) + r128_print_dirty( "dispatch_indices", sarea_priv->dirty ); + + if ( start != end ) { + buf_priv->dispatched = 1; + + if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { + r128_emit_state( dev_priv ); + } + + dwords = (end - start + 3) / sizeof(u32); + + data = (u32 *)((char *)dev->agp_buffer_map->handle + + buf->offset + start); + + data[0] = cpu_to_le32( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, + dwords-2 ) ); + + data[1] = cpu_to_le32( offset ); + data[2] = cpu_to_le32( R128_MAX_VB_VERTS ); + data[3] = cpu_to_le32( format ); + data[4] = cpu_to_le32( (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | + (count << 16)) ); + + if ( count & 0x1 ) { +#ifdef __LITTLE_ENDIAN + data[dwords-1] &= 0x0000ffff; +#else + data[dwords-1] &= 0xffff0000; +#endif + } + + do { + /* Emit the next set of up to three cliprects */ + if ( i < sarea_priv->nbox ) { + r128_emit_clip_rects( dev_priv, + &sarea_priv->boxes[i], + sarea_priv->nbox - i ); + } + + r128_cce_dispatch_indirect( dev, buf, start, end ); + + i += 3; + } while ( i < sarea_priv->nbox ); + } + + if ( buf_priv->discard ) { + buf_priv->age = dev_priv->sarea_priv->last_dispatch; + + /* Emit the vertex buffer age */ + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); + OUT_RING( buf_priv->age ); + + ADVANCE_RING(); + + buf->pending = 1; + /* FIXME: Check dispatched field */ + buf_priv->dispatched = 0; + } + + dev_priv->sarea_priv->last_dispatch++; + + sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; + sarea_priv->nbox = 0; +} + +static int r128_cce_dispatch_blit( DRMFILE filp, + drm_device_t *dev, + drm_r128_blit_t *blit ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_r128_buf_priv_t *buf_priv; + u32 *data; + int dword_shift, dwords; + RING_LOCALS; + DRM_DEBUG( "\n" ); + + /* The compiler won't optimize away a division by a variable, + * even if the only legal values are powers of two. Thus, we'll + * use a shift instead. + */ + switch ( blit->format ) { + case R128_DATATYPE_ARGB8888: + dword_shift = 0; + break; + case R128_DATATYPE_ARGB1555: + case R128_DATATYPE_RGB565: + case R128_DATATYPE_ARGB4444: + case R128_DATATYPE_YVYU422: + case R128_DATATYPE_VYUY422: + dword_shift = 1; + break; + case R128_DATATYPE_CI8: + case R128_DATATYPE_RGB8: + dword_shift = 2; + break; + default: + DRM_ERROR( "invalid blit format %d\n", blit->format ); + return DRM_ERR(EINVAL); + } + + /* Flush the pixel cache, and mark the contents as Read Invalid. + * This ensures no pixel data gets mixed up with the texture + * data from the host data blit, otherwise part of the texture + * image may be corrupted. + */ + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); + OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI ); + + ADVANCE_RING(); + + /* Dispatch the indirect buffer. + */ + buf = dma->buflist[blit->idx]; + buf_priv = buf->dev_private; + + if ( buf->filp != filp ) { + DRM_ERROR( "process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp ); + return DRM_ERR(EINVAL); + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", blit->idx ); + return DRM_ERR(EINVAL); + } + + buf_priv->discard = 1; + + dwords = (blit->width * blit->height) >> dword_shift; + + data = (u32 *)((char *)dev->agp_buffer_map->handle + buf->offset); + + data[0] = cpu_to_le32( CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ) ); + data[1] = cpu_to_le32( (R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_NONE | + (blit->format << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_S | + R128_DP_SRC_SOURCE_HOST_DATA | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS | + R128_GMC_WR_MSK_DIS) ); + + data[2] = cpu_to_le32( (blit->pitch << 21) | (blit->offset >> 5) ); + data[3] = cpu_to_le32( 0xffffffff ); + data[4] = cpu_to_le32( 0xffffffff ); + data[5] = cpu_to_le32( (blit->y << 16) | blit->x ); + data[6] = cpu_to_le32( (blit->height << 16) | blit->width ); + data[7] = cpu_to_le32( dwords ); + + buf->used = (dwords + 8) * sizeof(u32); + + r128_cce_dispatch_indirect( dev, buf, 0, buf->used ); + + /* Flush the pixel cache after the blit completes. This ensures + * the texture data is written out to memory before rendering + * continues. + */ + BEGIN_RING( 2 ); + + OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); + OUT_RING( R128_PC_FLUSH_GUI ); + + ADVANCE_RING(); + + return 0; +} + + +/* ================================================================ + * Tiled depth buffer management + * + * FIXME: These should all set the destination write mask for when we + * have hardware stencil support. + */ + +static int r128_cce_dispatch_write_span( drm_device_t *dev, + drm_r128_depth_t *depth ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + int count, x, y; + u32 *buffer; + u8 *mask; + int i, buffer_size, mask_size; + RING_LOCALS; + DRM_DEBUG( "\n" ); + + count = depth->n; + if (count > 4096 || count <= 0) + return DRM_ERR(EMSGSIZE); + + if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) { + return DRM_ERR(EFAULT); + } + if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) { + return DRM_ERR(EFAULT); + } + + buffer_size = depth->n * sizeof(u32); + buffer = drm_alloc( buffer_size, DRM_MEM_BUFS ); + if ( buffer == NULL ) + return DRM_ERR(ENOMEM); + if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { + drm_free( buffer, buffer_size, DRM_MEM_BUFS); + return DRM_ERR(EFAULT); + } + + mask_size = depth->n * sizeof(u8); + if ( depth->mask ) { + mask = drm_alloc( mask_size, DRM_MEM_BUFS ); + if ( mask == NULL ) { + drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + return DRM_ERR(ENOMEM); + } + if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { + drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + drm_free( mask, mask_size, DRM_MEM_BUFS ); + return DRM_ERR(EFAULT); + } + + for ( i = 0 ; i < count ; i++, x++ ) { + if ( mask[i] ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( buffer[i] ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (1 << 16) | 1 ); + + ADVANCE_RING(); + } + } + + drm_free( mask, mask_size, DRM_MEM_BUFS ); + } else { + for ( i = 0 ; i < count ; i++, x++ ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( buffer[i] ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (1 << 16) | 1 ); + + ADVANCE_RING(); + } + } + + drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + + return 0; +} + +static int r128_cce_dispatch_write_pixels( drm_device_t *dev, + drm_r128_depth_t *depth ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + int count, *x, *y; + u32 *buffer; + u8 *mask; + int i, xbuf_size, ybuf_size, buffer_size, mask_size; + RING_LOCALS; + DRM_DEBUG( "\n" ); + + count = depth->n; + if (count > 4096 || count <= 0) + return DRM_ERR(EMSGSIZE); + + xbuf_size = count * sizeof(*x); + ybuf_size = count * sizeof(*y); + x = drm_alloc( xbuf_size, DRM_MEM_BUFS ); + if ( x == NULL ) { + return DRM_ERR(ENOMEM); + } + y = drm_alloc( ybuf_size, DRM_MEM_BUFS ); + if ( y == NULL ) { + drm_free( x, xbuf_size, DRM_MEM_BUFS ); + return DRM_ERR(ENOMEM); + } + if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { + drm_free( x, xbuf_size, DRM_MEM_BUFS ); + drm_free( y, ybuf_size, DRM_MEM_BUFS ); + return DRM_ERR(EFAULT); + } + if ( DRM_COPY_FROM_USER( y, depth->y, xbuf_size ) ) { + drm_free( x, xbuf_size, DRM_MEM_BUFS ); + drm_free( y, ybuf_size, DRM_MEM_BUFS ); + return DRM_ERR(EFAULT); + } + + buffer_size = depth->n * sizeof(u32); + buffer = drm_alloc( buffer_size, DRM_MEM_BUFS ); + if ( buffer == NULL ) { + drm_free( x, xbuf_size, DRM_MEM_BUFS ); + drm_free( y, ybuf_size, DRM_MEM_BUFS ); + return DRM_ERR(ENOMEM); + } + if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { + drm_free( x, xbuf_size, DRM_MEM_BUFS ); + drm_free( y, ybuf_size, DRM_MEM_BUFS ); + drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + return DRM_ERR(EFAULT); + } + + if ( depth->mask ) { + mask_size = depth->n * sizeof(u8); + mask = drm_alloc( mask_size, DRM_MEM_BUFS ); + if ( mask == NULL ) { + drm_free( x, xbuf_size, DRM_MEM_BUFS ); + drm_free( y, ybuf_size, DRM_MEM_BUFS ); + drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + return DRM_ERR(ENOMEM); + } + if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { + drm_free( x, xbuf_size, DRM_MEM_BUFS ); + drm_free( y, ybuf_size, DRM_MEM_BUFS ); + drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + drm_free( mask, mask_size, DRM_MEM_BUFS ); + return DRM_ERR(EFAULT); + } + + for ( i = 0 ; i < count ; i++ ) { + if ( mask[i] ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( buffer[i] ); + + OUT_RING( (x[i] << 16) | y[i] ); + OUT_RING( (1 << 16) | 1 ); + + ADVANCE_RING(); + } + } + + drm_free( mask, mask_size, DRM_MEM_BUFS ); + } else { + for ( i = 0 ; i < count ; i++ ) { + BEGIN_RING( 6 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( buffer[i] ); + + OUT_RING( (x[i] << 16) | y[i] ); + OUT_RING( (1 << 16) | 1 ); + + ADVANCE_RING(); + } + } + + drm_free( x, xbuf_size, DRM_MEM_BUFS ); + drm_free( y, ybuf_size, DRM_MEM_BUFS ); + drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + + return 0; +} + +static int r128_cce_dispatch_read_span( drm_device_t *dev, + drm_r128_depth_t *depth ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + int count, x, y; + RING_LOCALS; + DRM_DEBUG( "\n" ); + + count = depth->n; + if (count > 4096 || count <= 0) + return DRM_ERR(EMSGSIZE); + + if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) { + return DRM_ERR(EFAULT); + } + if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) { + return DRM_ERR(EFAULT); + } + + BEGIN_RING( 7 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); + OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | + R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_NONE | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_S | + R128_DP_SRC_SOURCE_MEMORY | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( dev_priv->span_pitch_offset_c ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (0 << 16) | 0 ); + OUT_RING( (count << 16) | 1 ); + + ADVANCE_RING(); + + return 0; +} + +static int r128_cce_dispatch_read_pixels( drm_device_t *dev, + drm_r128_depth_t *depth ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + int count, *x, *y; + int i, xbuf_size, ybuf_size; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + count = depth->n; + if (count > 4096 || count <= 0) + return DRM_ERR(EMSGSIZE); + + if ( count > dev_priv->depth_pitch ) { + count = dev_priv->depth_pitch; + } + + xbuf_size = count * sizeof(*x); + ybuf_size = count * sizeof(*y); + x = drm_alloc( xbuf_size, DRM_MEM_BUFS ); + if ( x == NULL ) { + return DRM_ERR(ENOMEM); + } + y = drm_alloc( ybuf_size, DRM_MEM_BUFS ); + if ( y == NULL ) { + drm_free( x, xbuf_size, DRM_MEM_BUFS ); + return DRM_ERR(ENOMEM); + } + if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { + drm_free( x, xbuf_size, DRM_MEM_BUFS ); + drm_free( y, ybuf_size, DRM_MEM_BUFS ); + return DRM_ERR(EFAULT); + } + if ( DRM_COPY_FROM_USER( y, depth->y, ybuf_size ) ) { + drm_free( x, xbuf_size, DRM_MEM_BUFS ); + drm_free( y, ybuf_size, DRM_MEM_BUFS ); + return DRM_ERR(EFAULT); + } + + for ( i = 0 ; i < count ; i++ ) { + BEGIN_RING( 7 ); + + OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); + OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | + R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_NONE | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_S | + R128_DP_SRC_SOURCE_MEMORY | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS ); + + OUT_RING( dev_priv->depth_pitch_offset_c ); + OUT_RING( dev_priv->span_pitch_offset_c ); + + OUT_RING( (x[i] << 16) | y[i] ); + OUT_RING( (i << 16) | 0 ); + OUT_RING( (1 << 16) | 1 ); + + ADVANCE_RING(); + } + + drm_free( x, xbuf_size, DRM_MEM_BUFS ); + drm_free( y, ybuf_size, DRM_MEM_BUFS ); + + return 0; +} + + +/* ================================================================ + * Polygon stipple + */ + +static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + int i; + RING_LOCALS; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + BEGIN_RING( 33 ); + + OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) ); + for ( i = 0 ; i < 32 ; i++ ) { + OUT_RING( stipple[i] ); + } + + ADVANCE_RING(); +} + + +/* ================================================================ + * IOCTL functions + */ + +static int r128_cce_clear( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_clear_t clear; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( clear, (drm_r128_clear_t __user *) data, + sizeof(clear) ); + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + + if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; + + r128_cce_dispatch_clear( dev, &clear ); + COMMIT_RING(); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS; + + return 0; +} + +static int r128_do_init_pageflip( drm_device_t *dev ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "\n" ); + + dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET ); + dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL ); + + R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset ); + R128_WRITE( R128_CRTC_OFFSET_CNTL, + dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL ); + + dev_priv->page_flipping = 1; + dev_priv->current_page = 0; + dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page; + + return 0; +} + +int r128_do_cleanup_pageflip( drm_device_t *dev ) +{ + drm_r128_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "\n" ); + + R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset ); + R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); + + if (dev_priv->current_page != 0) { + r128_cce_dispatch_flip( dev ); + COMMIT_RING(); + } + + dev_priv->page_flipping = 0; + return 0; +} + +/* Swapping and flipping are different operations, need different ioctls. + * They can & should be intermixed to support multiple 3d windows. + */ + +static int r128_cce_flip( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + + if (!dev_priv->page_flipping) + r128_do_init_pageflip( dev ); + + r128_cce_dispatch_flip( dev ); + + COMMIT_RING(); + return 0; +} + +static int r128_cce_swap( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + + if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; + + r128_cce_dispatch_swap( dev ); + dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | + R128_UPLOAD_MASKS); + + COMMIT_RING(); + return 0; +} + +static int r128_cce_vertex( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_r128_buf_priv_t *buf_priv; + drm_r128_vertex_t vertex; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL( vertex, (drm_r128_vertex_t __user *) data, + sizeof(vertex) ); + + DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", + DRM_CURRENTPID, + vertex.idx, vertex.count, vertex.discard ); + + if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + vertex.idx, dma->buf_count - 1 ); + return DRM_ERR(EINVAL); + } + if ( vertex.prim < 0 || + vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { + DRM_ERROR( "buffer prim %d\n", vertex.prim ); + return DRM_ERR(EINVAL); + } + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + VB_AGE_TEST_WITH_RETURN( dev_priv ); + + buf = dma->buflist[vertex.idx]; + buf_priv = buf->dev_private; + + if ( buf->filp != filp ) { + DRM_ERROR( "process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp ); + return DRM_ERR(EINVAL); + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); + return DRM_ERR(EINVAL); + } + + buf->used = vertex.count; + buf_priv->prim = vertex.prim; + buf_priv->discard = vertex.discard; + + r128_cce_dispatch_vertex( dev, buf ); + + COMMIT_RING(); + return 0; +} + +static int r128_cce_indices( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_r128_buf_priv_t *buf_priv; + drm_r128_indices_t elts; + int count; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL( elts, (drm_r128_indices_t __user *) data, + sizeof(elts) ); + + DRM_DEBUG( "pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, + elts.idx, elts.start, elts.end, elts.discard ); + + if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + elts.idx, dma->buf_count - 1 ); + return DRM_ERR(EINVAL); + } + if ( elts.prim < 0 || + elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { + DRM_ERROR( "buffer prim %d\n", elts.prim ); + return DRM_ERR(EINVAL); + } + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + VB_AGE_TEST_WITH_RETURN( dev_priv ); + + buf = dma->buflist[elts.idx]; + buf_priv = buf->dev_private; + + if ( buf->filp != filp ) { + DRM_ERROR( "process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp ); + return DRM_ERR(EINVAL); + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", elts.idx ); + return DRM_ERR(EINVAL); + } + + count = (elts.end - elts.start) / sizeof(u16); + elts.start -= R128_INDEX_PRIM_OFFSET; + + if ( elts.start & 0x7 ) { + DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); + return DRM_ERR(EINVAL); + } + if ( elts.start < buf->used ) { + DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); + return DRM_ERR(EINVAL); + } + + buf->used = elts.end; + buf_priv->prim = elts.prim; + buf_priv->discard = elts.discard; + + r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count ); + + COMMIT_RING(); + return 0; +} + +static int r128_cce_blit( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_device_dma_t *dma = dev->dma; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_blit_t blit; + int ret; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( blit, (drm_r128_blit_t __user *) data, + sizeof(blit) ); + + DRM_DEBUG( "pid=%d index=%d\n", DRM_CURRENTPID, blit.idx ); + + if ( blit.idx < 0 || blit.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + blit.idx, dma->buf_count - 1 ); + return DRM_ERR(EINVAL); + } + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + VB_AGE_TEST_WITH_RETURN( dev_priv ); + + ret = r128_cce_dispatch_blit( filp, dev, &blit ); + + COMMIT_RING(); + return ret; +} + +static int r128_cce_depth( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_depth_t depth; + int ret; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( depth, (drm_r128_depth_t __user *) data, + sizeof(depth) ); + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + + ret = DRM_ERR(EINVAL); + switch ( depth.func ) { + case R128_WRITE_SPAN: + ret = r128_cce_dispatch_write_span( dev, &depth ); + case R128_WRITE_PIXELS: + ret = r128_cce_dispatch_write_pixels( dev, &depth ); + case R128_READ_SPAN: + ret = r128_cce_dispatch_read_span( dev, &depth ); + case R128_READ_PIXELS: + ret = r128_cce_dispatch_read_pixels( dev, &depth ); + } + + COMMIT_RING(); + return ret; +} + +static int r128_cce_stipple( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_stipple_t stipple; + u32 mask[32]; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( stipple, (drm_r128_stipple_t __user *) data, + sizeof(stipple) ); + + if ( DRM_COPY_FROM_USER( &mask, stipple.mask, + 32 * sizeof(u32) ) ) + return DRM_ERR( EFAULT ); + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + + r128_cce_dispatch_stipple( dev, mask ); + + COMMIT_RING(); + return 0; +} + +static int r128_cce_indirect( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_r128_buf_priv_t *buf_priv; + drm_r128_indirect_t indirect; +#if 0 + RING_LOCALS; +#endif + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL( indirect, (drm_r128_indirect_t __user *) data, + sizeof(indirect) ); + + DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", + indirect.idx, indirect.start, + indirect.end, indirect.discard ); + + if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + indirect.idx, dma->buf_count - 1 ); + return DRM_ERR(EINVAL); + } + + buf = dma->buflist[indirect.idx]; + buf_priv = buf->dev_private; + + if ( buf->filp != filp ) { + DRM_ERROR( "process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp ); + return DRM_ERR(EINVAL); + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); + return DRM_ERR(EINVAL); + } + + if ( indirect.start < buf->used ) { + DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", + indirect.start, buf->used ); + return DRM_ERR(EINVAL); + } + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + VB_AGE_TEST_WITH_RETURN( dev_priv ); + + buf->used = indirect.end; + buf_priv->discard = indirect.discard; + +#if 0 + /* Wait for the 3D stream to idle before the indirect buffer + * containing 2D acceleration commands is processed. + */ + BEGIN_RING( 2 ); + RADEON_WAIT_UNTIL_3D_IDLE(); + ADVANCE_RING(); +#endif + + /* Dispatch the indirect buffer full of commands from the + * X server. This is insecure and is thus only available to + * privileged clients. + */ + r128_cce_dispatch_indirect( dev, buf, indirect.start, indirect.end ); + + COMMIT_RING(); + return 0; +} + +static int r128_getparam( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_r128_private_t *dev_priv = dev->dev_private; + drm_r128_getparam_t param; + int value; + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL( param, (drm_r128_getparam_t __user *)data, + sizeof(param) ); + + DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); + + switch( param.param ) { + case R128_PARAM_IRQ_NR: + value = dev->irq; + break; + default: + return DRM_ERR(EINVAL); + } + + if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { + DRM_ERROR( "copy_to_user\n" ); + return DRM_ERR(EFAULT); + } + + return 0; +} + +void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp) +{ + if ( dev->dev_private ) { + drm_r128_private_t *dev_priv = dev->dev_private; + if ( dev_priv->page_flipping ) { + r128_do_cleanup_pageflip( dev ); + } + } +} + +void r128_driver_pretakedown(drm_device_t *dev) +{ + r128_do_cleanup_cce( dev ); +} + +drm_ioctl_desc_t r128_ioctls[] = { + [DRM_IOCTL_NR(DRM_R128_INIT)] = { r128_cce_init, 1, 1 }, + [DRM_IOCTL_NR(DRM_R128_CCE_START)] = { r128_cce_start, 1, 1 }, + [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = { r128_cce_stop, 1, 1 }, + [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = { r128_cce_reset, 1, 1 }, + [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = { r128_cce_idle, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_RESET)] = { r128_engine_reset, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = { r128_fullscreen, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_SWAP)] = { r128_cce_swap, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_FLIP)] = { r128_cce_flip, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_CLEAR)] = { r128_cce_clear, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_VERTEX)] = { r128_cce_vertex, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_INDICES)] = { r128_cce_indices, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_BLIT)] = { r128_cce_blit, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_DEPTH)] = { r128_cce_depth, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = { r128_cce_stipple, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = { r128_cce_indirect, 1, 1 }, + [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = { r128_getparam, 1, 0 }, +}; + +int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls); diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c new file mode 100644 index 000000000000..20bcf872b348 --- /dev/null +++ b/drivers/char/drm/radeon_cp.c @@ -0,0 +1,2061 @@ +/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Kevin E. Martin + * Gareth Hughes + */ + +#include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" +#include "radeon_drv.h" + +#define RADEON_FIFO_DEBUG 0 + +static int radeon_do_cleanup_cp( drm_device_t *dev ); + +/* CP microcode (from ATI) */ +static u32 R200_cp_microcode[][2] = { + { 0x21007000, 0000000000 }, + { 0x20007000, 0000000000 }, + { 0x000000ab, 0x00000004 }, + { 0x000000af, 0x00000004 }, + { 0x66544a49, 0000000000 }, + { 0x49494174, 0000000000 }, + { 0x54517d83, 0000000000 }, + { 0x498d8b64, 0000000000 }, + { 0x49494949, 0000000000 }, + { 0x49da493c, 0000000000 }, + { 0x49989898, 0000000000 }, + { 0xd34949d5, 0000000000 }, + { 0x9dc90e11, 0000000000 }, + { 0xce9b9b9b, 0000000000 }, + { 0x000f0000, 0x00000016 }, + { 0x352e232c, 0000000000 }, + { 0x00000013, 0x00000004 }, + { 0x000f0000, 0x00000016 }, + { 0x352e272c, 0000000000 }, + { 0x000f0001, 0x00000016 }, + { 0x3239362f, 0000000000 }, + { 0x000077ef, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x00000020, 0x0000001a }, + { 0x00004000, 0x0000001e }, + { 0x00061000, 0x00000002 }, + { 0x00000020, 0x0000001a }, + { 0x00004000, 0x0000001e }, + { 0x00061000, 0x00000002 }, + { 0x00000020, 0x0000001a }, + { 0x00004000, 0x0000001e }, + { 0x00000016, 0x00000004 }, + { 0x0003802a, 0x00000002 }, + { 0x040067e0, 0x00000002 }, + { 0x00000016, 0x00000004 }, + { 0x000077e0, 0x00000002 }, + { 0x00065000, 0x00000002 }, + { 0x000037e1, 0x00000002 }, + { 0x040067e1, 0x00000006 }, + { 0x000077e0, 0x00000002 }, + { 0x000077e1, 0x00000002 }, + { 0x000077e1, 0x00000006 }, + { 0xffffffff, 0000000000 }, + { 0x10000000, 0000000000 }, + { 0x0003802a, 0x00000002 }, + { 0x040067e0, 0x00000006 }, + { 0x00007675, 0x00000002 }, + { 0x00007676, 0x00000002 }, + { 0x00007677, 0x00000002 }, + { 0x00007678, 0x00000006 }, + { 0x0003802b, 0x00000002 }, + { 0x04002676, 0x00000002 }, + { 0x00007677, 0x00000002 }, + { 0x00007678, 0x00000006 }, + { 0x0000002e, 0x00000018 }, + { 0x0000002e, 0x00000018 }, + { 0000000000, 0x00000006 }, + { 0x0000002f, 0x00000018 }, + { 0x0000002f, 0x00000018 }, + { 0000000000, 0x00000006 }, + { 0x01605000, 0x00000002 }, + { 0x00065000, 0x00000002 }, + { 0x00098000, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x64c0603d, 0x00000004 }, + { 0x00080000, 0x00000016 }, + { 0000000000, 0000000000 }, + { 0x0400251d, 0x00000002 }, + { 0x00007580, 0x00000002 }, + { 0x00067581, 0x00000002 }, + { 0x04002580, 0x00000002 }, + { 0x00067581, 0x00000002 }, + { 0x00000046, 0x00000004 }, + { 0x00005000, 0000000000 }, + { 0x00061000, 0x00000002 }, + { 0x0000750e, 0x00000002 }, + { 0x00019000, 0x00000002 }, + { 0x00011055, 0x00000014 }, + { 0x00000055, 0x00000012 }, + { 0x0400250f, 0x00000002 }, + { 0x0000504a, 0x00000004 }, + { 0x00007565, 0x00000002 }, + { 0x00007566, 0x00000002 }, + { 0x00000051, 0x00000004 }, + { 0x01e655b4, 0x00000002 }, + { 0x4401b0dc, 0x00000002 }, + { 0x01c110dc, 0x00000002 }, + { 0x2666705d, 0x00000018 }, + { 0x040c2565, 0x00000002 }, + { 0x0000005d, 0x00000018 }, + { 0x04002564, 0x00000002 }, + { 0x00007566, 0x00000002 }, + { 0x00000054, 0x00000004 }, + { 0x00401060, 0x00000008 }, + { 0x00101000, 0x00000002 }, + { 0x000d80ff, 0x00000002 }, + { 0x00800063, 0x00000008 }, + { 0x000f9000, 0x00000002 }, + { 0x000e00ff, 0x00000002 }, + { 0000000000, 0x00000006 }, + { 0x00000080, 0x00000018 }, + { 0x00000054, 0x00000004 }, + { 0x00007576, 0x00000002 }, + { 0x00065000, 0x00000002 }, + { 0x00009000, 0x00000002 }, + { 0x00041000, 0x00000002 }, + { 0x0c00350e, 0x00000002 }, + { 0x00049000, 0x00000002 }, + { 0x00051000, 0x00000002 }, + { 0x01e785f8, 0x00000002 }, + { 0x00200000, 0x00000002 }, + { 0x00600073, 0x0000000c }, + { 0x00007563, 0x00000002 }, + { 0x006075f0, 0x00000021 }, + { 0x20007068, 0x00000004 }, + { 0x00005068, 0x00000004 }, + { 0x00007576, 0x00000002 }, + { 0x00007577, 0x00000002 }, + { 0x0000750e, 0x00000002 }, + { 0x0000750f, 0x00000002 }, + { 0x00a05000, 0x00000002 }, + { 0x00600076, 0x0000000c }, + { 0x006075f0, 0x00000021 }, + { 0x000075f8, 0x00000002 }, + { 0x00000076, 0x00000004 }, + { 0x000a750e, 0x00000002 }, + { 0x0020750f, 0x00000002 }, + { 0x00600079, 0x00000004 }, + { 0x00007570, 0x00000002 }, + { 0x00007571, 0x00000002 }, + { 0x00007572, 0x00000006 }, + { 0x00005000, 0x00000002 }, + { 0x00a05000, 0x00000002 }, + { 0x00007568, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x00000084, 0x0000000c }, + { 0x00058000, 0x00000002 }, + { 0x0c607562, 0x00000002 }, + { 0x00000086, 0x00000004 }, + { 0x00600085, 0x00000004 }, + { 0x400070dd, 0000000000 }, + { 0x000380dd, 0x00000002 }, + { 0x00000093, 0x0000001c }, + { 0x00065095, 0x00000018 }, + { 0x040025bb, 0x00000002 }, + { 0x00061096, 0x00000018 }, + { 0x040075bc, 0000000000 }, + { 0x000075bb, 0x00000002 }, + { 0x000075bc, 0000000000 }, + { 0x00090000, 0x00000006 }, + { 0x00090000, 0x00000002 }, + { 0x000d8002, 0x00000006 }, + { 0x00005000, 0x00000002 }, + { 0x00007821, 0x00000002 }, + { 0x00007800, 0000000000 }, + { 0x00007821, 0x00000002 }, + { 0x00007800, 0000000000 }, + { 0x01665000, 0x00000002 }, + { 0x000a0000, 0x00000002 }, + { 0x000671cc, 0x00000002 }, + { 0x0286f1cd, 0x00000002 }, + { 0x000000a3, 0x00000010 }, + { 0x21007000, 0000000000 }, + { 0x000000aa, 0x0000001c }, + { 0x00065000, 0x00000002 }, + { 0x000a0000, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x000b0000, 0x00000002 }, + { 0x38067000, 0x00000002 }, + { 0x000a00a6, 0x00000004 }, + { 0x20007000, 0000000000 }, + { 0x01200000, 0x00000002 }, + { 0x20077000, 0x00000002 }, + { 0x01200000, 0x00000002 }, + { 0x20007000, 0000000000 }, + { 0x00061000, 0x00000002 }, + { 0x0120751b, 0x00000002 }, + { 0x8040750a, 0x00000002 }, + { 0x8040750b, 0x00000002 }, + { 0x00110000, 0x00000002 }, + { 0x000380dd, 0x00000002 }, + { 0x000000bd, 0x0000001c }, + { 0x00061096, 0x00000018 }, + { 0x844075bd, 0x00000002 }, + { 0x00061095, 0x00000018 }, + { 0x840075bb, 0x00000002 }, + { 0x00061096, 0x00000018 }, + { 0x844075bc, 0x00000002 }, + { 0x000000c0, 0x00000004 }, + { 0x804075bd, 0x00000002 }, + { 0x800075bb, 0x00000002 }, + { 0x804075bc, 0x00000002 }, + { 0x00108000, 0x00000002 }, + { 0x01400000, 0x00000002 }, + { 0x006000c4, 0x0000000c }, + { 0x20c07000, 0x00000020 }, + { 0x000000c6, 0x00000012 }, + { 0x00800000, 0x00000006 }, + { 0x0080751d, 0x00000006 }, + { 0x000025bb, 0x00000002 }, + { 0x000040c0, 0x00000004 }, + { 0x0000775c, 0x00000002 }, + { 0x00a05000, 0x00000002 }, + { 0x00661000, 0x00000002 }, + { 0x0460275d, 0x00000020 }, + { 0x00004000, 0000000000 }, + { 0x00007999, 0x00000002 }, + { 0x00a05000, 0x00000002 }, + { 0x00661000, 0x00000002 }, + { 0x0460299b, 0x00000020 }, + { 0x00004000, 0000000000 }, + { 0x01e00830, 0x00000002 }, + { 0x21007000, 0000000000 }, + { 0x00005000, 0x00000002 }, + { 0x00038042, 0x00000002 }, + { 0x040025e0, 0x00000002 }, + { 0x000075e1, 0000000000 }, + { 0x00000001, 0000000000 }, + { 0x000380d9, 0x00000002 }, + { 0x04007394, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, +}; + + +static u32 radeon_cp_microcode[][2] = { + { 0x21007000, 0000000000 }, + { 0x20007000, 0000000000 }, + { 0x000000b4, 0x00000004 }, + { 0x000000b8, 0x00000004 }, + { 0x6f5b4d4c, 0000000000 }, + { 0x4c4c427f, 0000000000 }, + { 0x5b568a92, 0000000000 }, + { 0x4ca09c6d, 0000000000 }, + { 0xad4c4c4c, 0000000000 }, + { 0x4ce1af3d, 0000000000 }, + { 0xd8afafaf, 0000000000 }, + { 0xd64c4cdc, 0000000000 }, + { 0x4cd10d10, 0000000000 }, + { 0x000f0000, 0x00000016 }, + { 0x362f242d, 0000000000 }, + { 0x00000012, 0x00000004 }, + { 0x000f0000, 0x00000016 }, + { 0x362f282d, 0000000000 }, + { 0x000380e7, 0x00000002 }, + { 0x04002c97, 0x00000002 }, + { 0x000f0001, 0x00000016 }, + { 0x333a3730, 0000000000 }, + { 0x000077ef, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x00000021, 0x0000001a }, + { 0x00004000, 0x0000001e }, + { 0x00061000, 0x00000002 }, + { 0x00000021, 0x0000001a }, + { 0x00004000, 0x0000001e }, + { 0x00061000, 0x00000002 }, + { 0x00000021, 0x0000001a }, + { 0x00004000, 0x0000001e }, + { 0x00000017, 0x00000004 }, + { 0x0003802b, 0x00000002 }, + { 0x040067e0, 0x00000002 }, + { 0x00000017, 0x00000004 }, + { 0x000077e0, 0x00000002 }, + { 0x00065000, 0x00000002 }, + { 0x000037e1, 0x00000002 }, + { 0x040067e1, 0x00000006 }, + { 0x000077e0, 0x00000002 }, + { 0x000077e1, 0x00000002 }, + { 0x000077e1, 0x00000006 }, + { 0xffffffff, 0000000000 }, + { 0x10000000, 0000000000 }, + { 0x0003802b, 0x00000002 }, + { 0x040067e0, 0x00000006 }, + { 0x00007675, 0x00000002 }, + { 0x00007676, 0x00000002 }, + { 0x00007677, 0x00000002 }, + { 0x00007678, 0x00000006 }, + { 0x0003802c, 0x00000002 }, + { 0x04002676, 0x00000002 }, + { 0x00007677, 0x00000002 }, + { 0x00007678, 0x00000006 }, + { 0x0000002f, 0x00000018 }, + { 0x0000002f, 0x00000018 }, + { 0000000000, 0x00000006 }, + { 0x00000030, 0x00000018 }, + { 0x00000030, 0x00000018 }, + { 0000000000, 0x00000006 }, + { 0x01605000, 0x00000002 }, + { 0x00065000, 0x00000002 }, + { 0x00098000, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x64c0603e, 0x00000004 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00080000, 0x00000016 }, + { 0000000000, 0000000000 }, + { 0x0400251d, 0x00000002 }, + { 0x00007580, 0x00000002 }, + { 0x00067581, 0x00000002 }, + { 0x04002580, 0x00000002 }, + { 0x00067581, 0x00000002 }, + { 0x00000049, 0x00000004 }, + { 0x00005000, 0000000000 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x0000750e, 0x00000002 }, + { 0x00019000, 0x00000002 }, + { 0x00011055, 0x00000014 }, + { 0x00000055, 0x00000012 }, + { 0x0400250f, 0x00000002 }, + { 0x0000504f, 0x00000004 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00007565, 0x00000002 }, + { 0x00007566, 0x00000002 }, + { 0x00000058, 0x00000004 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x01e655b4, 0x00000002 }, + { 0x4401b0e4, 0x00000002 }, + { 0x01c110e4, 0x00000002 }, + { 0x26667066, 0x00000018 }, + { 0x040c2565, 0x00000002 }, + { 0x00000066, 0x00000018 }, + { 0x04002564, 0x00000002 }, + { 0x00007566, 0x00000002 }, + { 0x0000005d, 0x00000004 }, + { 0x00401069, 0x00000008 }, + { 0x00101000, 0x00000002 }, + { 0x000d80ff, 0x00000002 }, + { 0x0080006c, 0x00000008 }, + { 0x000f9000, 0x00000002 }, + { 0x000e00ff, 0x00000002 }, + { 0000000000, 0x00000006 }, + { 0x0000008f, 0x00000018 }, + { 0x0000005b, 0x00000004 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00007576, 0x00000002 }, + { 0x00065000, 0x00000002 }, + { 0x00009000, 0x00000002 }, + { 0x00041000, 0x00000002 }, + { 0x0c00350e, 0x00000002 }, + { 0x00049000, 0x00000002 }, + { 0x00051000, 0x00000002 }, + { 0x01e785f8, 0x00000002 }, + { 0x00200000, 0x00000002 }, + { 0x0060007e, 0x0000000c }, + { 0x00007563, 0x00000002 }, + { 0x006075f0, 0x00000021 }, + { 0x20007073, 0x00000004 }, + { 0x00005073, 0x00000004 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00007576, 0x00000002 }, + { 0x00007577, 0x00000002 }, + { 0x0000750e, 0x00000002 }, + { 0x0000750f, 0x00000002 }, + { 0x00a05000, 0x00000002 }, + { 0x00600083, 0x0000000c }, + { 0x006075f0, 0x00000021 }, + { 0x000075f8, 0x00000002 }, + { 0x00000083, 0x00000004 }, + { 0x000a750e, 0x00000002 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x0020750f, 0x00000002 }, + { 0x00600086, 0x00000004 }, + { 0x00007570, 0x00000002 }, + { 0x00007571, 0x00000002 }, + { 0x00007572, 0x00000006 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00005000, 0x00000002 }, + { 0x00a05000, 0x00000002 }, + { 0x00007568, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x00000095, 0x0000000c }, + { 0x00058000, 0x00000002 }, + { 0x0c607562, 0x00000002 }, + { 0x00000097, 0x00000004 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x00600096, 0x00000004 }, + { 0x400070e5, 0000000000 }, + { 0x000380e6, 0x00000002 }, + { 0x040025c5, 0x00000002 }, + { 0x000380e5, 0x00000002 }, + { 0x000000a8, 0x0000001c }, + { 0x000650aa, 0x00000018 }, + { 0x040025bb, 0x00000002 }, + { 0x000610ab, 0x00000018 }, + { 0x040075bc, 0000000000 }, + { 0x000075bb, 0x00000002 }, + { 0x000075bc, 0000000000 }, + { 0x00090000, 0x00000006 }, + { 0x00090000, 0x00000002 }, + { 0x000d8002, 0x00000006 }, + { 0x00007832, 0x00000002 }, + { 0x00005000, 0x00000002 }, + { 0x000380e7, 0x00000002 }, + { 0x04002c97, 0x00000002 }, + { 0x00007820, 0x00000002 }, + { 0x00007821, 0x00000002 }, + { 0x00007800, 0000000000 }, + { 0x01200000, 0x00000002 }, + { 0x20077000, 0x00000002 }, + { 0x01200000, 0x00000002 }, + { 0x20007000, 0x00000002 }, + { 0x00061000, 0x00000002 }, + { 0x0120751b, 0x00000002 }, + { 0x8040750a, 0x00000002 }, + { 0x8040750b, 0x00000002 }, + { 0x00110000, 0x00000002 }, + { 0x000380e5, 0x00000002 }, + { 0x000000c6, 0x0000001c }, + { 0x000610ab, 0x00000018 }, + { 0x844075bd, 0x00000002 }, + { 0x000610aa, 0x00000018 }, + { 0x840075bb, 0x00000002 }, + { 0x000610ab, 0x00000018 }, + { 0x844075bc, 0x00000002 }, + { 0x000000c9, 0x00000004 }, + { 0x804075bd, 0x00000002 }, + { 0x800075bb, 0x00000002 }, + { 0x804075bc, 0x00000002 }, + { 0x00108000, 0x00000002 }, + { 0x01400000, 0x00000002 }, + { 0x006000cd, 0x0000000c }, + { 0x20c07000, 0x00000020 }, + { 0x000000cf, 0x00000012 }, + { 0x00800000, 0x00000006 }, + { 0x0080751d, 0x00000006 }, + { 0000000000, 0000000000 }, + { 0x0000775c, 0x00000002 }, + { 0x00a05000, 0x00000002 }, + { 0x00661000, 0x00000002 }, + { 0x0460275d, 0x00000020 }, + { 0x00004000, 0000000000 }, + { 0x01e00830, 0x00000002 }, + { 0x21007000, 0000000000 }, + { 0x6464614d, 0000000000 }, + { 0x69687420, 0000000000 }, + { 0x00000073, 0000000000 }, + { 0000000000, 0000000000 }, + { 0x00005000, 0x00000002 }, + { 0x000380d0, 0x00000002 }, + { 0x040025e0, 0x00000002 }, + { 0x000075e1, 0000000000 }, + { 0x00000001, 0000000000 }, + { 0x000380e0, 0x00000002 }, + { 0x04002394, 0x00000002 }, + { 0x00005000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0x00000008, 0000000000 }, + { 0x00000004, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, +}; + +static u32 R300_cp_microcode[][2] = { + { 0x4200e000, 0000000000 }, + { 0x4000e000, 0000000000 }, + { 0x000000af, 0x00000008 }, + { 0x000000b3, 0x00000008 }, + { 0x6c5a504f, 0000000000 }, + { 0x4f4f497a, 0000000000 }, + { 0x5a578288, 0000000000 }, + { 0x4f91906a, 0000000000 }, + { 0x4f4f4f4f, 0000000000 }, + { 0x4fe24f44, 0000000000 }, + { 0x4f9c9c9c, 0000000000 }, + { 0xdc4f4fde, 0000000000 }, + { 0xa1cd4f4f, 0000000000 }, + { 0xd29d9d9d, 0000000000 }, + { 0x4f0f9fd7, 0000000000 }, + { 0x000ca000, 0x00000004 }, + { 0x000d0012, 0x00000038 }, + { 0x0000e8b4, 0x00000004 }, + { 0x000d0014, 0x00000038 }, + { 0x0000e8b6, 0x00000004 }, + { 0x000d0016, 0x00000038 }, + { 0x0000e854, 0x00000004 }, + { 0x000d0018, 0x00000038 }, + { 0x0000e855, 0x00000004 }, + { 0x000d001a, 0x00000038 }, + { 0x0000e856, 0x00000004 }, + { 0x000d001c, 0x00000038 }, + { 0x0000e857, 0x00000004 }, + { 0x000d001e, 0x00000038 }, + { 0x0000e824, 0x00000004 }, + { 0x000d0020, 0x00000038 }, + { 0x0000e825, 0x00000004 }, + { 0x000d0022, 0x00000038 }, + { 0x0000e830, 0x00000004 }, + { 0x000d0024, 0x00000038 }, + { 0x0000f0c0, 0x00000004 }, + { 0x000d0026, 0x00000038 }, + { 0x0000f0c1, 0x00000004 }, + { 0x000d0028, 0x00000038 }, + { 0x0000f041, 0x00000004 }, + { 0x000d002a, 0x00000038 }, + { 0x0000f184, 0x00000004 }, + { 0x000d002c, 0x00000038 }, + { 0x0000f185, 0x00000004 }, + { 0x000d002e, 0x00000038 }, + { 0x0000f186, 0x00000004 }, + { 0x000d0030, 0x00000038 }, + { 0x0000f187, 0x00000004 }, + { 0x000d0032, 0x00000038 }, + { 0x0000f180, 0x00000004 }, + { 0x000d0034, 0x00000038 }, + { 0x0000f393, 0x00000004 }, + { 0x000d0036, 0x00000038 }, + { 0x0000f38a, 0x00000004 }, + { 0x000d0038, 0x00000038 }, + { 0x0000f38e, 0x00000004 }, + { 0x0000e821, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00000043, 0x00000018 }, + { 0x00cce800, 0x00000004 }, + { 0x001b0001, 0x00000004 }, + { 0x08004800, 0x00000004 }, + { 0x001b0001, 0x00000004 }, + { 0x08004800, 0x00000004 }, + { 0x001b0001, 0x00000004 }, + { 0x08004800, 0x00000004 }, + { 0x0000003a, 0x00000008 }, + { 0x0000a000, 0000000000 }, + { 0x02c0a000, 0x00000004 }, + { 0x000ca000, 0x00000004 }, + { 0x00130000, 0x00000004 }, + { 0x000c2000, 0x00000004 }, + { 0xc980c045, 0x00000008 }, + { 0x2000451d, 0x00000004 }, + { 0x0000e580, 0x00000004 }, + { 0x000ce581, 0x00000004 }, + { 0x08004580, 0x00000004 }, + { 0x000ce581, 0x00000004 }, + { 0x0000004c, 0x00000008 }, + { 0x0000a000, 0000000000 }, + { 0x000c2000, 0x00000004 }, + { 0x0000e50e, 0x00000004 }, + { 0x00032000, 0x00000004 }, + { 0x00022056, 0x00000028 }, + { 0x00000056, 0x00000024 }, + { 0x0800450f, 0x00000004 }, + { 0x0000a050, 0x00000008 }, + { 0x0000e565, 0x00000004 }, + { 0x0000e566, 0x00000004 }, + { 0x00000057, 0x00000008 }, + { 0x03cca5b4, 0x00000004 }, + { 0x05432000, 0x00000004 }, + { 0x00022000, 0x00000004 }, + { 0x4ccce063, 0x00000030 }, + { 0x08274565, 0x00000004 }, + { 0x00000063, 0x00000030 }, + { 0x08004564, 0x00000004 }, + { 0x0000e566, 0x00000004 }, + { 0x0000005a, 0x00000008 }, + { 0x00802066, 0x00000010 }, + { 0x00202000, 0x00000004 }, + { 0x001b00ff, 0x00000004 }, + { 0x01000069, 0x00000010 }, + { 0x001f2000, 0x00000004 }, + { 0x001c00ff, 0x00000004 }, + { 0000000000, 0x0000000c }, + { 0x00000085, 0x00000030 }, + { 0x0000005a, 0x00000008 }, + { 0x0000e576, 0x00000004 }, + { 0x000ca000, 0x00000004 }, + { 0x00012000, 0x00000004 }, + { 0x00082000, 0x00000004 }, + { 0x1800650e, 0x00000004 }, + { 0x00092000, 0x00000004 }, + { 0x000a2000, 0x00000004 }, + { 0x000f0000, 0x00000004 }, + { 0x00400000, 0x00000004 }, + { 0x00000079, 0x00000018 }, + { 0x0000e563, 0x00000004 }, + { 0x00c0e5f9, 0x000000c2 }, + { 0x0000006e, 0x00000008 }, + { 0x0000a06e, 0x00000008 }, + { 0x0000e576, 0x00000004 }, + { 0x0000e577, 0x00000004 }, + { 0x0000e50e, 0x00000004 }, + { 0x0000e50f, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x0000007c, 0x00000018 }, + { 0x00c0e5f9, 0x000000c2 }, + { 0x0000007c, 0x00000008 }, + { 0x0014e50e, 0x00000004 }, + { 0x0040e50f, 0x00000004 }, + { 0x00c0007f, 0x00000008 }, + { 0x0000e570, 0x00000004 }, + { 0x0000e571, 0x00000004 }, + { 0x0000e572, 0x0000000c }, + { 0x0000a000, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x0000e568, 0x00000004 }, + { 0x000c2000, 0x00000004 }, + { 0x00000089, 0x00000018 }, + { 0x000b0000, 0x00000004 }, + { 0x18c0e562, 0x00000004 }, + { 0x0000008b, 0x00000008 }, + { 0x00c0008a, 0x00000008 }, + { 0x000700e4, 0x00000004 }, + { 0x00000097, 0x00000038 }, + { 0x000ca099, 0x00000030 }, + { 0x080045bb, 0x00000004 }, + { 0x000c209a, 0x00000030 }, + { 0x0800e5bc, 0000000000 }, + { 0x0000e5bb, 0x00000004 }, + { 0x0000e5bc, 0000000000 }, + { 0x00120000, 0x0000000c }, + { 0x00120000, 0x00000004 }, + { 0x001b0002, 0x0000000c }, + { 0x0000a000, 0x00000004 }, + { 0x0000e821, 0x00000004 }, + { 0x0000e800, 0000000000 }, + { 0x0000e821, 0x00000004 }, + { 0x0000e82e, 0000000000 }, + { 0x02cca000, 0x00000004 }, + { 0x00140000, 0x00000004 }, + { 0x000ce1cc, 0x00000004 }, + { 0x050de1cd, 0x00000004 }, + { 0x000000a7, 0x00000020 }, + { 0x4200e000, 0000000000 }, + { 0x000000ae, 0x00000038 }, + { 0x000ca000, 0x00000004 }, + { 0x00140000, 0x00000004 }, + { 0x000c2000, 0x00000004 }, + { 0x00160000, 0x00000004 }, + { 0x700ce000, 0x00000004 }, + { 0x001400aa, 0x00000008 }, + { 0x4000e000, 0000000000 }, + { 0x02400000, 0x00000004 }, + { 0x400ee000, 0x00000004 }, + { 0x02400000, 0x00000004 }, + { 0x4000e000, 0000000000 }, + { 0x000c2000, 0x00000004 }, + { 0x0240e51b, 0x00000004 }, + { 0x0080e50a, 0x00000005 }, + { 0x0080e50b, 0x00000005 }, + { 0x00220000, 0x00000004 }, + { 0x000700e4, 0x00000004 }, + { 0x000000c1, 0x00000038 }, + { 0x000c209a, 0x00000030 }, + { 0x0880e5bd, 0x00000005 }, + { 0x000c2099, 0x00000030 }, + { 0x0800e5bb, 0x00000005 }, + { 0x000c209a, 0x00000030 }, + { 0x0880e5bc, 0x00000005 }, + { 0x000000c4, 0x00000008 }, + { 0x0080e5bd, 0x00000005 }, + { 0x0000e5bb, 0x00000005 }, + { 0x0080e5bc, 0x00000005 }, + { 0x00210000, 0x00000004 }, + { 0x02800000, 0x00000004 }, + { 0x00c000c8, 0x00000018 }, + { 0x4180e000, 0x00000040 }, + { 0x000000ca, 0x00000024 }, + { 0x01000000, 0x0000000c }, + { 0x0100e51d, 0x0000000c }, + { 0x000045bb, 0x00000004 }, + { 0x000080c4, 0x00000008 }, + { 0x0000f3ce, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00cc2000, 0x00000004 }, + { 0x08c053cf, 0x00000040 }, + { 0x00008000, 0000000000 }, + { 0x0000f3d2, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00cc2000, 0x00000004 }, + { 0x08c053d3, 0x00000040 }, + { 0x00008000, 0000000000 }, + { 0x0000f39d, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00cc2000, 0x00000004 }, + { 0x08c0539e, 0x00000040 }, + { 0x00008000, 0000000000 }, + { 0x03c00830, 0x00000004 }, + { 0x4200e000, 0000000000 }, + { 0x0000a000, 0x00000004 }, + { 0x200045e0, 0x00000004 }, + { 0x0000e5e1, 0000000000 }, + { 0x00000001, 0000000000 }, + { 0x000700e1, 0x00000004 }, + { 0x0800e394, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, +}; + +static int RADEON_READ_PLL(drm_device_t *dev, int addr) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + + RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); + return RADEON_READ(RADEON_CLOCK_CNTL_DATA); +} + +#if RADEON_FIFO_DEBUG +static void radeon_status( drm_radeon_private_t *dev_priv ) +{ + printk( "%s:\n", __FUNCTION__ ); + printk( "RBBM_STATUS = 0x%08x\n", + (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) ); + printk( "CP_RB_RTPR = 0x%08x\n", + (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) ); + printk( "CP_RB_WTPR = 0x%08x\n", + (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) ); + printk( "AIC_CNTL = 0x%08x\n", + (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) ); + printk( "AIC_STAT = 0x%08x\n", + (unsigned int)RADEON_READ( RADEON_AIC_STAT ) ); + printk( "AIC_PT_BASE = 0x%08x\n", + (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) ); + printk( "TLB_ADDR = 0x%08x\n", + (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) ); + printk( "TLB_DATA = 0x%08x\n", + (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) ); +} +#endif + + +/* ================================================================ + * Engine, FIFO control + */ + +static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv ) +{ + u32 tmp; + int i; + + dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; + + tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ); + tmp |= RADEON_RB2D_DC_FLUSH_ALL; + RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp ); + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ) + & RADEON_RB2D_DC_BUSY) ) { + return 0; + } + DRM_UDELAY( 1 ); + } + +#if RADEON_FIFO_DEBUG + DRM_ERROR( "failed!\n" ); + radeon_status( dev_priv ); +#endif + return DRM_ERR(EBUSY); +} + +static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv, + int entries ) +{ + int i; + + dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + int slots = ( RADEON_READ( RADEON_RBBM_STATUS ) + & RADEON_RBBM_FIFOCNT_MASK ); + if ( slots >= entries ) return 0; + DRM_UDELAY( 1 ); + } + +#if RADEON_FIFO_DEBUG + DRM_ERROR( "failed!\n" ); + radeon_status( dev_priv ); +#endif + return DRM_ERR(EBUSY); +} + +static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv ) +{ + int i, ret; + + dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; + + ret = radeon_do_wait_for_fifo( dev_priv, 64 ); + if ( ret ) return ret; + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + if ( !(RADEON_READ( RADEON_RBBM_STATUS ) + & RADEON_RBBM_ACTIVE) ) { + radeon_do_pixcache_flush( dev_priv ); + return 0; + } + DRM_UDELAY( 1 ); + } + +#if RADEON_FIFO_DEBUG + DRM_ERROR( "failed!\n" ); + radeon_status( dev_priv ); +#endif + return DRM_ERR(EBUSY); +} + + +/* ================================================================ + * CP control, initialization + */ + +/* Load the microcode for the CP */ +static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv ) +{ + int i; + DRM_DEBUG( "\n" ); + + radeon_do_wait_for_idle( dev_priv ); + + RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 ); + + if (dev_priv->microcode_version==UCODE_R200) { + DRM_INFO("Loading R200 Microcode\n"); + for ( i = 0 ; i < 256 ; i++ ) + { + RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, + R200_cp_microcode[i][1] ); + RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, + R200_cp_microcode[i][0] ); + } + } else if (dev_priv->microcode_version==UCODE_R300) { + DRM_INFO("Loading R300 Microcode\n"); + for ( i = 0 ; i < 256 ; i++ ) + { + RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, + R300_cp_microcode[i][1] ); + RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, + R300_cp_microcode[i][0] ); + } + } else { + for ( i = 0 ; i < 256 ; i++ ) { + RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, + radeon_cp_microcode[i][1] ); + RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, + radeon_cp_microcode[i][0] ); + } + } +} + +/* Flush any pending commands to the CP. This should only be used just + * prior to a wait for idle, as it informs the engine that the command + * stream is ending. + */ +static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv ) +{ + DRM_DEBUG( "\n" ); +#if 0 + u32 tmp; + + tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31); + RADEON_WRITE( RADEON_CP_RB_WPTR, tmp ); +#endif +} + +/* Wait for the CP to go idle. + */ +int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ) +{ + RING_LOCALS; + DRM_DEBUG( "\n" ); + + BEGIN_RING( 6 ); + + RADEON_PURGE_CACHE(); + RADEON_PURGE_ZCACHE(); + RADEON_WAIT_UNTIL_IDLE(); + + ADVANCE_RING(); + COMMIT_RING(); + + return radeon_do_wait_for_idle( dev_priv ); +} + +/* Start the Command Processor. + */ +static void radeon_do_cp_start( drm_radeon_private_t *dev_priv ) +{ + RING_LOCALS; + DRM_DEBUG( "\n" ); + + radeon_do_wait_for_idle( dev_priv ); + + RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode ); + + dev_priv->cp_running = 1; + + BEGIN_RING( 6 ); + + RADEON_PURGE_CACHE(); + RADEON_PURGE_ZCACHE(); + RADEON_WAIT_UNTIL_IDLE(); + + ADVANCE_RING(); + COMMIT_RING(); +} + +/* Reset the Command Processor. This will not flush any pending + * commands, so you must wait for the CP command stream to complete + * before calling this routine. + */ +static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv ) +{ + u32 cur_read_ptr; + DRM_DEBUG( "\n" ); + + cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); + RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); + SET_RING_HEAD( dev_priv, cur_read_ptr ); + dev_priv->ring.tail = cur_read_ptr; +} + +/* Stop the Command Processor. This will not flush any pending + * commands, so you must flush the command stream and wait for the CP + * to go idle before calling this routine. + */ +static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv ) +{ + DRM_DEBUG( "\n" ); + + RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS ); + + dev_priv->cp_running = 0; +} + +/* Reset the engine. This will stop the CP if it is running. + */ +static int radeon_do_engine_reset( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; + DRM_DEBUG( "\n" ); + + radeon_do_pixcache_flush( dev_priv ); + + clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX ); + mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL ); + + RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl | + RADEON_FORCEON_MCLKA | + RADEON_FORCEON_MCLKB | + RADEON_FORCEON_YCLKA | + RADEON_FORCEON_YCLKB | + RADEON_FORCEON_MC | + RADEON_FORCEON_AIC ) ); + + rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET ); + + RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset | + RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | + RADEON_SOFT_RESET_PP | + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB ) ); + RADEON_READ( RADEON_RBBM_SOFT_RESET ); + RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset & + ~( RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | + RADEON_SOFT_RESET_PP | + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB ) ) ); + RADEON_READ( RADEON_RBBM_SOFT_RESET ); + + + RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl ); + RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index ); + RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset ); + + /* Reset the CP ring */ + radeon_do_cp_reset( dev_priv ); + + /* The CP is no longer running after an engine reset */ + dev_priv->cp_running = 0; + + /* Reset any pending vertex, indirect buffers */ + radeon_freelist_reset( dev ); + + return 0; +} + +static void radeon_cp_init_ring_buffer( drm_device_t *dev, + drm_radeon_private_t *dev_priv ) +{ + u32 ring_start, cur_read_ptr; + u32 tmp; + + /* Initialize the memory controller */ + RADEON_WRITE( RADEON_MC_FB_LOCATION, + ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 ) + | ( dev_priv->fb_location >> 16 ) ); + +#if __OS_HAS_AGP + if ( !dev_priv->is_pci ) { + RADEON_WRITE( RADEON_MC_AGP_LOCATION, + (((dev_priv->gart_vm_start - 1 + + dev_priv->gart_size) & 0xffff0000) | + (dev_priv->gart_vm_start >> 16)) ); + + ring_start = (dev_priv->cp_ring->offset + - dev->agp->base + + dev_priv->gart_vm_start); + } else +#endif + ring_start = (dev_priv->cp_ring->offset + - dev->sg->handle + + dev_priv->gart_vm_start); + + RADEON_WRITE( RADEON_CP_RB_BASE, ring_start ); + + /* Set the write pointer delay */ + RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 ); + + /* Initialize the ring buffer's read and write pointers */ + cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); + RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); + SET_RING_HEAD( dev_priv, cur_read_ptr ); + dev_priv->ring.tail = cur_read_ptr; + +#if __OS_HAS_AGP + if ( !dev_priv->is_pci ) { + RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, + dev_priv->ring_rptr->offset + - dev->agp->base + + dev_priv->gart_vm_start); + } else +#endif + { + drm_sg_mem_t *entry = dev->sg; + unsigned long tmp_ofs, page_ofs; + + tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; + page_ofs = tmp_ofs >> PAGE_SHIFT; + + RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, + entry->busaddr[page_ofs]); + DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", + (unsigned long) entry->busaddr[page_ofs], + entry->handle + tmp_ofs ); + } + + /* Initialize the scratch register pointer. This will cause + * the scratch register values to be written out to memory + * whenever they are updated. + * + * We simply put this behind the ring read pointer, this works + * with PCI GART as well as (whatever kind of) AGP GART + */ + RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR ) + + RADEON_SCRATCH_REG_OFFSET ); + + dev_priv->scratch = ((__volatile__ u32 *) + dev_priv->ring_rptr->handle + + (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); + + RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); + + /* Writeback doesn't seem to work everywhere, test it first */ + DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 ); + RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef ); + + for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) { + if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef ) + break; + DRM_UDELAY( 1 ); + } + + if ( tmp < dev_priv->usec_timeout ) { + dev_priv->writeback_works = 1; + DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp ); + } else { + dev_priv->writeback_works = 0; + DRM_DEBUG( "writeback test failed\n" ); + } + + dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; + RADEON_WRITE( RADEON_LAST_FRAME_REG, + dev_priv->sarea_priv->last_frame ); + + dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; + RADEON_WRITE( RADEON_LAST_DISPATCH_REG, + dev_priv->sarea_priv->last_dispatch ); + + dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; + RADEON_WRITE( RADEON_LAST_CLEAR_REG, + dev_priv->sarea_priv->last_clear ); + + /* Set ring buffer size */ +#ifdef __BIG_ENDIAN + RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT ); +#else + RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw ); +#endif + + radeon_do_wait_for_idle( dev_priv ); + + /* Turn on bus mastering */ + tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS; + RADEON_WRITE( RADEON_BUS_CNTL, tmp ); + + /* Sync everything up */ + RADEON_WRITE( RADEON_ISYNC_CNTL, + (RADEON_ISYNC_ANY2D_IDLE3D | + RADEON_ISYNC_ANY3D_IDLE2D | + RADEON_ISYNC_WAIT_IDLEGUI | + RADEON_ISYNC_CPSCRATCH_IDLEGUI) ); +} + +/* Enable or disable PCI GART on the chip */ +static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on ) +{ + u32 tmp = RADEON_READ( RADEON_AIC_CNTL ); + + if ( on ) { + RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN ); + + /* set PCI GART page-table base address + */ + RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart ); + + /* set address range for PCI address translate + */ + RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start ); + RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start + + dev_priv->gart_size - 1); + + /* Turn off AGP aperture -- is this required for PCI GART? + */ + RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ + RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */ + } else { + RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN ); + } +} + +static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private;; + DRM_DEBUG( "\n" ); + + dev_priv->is_pci = init->is_pci; + + if ( dev_priv->is_pci && !dev->sg ) { + DRM_ERROR( "PCI GART memory not allocated!\n" ); + dev->dev_private = (void *)dev_priv; + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + dev_priv->usec_timeout = init->usec_timeout; + if ( dev_priv->usec_timeout < 1 || + dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) { + DRM_DEBUG( "TIMEOUT problem!\n" ); + dev->dev_private = (void *)dev_priv; + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + switch(init->func) { + case RADEON_INIT_R200_CP: + dev_priv->microcode_version=UCODE_R200; + break; + case RADEON_INIT_R300_CP: + dev_priv->microcode_version=UCODE_R300; + break; + default: + dev_priv->microcode_version=UCODE_R100; + } + + dev_priv->do_boxes = 0; + dev_priv->cp_mode = init->cp_mode; + + /* We don't support anything other than bus-mastering ring mode, + * but the ring can be in either AGP or PCI space for the ring + * read pointer. + */ + if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) && + ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) { + DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode ); + dev->dev_private = (void *)dev_priv; + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + switch ( init->fb_bpp ) { + case 16: + dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; + break; + case 32: + default: + dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; + break; + } + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; + + switch ( init->depth_bpp ) { + case 16: + dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; + break; + case 32: + default: + dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; + break; + } + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; + + /* Hardware state for depth clears. Remove this if/when we no + * longer clear the depth buffer with a 3D rectangle. Hard-code + * all values to prevent unwanted 3D state from slipping through + * and screwing with the clear operation. + */ + dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | + (dev_priv->color_fmt << 10) | + (dev_priv->microcode_version == UCODE_R100 ? RADEON_ZBLOCK16 : 0)); + + dev_priv->depth_clear.rb3d_zstencilcntl = + (dev_priv->depth_fmt | + RADEON_Z_TEST_ALWAYS | + RADEON_STENCIL_TEST_ALWAYS | + RADEON_STENCIL_S_FAIL_REPLACE | + RADEON_STENCIL_ZPASS_REPLACE | + RADEON_STENCIL_ZFAIL_REPLACE | + RADEON_Z_WRITE_ENABLE); + + dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | + RADEON_BFACE_SOLID | + RADEON_FFACE_SOLID | + RADEON_FLAT_SHADE_VTX_LAST | + RADEON_DIFFUSE_SHADE_FLAT | + RADEON_ALPHA_SHADE_FLAT | + RADEON_SPECULAR_SHADE_FLAT | + RADEON_FOG_SHADE_FLAT | + RADEON_VTX_PIX_CENTER_OGL | + RADEON_ROUND_MODE_TRUNC | + RADEON_ROUND_PREC_8TH_PIX); + + DRM_GETSAREA(); + + dev_priv->fb_offset = init->fb_offset; + dev_priv->mmio_offset = init->mmio_offset; + dev_priv->ring_offset = init->ring_offset; + dev_priv->ring_rptr_offset = init->ring_rptr_offset; + dev_priv->buffers_offset = init->buffers_offset; + dev_priv->gart_textures_offset = init->gart_textures_offset; + + if(!dev_priv->sarea) { + DRM_ERROR("could not find sarea!\n"); + dev->dev_private = (void *)dev_priv; + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); + if(!dev_priv->mmio) { + DRM_ERROR("could not find mmio region!\n"); + dev->dev_private = (void *)dev_priv; + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); + if(!dev_priv->cp_ring) { + DRM_ERROR("could not find cp ring region!\n"); + dev->dev_private = (void *)dev_priv; + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); + if(!dev_priv->ring_rptr) { + DRM_ERROR("could not find ring read pointer!\n"); + dev->dev_private = (void *)dev_priv; + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); + if(!dev->agp_buffer_map) { + DRM_ERROR("could not find dma buffer region!\n"); + dev->dev_private = (void *)dev_priv; + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + + if ( init->gart_textures_offset ) { + dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset); + if ( !dev_priv->gart_textures ) { + DRM_ERROR("could not find GART texture region!\n"); + dev->dev_private = (void *)dev_priv; + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + } + + dev_priv->sarea_priv = + (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle + + init->sarea_priv_offset); + +#if __OS_HAS_AGP + if ( !dev_priv->is_pci ) { + drm_core_ioremap( dev_priv->cp_ring, dev ); + drm_core_ioremap( dev_priv->ring_rptr, dev ); + drm_core_ioremap( dev->agp_buffer_map, dev ); + if(!dev_priv->cp_ring->handle || + !dev_priv->ring_rptr->handle || + !dev->agp_buffer_map->handle) { + DRM_ERROR("could not find ioremap agp regions!\n"); + dev->dev_private = (void *)dev_priv; + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + } else +#endif + { + dev_priv->cp_ring->handle = + (void *)dev_priv->cp_ring->offset; + dev_priv->ring_rptr->handle = + (void *)dev_priv->ring_rptr->offset; + dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; + + DRM_DEBUG( "dev_priv->cp_ring->handle %p\n", + dev_priv->cp_ring->handle ); + DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n", + dev_priv->ring_rptr->handle ); + DRM_DEBUG( "dev->agp_buffer_map->handle %p\n", + dev->agp_buffer_map->handle ); + } + + dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION ) + & 0xffff ) << 16; + + dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) | + ( ( dev_priv->front_offset + + dev_priv->fb_location ) >> 10 ) ); + + dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) | + ( ( dev_priv->back_offset + + dev_priv->fb_location ) >> 10 ) ); + + dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) | + ( ( dev_priv->depth_offset + + dev_priv->fb_location ) >> 10 ) ); + + + dev_priv->gart_size = init->gart_size; + dev_priv->gart_vm_start = dev_priv->fb_location + + RADEON_READ( RADEON_CONFIG_APER_SIZE ); + +#if __OS_HAS_AGP + if ( !dev_priv->is_pci ) + dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset + - dev->agp->base + + dev_priv->gart_vm_start); + else +#endif + dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset + - dev->sg->handle + + dev_priv->gart_vm_start); + + DRM_DEBUG( "dev_priv->gart_size %d\n", + dev_priv->gart_size ); + DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n", + dev_priv->gart_vm_start ); + DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n", + dev_priv->gart_buffers_offset ); + + dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle; + dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle + + init->ring_size / sizeof(u32)); + dev_priv->ring.size = init->ring_size; + dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 ); + + dev_priv->ring.tail_mask = + (dev_priv->ring.size / sizeof(u32)) - 1; + + dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; + +#if __OS_HAS_AGP + if ( !dev_priv->is_pci ) { + /* Turn off PCI GART */ + radeon_set_pcigart( dev_priv, 0 ); + } else +#endif + { + if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart, + &dev_priv->bus_pci_gart)) { + DRM_ERROR( "failed to init PCI GART!\n" ); + dev->dev_private = (void *)dev_priv; + radeon_do_cleanup_cp(dev); + return DRM_ERR(ENOMEM); + } + + /* Turn on PCI GART */ + radeon_set_pcigart( dev_priv, 1 ); + } + + radeon_cp_load_microcode( dev_priv ); + radeon_cp_init_ring_buffer( dev, dev_priv ); + + dev_priv->last_buf = 0; + + dev->dev_private = (void *)dev_priv; + + radeon_do_engine_reset( dev ); + + return 0; +} + +static int radeon_do_cleanup_cp( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "\n" ); + + /* Make sure interrupts are disabled here because the uninstall ioctl + * may not have been called from userspace and after dev_private + * is freed, it's too late. + */ + if ( dev->irq_enabled ) drm_irq_uninstall(dev); + +#if __OS_HAS_AGP + if ( !dev_priv->is_pci ) { + if ( dev_priv->cp_ring != NULL ) + drm_core_ioremapfree( dev_priv->cp_ring, dev ); + if ( dev_priv->ring_rptr != NULL ) + drm_core_ioremapfree( dev_priv->ring_rptr, dev ); + if ( dev->agp_buffer_map != NULL ) + { + drm_core_ioremapfree( dev->agp_buffer_map, dev ); + dev->agp_buffer_map = NULL; + } + } else +#endif + { + if (!drm_ati_pcigart_cleanup( dev, + dev_priv->phys_pci_gart, + dev_priv->bus_pci_gart )) + DRM_ERROR( "failed to cleanup PCI GART!\n" ); + } + + /* only clear to the start of flags */ + memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); + + return 0; +} + +/* This code will reinit the Radeon CP hardware after a resume from disc. + * AFAIK, it would be very difficult to pickle the state at suspend time, so + * here we make sure that all Radeon hardware initialisation is re-done without + * affecting running applications. + * + * Charl P. Botha + */ +static int radeon_do_resume_cp( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + + if ( !dev_priv ) { + DRM_ERROR( "Called with no initialization\n" ); + return DRM_ERR( EINVAL ); + } + + DRM_DEBUG("Starting radeon_do_resume_cp()\n"); + +#if __OS_HAS_AGP + if ( !dev_priv->is_pci ) { + /* Turn off PCI GART */ + radeon_set_pcigart( dev_priv, 0 ); + } else +#endif + { + /* Turn on PCI GART */ + radeon_set_pcigart( dev_priv, 1 ); + } + + radeon_cp_load_microcode( dev_priv ); + radeon_cp_init_ring_buffer( dev, dev_priv ); + + radeon_do_engine_reset( dev ); + + DRM_DEBUG("radeon_do_resume_cp() complete\n"); + + return 0; +} + + +int radeon_cp_init( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_init_t init; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) ); + + switch ( init.func ) { + case RADEON_INIT_CP: + case RADEON_INIT_R200_CP: + case RADEON_INIT_R300_CP: + return radeon_do_init_cp( dev, &init ); + case RADEON_CLEANUP_CP: + return radeon_do_cleanup_cp( dev ); + } + + return DRM_ERR(EINVAL); +} + +int radeon_cp_start( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( dev_priv->cp_running ) { + DRM_DEBUG( "%s while CP running\n", __FUNCTION__ ); + return 0; + } + if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) { + DRM_DEBUG( "%s called with bogus CP mode (%d)\n", + __FUNCTION__, dev_priv->cp_mode ); + return 0; + } + + radeon_do_cp_start( dev_priv ); + + return 0; +} + +/* Stop the CP. The engine must have been idled before calling this + * routine. + */ +int radeon_cp_stop( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_cp_stop_t stop; + int ret; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) ); + + if (!dev_priv->cp_running) + return 0; + + /* Flush any pending CP commands. This ensures any outstanding + * commands are exectuted by the engine before we turn it off. + */ + if ( stop.flush ) { + radeon_do_cp_flush( dev_priv ); + } + + /* If we fail to make the engine go idle, we return an error + * code so that the DRM ioctl wrapper can try again. + */ + if ( stop.idle ) { + ret = radeon_do_cp_idle( dev_priv ); + if ( ret ) return ret; + } + + /* Finally, we can turn off the CP. If the engine isn't idle, + * we will get some dropped triangles as they won't be fully + * rendered before the CP is shut down. + */ + radeon_do_cp_stop( dev_priv ); + + /* Reset the engine */ + radeon_do_engine_reset( dev ); + + return 0; +} + + +void radeon_do_release( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + int i, ret; + + if (dev_priv) { + if (dev_priv->cp_running) { + /* Stop the cp */ + while ((ret = radeon_do_cp_idle( dev_priv )) != 0) { + DRM_DEBUG("radeon_do_cp_idle %d\n", ret); +#ifdef __linux__ + schedule(); +#else + tsleep(&ret, PZERO, "rdnrel", 1); +#endif + } + radeon_do_cp_stop( dev_priv ); + radeon_do_engine_reset( dev ); + } + + /* Disable *all* interrupts */ + if (dev_priv->mmio) /* remove this after permanent addmaps */ + RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); + + if (dev_priv->mmio) {/* remove all surfaces */ + for (i = 0; i < RADEON_MAX_SURFACES; i++) { + RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0); + RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0); + RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0); + } + } + + /* Free memory heap structures */ + radeon_mem_takedown( &(dev_priv->gart_heap) ); + radeon_mem_takedown( &(dev_priv->fb_heap) ); + + /* deallocate kernel resources */ + radeon_do_cleanup_cp( dev ); + } +} + +/* Just reset the CP ring. Called as part of an X Server engine reset. + */ +int radeon_cp_reset( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( !dev_priv ) { + DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + radeon_do_cp_reset( dev_priv ); + + /* The CP is no longer running after an engine reset */ + dev_priv->cp_running = 0; + + return 0; +} + +int radeon_cp_idle( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + return radeon_do_cp_idle( dev_priv ); +} + +/* Added by Charl P. Botha to call radeon_do_resume_cp(). + */ +int radeon_cp_resume( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + + return radeon_do_resume_cp(dev); +} + + +int radeon_engine_reset( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + return radeon_do_engine_reset( dev ); +} + + +/* ================================================================ + * Fullscreen mode + */ + +/* KW: Deprecated to say the least: + */ +int radeon_fullscreen( DRM_IOCTL_ARGS ) +{ + return 0; +} + + +/* ================================================================ + * Freelist management + */ + +/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through + * bufs until freelist code is used. Note this hides a problem with + * the scratch register * (used to keep track of last buffer + * completed) being written to before * the last buffer has actually + * completed rendering. + * + * KW: It's also a good way to find free buffers quickly. + * + * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't + * sleep. However, bugs in older versions of radeon_accel.c mean that + * we essentially have to do this, else old clients will break. + * + * However, it does leave open a potential deadlock where all the + * buffers are held by other clients, which can't release them because + * they can't get the lock. + */ + +drm_buf_t *radeon_freelist_get( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_buf_priv_t *buf_priv; + drm_buf_t *buf; + int i, t; + int start; + + if ( ++dev_priv->last_buf >= dma->buf_count ) + dev_priv->last_buf = 0; + + start = dev_priv->last_buf; + + for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { + u32 done_age = GET_SCRATCH( 1 ); + DRM_DEBUG("done_age = %d\n",done_age); + for ( i = start ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + if ( buf->filp == 0 || (buf->pending && + buf_priv->age <= done_age) ) { + dev_priv->stats.requested_bufs++; + buf->pending = 0; + return buf; + } + start = 0; + } + + if (t) { + DRM_UDELAY( 1 ); + dev_priv->stats.freelist_loops++; + } + } + + DRM_DEBUG( "returning NULL!\n" ); + return NULL; +} +#if 0 +drm_buf_t *radeon_freelist_get( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_buf_priv_t *buf_priv; + drm_buf_t *buf; + int i, t; + int start; + u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); + + if ( ++dev_priv->last_buf >= dma->buf_count ) + dev_priv->last_buf = 0; + + start = dev_priv->last_buf; + dev_priv->stats.freelist_loops++; + + for ( t = 0 ; t < 2 ; t++ ) { + for ( i = start ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + if ( buf->filp == 0 || (buf->pending && + buf_priv->age <= done_age) ) { + dev_priv->stats.requested_bufs++; + buf->pending = 0; + return buf; + } + } + start = 0; + } + + return NULL; +} +#endif + +void radeon_freelist_reset( drm_device_t *dev ) +{ + drm_device_dma_t *dma = dev->dma; + drm_radeon_private_t *dev_priv = dev->dev_private; + int i; + + dev_priv->last_buf = 0; + for ( i = 0 ; i < dma->buf_count ; i++ ) { + drm_buf_t *buf = dma->buflist[i]; + drm_radeon_buf_priv_t *buf_priv = buf->dev_private; + buf_priv->age = 0; + } +} + + +/* ================================================================ + * CP command submission + */ + +int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ) +{ + drm_radeon_ring_buffer_t *ring = &dev_priv->ring; + int i; + u32 last_head = GET_RING_HEAD( dev_priv ); + + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + u32 head = GET_RING_HEAD( dev_priv ); + + ring->space = (head - ring->tail) * sizeof(u32); + if ( ring->space <= 0 ) + ring->space += ring->size; + if ( ring->space > n ) + return 0; + + dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; + + if (head != last_head) + i = 0; + last_head = head; + + DRM_UDELAY( 1 ); + } + + /* FIXME: This return value is ignored in the BEGIN_RING macro! */ +#if RADEON_FIFO_DEBUG + radeon_status( dev_priv ); + DRM_ERROR( "failed!\n" ); +#endif + return DRM_ERR(EBUSY); +} + +static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) +{ + int i; + drm_buf_t *buf; + + for ( i = d->granted_count ; i < d->request_count ; i++ ) { + buf = radeon_freelist_get( dev ); + if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */ + + buf->filp = filp; + + if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, + sizeof(buf->idx) ) ) + return DRM_ERR(EFAULT); + if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, + sizeof(buf->total) ) ) + return DRM_ERR(EFAULT); + + d->granted_count++; + } + return 0; +} + +int radeon_cp_buffers( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_device_dma_t *dma = dev->dma; + int ret = 0; + drm_dma_t __user *argp = (void __user *)data; + drm_dma_t d; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); + + /* Please don't send us buffers. + */ + if ( d.send_count != 0 ) { + DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", + DRM_CURRENTPID, d.send_count ); + return DRM_ERR(EINVAL); + } + + /* We'll send you buffers. + */ + if ( d.request_count < 0 || d.request_count > dma->buf_count ) { + DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", + DRM_CURRENTPID, d.request_count, dma->buf_count ); + return DRM_ERR(EINVAL); + } + + d.granted_count = 0; + + if ( d.request_count ) { + ret = radeon_cp_get_buffers( filp, dev, &d ); + } + + DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); + + return ret; +} + +int radeon_driver_preinit(struct drm_device *dev, unsigned long flags) +{ + drm_radeon_private_t *dev_priv; + int ret = 0; + + dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); + if (dev_priv == NULL) + return DRM_ERR(ENOMEM); + + memset(dev_priv, 0, sizeof(drm_radeon_private_t)); + dev->dev_private = (void *)dev_priv; + dev_priv->flags = flags; + + switch (flags & CHIP_FAMILY_MASK) { + case CHIP_R100: + case CHIP_RV200: + case CHIP_R200: + case CHIP_R300: + dev_priv->flags |= CHIP_HAS_HIERZ; + break; + default: + /* all other chips have no hierarchical z buffer */ + break; + } + return ret; +} + +int radeon_driver_postcleanup(struct drm_device *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("\n"); + + drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); + + dev->dev_private = NULL; + return 0; +} diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h new file mode 100644 index 000000000000..c1e62d047989 --- /dev/null +++ b/drivers/char/drm/radeon_drm.h @@ -0,0 +1,659 @@ +/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Kevin E. Martin + * Gareth Hughes + * Keith Whitwell + */ + +#ifndef __RADEON_DRM_H__ +#define __RADEON_DRM_H__ + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the X server file (radeon_sarea.h) + */ +#ifndef __RADEON_SAREA_DEFINES__ +#define __RADEON_SAREA_DEFINES__ + +/* Old style state flags, required for sarea interface (1.1 and 1.2 + * clears) and 1.2 drm_vertex2 ioctl. + */ +#define RADEON_UPLOAD_CONTEXT 0x00000001 +#define RADEON_UPLOAD_VERTFMT 0x00000002 +#define RADEON_UPLOAD_LINE 0x00000004 +#define RADEON_UPLOAD_BUMPMAP 0x00000008 +#define RADEON_UPLOAD_MASKS 0x00000010 +#define RADEON_UPLOAD_VIEWPORT 0x00000020 +#define RADEON_UPLOAD_SETUP 0x00000040 +#define RADEON_UPLOAD_TCL 0x00000080 +#define RADEON_UPLOAD_MISC 0x00000100 +#define RADEON_UPLOAD_TEX0 0x00000200 +#define RADEON_UPLOAD_TEX1 0x00000400 +#define RADEON_UPLOAD_TEX2 0x00000800 +#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 +#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 +#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 +#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ +#define RADEON_REQUIRE_QUIESCENCE 0x00010000 +#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ +#define RADEON_UPLOAD_ALL 0x003effff +#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff + + +/* New style per-packet identifiers for use in cmd_buffer ioctl with + * the RADEON_EMIT_PACKET command. Comments relate new packets to old + * state bits and the packet size: + */ +#define RADEON_EMIT_PP_MISC 0 /* context/7 */ +#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ +#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ +#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ +#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ +#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ +#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ +#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ +#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ +#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ +#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ +#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ +#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ +#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ +#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ +#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ +#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ +#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ +#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ +#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ +#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ +#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ +#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ +#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ +#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ +#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ +#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ +#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ +#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ +#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ +#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ +#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ +#define R200_EMIT_VAP_CTL 32 /* vap/1 */ +#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ +#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ +#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ +#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ +#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ +#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ +#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ +#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ +#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ +#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ +#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ +#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ +#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ +#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ +#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ +#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ +#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ +#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ +#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ +#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ +#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ +#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ +#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ +#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ +#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ +#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ +#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ +#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ +#define R200_EMIT_PP_CUBIC_FACES_0 61 +#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 +#define R200_EMIT_PP_CUBIC_FACES_1 63 +#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 +#define R200_EMIT_PP_CUBIC_FACES_2 65 +#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 +#define R200_EMIT_PP_CUBIC_FACES_3 67 +#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 +#define R200_EMIT_PP_CUBIC_FACES_4 69 +#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 +#define R200_EMIT_PP_CUBIC_FACES_5 71 +#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 +#define RADEON_EMIT_PP_TEX_SIZE_0 73 +#define RADEON_EMIT_PP_TEX_SIZE_1 74 +#define RADEON_EMIT_PP_TEX_SIZE_2 75 +#define R200_EMIT_RB3D_BLENDCOLOR 76 +#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 +#define RADEON_EMIT_PP_CUBIC_FACES_0 78 +#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 +#define RADEON_EMIT_PP_CUBIC_FACES_1 80 +#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 +#define RADEON_EMIT_PP_CUBIC_FACES_2 82 +#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 +#define R200_EMIT_PP_TRI_PERF_CNTL 84 +#define RADEON_MAX_STATE_PACKETS 85 + +/* Commands understood by cmd_buffer ioctl. More can be added but + * obviously these can't be removed or changed: + */ +#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ +#define RADEON_CMD_SCALARS 2 /* emit scalar data */ +#define RADEON_CMD_VECTORS 3 /* emit vector data */ +#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ +#define RADEON_CMD_PACKET3 5 /* emit hw packet */ +#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ +#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ +#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: + * doesn't make the cpu wait, just + * the graphics hardware */ + + +typedef union { + int i; + struct { + unsigned char cmd_type, pad0, pad1, pad2; + } header; + struct { + unsigned char cmd_type, packet_id, pad0, pad1; + } packet; + struct { + unsigned char cmd_type, offset, stride, count; + } scalars; + struct { + unsigned char cmd_type, offset, stride, count; + } vectors; + struct { + unsigned char cmd_type, buf_idx, pad0, pad1; + } dma; + struct { + unsigned char cmd_type, flags, pad0, pad1; + } wait; +} drm_radeon_cmd_header_t; + +#define RADEON_WAIT_2D 0x1 +#define RADEON_WAIT_3D 0x2 + + +#define RADEON_FRONT 0x1 +#define RADEON_BACK 0x2 +#define RADEON_DEPTH 0x4 +#define RADEON_STENCIL 0x8 +#define RADEON_CLEAR_FASTZ 0x80000000 +#define RADEON_USE_HIERZ 0x40000000 +#define RADEON_USE_COMP_ZBUF 0x20000000 + +/* Primitive types + */ +#define RADEON_POINTS 0x1 +#define RADEON_LINES 0x2 +#define RADEON_LINE_STRIP 0x3 +#define RADEON_TRIANGLES 0x4 +#define RADEON_TRIANGLE_FAN 0x5 +#define RADEON_TRIANGLE_STRIP 0x6 + +/* Vertex/indirect buffer size + */ +#define RADEON_BUFFER_SIZE 65536 + +/* Byte offsets for indirect buffer data + */ +#define RADEON_INDEX_PRIM_OFFSET 20 + +#define RADEON_SCRATCH_REG_OFFSET 32 + +#define RADEON_NR_SAREA_CLIPRECTS 12 + +/* There are 2 heaps (local/GART). Each region within a heap is a + * minimum of 64k, and there are at most 64 of them per heap. + */ +#define RADEON_LOCAL_TEX_HEAP 0 +#define RADEON_GART_TEX_HEAP 1 +#define RADEON_NR_TEX_HEAPS 2 +#define RADEON_NR_TEX_REGIONS 64 +#define RADEON_LOG_TEX_GRANULARITY 16 + +#define RADEON_MAX_TEXTURE_LEVELS 12 +#define RADEON_MAX_TEXTURE_UNITS 3 + +#define RADEON_MAX_SURFACES 8 + +/* Blits have strict offset rules. All blit offset must be aligned on + * a 1K-byte boundary. + */ +#define RADEON_OFFSET_SHIFT 10 +#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) +#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) + +#endif /* __RADEON_SAREA_DEFINES__ */ + +typedef struct { + unsigned int red; + unsigned int green; + unsigned int blue; + unsigned int alpha; +} radeon_color_regs_t; + +typedef struct { + /* Context state */ + unsigned int pp_misc; /* 0x1c14 */ + unsigned int pp_fog_color; + unsigned int re_solid_color; + unsigned int rb3d_blendcntl; + unsigned int rb3d_depthoffset; + unsigned int rb3d_depthpitch; + unsigned int rb3d_zstencilcntl; + + unsigned int pp_cntl; /* 0x1c38 */ + unsigned int rb3d_cntl; + unsigned int rb3d_coloroffset; + unsigned int re_width_height; + unsigned int rb3d_colorpitch; + unsigned int se_cntl; + + /* Vertex format state */ + unsigned int se_coord_fmt; /* 0x1c50 */ + + /* Line state */ + unsigned int re_line_pattern; /* 0x1cd0 */ + unsigned int re_line_state; + + unsigned int se_line_width; /* 0x1db8 */ + + /* Bumpmap state */ + unsigned int pp_lum_matrix; /* 0x1d00 */ + + unsigned int pp_rot_matrix_0; /* 0x1d58 */ + unsigned int pp_rot_matrix_1; + + /* Mask state */ + unsigned int rb3d_stencilrefmask; /* 0x1d7c */ + unsigned int rb3d_ropcntl; + unsigned int rb3d_planemask; + + /* Viewport state */ + unsigned int se_vport_xscale; /* 0x1d98 */ + unsigned int se_vport_xoffset; + unsigned int se_vport_yscale; + unsigned int se_vport_yoffset; + unsigned int se_vport_zscale; + unsigned int se_vport_zoffset; + + /* Setup state */ + unsigned int se_cntl_status; /* 0x2140 */ + + /* Misc state */ + unsigned int re_top_left; /* 0x26c0 */ + unsigned int re_misc; +} drm_radeon_context_regs_t; + +typedef struct { + /* Zbias state */ + unsigned int se_zbias_factor; /* 0x1dac */ + unsigned int se_zbias_constant; +} drm_radeon_context2_regs_t; + + +/* Setup registers for each texture unit + */ +typedef struct { + unsigned int pp_txfilter; + unsigned int pp_txformat; + unsigned int pp_txoffset; + unsigned int pp_txcblend; + unsigned int pp_txablend; + unsigned int pp_tfactor; + unsigned int pp_border_color; +} drm_radeon_texture_regs_t; + +typedef struct { + unsigned int start; + unsigned int finish; + unsigned int prim:8; + unsigned int stateidx:8; + unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ + unsigned int vc_format; /* vertex format */ +} drm_radeon_prim_t; + + +typedef struct { + drm_radeon_context_regs_t context; + drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; + drm_radeon_context2_regs_t context2; + unsigned int dirty; +} drm_radeon_state_t; + + +typedef struct { + /* The channel for communication of state information to the + * kernel on firing a vertex buffer with either of the + * obsoleted vertex/index ioctls. + */ + drm_radeon_context_regs_t context_state; + drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; + unsigned int dirty; + unsigned int vertsize; + unsigned int vc_format; + + /* The current cliprects, or a subset thereof. + */ + drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS]; + unsigned int nbox; + + /* Counters for client-side throttling of rendering clients. + */ + unsigned int last_frame; + unsigned int last_dispatch; + unsigned int last_clear; + + drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; + unsigned int tex_age[RADEON_NR_TEX_HEAPS]; + int ctx_owner; + int pfState; /* number of 3d windows (0,1,2ormore) */ + int pfCurrentPage; /* which buffer is being displayed? */ + int crtc2_base; /* CRTC2 frame offset */ + int tiling_enabled; /* set by drm, read by 2d + 3d clients */ +} drm_radeon_sarea_t; + + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmRadeon.h) + * + * KW: actually it's illegal to change any of this (backwards compatibility). + */ + +/* Radeon specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_RADEON_CP_INIT 0x00 +#define DRM_RADEON_CP_START 0x01 +#define DRM_RADEON_CP_STOP 0x02 +#define DRM_RADEON_CP_RESET 0x03 +#define DRM_RADEON_CP_IDLE 0x04 +#define DRM_RADEON_RESET 0x05 +#define DRM_RADEON_FULLSCREEN 0x06 +#define DRM_RADEON_SWAP 0x07 +#define DRM_RADEON_CLEAR 0x08 +#define DRM_RADEON_VERTEX 0x09 +#define DRM_RADEON_INDICES 0x0A +#define DRM_RADEON_NOT_USED +#define DRM_RADEON_STIPPLE 0x0C +#define DRM_RADEON_INDIRECT 0x0D +#define DRM_RADEON_TEXTURE 0x0E +#define DRM_RADEON_VERTEX2 0x0F +#define DRM_RADEON_CMDBUF 0x10 +#define DRM_RADEON_GETPARAM 0x11 +#define DRM_RADEON_FLIP 0x12 +#define DRM_RADEON_ALLOC 0x13 +#define DRM_RADEON_FREE 0x14 +#define DRM_RADEON_INIT_HEAP 0x15 +#define DRM_RADEON_IRQ_EMIT 0x16 +#define DRM_RADEON_IRQ_WAIT 0x17 +#define DRM_RADEON_CP_RESUME 0x18 +#define DRM_RADEON_SETPARAM 0x19 +#define DRM_RADEON_SURF_ALLOC 0x1a +#define DRM_RADEON_SURF_FREE 0x1b + +#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) +#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) +#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) +#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) +#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) +#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) +#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) +#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) +#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) +#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) +#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) +#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) +#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) +#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) +#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) +#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) +#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) +#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) +#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) +#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) +#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) +#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) +#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) +#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) +#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) +#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) +#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) + +typedef struct drm_radeon_init { + enum { + RADEON_INIT_CP = 0x01, + RADEON_CLEANUP_CP = 0x02, + RADEON_INIT_R200_CP = 0x03, + RADEON_INIT_R300_CP = 0x04 + } func; + unsigned long sarea_priv_offset; + int is_pci; + int cp_mode; + int gart_size; + int ring_size; + int usec_timeout; + + unsigned int fb_bpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + unsigned int depth_bpp; + unsigned int depth_offset, depth_pitch; + + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long ring_offset; + unsigned long ring_rptr_offset; + unsigned long buffers_offset; + unsigned long gart_textures_offset; +} drm_radeon_init_t; + +typedef struct drm_radeon_cp_stop { + int flush; + int idle; +} drm_radeon_cp_stop_t; + +typedef struct drm_radeon_fullscreen { + enum { + RADEON_INIT_FULLSCREEN = 0x01, + RADEON_CLEANUP_FULLSCREEN = 0x02 + } func; +} drm_radeon_fullscreen_t; + +#define CLEAR_X1 0 +#define CLEAR_Y1 1 +#define CLEAR_X2 2 +#define CLEAR_Y2 3 +#define CLEAR_DEPTH 4 + +typedef union drm_radeon_clear_rect { + float f[5]; + unsigned int ui[5]; +} drm_radeon_clear_rect_t; + +typedef struct drm_radeon_clear { + unsigned int flags; + unsigned int clear_color; + unsigned int clear_depth; + unsigned int color_mask; + unsigned int depth_mask; /* misnamed field: should be stencil */ + drm_radeon_clear_rect_t __user *depth_boxes; +} drm_radeon_clear_t; + +typedef struct drm_radeon_vertex { + int prim; + int idx; /* Index of vertex buffer */ + int count; /* Number of vertices in buffer */ + int discard; /* Client finished with buffer? */ +} drm_radeon_vertex_t; + +typedef struct drm_radeon_indices { + int prim; + int idx; + int start; + int end; + int discard; /* Client finished with buffer? */ +} drm_radeon_indices_t; + +/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices + * - allows multiple primitives and state changes in a single ioctl + * - supports driver change to emit native primitives + */ +typedef struct drm_radeon_vertex2 { + int idx; /* Index of vertex buffer */ + int discard; /* Client finished with buffer? */ + int nr_states; + drm_radeon_state_t __user *state; + int nr_prims; + drm_radeon_prim_t __user *prim; +} drm_radeon_vertex2_t; + +/* v1.3 - obsoletes drm_radeon_vertex2 + * - allows arbitarily large cliprect list + * - allows updating of tcl packet, vector and scalar state + * - allows memory-efficient description of state updates + * - allows state to be emitted without a primitive + * (for clears, ctx switches) + * - allows more than one dma buffer to be referenced per ioctl + * - supports tcl driver + * - may be extended in future versions with new cmd types, packets + */ +typedef struct drm_radeon_cmd_buffer { + int bufsz; + char __user *buf; + int nbox; + drm_clip_rect_t __user *boxes; +} drm_radeon_cmd_buffer_t; + +typedef struct drm_radeon_tex_image { + unsigned int x, y; /* Blit coordinates */ + unsigned int width, height; + const void __user *data; +} drm_radeon_tex_image_t; + +typedef struct drm_radeon_texture { + unsigned int offset; + int pitch; + int format; + int width; /* Texture image coordinates */ + int height; + drm_radeon_tex_image_t __user *image; +} drm_radeon_texture_t; + +typedef struct drm_radeon_stipple { + unsigned int __user *mask; +} drm_radeon_stipple_t; + +typedef struct drm_radeon_indirect { + int idx; + int start; + int end; + int discard; +} drm_radeon_indirect_t; + + +/* 1.3: An ioctl to get parameters that aren't available to the 3d + * client any other way. + */ +#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ +#define RADEON_PARAM_LAST_FRAME 2 +#define RADEON_PARAM_LAST_DISPATCH 3 +#define RADEON_PARAM_LAST_CLEAR 4 +/* Added with DRM version 1.6. */ +#define RADEON_PARAM_IRQ_NR 5 +#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ +/* Added with DRM version 1.8. */ +#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ +#define RADEON_PARAM_STATUS_HANDLE 8 +#define RADEON_PARAM_SAREA_HANDLE 9 +#define RADEON_PARAM_GART_TEX_HANDLE 10 +#define RADEON_PARAM_SCRATCH_OFFSET 11 + +typedef struct drm_radeon_getparam { + int param; + void __user *value; +} drm_radeon_getparam_t; + +/* 1.6: Set up a memory manager for regions of shared memory: + */ +#define RADEON_MEM_REGION_GART 1 +#define RADEON_MEM_REGION_FB 2 + +typedef struct drm_radeon_mem_alloc { + int region; + int alignment; + int size; + int __user *region_offset; /* offset from start of fb or GART */ +} drm_radeon_mem_alloc_t; + +typedef struct drm_radeon_mem_free { + int region; + int region_offset; +} drm_radeon_mem_free_t; + +typedef struct drm_radeon_mem_init_heap { + int region; + int size; + int start; +} drm_radeon_mem_init_heap_t; + + +/* 1.6: Userspace can request & wait on irq's: + */ +typedef struct drm_radeon_irq_emit { + int __user *irq_seq; +} drm_radeon_irq_emit_t; + +typedef struct drm_radeon_irq_wait { + int irq_seq; +} drm_radeon_irq_wait_t; + + +/* 1.10: Clients tell the DRM where they think the framebuffer is located in + * the card's address space, via a new generic ioctl to set parameters + */ + +typedef struct drm_radeon_setparam { + unsigned int param; + int64_t value; +} drm_radeon_setparam_t; + +#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ +#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ + +/* 1.14: Clients can allocate/free a surface + */ +typedef struct drm_radeon_surface_alloc { + unsigned int address; + unsigned int size; + unsigned int flags; +} drm_radeon_surface_alloc_t; + +typedef struct drm_radeon_surface_free { + unsigned int address; +} drm_radeon_surface_free_t; + +#endif diff --git a/drivers/char/drm/radeon_drv.c b/drivers/char/drm/radeon_drv.c new file mode 100644 index 000000000000..7b983d96e53b --- /dev/null +++ b/drivers/char/drm/radeon_drv.c @@ -0,0 +1,127 @@ +/** + * \file radeon_drv.c + * ATI Radeon driver + * + * \author Gareth Hughes + */ + +/* + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + + +#include +#include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" +#include "radeon_drv.h" + +#include "drm_pciids.h" + +static int postinit( struct drm_device *dev, unsigned long flags ) +{ + DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, + dev->primary.minor, + pci_pretty_name(dev->pdev) + ); + return 0; +} + +static int version( drm_version_t *version ) +{ + int len; + + version->version_major = DRIVER_MAJOR; + version->version_minor = DRIVER_MINOR; + version->version_patchlevel = DRIVER_PATCHLEVEL; + DRM_COPY( version->name, DRIVER_NAME ); + DRM_COPY( version->date, DRIVER_DATE ); + DRM_COPY( version->desc, DRIVER_DESC ); + return 0; +} + +static struct pci_device_id pciidlist[] = { + radeon_PCI_IDS +}; + +extern drm_ioctl_desc_t radeon_ioctls[]; +extern int radeon_max_ioctl; + +static struct drm_driver driver = { + .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, + .dev_priv_size = sizeof(drm_radeon_buf_priv_t), + .preinit = radeon_driver_preinit, + .postcleanup = radeon_driver_postcleanup, + .prerelease = radeon_driver_prerelease, + .pretakedown = radeon_driver_pretakedown, + .open_helper = radeon_driver_open_helper, + .vblank_wait = radeon_driver_vblank_wait, + .irq_preinstall = radeon_driver_irq_preinstall, + .irq_postinstall = radeon_driver_irq_postinstall, + .irq_uninstall = radeon_driver_irq_uninstall, + .irq_handler = radeon_driver_irq_handler, + .free_filp_priv = radeon_driver_free_filp_priv, + .reclaim_buffers = drm_core_reclaim_buffers, + .get_map_ofs = drm_core_get_map_ofs, + .get_reg_ofs = drm_core_get_reg_ofs, + .postinit = postinit, + .version = version, + .ioctls = radeon_ioctls, + .dma_ioctl = radeon_cp_buffers, + .fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + }, + .pci_driver = { + .name = DRIVER_NAME, + .id_table = pciidlist, + } +}; + +static int __init radeon_init(void) +{ + driver.num_ioctls = radeon_max_ioctl; + return drm_init(&driver); +} + +static void __exit radeon_exit(void) +{ + drm_exit(&driver); +} + +module_init(radeon_init); +module_exit(radeon_exit); + +MODULE_AUTHOR( DRIVER_AUTHOR ); +MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h new file mode 100644 index 000000000000..5837098afae8 --- /dev/null +++ b/drivers/char/drm/radeon_drv.h @@ -0,0 +1,1044 @@ +/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Kevin E. Martin + * Gareth Hughes + */ + +#ifndef __RADEON_DRV_H__ +#define __RADEON_DRV_H__ + +/* General customization: + */ + +#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." + +#define DRIVER_NAME "radeon" +#define DRIVER_DESC "ATI Radeon" +#define DRIVER_DATE "20050311" + +/* Interface history: + * + * 1.1 - ?? + * 1.2 - Add vertex2 ioctl (keith) + * - Add stencil capability to clear ioctl (gareth, keith) + * - Increase MAX_TEXTURE_LEVELS (brian) + * 1.3 - Add cmdbuf ioctl (keith) + * - Add support for new radeon packets (keith) + * - Add getparam ioctl (keith) + * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). + * 1.4 - Add scratch registers to get_param ioctl. + * 1.5 - Add r200 packets to cmdbuf ioctl + * - Add r200 function to init ioctl + * - Add 'scalar2' instruction to cmdbuf + * 1.6 - Add static GART memory manager + * Add irq handler (won't be turned on unless X server knows to) + * Add irq ioctls and irq_active getparam. + * Add wait command for cmdbuf ioctl + * Add GART offset query for getparam + * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] + * and R200_PP_CUBIC_OFFSET_F1_[0..5]. + * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and + * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) + * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) + * Add 'GET' queries for starting additional clients on different VT's. + * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. + * Add texture rectangle support for r100. + * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which + * clients use to tell the DRM where they think the framebuffer is + * located in the card's address space + * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color + * and GL_EXT_blend_[func|equation]_separate on r200 + * 1.12- Add R300 CP microcode support - this just loads the CP on r300 + * (No 3D support yet - just microcode loading) + * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters + * - Add hyperz support, add hyperz flags to clear ioctl. + * 1.14- Add support for color tiling + * - Add R100/R200 surface allocation/free support + * 1.15- Add support for texture micro tiling + * - Add support for r100 cube maps + * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear + * texture filtering on r200 + */ +#define DRIVER_MAJOR 1 +#define DRIVER_MINOR 16 +#define DRIVER_PATCHLEVEL 0 + +#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) +#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) + +/* + * Radeon chip families + */ +enum radeon_family { + CHIP_R100, + CHIP_RS100, + CHIP_RV100, + CHIP_R200, + CHIP_RV200, + CHIP_RS200, + CHIP_R250, + CHIP_RS250, + CHIP_RV250, + CHIP_RV280, + CHIP_R300, + CHIP_RS300, + CHIP_RV350, + CHIP_LAST, +}; + +enum radeon_cp_microcode_version { + UCODE_R100, + UCODE_R200, + UCODE_R300, +}; + +/* + * Chip flags + */ +enum radeon_chip_flags { + CHIP_FAMILY_MASK = 0x0000ffffUL, + CHIP_FLAGS_MASK = 0xffff0000UL, + CHIP_IS_MOBILITY = 0x00010000UL, + CHIP_IS_IGP = 0x00020000UL, + CHIP_SINGLE_CRTC = 0x00040000UL, + CHIP_IS_AGP = 0x00080000UL, + CHIP_HAS_HIERZ = 0x00100000UL, +}; + +typedef struct drm_radeon_freelist { + unsigned int age; + drm_buf_t *buf; + struct drm_radeon_freelist *next; + struct drm_radeon_freelist *prev; +} drm_radeon_freelist_t; + +typedef struct drm_radeon_ring_buffer { + u32 *start; + u32 *end; + int size; + int size_l2qw; + + u32 tail; + u32 tail_mask; + int space; + + int high_mark; +} drm_radeon_ring_buffer_t; + +typedef struct drm_radeon_depth_clear_t { + u32 rb3d_cntl; + u32 rb3d_zstencilcntl; + u32 se_cntl; +} drm_radeon_depth_clear_t; + +struct drm_radeon_driver_file_fields { + int64_t radeon_fb_delta; +}; + +struct mem_block { + struct mem_block *next; + struct mem_block *prev; + int start; + int size; + DRMFILE filp; /* 0: free, -1: heap, other: real files */ +}; + +struct radeon_surface { + int refcount; + u32 lower; + u32 upper; + u32 flags; +}; + +struct radeon_virt_surface { + int surface_index; + u32 lower; + u32 upper; + u32 flags; + DRMFILE filp; +}; + +typedef struct drm_radeon_private { + drm_radeon_ring_buffer_t ring; + drm_radeon_sarea_t *sarea_priv; + + u32 fb_location; + + int gart_size; + u32 gart_vm_start; + unsigned long gart_buffers_offset; + + int cp_mode; + int cp_running; + + drm_radeon_freelist_t *head; + drm_radeon_freelist_t *tail; + int last_buf; + volatile u32 *scratch; + int writeback_works; + + int usec_timeout; + + int microcode_version; + + int is_pci; + unsigned long phys_pci_gart; + dma_addr_t bus_pci_gart; + + struct { + u32 boxes; + int freelist_timeouts; + int freelist_loops; + int requested_bufs; + int last_frame_reads; + int last_clear_reads; + int clears; + int texture_uploads; + } stats; + + int do_boxes; + int page_flipping; + int current_page; + + u32 color_fmt; + unsigned int front_offset; + unsigned int front_pitch; + unsigned int back_offset; + unsigned int back_pitch; + + u32 depth_fmt; + unsigned int depth_offset; + unsigned int depth_pitch; + + u32 front_pitch_offset; + u32 back_pitch_offset; + u32 depth_pitch_offset; + + drm_radeon_depth_clear_t depth_clear; + + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long ring_offset; + unsigned long ring_rptr_offset; + unsigned long buffers_offset; + unsigned long gart_textures_offset; + + drm_local_map_t *sarea; + drm_local_map_t *mmio; + drm_local_map_t *cp_ring; + drm_local_map_t *ring_rptr; + drm_local_map_t *gart_textures; + + struct mem_block *gart_heap; + struct mem_block *fb_heap; + + /* SW interrupt */ + wait_queue_head_t swi_queue; + atomic_t swi_emitted; + + struct radeon_surface surfaces[RADEON_MAX_SURFACES]; + struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; + + /* starting from here on, data is preserved accross an open */ + uint32_t flags; /* see radeon_chip_flags */ +} drm_radeon_private_t; + +typedef struct drm_radeon_buf_priv { + u32 age; +} drm_radeon_buf_priv_t; + + /* radeon_cp.c */ +extern int radeon_cp_init( DRM_IOCTL_ARGS ); +extern int radeon_cp_start( DRM_IOCTL_ARGS ); +extern int radeon_cp_stop( DRM_IOCTL_ARGS ); +extern int radeon_cp_reset( DRM_IOCTL_ARGS ); +extern int radeon_cp_idle( DRM_IOCTL_ARGS ); +extern int radeon_cp_resume( DRM_IOCTL_ARGS ); +extern int radeon_engine_reset( DRM_IOCTL_ARGS ); +extern int radeon_fullscreen( DRM_IOCTL_ARGS ); +extern int radeon_cp_buffers( DRM_IOCTL_ARGS ); + +extern void radeon_freelist_reset( drm_device_t *dev ); +extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); + +extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); + +extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ); + +extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); +extern int radeon_driver_postcleanup(struct drm_device *dev); + +extern int radeon_mem_alloc( DRM_IOCTL_ARGS ); +extern int radeon_mem_free( DRM_IOCTL_ARGS ); +extern int radeon_mem_init_heap( DRM_IOCTL_ARGS ); +extern void radeon_mem_takedown( struct mem_block **heap ); +extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap ); + + /* radeon_irq.c */ +extern int radeon_irq_emit( DRM_IOCTL_ARGS ); +extern int radeon_irq_wait( DRM_IOCTL_ARGS ); + +extern void radeon_do_release(drm_device_t *dev); +extern int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); +extern irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS ); +extern void radeon_driver_irq_preinstall( drm_device_t *dev ); +extern void radeon_driver_irq_postinstall( drm_device_t *dev ); +extern void radeon_driver_irq_uninstall( drm_device_t *dev ); +extern void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp); +extern void radeon_driver_pretakedown(drm_device_t *dev); +extern int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv); +extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv); + +extern int radeon_preinit( struct drm_device *dev, unsigned long flags ); +extern int radeon_postinit( struct drm_device *dev, unsigned long flags ); +extern int radeon_postcleanup( struct drm_device *dev ); + +/* Flags for stats.boxes + */ +#define RADEON_BOX_DMA_IDLE 0x1 +#define RADEON_BOX_RING_FULL 0x2 +#define RADEON_BOX_FLIP 0x4 +#define RADEON_BOX_WAIT_IDLE 0x8 +#define RADEON_BOX_TEXTURE_LOAD 0x10 + + + +/* Register definitions, register access macros and drmAddMap constants + * for Radeon kernel driver. + */ + +#define RADEON_AGP_COMMAND 0x0f60 +#define RADEON_AUX_SCISSOR_CNTL 0x26f0 +# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) +# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) +# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) +# define RADEON_SCISSOR_0_ENABLE (1 << 28) +# define RADEON_SCISSOR_1_ENABLE (1 << 29) +# define RADEON_SCISSOR_2_ENABLE (1 << 30) + +#define RADEON_BUS_CNTL 0x0030 +# define RADEON_BUS_MASTER_DIS (1 << 6) + +#define RADEON_CLOCK_CNTL_DATA 0x000c +# define RADEON_PLL_WR_EN (1 << 7) +#define RADEON_CLOCK_CNTL_INDEX 0x0008 +#define RADEON_CONFIG_APER_SIZE 0x0108 +#define RADEON_CRTC_OFFSET 0x0224 +#define RADEON_CRTC_OFFSET_CNTL 0x0228 +# define RADEON_CRTC_TILE_EN (1 << 15) +# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) +#define RADEON_CRTC2_OFFSET 0x0324 +#define RADEON_CRTC2_OFFSET_CNTL 0x0328 + +#define RADEON_RB3D_COLOROFFSET 0x1c40 +#define RADEON_RB3D_COLORPITCH 0x1c48 + +#define RADEON_DP_GUI_MASTER_CNTL 0x146c +# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) +# define RADEON_GMC_BRUSH_NONE (15 << 4) +# define RADEON_GMC_DST_16BPP (4 << 8) +# define RADEON_GMC_DST_24BPP (5 << 8) +# define RADEON_GMC_DST_32BPP (6 << 8) +# define RADEON_GMC_DST_DATATYPE_SHIFT 8 +# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) +# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) +# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) +# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define RADEON_GMC_WR_MSK_DIS (1 << 30) +# define RADEON_ROP3_S 0x00cc0000 +# define RADEON_ROP3_P 0x00f00000 +#define RADEON_DP_WRITE_MASK 0x16cc +#define RADEON_DST_PITCH_OFFSET 0x142c +#define RADEON_DST_PITCH_OFFSET_C 0x1c80 +# define RADEON_DST_TILE_LINEAR (0 << 30) +# define RADEON_DST_TILE_MACRO (1 << 30) +# define RADEON_DST_TILE_MICRO (2 << 30) +# define RADEON_DST_TILE_BOTH (3 << 30) + +#define RADEON_SCRATCH_REG0 0x15e0 +#define RADEON_SCRATCH_REG1 0x15e4 +#define RADEON_SCRATCH_REG2 0x15e8 +#define RADEON_SCRATCH_REG3 0x15ec +#define RADEON_SCRATCH_REG4 0x15f0 +#define RADEON_SCRATCH_REG5 0x15f4 +#define RADEON_SCRATCH_UMSK 0x0770 +#define RADEON_SCRATCH_ADDR 0x0774 + +#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) + +#define GET_SCRATCH( x ) (dev_priv->writeback_works \ + ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ + : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) + + +#define RADEON_GEN_INT_CNTL 0x0040 +# define RADEON_CRTC_VBLANK_MASK (1 << 0) +# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) +# define RADEON_SW_INT_ENABLE (1 << 25) + +#define RADEON_GEN_INT_STATUS 0x0044 +# define RADEON_CRTC_VBLANK_STAT (1 << 0) +# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) +# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) +# define RADEON_SW_INT_TEST (1 << 25) +# define RADEON_SW_INT_TEST_ACK (1 << 25) +# define RADEON_SW_INT_FIRE (1 << 26) + +#define RADEON_HOST_PATH_CNTL 0x0130 +# define RADEON_HDP_SOFT_RESET (1 << 26) +# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) +# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) + +#define RADEON_ISYNC_CNTL 0x1724 +# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) +# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) +# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) +# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) +# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) +# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) + +#define RADEON_RBBM_GUICNTL 0x172c +# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) +# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) +# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) +# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) + +#define RADEON_MC_AGP_LOCATION 0x014c +#define RADEON_MC_FB_LOCATION 0x0148 +#define RADEON_MCLK_CNTL 0x0012 +# define RADEON_FORCEON_MCLKA (1 << 16) +# define RADEON_FORCEON_MCLKB (1 << 17) +# define RADEON_FORCEON_YCLKA (1 << 18) +# define RADEON_FORCEON_YCLKB (1 << 19) +# define RADEON_FORCEON_MC (1 << 20) +# define RADEON_FORCEON_AIC (1 << 21) + +#define RADEON_PP_BORDER_COLOR_0 0x1d40 +#define RADEON_PP_BORDER_COLOR_1 0x1d44 +#define RADEON_PP_BORDER_COLOR_2 0x1d48 +#define RADEON_PP_CNTL 0x1c38 +# define RADEON_SCISSOR_ENABLE (1 << 1) +#define RADEON_PP_LUM_MATRIX 0x1d00 +#define RADEON_PP_MISC 0x1c14 +#define RADEON_PP_ROT_MATRIX_0 0x1d58 +#define RADEON_PP_TXFILTER_0 0x1c54 +#define RADEON_PP_TXOFFSET_0 0x1c5c +#define RADEON_PP_TXFILTER_1 0x1c6c +#define RADEON_PP_TXFILTER_2 0x1c84 + +#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c +# define RADEON_RB2D_DC_FLUSH (3 << 0) +# define RADEON_RB2D_DC_FREE (3 << 2) +# define RADEON_RB2D_DC_FLUSH_ALL 0xf +# define RADEON_RB2D_DC_BUSY (1 << 31) +#define RADEON_RB3D_CNTL 0x1c3c +# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) +# define RADEON_PLANE_MASK_ENABLE (1 << 1) +# define RADEON_DITHER_ENABLE (1 << 2) +# define RADEON_ROUND_ENABLE (1 << 3) +# define RADEON_SCALE_DITHER_ENABLE (1 << 4) +# define RADEON_DITHER_INIT (1 << 5) +# define RADEON_ROP_ENABLE (1 << 6) +# define RADEON_STENCIL_ENABLE (1 << 7) +# define RADEON_Z_ENABLE (1 << 8) +# define RADEON_ZBLOCK16 (1 << 15) +#define RADEON_RB3D_DEPTHOFFSET 0x1c24 +#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 +#define RADEON_RB3D_DEPTHPITCH 0x1c28 +#define RADEON_RB3D_PLANEMASK 0x1d84 +#define RADEON_RB3D_STENCILREFMASK 0x1d7c +#define RADEON_RB3D_ZCACHE_MODE 0x3250 +#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 +# define RADEON_RB3D_ZC_FLUSH (1 << 0) +# define RADEON_RB3D_ZC_FREE (1 << 2) +# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 +# define RADEON_RB3D_ZC_BUSY (1 << 31) +#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c +# define RADEON_Z_TEST_MASK (7 << 4) +# define RADEON_Z_TEST_ALWAYS (7 << 4) +# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) +# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) +# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) +# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) +# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) +# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) +# define RADEON_FORCE_Z_DIRTY (1 << 29) +# define RADEON_Z_WRITE_ENABLE (1 << 30) +# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) +#define RADEON_RBBM_SOFT_RESET 0x00f0 +# define RADEON_SOFT_RESET_CP (1 << 0) +# define RADEON_SOFT_RESET_HI (1 << 1) +# define RADEON_SOFT_RESET_SE (1 << 2) +# define RADEON_SOFT_RESET_RE (1 << 3) +# define RADEON_SOFT_RESET_PP (1 << 4) +# define RADEON_SOFT_RESET_E2 (1 << 5) +# define RADEON_SOFT_RESET_RB (1 << 6) +# define RADEON_SOFT_RESET_HDP (1 << 7) +#define RADEON_RBBM_STATUS 0x0e40 +# define RADEON_RBBM_FIFOCNT_MASK 0x007f +# define RADEON_RBBM_ACTIVE (1 << 31) +#define RADEON_RE_LINE_PATTERN 0x1cd0 +#define RADEON_RE_MISC 0x26c4 +#define RADEON_RE_TOP_LEFT 0x26c0 +#define RADEON_RE_WIDTH_HEIGHT 0x1c44 +#define RADEON_RE_STIPPLE_ADDR 0x1cc8 +#define RADEON_RE_STIPPLE_DATA 0x1ccc + +#define RADEON_SCISSOR_TL_0 0x1cd8 +#define RADEON_SCISSOR_BR_0 0x1cdc +#define RADEON_SCISSOR_TL_1 0x1ce0 +#define RADEON_SCISSOR_BR_1 0x1ce4 +#define RADEON_SCISSOR_TL_2 0x1ce8 +#define RADEON_SCISSOR_BR_2 0x1cec +#define RADEON_SE_COORD_FMT 0x1c50 +#define RADEON_SE_CNTL 0x1c4c +# define RADEON_FFACE_CULL_CW (0 << 0) +# define RADEON_BFACE_SOLID (3 << 1) +# define RADEON_FFACE_SOLID (3 << 3) +# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) +# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) +# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) +# define RADEON_ALPHA_SHADE_FLAT (1 << 10) +# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) +# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) +# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) +# define RADEON_FOG_SHADE_FLAT (1 << 14) +# define RADEON_FOG_SHADE_GOURAUD (2 << 14) +# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) +# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) +# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) +# define RADEON_ROUND_MODE_TRUNC (0 << 28) +# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) +#define RADEON_SE_CNTL_STATUS 0x2140 +#define RADEON_SE_LINE_WIDTH 0x1db8 +#define RADEON_SE_VPORT_XSCALE 0x1d98 +#define RADEON_SE_ZBIAS_FACTOR 0x1db0 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 +#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 +#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 +# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 +# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 +#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 +#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 +# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 +#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C +#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 +#define RADEON_SURFACE_ACCESS_CLR 0x0bfc +#define RADEON_SURFACE_CNTL 0x0b00 +# define RADEON_SURF_TRANSLATION_DIS (1 << 8) +# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) +# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) +# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) +# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) +# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) +# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) +# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) +# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) +#define RADEON_SURFACE0_INFO 0x0b0c +# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) +# define RADEON_SURF_TILE_MODE_MASK (3 << 16) +# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) +# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) +# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) +# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) +#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 +#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 +# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) +#define RADEON_SURFACE1_INFO 0x0b1c +#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 +#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 +#define RADEON_SURFACE2_INFO 0x0b2c +#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 +#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 +#define RADEON_SURFACE3_INFO 0x0b3c +#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 +#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 +#define RADEON_SURFACE4_INFO 0x0b4c +#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 +#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 +#define RADEON_SURFACE5_INFO 0x0b5c +#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 +#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 +#define RADEON_SURFACE6_INFO 0x0b6c +#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 +#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 +#define RADEON_SURFACE7_INFO 0x0b7c +#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 +#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 +#define RADEON_SW_SEMAPHORE 0x013c + +#define RADEON_WAIT_UNTIL 0x1720 +# define RADEON_WAIT_CRTC_PFLIP (1 << 0) +# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) +# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) +# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) + +#define RADEON_RB3D_ZMASKOFFSET 0x3234 +#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c +# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) + + +/* CP registers */ +#define RADEON_CP_ME_RAM_ADDR 0x07d4 +#define RADEON_CP_ME_RAM_RADDR 0x07d8 +#define RADEON_CP_ME_RAM_DATAH 0x07dc +#define RADEON_CP_ME_RAM_DATAL 0x07e0 + +#define RADEON_CP_RB_BASE 0x0700 +#define RADEON_CP_RB_CNTL 0x0704 +# define RADEON_BUF_SWAP_32BIT (2 << 16) +#define RADEON_CP_RB_RPTR_ADDR 0x070c +#define RADEON_CP_RB_RPTR 0x0710 +#define RADEON_CP_RB_WPTR 0x0714 + +#define RADEON_CP_RB_WPTR_DELAY 0x0718 +# define RADEON_PRE_WRITE_TIMER_SHIFT 0 +# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 + +#define RADEON_CP_IB_BASE 0x0738 + +#define RADEON_CP_CSQ_CNTL 0x0740 +# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) +# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) +# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) +# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) +# define RADEON_CSQ_PRIBM_INDBM (4 << 28) +# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) + +#define RADEON_AIC_CNTL 0x01d0 +# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) +#define RADEON_AIC_STAT 0x01d4 +#define RADEON_AIC_PT_BASE 0x01d8 +#define RADEON_AIC_LO_ADDR 0x01dc +#define RADEON_AIC_HI_ADDR 0x01e0 +#define RADEON_AIC_TLB_ADDR 0x01e4 +#define RADEON_AIC_TLB_DATA 0x01e8 + +/* CP command packets */ +#define RADEON_CP_PACKET0 0x00000000 +# define RADEON_ONE_REG_WR (1 << 15) +#define RADEON_CP_PACKET1 0x40000000 +#define RADEON_CP_PACKET2 0x80000000 +#define RADEON_CP_PACKET3 0xC0000000 +# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 +# define RADEON_WAIT_FOR_IDLE 0x00002600 +# define RADEON_3D_DRAW_VBUF 0x00002800 +# define RADEON_3D_DRAW_IMMD 0x00002900 +# define RADEON_3D_DRAW_INDX 0x00002A00 +# define RADEON_3D_LOAD_VBPNTR 0x00002F00 +# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 +# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 +# define RADEON_3D_CLEAR_ZMASK 0x00003200 +# define RADEON_3D_CLEAR_HIZ 0x00003700 +# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 +# define RADEON_CNTL_PAINT_MULTI 0x00009A00 +# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 +# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 + +#define RADEON_CP_PACKET_MASK 0xC0000000 +#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 +#define RADEON_CP_PACKET0_REG_MASK 0x000007ff +#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff +#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 + +#define RADEON_VTX_Z_PRESENT (1 << 31) +#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) + +#define RADEON_PRIM_TYPE_NONE (0 << 0) +#define RADEON_PRIM_TYPE_POINT (1 << 0) +#define RADEON_PRIM_TYPE_LINE (2 << 0) +#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) +#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) +#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) +#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) +#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) +#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) +#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) +#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) +#define RADEON_PRIM_TYPE_MASK 0xf +#define RADEON_PRIM_WALK_IND (1 << 4) +#define RADEON_PRIM_WALK_LIST (2 << 4) +#define RADEON_PRIM_WALK_RING (3 << 4) +#define RADEON_COLOR_ORDER_BGRA (0 << 6) +#define RADEON_COLOR_ORDER_RGBA (1 << 6) +#define RADEON_MAOS_ENABLE (1 << 7) +#define RADEON_VTX_FMT_R128_MODE (0 << 8) +#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) +#define RADEON_NUM_VERTICES_SHIFT 16 + +#define RADEON_COLOR_FORMAT_CI8 2 +#define RADEON_COLOR_FORMAT_ARGB1555 3 +#define RADEON_COLOR_FORMAT_RGB565 4 +#define RADEON_COLOR_FORMAT_ARGB8888 6 +#define RADEON_COLOR_FORMAT_RGB332 7 +#define RADEON_COLOR_FORMAT_RGB8 9 +#define RADEON_COLOR_FORMAT_ARGB4444 15 + +#define RADEON_TXFORMAT_I8 0 +#define RADEON_TXFORMAT_AI88 1 +#define RADEON_TXFORMAT_RGB332 2 +#define RADEON_TXFORMAT_ARGB1555 3 +#define RADEON_TXFORMAT_RGB565 4 +#define RADEON_TXFORMAT_ARGB4444 5 +#define RADEON_TXFORMAT_ARGB8888 6 +#define RADEON_TXFORMAT_RGBA8888 7 +#define RADEON_TXFORMAT_Y8 8 +#define RADEON_TXFORMAT_VYUY422 10 +#define RADEON_TXFORMAT_YVYU422 11 +#define RADEON_TXFORMAT_DXT1 12 +#define RADEON_TXFORMAT_DXT23 14 +#define RADEON_TXFORMAT_DXT45 15 + +#define R200_PP_TXCBLEND_0 0x2f00 +#define R200_PP_TXCBLEND_1 0x2f10 +#define R200_PP_TXCBLEND_2 0x2f20 +#define R200_PP_TXCBLEND_3 0x2f30 +#define R200_PP_TXCBLEND_4 0x2f40 +#define R200_PP_TXCBLEND_5 0x2f50 +#define R200_PP_TXCBLEND_6 0x2f60 +#define R200_PP_TXCBLEND_7 0x2f70 +#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 +#define R200_PP_TFACTOR_0 0x2ee0 +#define R200_SE_VTX_FMT_0 0x2088 +#define R200_SE_VAP_CNTL 0x2080 +#define R200_SE_TCL_MATRIX_SEL_0 0x2230 +#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 +#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 +#define R200_PP_TXFILTER_5 0x2ca0 +#define R200_PP_TXFILTER_4 0x2c80 +#define R200_PP_TXFILTER_3 0x2c60 +#define R200_PP_TXFILTER_2 0x2c40 +#define R200_PP_TXFILTER_1 0x2c20 +#define R200_PP_TXFILTER_0 0x2c00 +#define R200_PP_TXOFFSET_5 0x2d78 +#define R200_PP_TXOFFSET_4 0x2d60 +#define R200_PP_TXOFFSET_3 0x2d48 +#define R200_PP_TXOFFSET_2 0x2d30 +#define R200_PP_TXOFFSET_1 0x2d18 +#define R200_PP_TXOFFSET_0 0x2d00 + +#define R200_PP_CUBIC_FACES_0 0x2c18 +#define R200_PP_CUBIC_FACES_1 0x2c38 +#define R200_PP_CUBIC_FACES_2 0x2c58 +#define R200_PP_CUBIC_FACES_3 0x2c78 +#define R200_PP_CUBIC_FACES_4 0x2c98 +#define R200_PP_CUBIC_FACES_5 0x2cb8 +#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 +#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 +#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c +#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 +#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 +#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c +#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 +#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 +#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 +#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c +#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 +#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 +#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c +#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 +#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 +#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c +#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 +#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 +#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 +#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c +#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 +#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 +#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c +#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 +#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 +#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c +#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 +#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 +#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 +#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c + +#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 +#define R200_SE_VTE_CNTL 0x20b0 +#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 +#define R200_PP_TAM_DEBUG3 0x2d9c +#define R200_PP_CNTL_X 0x2cc4 +#define R200_SE_VAP_CNTL_STATUS 0x2140 +#define R200_RE_SCISSOR_TL_0 0x1cd8 +#define R200_RE_SCISSOR_TL_1 0x1ce0 +#define R200_RE_SCISSOR_TL_2 0x1ce8 +#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 +#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 +#define R200_SE_VTX_STATE_CNTL 0x2180 +#define R200_RE_POINTSIZE 0x2648 +#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 + +#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ +#define RADEON_PP_TEX_SIZE_1 0x1d0c +#define RADEON_PP_TEX_SIZE_2 0x1d14 + +#define RADEON_PP_CUBIC_FACES_0 0x1d24 +#define RADEON_PP_CUBIC_FACES_1 0x1d28 +#define RADEON_PP_CUBIC_FACES_2 0x1d2c +#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ +#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 +#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 + +#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 +#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 +#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 +#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 +#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 +#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 +#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 +#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b +#define R200_3D_DRAW_IMMD_2 0xC0003500 +#define R200_SE_VTX_FMT_1 0x208c +#define R200_RE_CNTL 0x1c50 + +#define R200_RB3D_BLENDCOLOR 0x3218 + +#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 + +#define R200_PP_TRI_PERF 0x2cf8 + +/* Constants */ +#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ + +#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 +#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 +#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 +#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 +#define RADEON_LAST_DISPATCH 1 + +#define RADEON_MAX_VB_AGE 0x7fffffff +#define RADEON_MAX_VB_VERTS (0xffff) + +#define RADEON_RING_HIGH_MARK 128 + +#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) +#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) +#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) +#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) + +#define RADEON_WRITE_PLL( addr, val ) \ +do { \ + RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ + ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ + RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ +} while (0) + +#define CP_PACKET0( reg, n ) \ + (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) +#define CP_PACKET0_TABLE( reg, n ) \ + (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) +#define CP_PACKET1( reg0, reg1 ) \ + (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) +#define CP_PACKET2() \ + (RADEON_CP_PACKET2) +#define CP_PACKET3( pkt, n ) \ + (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) + + +/* ================================================================ + * Engine control helper macros + */ + +#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ + OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ + OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ + RADEON_WAIT_HOST_IDLECLEAN) ); \ +} while (0) + +#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ + OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ + OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ + RADEON_WAIT_HOST_IDLECLEAN) ); \ +} while (0) + +#define RADEON_WAIT_UNTIL_IDLE() do { \ + OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ + OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ + RADEON_WAIT_3D_IDLECLEAN | \ + RADEON_WAIT_HOST_IDLECLEAN) ); \ +} while (0) + +#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ + OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ + OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ +} while (0) + +#define RADEON_FLUSH_CACHE() do { \ + OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ + OUT_RING( RADEON_RB2D_DC_FLUSH ); \ +} while (0) + +#define RADEON_PURGE_CACHE() do { \ + OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ + OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ +} while (0) + +#define RADEON_FLUSH_ZCACHE() do { \ + OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ + OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ +} while (0) + +#define RADEON_PURGE_ZCACHE() do { \ + OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ + OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ +} while (0) + + +/* ================================================================ + * Misc helper macros + */ + +/* Perfbox functionality only. + */ +#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ +do { \ + if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ + u32 head = GET_RING_HEAD( dev_priv ); \ + if (head == dev_priv->ring.tail) \ + dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ + } \ +} while (0) + +#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ +do { \ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ + if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ + int __ret = radeon_do_cp_idle( dev_priv ); \ + if ( __ret ) return __ret; \ + sarea_priv->last_dispatch = 0; \ + radeon_freelist_reset( dev ); \ + } \ +} while (0) + +#define RADEON_DISPATCH_AGE( age ) do { \ + OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ + OUT_RING( age ); \ +} while (0) + +#define RADEON_FRAME_AGE( age ) do { \ + OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ + OUT_RING( age ); \ +} while (0) + +#define RADEON_CLEAR_AGE( age ) do { \ + OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ + OUT_RING( age ); \ +} while (0) + + +/* ================================================================ + * Ring control + */ + +#define RADEON_VERBOSE 0 + +#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; + +#define BEGIN_RING( n ) do { \ + if ( RADEON_VERBOSE ) { \ + DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ + n, __FUNCTION__ ); \ + } \ + if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ + COMMIT_RING(); \ + radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ + } \ + _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ + ring = dev_priv->ring.start; \ + write = dev_priv->ring.tail; \ + mask = dev_priv->ring.tail_mask; \ +} while (0) + +#define ADVANCE_RING() do { \ + if ( RADEON_VERBOSE ) { \ + DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ + write, dev_priv->ring.tail ); \ + } \ + if (((dev_priv->ring.tail + _nr) & mask) != write) { \ + DRM_ERROR( \ + "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ + ((dev_priv->ring.tail + _nr) & mask), \ + write, __LINE__); \ + } else \ + dev_priv->ring.tail = write; \ +} while (0) + +#define COMMIT_RING() do { \ + /* Flush writes to ring */ \ + DRM_MEMORYBARRIER(); \ + GET_RING_HEAD( dev_priv ); \ + RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ + /* read from PCI bus to ensure correct posting */ \ + RADEON_READ( RADEON_CP_RB_RPTR ); \ +} while (0) + +#define OUT_RING( x ) do { \ + if ( RADEON_VERBOSE ) { \ + DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ + (unsigned int)(x), write ); \ + } \ + ring[write++] = (x); \ + write &= mask; \ +} while (0) + +#define OUT_RING_REG( reg, val ) do { \ + OUT_RING( CP_PACKET0( reg, 0 ) ); \ + OUT_RING( val ); \ +} while (0) + + +#define OUT_RING_TABLE( tab, sz ) do { \ + int _size = (sz); \ + int *_tab = (int *)(tab); \ + \ + if (write + _size > mask) { \ + int _i = (mask+1) - write; \ + _size -= _i; \ + while (_i > 0 ) { \ + *(int *)(ring + write) = *_tab++; \ + write++; \ + _i--; \ + } \ + write = 0; \ + _tab += _i; \ + } \ + \ + while (_size > 0) { \ + *(ring + write) = *_tab++; \ + write++; \ + _size--; \ + } \ + write &= mask; \ +} while (0) + + +#endif /* __RADEON_DRV_H__ */ diff --git a/drivers/char/drm/radeon_irq.c b/drivers/char/drm/radeon_irq.c new file mode 100644 index 000000000000..5b18bee6492e --- /dev/null +++ b/drivers/char/drm/radeon_irq.c @@ -0,0 +1,251 @@ +/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- + * + * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + * + * The Weather Channel (TM) funded Tungsten Graphics to develop the + * initial release of the Radeon 8500 driver under the XFree86 license. + * This notice must be preserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Keith Whitwell + * Michel D�zer + */ + +#include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" +#include "radeon_drv.h" + +/* Interrupts - Used for device synchronization and flushing in the + * following circumstances: + * + * - Exclusive FB access with hw idle: + * - Wait for GUI Idle (?) interrupt, then do normal flush. + * + * - Frame throttling, NV_fence: + * - Drop marker irq's into command stream ahead of time. + * - Wait on irq's with lock *not held* + * - Check each for termination condition + * + * - Internally in cp_getbuffer, etc: + * - as above, but wait with lock held??? + * + * NOTE: These functions are misleadingly named -- the irq's aren't + * tied to dma at all, this is just a hangover from dri prehistory. + */ + +irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS ) +{ + drm_device_t *dev = (drm_device_t *) arg; + drm_radeon_private_t *dev_priv = + (drm_radeon_private_t *)dev->dev_private; + u32 stat; + + /* Only consider the bits we're interested in - others could be used + * outside the DRM + */ + stat = RADEON_READ(RADEON_GEN_INT_STATUS) + & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT); + if (!stat) + return IRQ_NONE; + + /* SW interrupt */ + if (stat & RADEON_SW_INT_TEST) { + DRM_WAKEUP( &dev_priv->swi_queue ); + } + + /* VBLANK interrupt */ + if (stat & RADEON_CRTC_VBLANK_STAT) { + atomic_inc(&dev->vbl_received); + DRM_WAKEUP(&dev->vbl_queue); + drm_vbl_send_signals( dev ); + } + + /* Acknowledge interrupts we handle */ + RADEON_WRITE(RADEON_GEN_INT_STATUS, stat); + return IRQ_HANDLED; +} + +static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv) +{ + u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS ) + & (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT); + if (tmp) + RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp ); +} + +static int radeon_emit_irq(drm_device_t *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + unsigned int ret; + RING_LOCALS; + + atomic_inc(&dev_priv->swi_emitted); + ret = atomic_read(&dev_priv->swi_emitted); + + BEGIN_RING( 4 ); + OUT_RING_REG( RADEON_LAST_SWI_REG, ret ); + OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE ); + ADVANCE_RING(); + COMMIT_RING(); + + return ret; +} + + +static int radeon_wait_irq(drm_device_t *dev, int swi_nr) +{ + drm_radeon_private_t *dev_priv = + (drm_radeon_private_t *)dev->dev_private; + int ret = 0; + + if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr) + return 0; + + dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; + + /* This is a hack to work around mysterious freezes on certain + * systems: + */ + radeon_acknowledge_irqs( dev_priv ); + + DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ, + RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr ); + + return ret; +} + +int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) +{ + drm_radeon_private_t *dev_priv = + (drm_radeon_private_t *)dev->dev_private; + unsigned int cur_vblank; + int ret = 0; + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + radeon_acknowledge_irqs( dev_priv ); + + dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; + + /* Assume that the user has missed the current sequence number + * by about a day rather than she wants to wait for years + * using vertical blanks... + */ + DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, + ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) + - *sequence ) <= (1<<23) ) ); + + *sequence = cur_vblank; + + return ret; +} + + +/* Needs the lock as it touches the ring. + */ +int radeon_irq_emit( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_irq_emit_t emit; + int result; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t __user *)data, + sizeof(emit) ); + + result = radeon_emit_irq( dev ); + + if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) { + DRM_ERROR( "copy_to_user\n" ); + return DRM_ERR(EFAULT); + } + + return 0; +} + + +/* Doesn't need the hardware lock. + */ +int radeon_irq_wait( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_irq_wait_t irqwait; + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t __user*)data, + sizeof(irqwait) ); + + return radeon_wait_irq( dev, irqwait.irq_seq ); +} + + +/* drm_dma.h hooks +*/ +void radeon_driver_irq_preinstall( drm_device_t *dev ) { + drm_radeon_private_t *dev_priv = + (drm_radeon_private_t *)dev->dev_private; + + /* Disable *all* interrupts */ + RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); + + /* Clear bits if they're already high */ + radeon_acknowledge_irqs( dev_priv ); +} + +void radeon_driver_irq_postinstall( drm_device_t *dev ) { + drm_radeon_private_t *dev_priv = + (drm_radeon_private_t *)dev->dev_private; + + atomic_set(&dev_priv->swi_emitted, 0); + DRM_INIT_WAITQUEUE( &dev_priv->swi_queue ); + + /* Turn on SW and VBL ints */ + RADEON_WRITE( RADEON_GEN_INT_CNTL, + RADEON_CRTC_VBLANK_MASK | + RADEON_SW_INT_ENABLE ); +} + +void radeon_driver_irq_uninstall( drm_device_t *dev ) { + drm_radeon_private_t *dev_priv = + (drm_radeon_private_t *)dev->dev_private; + if (!dev_priv) + return; + + /* Disable *all* interrupts */ + RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); +} diff --git a/drivers/char/drm/radeon_mem.c b/drivers/char/drm/radeon_mem.c new file mode 100644 index 000000000000..134f894e6e4b --- /dev/null +++ b/drivers/char/drm/radeon_mem.c @@ -0,0 +1,322 @@ +/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*- + * + * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + * + * The Weather Channel (TM) funded Tungsten Graphics to develop the + * initial release of the Radeon 8500 driver under the XFree86 license. + * This notice must be preserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Keith Whitwell + */ + +#include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" +#include "radeon_drv.h" + +/* Very simple allocator for GART memory, working on a static range + * already mapped into each client's address space. + */ + +static struct mem_block *split_block(struct mem_block *p, int start, int size, + DRMFILE filp ) +{ + /* Maybe cut off the start of an existing block */ + if (start > p->start) { + struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFS ); + if (!newblock) + goto out; + newblock->start = start; + newblock->size = p->size - (start - p->start); + newblock->filp = NULL; + newblock->next = p->next; + newblock->prev = p; + p->next->prev = newblock; + p->next = newblock; + p->size -= newblock->size; + p = newblock; + } + + /* Maybe cut off the end of an existing block */ + if (size < p->size) { + struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFS ); + if (!newblock) + goto out; + newblock->start = start + size; + newblock->size = p->size - size; + newblock->filp = NULL; + newblock->next = p->next; + newblock->prev = p; + p->next->prev = newblock; + p->next = newblock; + p->size = size; + } + + out: + /* Our block is in the middle */ + p->filp = filp; + return p; +} + +static struct mem_block *alloc_block( struct mem_block *heap, int size, + int align2, DRMFILE filp ) +{ + struct mem_block *p; + int mask = (1 << align2)-1; + + list_for_each(p, heap) { + int start = (p->start + mask) & ~mask; + if (p->filp == 0 && start + size <= p->start + p->size) + return split_block( p, start, size, filp ); + } + + return NULL; +} + +static struct mem_block *find_block( struct mem_block *heap, int start ) +{ + struct mem_block *p; + + list_for_each(p, heap) + if (p->start == start) + return p; + + return NULL; +} + + +static void free_block( struct mem_block *p ) +{ + p->filp = NULL; + + /* Assumes a single contiguous range. Needs a special filp in + * 'heap' to stop it being subsumed. + */ + if (p->next->filp == 0) { + struct mem_block *q = p->next; + p->size += q->size; + p->next = q->next; + p->next->prev = p; + drm_free(q, sizeof(*q), DRM_MEM_BUFS ); + } + + if (p->prev->filp == 0) { + struct mem_block *q = p->prev; + q->size += p->size; + q->next = p->next; + q->next->prev = q; + drm_free(p, sizeof(*q), DRM_MEM_BUFS ); + } +} + +/* Initialize. How to check for an uninitialized heap? + */ +static int init_heap(struct mem_block **heap, int start, int size) +{ + struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS ); + + if (!blocks) + return DRM_ERR(ENOMEM); + + *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS ); + if (!*heap) { + drm_free( blocks, sizeof(*blocks), DRM_MEM_BUFS ); + return DRM_ERR(ENOMEM); + } + + blocks->start = start; + blocks->size = size; + blocks->filp = NULL; + blocks->next = blocks->prev = *heap; + + memset( *heap, 0, sizeof(**heap) ); + (*heap)->filp = (DRMFILE) -1; + (*heap)->next = (*heap)->prev = blocks; + return 0; +} + + +/* Free all blocks associated with the releasing file. + */ +void radeon_mem_release( DRMFILE filp, struct mem_block *heap ) +{ + struct mem_block *p; + + if (!heap || !heap->next) + return; + + list_for_each(p, heap) { + if (p->filp == filp) + p->filp = NULL; + } + + /* Assumes a single contiguous range. Needs a special filp in + * 'heap' to stop it being subsumed. + */ + list_for_each(p, heap) { + while (p->filp == 0 && p->next->filp == 0) { + struct mem_block *q = p->next; + p->size += q->size; + p->next = q->next; + p->next->prev = p; + drm_free(q, sizeof(*q),DRM_MEM_DRIVER); + } + } +} + +/* Shutdown. + */ +void radeon_mem_takedown( struct mem_block **heap ) +{ + struct mem_block *p; + + if (!*heap) + return; + + for (p = (*heap)->next ; p != *heap ; ) { + struct mem_block *q = p; + p = p->next; + drm_free(q, sizeof(*q),DRM_MEM_DRIVER); + } + + drm_free( *heap, sizeof(**heap),DRM_MEM_DRIVER ); + *heap = NULL; +} + + + +/* IOCTL HANDLERS */ + +static struct mem_block **get_heap( drm_radeon_private_t *dev_priv, + int region ) +{ + switch( region ) { + case RADEON_MEM_REGION_GART: + return &dev_priv->gart_heap; + case RADEON_MEM_REGION_FB: + return &dev_priv->fb_heap; + default: + return NULL; + } +} + +int radeon_mem_alloc( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_mem_alloc_t alloc; + struct mem_block *block, **heap; + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL( alloc, (drm_radeon_mem_alloc_t __user *)data, + sizeof(alloc) ); + + heap = get_heap( dev_priv, alloc.region ); + if (!heap || !*heap) + return DRM_ERR(EFAULT); + + /* Make things easier on ourselves: all allocations at least + * 4k aligned. + */ + if (alloc.alignment < 12) + alloc.alignment = 12; + + block = alloc_block( *heap, alloc.size, alloc.alignment, + filp ); + + if (!block) + return DRM_ERR(ENOMEM); + + if ( DRM_COPY_TO_USER( alloc.region_offset, &block->start, + sizeof(int) ) ) { + DRM_ERROR( "copy_to_user\n" ); + return DRM_ERR(EFAULT); + } + + return 0; +} + + + +int radeon_mem_free( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_mem_free_t memfree; + struct mem_block *block, **heap; + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL( memfree, (drm_radeon_mem_free_t __user *)data, + sizeof(memfree) ); + + heap = get_heap( dev_priv, memfree.region ); + if (!heap || !*heap) + return DRM_ERR(EFAULT); + + block = find_block( *heap, memfree.region_offset ); + if (!block) + return DRM_ERR(EFAULT); + + if (block->filp != filp) + return DRM_ERR(EPERM); + + free_block( block ); + return 0; +} + +int radeon_mem_init_heap( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_mem_init_heap_t initheap; + struct mem_block **heap; + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL( initheap, (drm_radeon_mem_init_heap_t __user *)data, + sizeof(initheap) ); + + heap = get_heap( dev_priv, initheap.region ); + if (!heap) + return DRM_ERR(EFAULT); + + if (*heap) { + DRM_ERROR("heap already initialized?"); + return DRM_ERR(EFAULT); + } + + return init_heap( heap, initheap.start, initheap.size ); +} + + diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c new file mode 100644 index 000000000000..1f79e249146c --- /dev/null +++ b/drivers/char/drm/radeon_state.c @@ -0,0 +1,3102 @@ +/* radeon_state.c -- State support for Radeon -*- linux-c -*- + * + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Gareth Hughes + * Kevin E. Martin + */ + +#include "drmP.h" +#include "drm.h" +#include "drm_sarea.h" +#include "radeon_drm.h" +#include "radeon_drv.h" + +/* ================================================================ + * Helper functions for client state checking and fixup + */ + +static __inline__ int radeon_check_and_fixup_offset( drm_radeon_private_t *dev_priv, + drm_file_t *filp_priv, + u32 *offset ) { + u32 off = *offset; + struct drm_radeon_driver_file_fields *radeon_priv; + + if ( off >= dev_priv->fb_location && + off < ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) + return 0; + + radeon_priv = filp_priv->driver_priv; + off += radeon_priv->radeon_fb_delta; + + DRM_DEBUG( "offset fixed up to 0x%x\n", off ); + + if ( off < dev_priv->fb_location || + off >= ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) + return DRM_ERR( EINVAL ); + + *offset = off; + + return 0; +} + +static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_priv, + drm_file_t *filp_priv, + int id, + u32 __user *data ) { + switch ( id ) { + + case RADEON_EMIT_PP_MISC: + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, + &data[( RADEON_RB3D_DEPTHOFFSET + - RADEON_PP_MISC ) / 4] ) ) { + DRM_ERROR( "Invalid depth buffer offset\n" ); + return DRM_ERR( EINVAL ); + } + break; + + case RADEON_EMIT_PP_CNTL: + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, + &data[( RADEON_RB3D_COLOROFFSET + - RADEON_PP_CNTL ) / 4] ) ) { + DRM_ERROR( "Invalid colour buffer offset\n" ); + return DRM_ERR( EINVAL ); + } + break; + + case R200_EMIT_PP_TXOFFSET_0: + case R200_EMIT_PP_TXOFFSET_1: + case R200_EMIT_PP_TXOFFSET_2: + case R200_EMIT_PP_TXOFFSET_3: + case R200_EMIT_PP_TXOFFSET_4: + case R200_EMIT_PP_TXOFFSET_5: + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, + &data[0] ) ) { + DRM_ERROR( "Invalid R200 texture offset\n" ); + return DRM_ERR( EINVAL ); + } + break; + + case RADEON_EMIT_PP_TXFILTER_0: + case RADEON_EMIT_PP_TXFILTER_1: + case RADEON_EMIT_PP_TXFILTER_2: + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, + &data[( RADEON_PP_TXOFFSET_0 + - RADEON_PP_TXFILTER_0 ) / 4] ) ) { + DRM_ERROR( "Invalid R100 texture offset\n" ); + return DRM_ERR( EINVAL ); + } + break; + + case R200_EMIT_PP_CUBIC_OFFSETS_0: + case R200_EMIT_PP_CUBIC_OFFSETS_1: + case R200_EMIT_PP_CUBIC_OFFSETS_2: + case R200_EMIT_PP_CUBIC_OFFSETS_3: + case R200_EMIT_PP_CUBIC_OFFSETS_4: + case R200_EMIT_PP_CUBIC_OFFSETS_5: { + int i; + for ( i = 0; i < 5; i++ ) { + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, + &data[i] ) ) { + DRM_ERROR( "Invalid R200 cubic texture offset\n" ); + return DRM_ERR( EINVAL ); + } + } + break; + } + + case RADEON_EMIT_PP_CUBIC_OFFSETS_T0: + case RADEON_EMIT_PP_CUBIC_OFFSETS_T1: + case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{ + int i; + for (i = 0; i < 5; i++) { + if (radeon_check_and_fixup_offset(dev_priv, + filp_priv, + &data[i])) { + DRM_ERROR + ("Invalid R100 cubic texture offset\n"); + return DRM_ERR(EINVAL); + } + } + } + break; + + case RADEON_EMIT_RB3D_COLORPITCH: + case RADEON_EMIT_RE_LINE_PATTERN: + case RADEON_EMIT_SE_LINE_WIDTH: + case RADEON_EMIT_PP_LUM_MATRIX: + case RADEON_EMIT_PP_ROT_MATRIX_0: + case RADEON_EMIT_RB3D_STENCILREFMASK: + case RADEON_EMIT_SE_VPORT_XSCALE: + case RADEON_EMIT_SE_CNTL: + case RADEON_EMIT_SE_CNTL_STATUS: + case RADEON_EMIT_RE_MISC: + case RADEON_EMIT_PP_BORDER_COLOR_0: + case RADEON_EMIT_PP_BORDER_COLOR_1: + case RADEON_EMIT_PP_BORDER_COLOR_2: + case RADEON_EMIT_SE_ZBIAS_FACTOR: + case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT: + case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED: + case R200_EMIT_PP_TXCBLEND_0: + case R200_EMIT_PP_TXCBLEND_1: + case R200_EMIT_PP_TXCBLEND_2: + case R200_EMIT_PP_TXCBLEND_3: + case R200_EMIT_PP_TXCBLEND_4: + case R200_EMIT_PP_TXCBLEND_5: + case R200_EMIT_PP_TXCBLEND_6: + case R200_EMIT_PP_TXCBLEND_7: + case R200_EMIT_TCL_LIGHT_MODEL_CTL_0: + case R200_EMIT_TFACTOR_0: + case R200_EMIT_VTX_FMT_0: + case R200_EMIT_VAP_CTL: + case R200_EMIT_MATRIX_SELECT_0: + case R200_EMIT_TEX_PROC_CTL_2: + case R200_EMIT_TCL_UCP_VERT_BLEND_CTL: + case R200_EMIT_PP_TXFILTER_0: + case R200_EMIT_PP_TXFILTER_1: + case R200_EMIT_PP_TXFILTER_2: + case R200_EMIT_PP_TXFILTER_3: + case R200_EMIT_PP_TXFILTER_4: + case R200_EMIT_PP_TXFILTER_5: + case R200_EMIT_VTE_CNTL: + case R200_EMIT_OUTPUT_VTX_COMP_SEL: + case R200_EMIT_PP_TAM_DEBUG3: + case R200_EMIT_PP_CNTL_X: + case R200_EMIT_RB3D_DEPTHXY_OFFSET: + case R200_EMIT_RE_AUX_SCISSOR_CNTL: + case R200_EMIT_RE_SCISSOR_TL_0: + case R200_EMIT_RE_SCISSOR_TL_1: + case R200_EMIT_RE_SCISSOR_TL_2: + case R200_EMIT_SE_VAP_CNTL_STATUS: + case R200_EMIT_SE_VTX_STATE_CNTL: + case R200_EMIT_RE_POINTSIZE: + case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0: + case R200_EMIT_PP_CUBIC_FACES_0: + case R200_EMIT_PP_CUBIC_FACES_1: + case R200_EMIT_PP_CUBIC_FACES_2: + case R200_EMIT_PP_CUBIC_FACES_3: + case R200_EMIT_PP_CUBIC_FACES_4: + case R200_EMIT_PP_CUBIC_FACES_5: + case RADEON_EMIT_PP_TEX_SIZE_0: + case RADEON_EMIT_PP_TEX_SIZE_1: + case RADEON_EMIT_PP_TEX_SIZE_2: + case R200_EMIT_RB3D_BLENDCOLOR: + case R200_EMIT_TCL_POINT_SPRITE_CNTL: + case RADEON_EMIT_PP_CUBIC_FACES_0: + case RADEON_EMIT_PP_CUBIC_FACES_1: + case RADEON_EMIT_PP_CUBIC_FACES_2: + case R200_EMIT_PP_TRI_PERF_CNTL: + /* These packets don't contain memory offsets */ + break; + + default: + DRM_ERROR( "Unknown state packet ID %d\n", id ); + return DRM_ERR( EINVAL ); + } + + return 0; +} + +static __inline__ int radeon_check_and_fixup_packet3( drm_radeon_private_t *dev_priv, + drm_file_t *filp_priv, + drm_radeon_cmd_buffer_t *cmdbuf, + unsigned int *cmdsz ) { + u32 *cmd = (u32 *) cmdbuf->buf; + + *cmdsz = 2 + ( ( cmd[0] & RADEON_CP_PACKET_COUNT_MASK ) >> 16 ); + + if ( ( cmd[0] & 0xc0000000 ) != RADEON_CP_PACKET3 ) { + DRM_ERROR( "Not a type 3 packet\n" ); + return DRM_ERR( EINVAL ); + } + + if ( 4 * *cmdsz > cmdbuf->bufsz ) { + DRM_ERROR( "Packet size larger than size of data provided\n" ); + return DRM_ERR( EINVAL ); + } + + /* Check client state and fix it up if necessary */ + if ( cmd[0] & 0x8000 ) { /* MSB of opcode: next DWORD GUI_CNTL */ + u32 offset; + + if ( cmd[1] & ( RADEON_GMC_SRC_PITCH_OFFSET_CNTL + | RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { + offset = cmd[2] << 10; + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { + DRM_ERROR( "Invalid first packet offset\n" ); + return DRM_ERR( EINVAL ); + } + cmd[2] = ( cmd[2] & 0xffc00000 ) | offset >> 10; + } + + if ( ( cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL ) && + ( cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { + offset = cmd[3] << 10; + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { + DRM_ERROR( "Invalid second packet offset\n" ); + return DRM_ERR( EINVAL ); + } + cmd[3] = ( cmd[3] & 0xffc00000 ) | offset >> 10; + } + } + + return 0; +} + + +/* ================================================================ + * CP hardware state programming functions + */ + +static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv, + drm_clip_rect_t *box ) +{ + RING_LOCALS; + + DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n", + box->x1, box->y1, box->x2, box->y2 ); + + BEGIN_RING( 4 ); + OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) ); + OUT_RING( (box->y1 << 16) | box->x1 ); + OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) ); + OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) ); + ADVANCE_RING(); +} + +/* Emit 1.1 state + */ +static int radeon_emit_state( drm_radeon_private_t *dev_priv, + drm_file_t *filp_priv, + drm_radeon_context_regs_t *ctx, + drm_radeon_texture_regs_t *tex, + unsigned int dirty ) +{ + RING_LOCALS; + DRM_DEBUG( "dirty=0x%08x\n", dirty ); + + if ( dirty & RADEON_UPLOAD_CONTEXT ) { + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, + &ctx->rb3d_depthoffset ) ) { + DRM_ERROR( "Invalid depth buffer offset\n" ); + return DRM_ERR( EINVAL ); + } + + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, + &ctx->rb3d_coloroffset ) ) { + DRM_ERROR( "Invalid depth buffer offset\n" ); + return DRM_ERR( EINVAL ); + } + + BEGIN_RING( 14 ); + OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) ); + OUT_RING( ctx->pp_misc ); + OUT_RING( ctx->pp_fog_color ); + OUT_RING( ctx->re_solid_color ); + OUT_RING( ctx->rb3d_blendcntl ); + OUT_RING( ctx->rb3d_depthoffset ); + OUT_RING( ctx->rb3d_depthpitch ); + OUT_RING( ctx->rb3d_zstencilcntl ); + OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) ); + OUT_RING( ctx->pp_cntl ); + OUT_RING( ctx->rb3d_cntl ); + OUT_RING( ctx->rb3d_coloroffset ); + OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) ); + OUT_RING( ctx->rb3d_colorpitch ); + ADVANCE_RING(); + } + + if ( dirty & RADEON_UPLOAD_VERTFMT ) { + BEGIN_RING( 2 ); + OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) ); + OUT_RING( ctx->se_coord_fmt ); + ADVANCE_RING(); + } + + if ( dirty & RADEON_UPLOAD_LINE ) { + BEGIN_RING( 5 ); + OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) ); + OUT_RING( ctx->re_line_pattern ); + OUT_RING( ctx->re_line_state ); + OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) ); + OUT_RING( ctx->se_line_width ); + ADVANCE_RING(); + } + + if ( dirty & RADEON_UPLOAD_BUMPMAP ) { + BEGIN_RING( 5 ); + OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) ); + OUT_RING( ctx->pp_lum_matrix ); + OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) ); + OUT_RING( ctx->pp_rot_matrix_0 ); + OUT_RING( ctx->pp_rot_matrix_1 ); + ADVANCE_RING(); + } + + if ( dirty & RADEON_UPLOAD_MASKS ) { + BEGIN_RING( 4 ); + OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) ); + OUT_RING( ctx->rb3d_stencilrefmask ); + OUT_RING( ctx->rb3d_ropcntl ); + OUT_RING( ctx->rb3d_planemask ); + ADVANCE_RING(); + } + + if ( dirty & RADEON_UPLOAD_VIEWPORT ) { + BEGIN_RING( 7 ); + OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) ); + OUT_RING( ctx->se_vport_xscale ); + OUT_RING( ctx->se_vport_xoffset ); + OUT_RING( ctx->se_vport_yscale ); + OUT_RING( ctx->se_vport_yoffset ); + OUT_RING( ctx->se_vport_zscale ); + OUT_RING( ctx->se_vport_zoffset ); + ADVANCE_RING(); + } + + if ( dirty & RADEON_UPLOAD_SETUP ) { + BEGIN_RING( 4 ); + OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); + OUT_RING( ctx->se_cntl ); + OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) ); + OUT_RING( ctx->se_cntl_status ); + ADVANCE_RING(); + } + + if ( dirty & RADEON_UPLOAD_MISC ) { + BEGIN_RING( 2 ); + OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) ); + OUT_RING( ctx->re_misc ); + ADVANCE_RING(); + } + + if ( dirty & RADEON_UPLOAD_TEX0 ) { + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, + &tex[0].pp_txoffset ) ) { + DRM_ERROR( "Invalid texture offset for unit 0\n" ); + return DRM_ERR( EINVAL ); + } + + BEGIN_RING( 9 ); + OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) ); + OUT_RING( tex[0].pp_txfilter ); + OUT_RING( tex[0].pp_txformat ); + OUT_RING( tex[0].pp_txoffset ); + OUT_RING( tex[0].pp_txcblend ); + OUT_RING( tex[0].pp_txablend ); + OUT_RING( tex[0].pp_tfactor ); + OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) ); + OUT_RING( tex[0].pp_border_color ); + ADVANCE_RING(); + } + + if ( dirty & RADEON_UPLOAD_TEX1 ) { + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, + &tex[1].pp_txoffset ) ) { + DRM_ERROR( "Invalid texture offset for unit 1\n" ); + return DRM_ERR( EINVAL ); + } + + BEGIN_RING( 9 ); + OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) ); + OUT_RING( tex[1].pp_txfilter ); + OUT_RING( tex[1].pp_txformat ); + OUT_RING( tex[1].pp_txoffset ); + OUT_RING( tex[1].pp_txcblend ); + OUT_RING( tex[1].pp_txablend ); + OUT_RING( tex[1].pp_tfactor ); + OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) ); + OUT_RING( tex[1].pp_border_color ); + ADVANCE_RING(); + } + + if ( dirty & RADEON_UPLOAD_TEX2 ) { + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, + &tex[2].pp_txoffset ) ) { + DRM_ERROR( "Invalid texture offset for unit 2\n" ); + return DRM_ERR( EINVAL ); + } + + BEGIN_RING( 9 ); + OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) ); + OUT_RING( tex[2].pp_txfilter ); + OUT_RING( tex[2].pp_txformat ); + OUT_RING( tex[2].pp_txoffset ); + OUT_RING( tex[2].pp_txcblend ); + OUT_RING( tex[2].pp_txablend ); + OUT_RING( tex[2].pp_tfactor ); + OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) ); + OUT_RING( tex[2].pp_border_color ); + ADVANCE_RING(); + } + + return 0; +} + +/* Emit 1.2 state + */ +static int radeon_emit_state2( drm_radeon_private_t *dev_priv, + drm_file_t *filp_priv, + drm_radeon_state_t *state ) +{ + RING_LOCALS; + + if (state->dirty & RADEON_UPLOAD_ZBIAS) { + BEGIN_RING( 3 ); + OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) ); + OUT_RING( state->context2.se_zbias_factor ); + OUT_RING( state->context2.se_zbias_constant ); + ADVANCE_RING(); + } + + return radeon_emit_state( dev_priv, filp_priv, &state->context, + state->tex, state->dirty ); +} + +/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in + * 1.3 cmdbuffers allow all previous state to be updated as well as + * the tcl scalar and vector areas. + */ +static struct { + int start; + int len; + const char *name; +} packet[RADEON_MAX_STATE_PACKETS] = { + { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, + { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, + { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, + { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, + { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, + { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, + { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, + { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, + { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, + { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, + { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, + { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, + { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, + { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, + { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, + { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, + { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, + { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, + { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, + { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, + { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, + { R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" }, + { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" }, + { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" }, + { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" }, + { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" }, + { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" }, + { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" }, + { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" }, + { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, + { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" }, + { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" }, + { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" }, + { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" }, + { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" }, + { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, + { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" }, + { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" }, + { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" }, + { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" }, + { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" }, + { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" }, + { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" }, + { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" }, + { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" }, + { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" }, + { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" }, + { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" }, + { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" }, + { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, + { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" }, + { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, + { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, + { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, + { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, + { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, + { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, + { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, + { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, + { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, + { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, + { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */ + { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */ + { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" }, + { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" }, + { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" }, + { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" }, + { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" }, + { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" }, + { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" }, + { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" }, + { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" }, + { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, + { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, + { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, + { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, + { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, + { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" }, + { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, + { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, + { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, + { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, + { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, + { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, + { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, +}; + + + +/* ================================================================ + * Performance monitoring functions + */ + +static void radeon_clear_box( drm_radeon_private_t *dev_priv, + int x, int y, int w, int h, + int r, int g, int b ) +{ + u32 color; + RING_LOCALS; + + x += dev_priv->sarea_priv->boxes[0].x1; + y += dev_priv->sarea_priv->boxes[0].y1; + + switch ( dev_priv->color_fmt ) { + case RADEON_COLOR_FORMAT_RGB565: + color = (((r & 0xf8) << 8) | + ((g & 0xfc) << 3) | + ((b & 0xf8) >> 3)); + break; + case RADEON_COLOR_FORMAT_ARGB8888: + default: + color = (((0xff) << 24) | (r << 16) | (g << 8) | b); + break; + } + + BEGIN_RING( 4 ); + RADEON_WAIT_UNTIL_3D_IDLE(); + OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); + OUT_RING( 0xffffffff ); + ADVANCE_RING(); + + BEGIN_RING( 6 ); + + OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_P | + RADEON_GMC_CLR_CMP_CNTL_DIS ); + + if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { + OUT_RING( dev_priv->front_pitch_offset ); + } else { + OUT_RING( dev_priv->back_pitch_offset ); + } + + OUT_RING( color ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); +} + +static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) +{ + /* Collapse various things into a wait flag -- trying to + * guess if userspase slept -- better just to have them tell us. + */ + if (dev_priv->stats.last_frame_reads > 1 || + dev_priv->stats.last_clear_reads > dev_priv->stats.clears) { + dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; + } + + if (dev_priv->stats.freelist_loops) { + dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; + } + + /* Purple box for page flipping + */ + if ( dev_priv->stats.boxes & RADEON_BOX_FLIP ) + radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 ); + + /* Red box if we have to wait for idle at any point + */ + if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE ) + radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 ); + + /* Blue box: lost context? + */ + + /* Yellow box for texture swaps + */ + if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD ) + radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 ); + + /* Green box if hardware never idles (as far as we can tell) + */ + if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) ) + radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); + + + /* Draw bars indicating number of buffers allocated + * (not a great measure, easily confused) + */ + if (dev_priv->stats.requested_bufs) { + if (dev_priv->stats.requested_bufs > 100) + dev_priv->stats.requested_bufs = 100; + + radeon_clear_box( dev_priv, 4, 16, + dev_priv->stats.requested_bufs, 4, + 196, 128, 128 ); + } + + memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) ); + +} +/* ================================================================ + * CP command dispatch functions + */ + +static void radeon_cp_dispatch_clear( drm_device_t *dev, + drm_radeon_clear_t *clear, + drm_radeon_clear_rect_t *depth_boxes ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + unsigned int flags = clear->flags; + u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0; + int i; + RING_LOCALS; + DRM_DEBUG( "flags = 0x%x\n", flags ); + + dev_priv->stats.clears++; + + if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { + unsigned int tmp = flags; + + flags &= ~(RADEON_FRONT | RADEON_BACK); + if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK; + if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT; + } + + if ( flags & (RADEON_FRONT | RADEON_BACK) ) { + + BEGIN_RING( 4 ); + + /* Ensure the 3D stream is idle before doing a + * 2D fill to clear the front or back buffer. + */ + RADEON_WAIT_UNTIL_3D_IDLE(); + + OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); + OUT_RING( clear->color_mask ); + + ADVANCE_RING(); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->ctx_owner = 0; + + for ( i = 0 ; i < nbox ; i++ ) { + int x = pbox[i].x1; + int y = pbox[i].y1; + int w = pbox[i].x2 - x; + int h = pbox[i].y2 - y; + + DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", + x, y, w, h, flags ); + + if ( flags & RADEON_FRONT ) { + BEGIN_RING( 6 ); + + OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_P | + RADEON_GMC_CLR_CMP_CNTL_DIS ); + + OUT_RING( dev_priv->front_pitch_offset ); + OUT_RING( clear->clear_color ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + + if ( flags & RADEON_BACK ) { + BEGIN_RING( 6 ); + + OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); + OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_P | + RADEON_GMC_CLR_CMP_CNTL_DIS ); + + OUT_RING( dev_priv->back_pitch_offset ); + OUT_RING( clear->clear_color ); + + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + } + } + + /* hyper z clear */ + /* no docs available, based on reverse engeneering by Stephane Marchesin */ + if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) && (flags & RADEON_CLEAR_FASTZ)) { + + int i; + int depthpixperline = dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z? + (dev_priv->depth_pitch / 2): (dev_priv->depth_pitch / 4); + + u32 clearmask; + + u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth | + ((clear->depth_mask & 0xff) << 24); + + + /* Make sure we restore the 3D state next time. + * we haven't touched any "normal" state - still need this? + */ + dev_priv->sarea_priv->ctx_owner = 0; + + if ((dev_priv->flags & CHIP_HAS_HIERZ) && (flags & RADEON_USE_HIERZ)) { + /* FIXME : reverse engineer that for Rx00 cards */ + /* FIXME : the mask supposedly contains low-res z values. So can't set + just to the max (0xff? or actually 0x3fff?), need to take z clear + value into account? */ + /* pattern seems to work for r100, though get slight + rendering errors with glxgears. If hierz is not enabled for r100, + only 4 bits which indicate clear (15,16,31,32, all zero) matter, the + other ones are ignored, and the same clear mask can be used. That's + very different behaviour than R200 which needs different clear mask + and different number of tiles to clear if hierz is enabled or not !?! + */ + clearmask = (0xff<<22)|(0xff<<6)| 0x003f003f; + } + else { + /* clear mask : chooses the clearing pattern. + rv250: could be used to clear only parts of macrotiles + (but that would get really complicated...)? + bit 0 and 1 (either or both of them ?!?!) are used to + not clear tile (or maybe one of the bits indicates if the tile is + compressed or not), bit 2 and 3 to not clear tile 1,...,. + Pattern is as follows: + | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29| + bits ------------------------------------------------- + | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31| + rv100: clearmask covers 2x8 4x1 tiles, but one clear still + covers 256 pixels ?!? + */ + clearmask = 0x0; + } + + BEGIN_RING( 8 ); + RADEON_WAIT_UNTIL_2D_IDLE(); + OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE, + tempRB3D_DEPTHCLEARVALUE); + /* what offset is this exactly ? */ + OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET, 0 ); + /* need ctlstat, otherwise get some strange black flickering */ + OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL ); + ADVANCE_RING(); + + for (i = 0; i < nbox; i++) { + int tileoffset, nrtilesx, nrtilesy, j; + /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */ + if ((dev_priv->flags&CHIP_HAS_HIERZ) && !(dev_priv->microcode_version==UCODE_R200)) { + /* FIXME : figure this out for r200 (when hierz is enabled). Or + maybe r200 actually doesn't need to put the low-res z value into + the tile cache like r100, but just needs to clear the hi-level z-buffer? + Works for R100, both with hierz and without. + R100 seems to operate on 2x1 8x8 tiles, but... + odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially + problematic with resolutions which are not 64 pix aligned? */ + tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 6; + nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; + nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); + for (j = 0; j <= nrtilesy; j++) { + BEGIN_RING( 4 ); + OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); + /* first tile */ + OUT_RING( tileoffset * 8 ); + /* the number of tiles to clear */ + OUT_RING( nrtilesx + 4 ); + /* clear mask : chooses the clearing pattern. */ + OUT_RING( clearmask ); + ADVANCE_RING(); + tileoffset += depthpixperline >> 6; + } + } + else if (dev_priv->microcode_version==UCODE_R200) { + /* works for rv250. */ + /* find first macro tile (8x2 4x4 z-pixels on rv250) */ + tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 5; + nrtilesx = (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5); + nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); + for (j = 0; j <= nrtilesy; j++) { + BEGIN_RING( 4 ); + OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); + /* first tile */ + /* judging by the first tile offset needed, could possibly + directly address/clear 4x4 tiles instead of 8x2 * 4x4 + macro tiles, though would still need clear mask for + right/bottom if truely 4x4 granularity is desired ? */ + OUT_RING( tileoffset * 16 ); + /* the number of tiles to clear */ + OUT_RING( nrtilesx + 1 ); + /* clear mask : chooses the clearing pattern. */ + OUT_RING( clearmask ); + ADVANCE_RING(); + tileoffset += depthpixperline >> 5; + } + } + else { /* rv 100 */ + /* rv100 might not need 64 pix alignment, who knows */ + /* offsets are, hmm, weird */ + tileoffset = ((pbox[i].y1 >> 4) * depthpixperline + pbox[i].x1) >> 6; + nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; + nrtilesy = (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4); + for (j = 0; j <= nrtilesy; j++) { + BEGIN_RING( 4 ); + OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); + OUT_RING( tileoffset * 128 ); + /* the number of tiles to clear */ + OUT_RING( nrtilesx + 4 ); + /* clear mask : chooses the clearing pattern. */ + OUT_RING( clearmask ); + ADVANCE_RING(); + tileoffset += depthpixperline >> 6; + } + } + } + + /* TODO don't always clear all hi-level z tiles */ + if ((dev_priv->flags & CHIP_HAS_HIERZ) && (dev_priv->microcode_version==UCODE_R200) + && (flags & RADEON_USE_HIERZ)) + /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */ + /* FIXME : the mask supposedly contains low-res z values. So can't set + just to the max (0xff? or actually 0x3fff?), need to take z clear + value into account? */ + { + BEGIN_RING( 4 ); + OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) ); + OUT_RING( 0x0 ); /* First tile */ + OUT_RING( 0x3cc0 ); + OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f); + ADVANCE_RING(); + } + } + + /* We have to clear the depth and/or stencil buffers by + * rendering a quad into just those buffers. Thus, we have to + * make sure the 3D engine is configured correctly. + */ + if ((dev_priv->microcode_version == UCODE_R200) && + (flags & (RADEON_DEPTH | RADEON_STENCIL))) { + + int tempPP_CNTL; + int tempRE_CNTL; + int tempRB3D_CNTL; + int tempRB3D_ZSTENCILCNTL; + int tempRB3D_STENCILREFMASK; + int tempRB3D_PLANEMASK; + int tempSE_CNTL; + int tempSE_VTE_CNTL; + int tempSE_VTX_FMT_0; + int tempSE_VTX_FMT_1; + int tempSE_VAP_CNTL; + int tempRE_AUX_SCISSOR_CNTL; + + tempPP_CNTL = 0; + tempRE_CNTL = 0; + + tempRB3D_CNTL = depth_clear->rb3d_cntl; + + tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; + tempRB3D_STENCILREFMASK = 0x0; + + tempSE_CNTL = depth_clear->se_cntl; + + + + /* Disable TCL */ + + tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ + (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT)); + + tempRB3D_PLANEMASK = 0x0; + + tempRE_AUX_SCISSOR_CNTL = 0x0; + + tempSE_VTE_CNTL = + SE_VTE_CNTL__VTX_XY_FMT_MASK | + SE_VTE_CNTL__VTX_Z_FMT_MASK; + + /* Vertex format (X, Y, Z, W)*/ + tempSE_VTX_FMT_0 = + SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK | + SE_VTX_FMT_0__VTX_W0_PRESENT_MASK; + tempSE_VTX_FMT_1 = 0x0; + + + /* + * Depth buffer specific enables + */ + if (flags & RADEON_DEPTH) { + /* Enable depth buffer */ + tempRB3D_CNTL |= RADEON_Z_ENABLE; + } else { + /* Disable depth buffer */ + tempRB3D_CNTL &= ~RADEON_Z_ENABLE; + } + + /* + * Stencil buffer specific enables + */ + if ( flags & RADEON_STENCIL ) { + tempRB3D_CNTL |= RADEON_STENCIL_ENABLE; + tempRB3D_STENCILREFMASK = clear->depth_mask; + } else { + tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE; + tempRB3D_STENCILREFMASK = 0x00000000; + } + + if (flags & RADEON_USE_COMP_ZBUF) { + tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | + RADEON_Z_DECOMPRESSION_ENABLE; + } + if (flags & RADEON_USE_HIERZ) { + tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; + } + + BEGIN_RING( 26 ); + RADEON_WAIT_UNTIL_2D_IDLE(); + + OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL ); + OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL ); + OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL ); + OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, + tempRB3D_ZSTENCILCNTL ); + OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, + tempRB3D_STENCILREFMASK ); + OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK ); + OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL ); + OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL ); + OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 ); + OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 ); + OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL ); + OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL, + tempRE_AUX_SCISSOR_CNTL ); + ADVANCE_RING(); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->ctx_owner = 0; + + for ( i = 0 ; i < nbox ; i++ ) { + + /* Funny that this should be required -- + * sets top-left? + */ + radeon_emit_clip_rect( dev_priv, + &sarea_priv->boxes[i] ); + + BEGIN_RING( 14 ); + OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) ); + OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | + RADEON_PRIM_WALK_RING | + (3 << RADEON_NUM_VERTICES_SHIFT)) ); + OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); + OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); + OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); + OUT_RING( 0x3f800000 ); + OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); + OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); + OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); + OUT_RING( 0x3f800000 ); + OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); + OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); + OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); + OUT_RING( 0x3f800000 ); + ADVANCE_RING(); + } + } + else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) { + + int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; + + rb3d_cntl = depth_clear->rb3d_cntl; + + if ( flags & RADEON_DEPTH ) { + rb3d_cntl |= RADEON_Z_ENABLE; + } else { + rb3d_cntl &= ~RADEON_Z_ENABLE; + } + + if ( flags & RADEON_STENCIL ) { + rb3d_cntl |= RADEON_STENCIL_ENABLE; + rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ + } else { + rb3d_cntl &= ~RADEON_STENCIL_ENABLE; + rb3d_stencilrefmask = 0x00000000; + } + + if (flags & RADEON_USE_COMP_ZBUF) { + tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | + RADEON_Z_DECOMPRESSION_ENABLE; + } + if (flags & RADEON_USE_HIERZ) { + tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; + } + + BEGIN_RING( 13 ); + RADEON_WAIT_UNTIL_2D_IDLE(); + + OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) ); + OUT_RING( 0x00000000 ); + OUT_RING( rb3d_cntl ); + + OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL ); + OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, + rb3d_stencilrefmask ); + OUT_RING_REG( RADEON_RB3D_PLANEMASK, + 0x00000000 ); + OUT_RING_REG( RADEON_SE_CNTL, + depth_clear->se_cntl ); + ADVANCE_RING(); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->ctx_owner = 0; + + for ( i = 0 ; i < nbox ; i++ ) { + + /* Funny that this should be required -- + * sets top-left? + */ + radeon_emit_clip_rect( dev_priv, + &sarea_priv->boxes[i] ); + + BEGIN_RING( 15 ); + + OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) ); + OUT_RING( RADEON_VTX_Z_PRESENT | + RADEON_VTX_PKCOLOR_PRESENT); + OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | + RADEON_PRIM_WALK_RING | + RADEON_MAOS_ENABLE | + RADEON_VTX_FMT_RADEON_MODE | + (3 << RADEON_NUM_VERTICES_SHIFT)) ); + + + OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); + OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); + OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); + OUT_RING( 0x0 ); + + OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); + OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); + OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); + OUT_RING( 0x0 ); + + OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); + OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); + OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); + OUT_RING( 0x0 ); + + ADVANCE_RING(); + } + } + + /* Increment the clear counter. The client-side 3D driver must + * wait on this value before performing the clear ioctl. We + * need this because the card's so damned fast... + */ + dev_priv->sarea_priv->last_clear++; + + BEGIN_RING( 4 ); + + RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear ); + RADEON_WAIT_UNTIL_IDLE(); + + ADVANCE_RING(); +} + +static void radeon_cp_dispatch_swap( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + int nbox = sarea_priv->nbox; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int i; + RING_LOCALS; + DRM_DEBUG( "\n" ); + + /* Do some trivial performance monitoring... + */ + if (dev_priv->do_boxes) + radeon_cp_performance_boxes( dev_priv ); + + + /* Wait for the 3D stream to idle before dispatching the bitblt. + * This will prevent data corruption between the two streams. + */ + BEGIN_RING( 2 ); + + RADEON_WAIT_UNTIL_3D_IDLE(); + + ADVANCE_RING(); + + for ( i = 0 ; i < nbox ; i++ ) { + int x = pbox[i].x1; + int y = pbox[i].y1; + int w = pbox[i].x2 - x; + int h = pbox[i].y2 - y; + + DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n", + x, y, w, h ); + + BEGIN_RING( 7 ); + + OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) ); + OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL | + RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_NONE | + (dev_priv->color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_S | + RADEON_DP_SRC_SOURCE_MEMORY | + RADEON_GMC_CLR_CMP_CNTL_DIS | + RADEON_GMC_WR_MSK_DIS ); + + /* Make this work even if front & back are flipped: + */ + if (dev_priv->current_page == 0) { + OUT_RING( dev_priv->back_pitch_offset ); + OUT_RING( dev_priv->front_pitch_offset ); + } + else { + OUT_RING( dev_priv->front_pitch_offset ); + OUT_RING( dev_priv->back_pitch_offset ); + } + + OUT_RING( (x << 16) | y ); + OUT_RING( (x << 16) | y ); + OUT_RING( (w << 16) | h ); + + ADVANCE_RING(); + } + + /* Increment the frame counter. The client-side 3D driver must + * throttle the framerate by waiting for this value before + * performing the swapbuffer ioctl. + */ + dev_priv->sarea_priv->last_frame++; + + BEGIN_RING( 4 ); + + RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); + RADEON_WAIT_UNTIL_2D_IDLE(); + + ADVANCE_RING(); +} + +static void radeon_cp_dispatch_flip( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle; + int offset = (dev_priv->current_page == 1) + ? dev_priv->front_offset : dev_priv->back_offset; + RING_LOCALS; + DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, + dev_priv->sarea_priv->pfCurrentPage); + + /* Do some trivial performance monitoring... + */ + if (dev_priv->do_boxes) { + dev_priv->stats.boxes |= RADEON_BOX_FLIP; + radeon_cp_performance_boxes( dev_priv ); + } + + /* Update the frame offsets for both CRTCs + */ + BEGIN_RING( 6 ); + + RADEON_WAIT_UNTIL_3D_IDLE(); + OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch + + sarea->frame.x + * ( dev_priv->color_fmt - 2 ) ) & ~7 ) + + offset ); + OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base + + offset ); + + ADVANCE_RING(); + + /* Increment the frame counter. The client-side 3D driver must + * throttle the framerate by waiting for this value before + * performing the swapbuffer ioctl. + */ + dev_priv->sarea_priv->last_frame++; + dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = + 1 - dev_priv->current_page; + + BEGIN_RING( 2 ); + + RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); + + ADVANCE_RING(); +} + +static int bad_prim_vertex_nr( int primitive, int nr ) +{ + switch (primitive & RADEON_PRIM_TYPE_MASK) { + case RADEON_PRIM_TYPE_NONE: + case RADEON_PRIM_TYPE_POINT: + return nr < 1; + case RADEON_PRIM_TYPE_LINE: + return (nr & 1) || nr == 0; + case RADEON_PRIM_TYPE_LINE_STRIP: + return nr < 2; + case RADEON_PRIM_TYPE_TRI_LIST: + case RADEON_PRIM_TYPE_3VRT_POINT_LIST: + case RADEON_PRIM_TYPE_3VRT_LINE_LIST: + case RADEON_PRIM_TYPE_RECT_LIST: + return nr % 3 || nr == 0; + case RADEON_PRIM_TYPE_TRI_FAN: + case RADEON_PRIM_TYPE_TRI_STRIP: + return nr < 3; + default: + return 1; + } +} + + + +typedef struct { + unsigned int start; + unsigned int finish; + unsigned int prim; + unsigned int numverts; + unsigned int offset; + unsigned int vc_format; +} drm_radeon_tcl_prim_t; + +static void radeon_cp_dispatch_vertex( drm_device_t *dev, + drm_buf_t *buf, + drm_radeon_tcl_prim_t *prim ) + +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start; + int numverts = (int)prim->numverts; + int nbox = sarea_priv->nbox; + int i = 0; + RING_LOCALS; + + DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n", + prim->prim, + prim->vc_format, + prim->start, + prim->finish, + prim->numverts); + + if (bad_prim_vertex_nr( prim->prim, prim->numverts )) { + DRM_ERROR( "bad prim %x numverts %d\n", + prim->prim, prim->numverts ); + return; + } + + do { + /* Emit the next cliprect */ + if ( i < nbox ) { + radeon_emit_clip_rect( dev_priv, + &sarea_priv->boxes[i] ); + } + + /* Emit the vertex buffer rendering commands */ + BEGIN_RING( 5 ); + + OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) ); + OUT_RING( offset ); + OUT_RING( numverts ); + OUT_RING( prim->vc_format ); + OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST | + RADEON_COLOR_ORDER_RGBA | + RADEON_VTX_FMT_RADEON_MODE | + (numverts << RADEON_NUM_VERTICES_SHIFT) ); + + ADVANCE_RING(); + + i++; + } while ( i < nbox ); +} + + + +static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_buf_priv_t *buf_priv = buf->dev_private; + RING_LOCALS; + + buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; + + /* Emit the vertex buffer age */ + BEGIN_RING( 2 ); + RADEON_DISPATCH_AGE( buf_priv->age ); + ADVANCE_RING(); + + buf->pending = 1; + buf->used = 0; +} + +static void radeon_cp_dispatch_indirect( drm_device_t *dev, + drm_buf_t *buf, + int start, int end ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", + buf->idx, start, end ); + + if ( start != end ) { + int offset = (dev_priv->gart_buffers_offset + + buf->offset + start); + int dwords = (end - start + 3) / sizeof(u32); + + /* Indirect buffer data must be an even number of + * dwords, so if we've been given an odd number we must + * pad the data with a Type-2 CP packet. + */ + if ( dwords & 1 ) { + u32 *data = (u32 *) + ((char *)dev->agp_buffer_map->handle + + buf->offset + start); + data[dwords++] = RADEON_CP_PACKET2; + } + + /* Fire off the indirect buffer */ + BEGIN_RING( 3 ); + + OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) ); + OUT_RING( offset ); + OUT_RING( dwords ); + + ADVANCE_RING(); + } +} + + +static void radeon_cp_dispatch_indices( drm_device_t *dev, + drm_buf_t *elt_buf, + drm_radeon_tcl_prim_t *prim ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + int offset = dev_priv->gart_buffers_offset + prim->offset; + u32 *data; + int dwords; + int i = 0; + int start = prim->start + RADEON_INDEX_PRIM_OFFSET; + int count = (prim->finish - start) / sizeof(u16); + int nbox = sarea_priv->nbox; + + DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", + prim->prim, + prim->vc_format, + prim->start, + prim->finish, + prim->offset, + prim->numverts); + + if (bad_prim_vertex_nr( prim->prim, count )) { + DRM_ERROR( "bad prim %x count %d\n", + prim->prim, count ); + return; + } + + + if ( start >= prim->finish || + (prim->start & 0x7) ) { + DRM_ERROR( "buffer prim %d\n", prim->prim ); + return; + } + + dwords = (prim->finish - prim->start + 3) / sizeof(u32); + + data = (u32 *)((char *)dev->agp_buffer_map->handle + + elt_buf->offset + prim->start); + + data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 ); + data[1] = offset; + data[2] = prim->numverts; + data[3] = prim->vc_format; + data[4] = (prim->prim | + RADEON_PRIM_WALK_IND | + RADEON_COLOR_ORDER_RGBA | + RADEON_VTX_FMT_RADEON_MODE | + (count << RADEON_NUM_VERTICES_SHIFT) ); + + do { + if ( i < nbox ) + radeon_emit_clip_rect( dev_priv, + &sarea_priv->boxes[i] ); + + radeon_cp_dispatch_indirect( dev, elt_buf, + prim->start, + prim->finish ); + + i++; + } while ( i < nbox ); + +} + +#define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32)) + +static int radeon_cp_dispatch_texture( DRMFILE filp, + drm_device_t *dev, + drm_radeon_texture_t *tex, + drm_radeon_tex_image_t *image ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_file_t *filp_priv; + drm_buf_t *buf; + u32 format; + u32 *buffer; + const u8 __user *data; + int size, dwords, tex_width, blit_width; + u32 height; + int i; + u32 texpitch, microtile; + RING_LOCALS; + + DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + + if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &tex->offset ) ) { + DRM_ERROR( "Invalid destination offset\n" ); + return DRM_ERR( EINVAL ); + } + + dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; + + /* Flush the pixel cache. This ensures no pixel data gets mixed + * up with the texture data from the host data blit, otherwise + * part of the texture image may be corrupted. + */ + BEGIN_RING( 4 ); + RADEON_FLUSH_CACHE(); + RADEON_WAIT_UNTIL_IDLE(); + ADVANCE_RING(); + +#ifdef __BIG_ENDIAN + /* The Mesa texture functions provide the data in little endian as the + * chip wants it, but we need to compensate for the fact that the CP + * ring gets byte-swapped + */ + BEGIN_RING( 2 ); + OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT ); + ADVANCE_RING(); +#endif + + + /* The compiler won't optimize away a division by a variable, + * even if the only legal values are powers of two. Thus, we'll + * use a shift instead. + */ + switch ( tex->format ) { + case RADEON_TXFORMAT_ARGB8888: + case RADEON_TXFORMAT_RGBA8888: + format = RADEON_COLOR_FORMAT_ARGB8888; + tex_width = tex->width * 4; + blit_width = image->width * 4; + break; + case RADEON_TXFORMAT_AI88: + case RADEON_TXFORMAT_ARGB1555: + case RADEON_TXFORMAT_RGB565: + case RADEON_TXFORMAT_ARGB4444: + case RADEON_TXFORMAT_VYUY422: + case RADEON_TXFORMAT_YVYU422: + format = RADEON_COLOR_FORMAT_RGB565; + tex_width = tex->width * 2; + blit_width = image->width * 2; + break; + case RADEON_TXFORMAT_I8: + case RADEON_TXFORMAT_RGB332: + format = RADEON_COLOR_FORMAT_CI8; + tex_width = tex->width * 1; + blit_width = image->width * 1; + break; + default: + DRM_ERROR( "invalid texture format %d\n", tex->format ); + return DRM_ERR(EINVAL); + } + texpitch = tex->pitch; + if ((texpitch << 22) & RADEON_DST_TILE_MICRO) { + microtile = 1; + if (tex_width < 64) { + texpitch &= ~(RADEON_DST_TILE_MICRO >> 22); + /* we got tiled coordinates, untile them */ + image->x *= 2; + } + } + else microtile = 0; + + DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width ); + + do { + DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", + tex->offset >> 10, tex->pitch, tex->format, + image->x, image->y, image->width, image->height ); + + /* Make a copy of some parameters in case we have to + * update them for a multi-pass texture blit. + */ + height = image->height; + data = (const u8 __user *)image->data; + + size = height * blit_width; + + if ( size > RADEON_MAX_TEXTURE_SIZE ) { + height = RADEON_MAX_TEXTURE_SIZE / blit_width; + size = height * blit_width; + } else if ( size < 4 && size > 0 ) { + size = 4; + } else if ( size == 0 ) { + return 0; + } + + buf = radeon_freelist_get( dev ); + if ( 0 && !buf ) { + radeon_do_cp_idle( dev_priv ); + buf = radeon_freelist_get( dev ); + } + if ( !buf ) { + DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n"); + if (DRM_COPY_TO_USER( tex->image, image, sizeof(*image) )) + return DRM_ERR(EFAULT); + return DRM_ERR(EAGAIN); + } + + + /* Dispatch the indirect buffer. + */ + buffer = (u32*)((char*)dev->agp_buffer_map->handle + buf->offset); + dwords = size / 4; + buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 ); + buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_NONE | + (format << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_S | + RADEON_DP_SRC_SOURCE_HOST_DATA | + RADEON_GMC_CLR_CMP_CNTL_DIS | + RADEON_GMC_WR_MSK_DIS); + + buffer[2] = (texpitch << 22) | (tex->offset >> 10); + buffer[3] = 0xffffffff; + buffer[4] = 0xffffffff; + buffer[5] = (image->y << 16) | image->x; + buffer[6] = (height << 16) | image->width; + buffer[7] = dwords; + buffer += 8; + + + + if (microtile) { + /* texture micro tiling in use, minimum texture width is thus 16 bytes. + however, we cannot use blitter directly for texture width < 64 bytes, + since minimum tex pitch is 64 bytes and we need this to match + the texture width, otherwise the blitter will tile it wrong. + Thus, tiling manually in this case. Additionally, need to special + case tex height = 1, since our actual image will have height 2 + and we need to ensure we don't read beyond the texture size + from user space. */ + if (tex->height == 1) { + if (tex_width >= 64 || tex_width <= 16) { + if (DRM_COPY_FROM_USER(buffer, data, + tex_width * sizeof(u32))) { + DRM_ERROR("EFAULT on pad, %d bytes\n", + tex_width); + return DRM_ERR(EFAULT); + } + } else if (tex_width == 32) { + if (DRM_COPY_FROM_USER(buffer, data, 16)) { + DRM_ERROR("EFAULT on pad, %d bytes\n", + tex_width); + return DRM_ERR(EFAULT); + } + if (DRM_COPY_FROM_USER(buffer + 8, data + 16, 16)) { + DRM_ERROR("EFAULT on pad, %d bytes\n", + tex_width); + return DRM_ERR(EFAULT); + } + } + } else if (tex_width >= 64 || tex_width == 16) { + if (DRM_COPY_FROM_USER(buffer, data, + dwords * sizeof(u32))) { + DRM_ERROR("EFAULT on data, %d dwords\n", + dwords); + return DRM_ERR(EFAULT); + } + } else if (tex_width < 16) { + for (i = 0; i < tex->height; i++) { + if (DRM_COPY_FROM_USER(buffer, data, tex_width)) { + DRM_ERROR("EFAULT on pad, %d bytes\n", + tex_width); + return DRM_ERR(EFAULT); + } + buffer += 4; + data += tex_width; + } + } else if (tex_width == 32) { + /* TODO: make sure this works when not fitting in one buffer + (i.e. 32bytes x 2048...) */ + for (i = 0; i < tex->height; i += 2) { + if (DRM_COPY_FROM_USER(buffer, data, 16)) { + DRM_ERROR("EFAULT on pad, %d bytes\n", + tex_width); + return DRM_ERR(EFAULT); + } + data += 16; + if (DRM_COPY_FROM_USER(buffer + 8, data, 16)) { + DRM_ERROR("EFAULT on pad, %d bytes\n", + tex_width); + return DRM_ERR(EFAULT); + } + data += 16; + if (DRM_COPY_FROM_USER(buffer + 4, data, 16)) { + DRM_ERROR("EFAULT on pad, %d bytes\n", + tex_width); + return DRM_ERR(EFAULT); + } + data += 16; + if (DRM_COPY_FROM_USER(buffer + 12, data, 16)) { + DRM_ERROR("EFAULT on pad, %d bytes\n", + tex_width); + return DRM_ERR(EFAULT); + } + data += 16; + buffer += 16; + } + } + } + else { + if (tex_width >= 32) { + /* Texture image width is larger than the minimum, so we + * can upload it directly. + */ + if (DRM_COPY_FROM_USER(buffer, data, + dwords * sizeof(u32))) { + DRM_ERROR("EFAULT on data, %d dwords\n", + dwords); + return DRM_ERR(EFAULT); + } + } else { + /* Texture image width is less than the minimum, so we + * need to pad out each image scanline to the minimum + * width. + */ + for (i = 0 ; i < tex->height ; i++) { + if (DRM_COPY_FROM_USER(buffer, data, tex_width )) { + DRM_ERROR("EFAULT on pad, %d bytes\n", tex_width); + return DRM_ERR(EFAULT); + } + buffer += 8; + data += tex_width; + } + } + } + + buf->filp = filp; + buf->used = (dwords + 8) * sizeof(u32); + radeon_cp_dispatch_indirect( dev, buf, 0, buf->used ); + radeon_cp_discard_buffer( dev, buf ); + + /* Update the input parameters for next time */ + image->y += height; + image->height -= height; + image->data = (const u8 __user *)image->data + size; + } while (image->height > 0); + + /* Flush the pixel cache after the blit completes. This ensures + * the texture data is written out to memory before rendering + * continues. + */ + BEGIN_RING( 4 ); + RADEON_FLUSH_CACHE(); + RADEON_WAIT_UNTIL_2D_IDLE(); + ADVANCE_RING(); + return 0; +} + + +static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + int i; + RING_LOCALS; + DRM_DEBUG( "\n" ); + + BEGIN_RING( 35 ); + + OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) ); + OUT_RING( 0x00000000 ); + + OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) ); + for ( i = 0 ; i < 32 ; i++ ) { + OUT_RING( stipple[i] ); + } + + ADVANCE_RING(); +} + +static void radeon_apply_surface_regs(int surf_index, drm_radeon_private_t *dev_priv) +{ + if (!dev_priv->mmio) + return; + + radeon_do_cp_idle(dev_priv); + + RADEON_WRITE(RADEON_SURFACE0_INFO + 16*surf_index, + dev_priv->surfaces[surf_index].flags); + RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*surf_index, + dev_priv->surfaces[surf_index].lower); + RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*surf_index, + dev_priv->surfaces[surf_index].upper); +} + + +/* Allocates a virtual surface + * doesn't always allocate a real surface, will stretch an existing + * surface when possible. + * + * Note that refcount can be at most 2, since during a free refcount=3 + * might mean we have to allocate a new surface which might not always + * be available. + * For example : we allocate three contigous surfaces ABC. If B is + * freed, we suddenly need two surfaces to store A and C, which might + * not always be available. + */ +static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *dev_priv, DRMFILE filp) +{ + struct radeon_virt_surface *s; + int i; + int virt_surface_index; + uint32_t new_upper, new_lower; + + new_lower = new->address; + new_upper = new_lower + new->size - 1; + + /* sanity check */ + if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) || + ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) != RADEON_SURF_ADDRESS_FIXED_MASK) || + ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0)) + return -1; + + /* make sure there is no overlap with existing surfaces */ + for (i = 0; i < RADEON_MAX_SURFACES; i++) { + if ((dev_priv->surfaces[i].refcount != 0) && + (( (new_lower >= dev_priv->surfaces[i].lower) && + (new_lower < dev_priv->surfaces[i].upper) ) || + ( (new_lower < dev_priv->surfaces[i].lower) && + (new_upper > dev_priv->surfaces[i].lower) )) ){ + return -1;} + } + + /* find a virtual surface */ + for (i = 0; i < 2*RADEON_MAX_SURFACES; i++) + if (dev_priv->virt_surfaces[i].filp == 0) + break; + if (i == 2*RADEON_MAX_SURFACES) { + return -1;} + virt_surface_index = i; + + /* try to reuse an existing surface */ + for (i = 0; i < RADEON_MAX_SURFACES; i++) { + /* extend before */ + if ((dev_priv->surfaces[i].refcount == 1) && + (new->flags == dev_priv->surfaces[i].flags) && + (new_upper + 1 == dev_priv->surfaces[i].lower)) { + s = &(dev_priv->virt_surfaces[virt_surface_index]); + s->surface_index = i; + s->lower = new_lower; + s->upper = new_upper; + s->flags = new->flags; + s->filp = filp; + dev_priv->surfaces[i].refcount++; + dev_priv->surfaces[i].lower = s->lower; + radeon_apply_surface_regs(s->surface_index, dev_priv); + return virt_surface_index; + } + + /* extend after */ + if ((dev_priv->surfaces[i].refcount == 1) && + (new->flags == dev_priv->surfaces[i].flags) && + (new_lower == dev_priv->surfaces[i].upper + 1)) { + s = &(dev_priv->virt_surfaces[virt_surface_index]); + s->surface_index = i; + s->lower = new_lower; + s->upper = new_upper; + s->flags = new->flags; + s->filp = filp; + dev_priv->surfaces[i].refcount++; + dev_priv->surfaces[i].upper = s->upper; + radeon_apply_surface_regs(s->surface_index, dev_priv); + return virt_surface_index; + } + } + + /* okay, we need a new one */ + for (i = 0; i < RADEON_MAX_SURFACES; i++) { + if (dev_priv->surfaces[i].refcount == 0) { + s = &(dev_priv->virt_surfaces[virt_surface_index]); + s->surface_index = i; + s->lower = new_lower; + s->upper = new_upper; + s->flags = new->flags; + s->filp = filp; + dev_priv->surfaces[i].refcount = 1; + dev_priv->surfaces[i].lower = s->lower; + dev_priv->surfaces[i].upper = s->upper; + dev_priv->surfaces[i].flags = s->flags; + radeon_apply_surface_regs(s->surface_index, dev_priv); + return virt_surface_index; + } + } + + /* we didn't find anything */ + return -1; +} + +static int free_surface(DRMFILE filp, drm_radeon_private_t *dev_priv, int lower) +{ + struct radeon_virt_surface *s; + int i; + /* find the virtual surface */ + for(i = 0; i < 2*RADEON_MAX_SURFACES; i++) { + s = &(dev_priv->virt_surfaces[i]); + if (s->filp) { + if ((lower == s->lower) && (filp == s->filp)) { + if (dev_priv->surfaces[s->surface_index].lower == s->lower) + dev_priv->surfaces[s->surface_index].lower = s->upper; + + if (dev_priv->surfaces[s->surface_index].upper == s->upper) + dev_priv->surfaces[s->surface_index].upper = s->lower; + + dev_priv->surfaces[s->surface_index].refcount--; + if (dev_priv->surfaces[s->surface_index].refcount == 0) + dev_priv->surfaces[s->surface_index].flags = 0; + s->filp = NULL; + radeon_apply_surface_regs(s->surface_index, dev_priv); + return 0; + } + } + } + return 1; +} + +static void radeon_surfaces_release(DRMFILE filp, drm_radeon_private_t *dev_priv) +{ + int i; + for( i = 0; i < 2*RADEON_MAX_SURFACES; i++) + { + if (dev_priv->virt_surfaces[i].filp == filp) + free_surface(filp, dev_priv, dev_priv->virt_surfaces[i].lower); + } +} + +/* ================================================================ + * IOCTL functions + */ +static int radeon_surface_alloc(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_surface_alloc_t alloc; + + if (!dev_priv) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_surface_alloc_t __user *)data, + sizeof(alloc)); + + if (alloc_surface(&alloc, dev_priv, filp) == -1) + return DRM_ERR(EINVAL); + else + return 0; +} + +static int radeon_surface_free(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_surface_free_t memfree; + + if (!dev_priv) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *)data, + sizeof(memfree) ); + + if (free_surface(filp, dev_priv, memfree.address)) + return DRM_ERR(EINVAL); + else + return 0; +} + +static int radeon_cp_clear( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_clear_t clear; + drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t __user *)data, + sizeof(clear) ); + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + + if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; + + if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes, + sarea_priv->nbox * sizeof(depth_boxes[0]) ) ) + return DRM_ERR(EFAULT); + + radeon_cp_dispatch_clear( dev, &clear, depth_boxes ); + + COMMIT_RING(); + return 0; +} + + +/* Not sure why this isn't set all the time: + */ +static int radeon_do_init_pageflip( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + + DRM_DEBUG( "\n" ); + + BEGIN_RING( 6 ); + RADEON_WAIT_UNTIL_3D_IDLE(); + OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) ); + OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); + OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) ); + OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); + ADVANCE_RING(); + + dev_priv->page_flipping = 1; + dev_priv->current_page = 0; + dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page; + + return 0; +} + +/* Called whenever a client dies, from drm_release. + * NOTE: Lock isn't necessarily held when this is called! + */ +static int radeon_do_cleanup_pageflip( drm_device_t *dev ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "\n" ); + + if (dev_priv->current_page != 0) + radeon_cp_dispatch_flip( dev ); + + dev_priv->page_flipping = 0; + return 0; +} + +/* Swapping and flipping are different operations, need different ioctls. + * They can & should be intermixed to support multiple 3d windows. + */ +static int radeon_cp_flip( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + + if (!dev_priv->page_flipping) + radeon_do_init_pageflip( dev ); + + radeon_cp_dispatch_flip( dev ); + + COMMIT_RING(); + return 0; +} + +static int radeon_cp_swap( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + DRM_DEBUG( "\n" ); + + LOCK_TEST_WITH_RETURN( dev, filp ); + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + + if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; + + radeon_cp_dispatch_swap( dev ); + dev_priv->sarea_priv->ctx_owner = 0; + + COMMIT_RING(); + return 0; +} + +static int radeon_cp_vertex( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_file_t *filp_priv; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_radeon_vertex_t vertex; + drm_radeon_tcl_prim_t prim; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + + DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t __user *)data, + sizeof(vertex) ); + + DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", + DRM_CURRENTPID, + vertex.idx, vertex.count, vertex.discard ); + + if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + vertex.idx, dma->buf_count - 1 ); + return DRM_ERR(EINVAL); + } + if ( vertex.prim < 0 || + vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { + DRM_ERROR( "buffer prim %d\n", vertex.prim ); + return DRM_ERR(EINVAL); + } + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + VB_AGE_TEST_WITH_RETURN( dev_priv ); + + buf = dma->buflist[vertex.idx]; + + if ( buf->filp != filp ) { + DRM_ERROR( "process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp ); + return DRM_ERR(EINVAL); + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); + return DRM_ERR(EINVAL); + } + + /* Build up a prim_t record: + */ + if (vertex.count) { + buf->used = vertex.count; /* not used? */ + + if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { + if ( radeon_emit_state( dev_priv, filp_priv, + &sarea_priv->context_state, + sarea_priv->tex_state, + sarea_priv->dirty ) ) { + DRM_ERROR( "radeon_emit_state failed\n" ); + return DRM_ERR( EINVAL ); + } + + sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | + RADEON_UPLOAD_TEX1IMAGES | + RADEON_UPLOAD_TEX2IMAGES | + RADEON_REQUIRE_QUIESCENCE); + } + + prim.start = 0; + prim.finish = vertex.count; /* unused */ + prim.prim = vertex.prim; + prim.numverts = vertex.count; + prim.vc_format = dev_priv->sarea_priv->vc_format; + + radeon_cp_dispatch_vertex( dev, buf, &prim ); + } + + if (vertex.discard) { + radeon_cp_discard_buffer( dev, buf ); + } + + COMMIT_RING(); + return 0; +} + +static int radeon_cp_indices( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_file_t *filp_priv; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_radeon_indices_t elts; + drm_radeon_tcl_prim_t prim; + int count; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + + DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t __user *)data, + sizeof(elts) ); + + DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n", + DRM_CURRENTPID, + elts.idx, elts.start, elts.end, elts.discard ); + + if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + elts.idx, dma->buf_count - 1 ); + return DRM_ERR(EINVAL); + } + if ( elts.prim < 0 || + elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { + DRM_ERROR( "buffer prim %d\n", elts.prim ); + return DRM_ERR(EINVAL); + } + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + VB_AGE_TEST_WITH_RETURN( dev_priv ); + + buf = dma->buflist[elts.idx]; + + if ( buf->filp != filp ) { + DRM_ERROR( "process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp ); + return DRM_ERR(EINVAL); + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", elts.idx ); + return DRM_ERR(EINVAL); + } + + count = (elts.end - elts.start) / sizeof(u16); + elts.start -= RADEON_INDEX_PRIM_OFFSET; + + if ( elts.start & 0x7 ) { + DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); + return DRM_ERR(EINVAL); + } + if ( elts.start < buf->used ) { + DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); + return DRM_ERR(EINVAL); + } + + buf->used = elts.end; + + if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { + if ( radeon_emit_state( dev_priv, filp_priv, + &sarea_priv->context_state, + sarea_priv->tex_state, + sarea_priv->dirty ) ) { + DRM_ERROR( "radeon_emit_state failed\n" ); + return DRM_ERR( EINVAL ); + } + + sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | + RADEON_UPLOAD_TEX1IMAGES | + RADEON_UPLOAD_TEX2IMAGES | + RADEON_REQUIRE_QUIESCENCE); + } + + + /* Build up a prim_t record: + */ + prim.start = elts.start; + prim.finish = elts.end; + prim.prim = elts.prim; + prim.offset = 0; /* offset from start of dma buffers */ + prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ + prim.vc_format = dev_priv->sarea_priv->vc_format; + + radeon_cp_dispatch_indices( dev, buf, &prim ); + if (elts.discard) { + radeon_cp_discard_buffer( dev, buf ); + } + + COMMIT_RING(); + return 0; +} + +static int radeon_cp_texture( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_texture_t tex; + drm_radeon_tex_image_t image; + int ret; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t __user *)data, sizeof(tex) ); + + if ( tex.image == NULL ) { + DRM_ERROR( "null texture image!\n" ); + return DRM_ERR(EINVAL); + } + + if ( DRM_COPY_FROM_USER( &image, + (drm_radeon_tex_image_t __user *)tex.image, + sizeof(image) ) ) + return DRM_ERR(EFAULT); + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + VB_AGE_TEST_WITH_RETURN( dev_priv ); + + ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image ); + + COMMIT_RING(); + return ret; +} + +static int radeon_cp_stipple( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_stipple_t stipple; + u32 mask[32]; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t __user *)data, + sizeof(stipple) ); + + if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) ) + return DRM_ERR(EFAULT); + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + + radeon_cp_dispatch_stipple( dev, mask ); + + COMMIT_RING(); + return 0; +} + +static int radeon_cp_indirect( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_radeon_indirect_t indirect; + RING_LOCALS; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t __user *)data, + sizeof(indirect) ); + + DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", + indirect.idx, indirect.start, + indirect.end, indirect.discard ); + + if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + indirect.idx, dma->buf_count - 1 ); + return DRM_ERR(EINVAL); + } + + buf = dma->buflist[indirect.idx]; + + if ( buf->filp != filp ) { + DRM_ERROR( "process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp ); + return DRM_ERR(EINVAL); + } + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); + return DRM_ERR(EINVAL); + } + + if ( indirect.start < buf->used ) { + DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", + indirect.start, buf->used ); + return DRM_ERR(EINVAL); + } + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + VB_AGE_TEST_WITH_RETURN( dev_priv ); + + buf->used = indirect.end; + + /* Wait for the 3D stream to idle before the indirect buffer + * containing 2D acceleration commands is processed. + */ + BEGIN_RING( 2 ); + + RADEON_WAIT_UNTIL_3D_IDLE(); + + ADVANCE_RING(); + + /* Dispatch the indirect buffer full of commands from the + * X server. This is insecure and is thus only available to + * privileged clients. + */ + radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end ); + if (indirect.discard) { + radeon_cp_discard_buffer( dev, buf ); + } + + + COMMIT_RING(); + return 0; +} + +static int radeon_cp_vertex2( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_file_t *filp_priv; + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_radeon_vertex2_t vertex; + int i; + unsigned char laststate; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + + DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t __user *)data, + sizeof(vertex) ); + + DRM_DEBUG( "pid=%d index=%d discard=%d\n", + DRM_CURRENTPID, + vertex.idx, vertex.discard ); + + if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + vertex.idx, dma->buf_count - 1 ); + return DRM_ERR(EINVAL); + } + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + VB_AGE_TEST_WITH_RETURN( dev_priv ); + + buf = dma->buflist[vertex.idx]; + + if ( buf->filp != filp ) { + DRM_ERROR( "process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp ); + return DRM_ERR(EINVAL); + } + + if ( buf->pending ) { + DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); + return DRM_ERR(EINVAL); + } + + if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) + return DRM_ERR(EINVAL); + + for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) { + drm_radeon_prim_t prim; + drm_radeon_tcl_prim_t tclprim; + + if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) ) + return DRM_ERR(EFAULT); + + if ( prim.stateidx != laststate ) { + drm_radeon_state_t state; + + if ( DRM_COPY_FROM_USER( &state, + &vertex.state[prim.stateidx], + sizeof(state) ) ) + return DRM_ERR(EFAULT); + + if ( radeon_emit_state2( dev_priv, filp_priv, &state ) ) { + DRM_ERROR( "radeon_emit_state2 failed\n" ); + return DRM_ERR( EINVAL ); + } + + laststate = prim.stateidx; + } + + tclprim.start = prim.start; + tclprim.finish = prim.finish; + tclprim.prim = prim.prim; + tclprim.vc_format = prim.vc_format; + + if ( prim.prim & RADEON_PRIM_WALK_IND ) { + tclprim.offset = prim.numverts * 64; + tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ + + radeon_cp_dispatch_indices( dev, buf, &tclprim ); + } else { + tclprim.numverts = prim.numverts; + tclprim.offset = 0; /* not used */ + + radeon_cp_dispatch_vertex( dev, buf, &tclprim ); + } + + if (sarea_priv->nbox == 1) + sarea_priv->nbox = 0; + } + + if ( vertex.discard ) { + radeon_cp_discard_buffer( dev, buf ); + } + + COMMIT_RING(); + return 0; +} + + +static int radeon_emit_packets( + drm_radeon_private_t *dev_priv, + drm_file_t *filp_priv, + drm_radeon_cmd_header_t header, + drm_radeon_cmd_buffer_t *cmdbuf ) +{ + int id = (int)header.packet.packet_id; + int sz, reg; + int *data = (int *)cmdbuf->buf; + RING_LOCALS; + + if (id >= RADEON_MAX_STATE_PACKETS) + return DRM_ERR(EINVAL); + + sz = packet[id].len; + reg = packet[id].start; + + if (sz * sizeof(int) > cmdbuf->bufsz) { + DRM_ERROR( "Packet size provided larger than data provided\n" ); + return DRM_ERR(EINVAL); + } + + if ( radeon_check_and_fixup_packets( dev_priv, filp_priv, id, data ) ) { + DRM_ERROR( "Packet verification failed\n" ); + return DRM_ERR( EINVAL ); + } + + BEGIN_RING(sz+1); + OUT_RING( CP_PACKET0( reg, (sz-1) ) ); + OUT_RING_TABLE( data, sz ); + ADVANCE_RING(); + + cmdbuf->buf += sz * sizeof(int); + cmdbuf->bufsz -= sz * sizeof(int); + return 0; +} + +static __inline__ int radeon_emit_scalars( + drm_radeon_private_t *dev_priv, + drm_radeon_cmd_header_t header, + drm_radeon_cmd_buffer_t *cmdbuf ) +{ + int sz = header.scalars.count; + int start = header.scalars.offset; + int stride = header.scalars.stride; + RING_LOCALS; + + BEGIN_RING( 3+sz ); + OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); + OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); + OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); + OUT_RING_TABLE( cmdbuf->buf, sz ); + ADVANCE_RING(); + cmdbuf->buf += sz * sizeof(int); + cmdbuf->bufsz -= sz * sizeof(int); + return 0; +} + +/* God this is ugly + */ +static __inline__ int radeon_emit_scalars2( + drm_radeon_private_t *dev_priv, + drm_radeon_cmd_header_t header, + drm_radeon_cmd_buffer_t *cmdbuf ) +{ + int sz = header.scalars.count; + int start = ((unsigned int)header.scalars.offset) + 0x100; + int stride = header.scalars.stride; + RING_LOCALS; + + BEGIN_RING( 3+sz ); + OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); + OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); + OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); + OUT_RING_TABLE( cmdbuf->buf, sz ); + ADVANCE_RING(); + cmdbuf->buf += sz * sizeof(int); + cmdbuf->bufsz -= sz * sizeof(int); + return 0; +} + +static __inline__ int radeon_emit_vectors( + drm_radeon_private_t *dev_priv, + drm_radeon_cmd_header_t header, + drm_radeon_cmd_buffer_t *cmdbuf ) +{ + int sz = header.vectors.count; + int start = header.vectors.offset; + int stride = header.vectors.stride; + RING_LOCALS; + + BEGIN_RING( 3+sz ); + OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) ); + OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); + OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) ); + OUT_RING_TABLE( cmdbuf->buf, sz ); + ADVANCE_RING(); + + cmdbuf->buf += sz * sizeof(int); + cmdbuf->bufsz -= sz * sizeof(int); + return 0; +} + + +static int radeon_emit_packet3( drm_device_t *dev, + drm_file_t *filp_priv, + drm_radeon_cmd_buffer_t *cmdbuf ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + unsigned int cmdsz; + int ret; + RING_LOCALS; + + DRM_DEBUG("\n"); + + if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, + cmdbuf, &cmdsz ) ) ) { + DRM_ERROR( "Packet verification failed\n" ); + return ret; + } + + BEGIN_RING( cmdsz ); + OUT_RING_TABLE( cmdbuf->buf, cmdsz ); + ADVANCE_RING(); + + cmdbuf->buf += cmdsz * 4; + cmdbuf->bufsz -= cmdsz * 4; + return 0; +} + + +static int radeon_emit_packet3_cliprect( drm_device_t *dev, + drm_file_t *filp_priv, + drm_radeon_cmd_buffer_t *cmdbuf, + int orig_nbox ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_clip_rect_t box; + unsigned int cmdsz; + int ret; + drm_clip_rect_t __user *boxes = cmdbuf->boxes; + int i = 0; + RING_LOCALS; + + DRM_DEBUG("\n"); + + if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, + cmdbuf, &cmdsz ) ) ) { + DRM_ERROR( "Packet verification failed\n" ); + return ret; + } + + if (!orig_nbox) + goto out; + + do { + if ( i < cmdbuf->nbox ) { + if (DRM_COPY_FROM_USER( &box, &boxes[i], sizeof(box) )) + return DRM_ERR(EFAULT); + /* FIXME The second and subsequent times round + * this loop, send a WAIT_UNTIL_3D_IDLE before + * calling emit_clip_rect(). This fixes a + * lockup on fast machines when sending + * several cliprects with a cmdbuf, as when + * waving a 2D window over a 3D + * window. Something in the commands from user + * space seems to hang the card when they're + * sent several times in a row. That would be + * the correct place to fix it but this works + * around it until I can figure that out - Tim + * Smith */ + if ( i ) { + BEGIN_RING( 2 ); + RADEON_WAIT_UNTIL_3D_IDLE(); + ADVANCE_RING(); + } + radeon_emit_clip_rect( dev_priv, &box ); + } + + BEGIN_RING( cmdsz ); + OUT_RING_TABLE( cmdbuf->buf, cmdsz ); + ADVANCE_RING(); + + } while ( ++i < cmdbuf->nbox ); + if (cmdbuf->nbox == 1) + cmdbuf->nbox = 0; + + out: + cmdbuf->buf += cmdsz * 4; + cmdbuf->bufsz -= cmdsz * 4; + return 0; +} + + +static int radeon_emit_wait( drm_device_t *dev, int flags ) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + + DRM_DEBUG("%s: %x\n", __FUNCTION__, flags); + switch (flags) { + case RADEON_WAIT_2D: + BEGIN_RING( 2 ); + RADEON_WAIT_UNTIL_2D_IDLE(); + ADVANCE_RING(); + break; + case RADEON_WAIT_3D: + BEGIN_RING( 2 ); + RADEON_WAIT_UNTIL_3D_IDLE(); + ADVANCE_RING(); + break; + case RADEON_WAIT_2D|RADEON_WAIT_3D: + BEGIN_RING( 2 ); + RADEON_WAIT_UNTIL_IDLE(); + ADVANCE_RING(); + break; + default: + return DRM_ERR(EINVAL); + } + + return 0; +} + +static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_file_t *filp_priv; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf = NULL; + int idx; + drm_radeon_cmd_buffer_t cmdbuf; + drm_radeon_cmd_header_t header; + int orig_nbox, orig_bufsz; + char *kbuf=NULL; + + LOCK_TEST_WITH_RETURN( dev, filp ); + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + + DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t __user *)data, + sizeof(cmdbuf) ); + + RING_SPACE_TEST_WITH_RETURN( dev_priv ); + VB_AGE_TEST_WITH_RETURN( dev_priv ); + + if (cmdbuf.bufsz > 64*1024 || cmdbuf.bufsz<0) { + return DRM_ERR(EINVAL); + } + + /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid + * races between checking values and using those values in other code, + * and simply to avoid a lot of function calls to copy in data. + */ + orig_bufsz = cmdbuf.bufsz; + if (orig_bufsz != 0) { + kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER); + if (kbuf == NULL) + return DRM_ERR(ENOMEM); + if (DRM_COPY_FROM_USER(kbuf, cmdbuf.buf, cmdbuf.bufsz)) { + drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); + return DRM_ERR(EFAULT); + } + cmdbuf.buf = kbuf; + } + + orig_nbox = cmdbuf.nbox; + + while ( cmdbuf.bufsz >= sizeof(header) ) { + + header.i = *(int *)cmdbuf.buf; + cmdbuf.buf += sizeof(header); + cmdbuf.bufsz -= sizeof(header); + + switch (header.header.cmd_type) { + case RADEON_CMD_PACKET: + DRM_DEBUG("RADEON_CMD_PACKET\n"); + if (radeon_emit_packets( dev_priv, filp_priv, header, &cmdbuf )) { + DRM_ERROR("radeon_emit_packets failed\n"); + goto err; + } + break; + + case RADEON_CMD_SCALARS: + DRM_DEBUG("RADEON_CMD_SCALARS\n"); + if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) { + DRM_ERROR("radeon_emit_scalars failed\n"); + goto err; + } + break; + + case RADEON_CMD_VECTORS: + DRM_DEBUG("RADEON_CMD_VECTORS\n"); + if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) { + DRM_ERROR("radeon_emit_vectors failed\n"); + goto err; + } + break; + + case RADEON_CMD_DMA_DISCARD: + DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); + idx = header.dma.buf_idx; + if ( idx < 0 || idx >= dma->buf_count ) { + DRM_ERROR( "buffer index %d (of %d max)\n", + idx, dma->buf_count - 1 ); + goto err; + } + + buf = dma->buflist[idx]; + if ( buf->filp != filp || buf->pending ) { + DRM_ERROR( "bad buffer %p %p %d\n", + buf->filp, filp, buf->pending); + goto err; + } + + radeon_cp_discard_buffer( dev, buf ); + break; + + case RADEON_CMD_PACKET3: + DRM_DEBUG("RADEON_CMD_PACKET3\n"); + if (radeon_emit_packet3( dev, filp_priv, &cmdbuf )) { + DRM_ERROR("radeon_emit_packet3 failed\n"); + goto err; + } + break; + + case RADEON_CMD_PACKET3_CLIP: + DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); + if (radeon_emit_packet3_cliprect( dev, filp_priv, &cmdbuf, orig_nbox )) { + DRM_ERROR("radeon_emit_packet3_clip failed\n"); + goto err; + } + break; + + case RADEON_CMD_SCALARS2: + DRM_DEBUG("RADEON_CMD_SCALARS2\n"); + if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) { + DRM_ERROR("radeon_emit_scalars2 failed\n"); + goto err; + } + break; + + case RADEON_CMD_WAIT: + DRM_DEBUG("RADEON_CMD_WAIT\n"); + if (radeon_emit_wait( dev, header.wait.flags )) { + DRM_ERROR("radeon_emit_wait failed\n"); + goto err; + } + break; + default: + DRM_ERROR("bad cmd_type %d at %p\n", + header.header.cmd_type, + cmdbuf.buf - sizeof(header)); + goto err; + } + } + + if (orig_bufsz != 0) + drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); + + DRM_DEBUG("DONE\n"); + COMMIT_RING(); + return 0; + +err: + if (orig_bufsz != 0) + drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); + return DRM_ERR(EINVAL); +} + + + +static int radeon_cp_getparam( DRM_IOCTL_ARGS ) +{ + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_radeon_getparam_t param; + int value; + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR(EINVAL); + } + + DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t __user *)data, + sizeof(param) ); + + DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); + + switch( param.param ) { + case RADEON_PARAM_GART_BUFFER_OFFSET: + value = dev_priv->gart_buffers_offset; + break; + case RADEON_PARAM_LAST_FRAME: + dev_priv->stats.last_frame_reads++; + value = GET_SCRATCH( 0 ); + break; + case RADEON_PARAM_LAST_DISPATCH: + value = GET_SCRATCH( 1 ); + break; + case RADEON_PARAM_LAST_CLEAR: + dev_priv->stats.last_clear_reads++; + value = GET_SCRATCH( 2 ); + break; + case RADEON_PARAM_IRQ_NR: + value = dev->irq; + break; + case RADEON_PARAM_GART_BASE: + value = dev_priv->gart_vm_start; + break; + case RADEON_PARAM_REGISTER_HANDLE: + value = dev_priv->mmio_offset; + break; + case RADEON_PARAM_STATUS_HANDLE: + value = dev_priv->ring_rptr_offset; + break; +#if BITS_PER_LONG == 32 + /* + * This ioctl() doesn't work on 64-bit platforms because hw_lock is a + * pointer which can't fit into an int-sized variable. According to + * Michel Dänzer, the ioctl() is only used on embedded platforms, so + * not supporting it shouldn't be a problem. If the same functionality + * is needed on 64-bit platforms, a new ioctl() would have to be added, + * so backwards-compatibility for the embedded platforms can be + * maintained. --davidm 4-Feb-2004. + */ + case RADEON_PARAM_SAREA_HANDLE: + /* The lock is the first dword in the sarea. */ + value = (long)dev->lock.hw_lock; + break; +#endif + case RADEON_PARAM_GART_TEX_HANDLE: + value = dev_priv->gart_textures_offset; + break; + default: + return DRM_ERR(EINVAL); + } + + if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { + DRM_ERROR( "copy_to_user\n" ); + return DRM_ERR(EFAULT); + } + + return 0; +} + +static int radeon_cp_setparam( DRM_IOCTL_ARGS ) { + DRM_DEVICE; + drm_radeon_private_t *dev_priv = dev->dev_private; + drm_file_t *filp_priv; + drm_radeon_setparam_t sp; + struct drm_radeon_driver_file_fields *radeon_priv; + + if ( !dev_priv ) { + DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + return DRM_ERR( EINVAL ); + } + + DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + + DRM_COPY_FROM_USER_IOCTL( sp, ( drm_radeon_setparam_t __user * )data, + sizeof( sp ) ); + + switch( sp.param ) { + case RADEON_SETPARAM_FB_LOCATION: + radeon_priv = filp_priv->driver_priv; + radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value; + break; + case RADEON_SETPARAM_SWITCH_TILING: + if (sp.value == 0) { + DRM_DEBUG( "color tiling disabled\n" ); + dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; + dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; + dev_priv->sarea_priv->tiling_enabled = 0; + } + else if (sp.value == 1) { + DRM_DEBUG( "color tiling enabled\n" ); + dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; + dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; + dev_priv->sarea_priv->tiling_enabled = 1; + } + break; + default: + DRM_DEBUG( "Invalid parameter %d\n", sp.param ); + return DRM_ERR( EINVAL ); + } + + return 0; +} + +/* When a client dies: + * - Check for and clean up flipped page state + * - Free any alloced GART memory. + * + * DRM infrastructure takes care of reclaiming dma buffers. + */ +void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp) +{ + if ( dev->dev_private ) { + drm_radeon_private_t *dev_priv = dev->dev_private; + if ( dev_priv->page_flipping ) { + radeon_do_cleanup_pageflip( dev ); + } + radeon_mem_release( filp, dev_priv->gart_heap ); + radeon_mem_release( filp, dev_priv->fb_heap ); + radeon_surfaces_release(filp, dev_priv); + } +} + +void radeon_driver_pretakedown(drm_device_t *dev) +{ + radeon_do_release(dev); +} + +int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + struct drm_radeon_driver_file_fields *radeon_priv; + + radeon_priv = (struct drm_radeon_driver_file_fields *)drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES); + + if (!radeon_priv) + return -ENOMEM; + + filp_priv->driver_priv = radeon_priv; + if ( dev_priv ) + radeon_priv->radeon_fb_delta = dev_priv->fb_location; + else + radeon_priv->radeon_fb_delta = 0; + return 0; +} + + +void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv) +{ + struct drm_radeon_driver_file_fields *radeon_priv = filp_priv->driver_priv; + + drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); +} + +drm_ioctl_desc_t radeon_ioctls[] = { + [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 }, + [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = { radeon_cp_start, 1, 1 }, + [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, + [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, + [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = { radeon_cp_resume, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_RESET)] = { radeon_engine_reset, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = { radeon_cp_clear, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = { radeon_cp_vertex, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = { radeon_cp_texture, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = { radeon_cp_indirect, 1, 1 }, + [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = { radeon_cp_vertex2, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = { radeon_cp_cmdbuf, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = { radeon_cp_getparam, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = { radeon_cp_flip, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = { radeon_mem_alloc, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_FREE)] = { radeon_mem_free, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = { radeon_mem_init_heap,1, 1 }, + [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = { radeon_irq_emit, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = { radeon_irq_wait, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = { radeon_cp_setparam, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = { radeon_surface_alloc,1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = { radeon_surface_free, 1, 0 } +}; + +int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); diff --git a/drivers/char/drm/sis_drm.h b/drivers/char/drm/sis_drm.h new file mode 100644 index 000000000000..e99c3a43abbc --- /dev/null +++ b/drivers/char/drm/sis_drm.h @@ -0,0 +1,42 @@ + +#ifndef __SIS_DRM_H__ +#define __SIS_DRM_H__ + +/* SiS specific ioctls */ +#define NOT_USED_0_3 +#define DRM_SIS_FB_ALLOC 0x04 +#define DRM_SIS_FB_FREE 0x05 +#define NOT_USED_6_12 +#define DRM_SIS_AGP_INIT 0x13 +#define DRM_SIS_AGP_ALLOC 0x14 +#define DRM_SIS_AGP_FREE 0x15 +#define DRM_SIS_FB_INIT 0x16 + +#define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t) +#define DRM_IOCTL_SIS_FB_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t) +#define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t) +#define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t) +#define DRM_IOCTL_SIS_AGP_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t) +#define DRM_IOCTL_SIS_FB_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t) +/* +#define DRM_IOCTL_SIS_FLIP DRM_IOW( 0x48, drm_sis_flip_t) +#define DRM_IOCTL_SIS_FLIP_INIT DRM_IO( 0x49) +#define DRM_IOCTL_SIS_FLIP_FINAL DRM_IO( 0x50) +*/ + +typedef struct { + int context; + unsigned int offset; + unsigned int size; + unsigned long free; +} drm_sis_mem_t; + +typedef struct { + unsigned int offset, size; +} drm_sis_agp_t; + +typedef struct { + unsigned int offset, size; +} drm_sis_fb_t; + +#endif /* __SIS_DRM_H__ */ diff --git a/drivers/char/drm/sis_drv.c b/drivers/char/drm/sis_drv.c new file mode 100644 index 000000000000..f441714faae3 --- /dev/null +++ b/drivers/char/drm/sis_drv.c @@ -0,0 +1,110 @@ +/* sis.c -- sis driver -*- linux-c -*- + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "drmP.h" +#include "sis_drm.h" +#include "sis_drv.h" + +#include "drm_pciids.h" + +static int postinit( struct drm_device *dev, unsigned long flags ) +{ + DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, + dev->primary.minor, + pci_pretty_name(dev->pdev) + ); + return 0; +} + +static int version( drm_version_t *version ) +{ + int len; + + version->version_major = DRIVER_MAJOR; + version->version_minor = DRIVER_MINOR; + version->version_patchlevel = DRIVER_PATCHLEVEL; + DRM_COPY( version->name, DRIVER_NAME ); + DRM_COPY( version->date, DRIVER_DATE ); + DRM_COPY( version->desc, DRIVER_DESC ); + return 0; +} + +static struct pci_device_id pciidlist[] = { + sisdrv_PCI_IDS +}; + +extern drm_ioctl_desc_t sis_ioctls[]; +extern int sis_max_ioctl; + +static struct drm_driver driver = { + .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR, + .context_ctor = sis_init_context, + .context_dtor = sis_final_context, + .reclaim_buffers = drm_core_reclaim_buffers, + .get_map_ofs = drm_core_get_map_ofs, + .get_reg_ofs = drm_core_get_reg_ofs, + .postinit = postinit, + .version = version, + .ioctls = sis_ioctls, + .fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + }, + .pci_driver = { + .name = DRIVER_NAME, + .id_table = pciidlist, + } +}; + +static int __init sis_init(void) +{ + driver.num_ioctls = sis_max_ioctl; + return drm_init(&driver); +} + +static void __exit sis_exit(void) +{ + drm_exit(&driver); +} + +module_init(sis_init); +module_exit(sis_exit); + +MODULE_AUTHOR( DRIVER_AUTHOR ); +MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/sis_drv.h b/drivers/char/drm/sis_drv.h new file mode 100644 index 000000000000..5be36b5caec9 --- /dev/null +++ b/drivers/char/drm/sis_drv.h @@ -0,0 +1,52 @@ +/* sis_drv.h -- Private header for sis driver -*- linux-c -*- + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _SIS_DRV_H_ +#define _SIS_DRV_H_ + +/* General customization: + */ + +#define DRIVER_AUTHOR "SIS" +#define DRIVER_NAME "sis" +#define DRIVER_DESC "SIS 300/630/540" +#define DRIVER_DATE "20030826" +#define DRIVER_MAJOR 1 +#define DRIVER_MINOR 1 +#define DRIVER_PATCHLEVEL 0 + +#include "sis_ds.h" + +typedef struct drm_sis_private { + memHeap_t *AGPHeap; + memHeap_t *FBHeap; +} drm_sis_private_t; + +extern int sis_init_context(drm_device_t *dev, int context); +extern int sis_final_context(drm_device_t *dev, int context); + +#endif diff --git a/drivers/char/drm/sis_ds.c b/drivers/char/drm/sis_ds.c new file mode 100644 index 000000000000..e37ed8ce48df --- /dev/null +++ b/drivers/char/drm/sis_ds.c @@ -0,0 +1,301 @@ +/* sis_ds.c -- Private header for Direct Rendering Manager -*- linux-c -*- + * Created: Mon Jan 4 10:05:05 1999 by sclin@sis.com.tw + * + * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Sung-Ching Lin + * + */ + +#include "drmP.h" +#include "drm.h" +#include "sis_ds.h" + +/* Set Data Structure, not check repeated value + * temporarily used + */ + +set_t *setInit(void) +{ + int i; + set_t *set; + + set = (set_t *)drm_alloc(sizeof(set_t), DRM_MEM_DRIVER); + if (set != NULL) { + for (i = 0; i < SET_SIZE; i++) { + set->list[i].free_next = i + 1; + set->list[i].alloc_next = -1; + } + set->list[SET_SIZE-1].free_next = -1; + set->free = 0; + set->alloc = -1; + set->trace = -1; + } + return set; +} + +int setAdd(set_t *set, ITEM_TYPE item) +{ + int free = set->free; + + if (free != -1) { + set->list[free].val = item; + set->free = set->list[free].free_next; + } else { + return 0; + } + + set->list[free].alloc_next = set->alloc; + set->alloc = free; + set->list[free].free_next = -1; + + return 1; +} + +int setDel(set_t *set, ITEM_TYPE item) +{ + int alloc = set->alloc; + int prev = -1; + + while (alloc != -1) { + if (set->list[alloc].val == item) { + if (prev != -1) + set->list[prev].alloc_next = + set->list[alloc].alloc_next; + else + set->alloc = set->list[alloc].alloc_next; + break; + } + prev = alloc; + alloc = set->list[alloc].alloc_next; + } + + if (alloc == -1) + return 0; + + set->list[alloc].free_next = set->free; + set->free = alloc; + set->list[alloc].alloc_next = -1; + + return 1; +} + +/* setFirst -> setAdd -> setNext is wrong */ + +int setFirst(set_t *set, ITEM_TYPE *item) +{ + if (set->alloc == -1) + return 0; + + *item = set->list[set->alloc].val; + set->trace = set->list[set->alloc].alloc_next; + + return 1; +} + +int setNext(set_t *set, ITEM_TYPE *item) +{ + if (set->trace == -1) + return 0; + + *item = set->list[set->trace].val; + set->trace = set->list[set->trace].alloc_next; + + return 1; +} + +int setDestroy(set_t *set) +{ + drm_free(set, sizeof(set_t), DRM_MEM_DRIVER); + + return 1; +} + +/* + * GLX Hardware Device Driver common code + * Copyright (C) 1999 Wittawat Yamwong + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#define ISFREE(bptr) ((bptr)->free) + +memHeap_t *mmInit(int ofs, + int size) +{ + PMemBlock blocks; + + if (size <= 0) + return NULL; + + blocks = (TMemBlock *)drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER); + if (blocks != NULL) { + blocks->ofs = ofs; + blocks->size = size; + blocks->free = 1; + return (memHeap_t *)blocks; + } else + return NULL; +} + +/* Checks if a pointer 'b' is part of the heap 'heap' */ +int mmBlockInHeap(memHeap_t *heap, PMemBlock b) +{ + TMemBlock *p; + + if (heap == NULL || b == NULL) + return 0; + + p = heap; + while (p != NULL && p != b) { + p = p->next; + } + if (p == b) + return 1; + else + return 0; +} + +static TMemBlock* SliceBlock(TMemBlock *p, + int startofs, int size, + int reserved, int alignment) +{ + TMemBlock *newblock; + + /* break left */ + if (startofs > p->ofs) { + newblock = (TMemBlock*) drm_calloc(1, sizeof(TMemBlock), + DRM_MEM_DRIVER); + newblock->ofs = startofs; + newblock->size = p->size - (startofs - p->ofs); + newblock->free = 1; + newblock->next = p->next; + p->size -= newblock->size; + p->next = newblock; + p = newblock; + } + + /* break right */ + if (size < p->size) { + newblock = (TMemBlock*) drm_calloc(1, sizeof(TMemBlock), + DRM_MEM_DRIVER); + newblock->ofs = startofs + size; + newblock->size = p->size - size; + newblock->free = 1; + newblock->next = p->next; + p->size = size; + p->next = newblock; + } + + /* p = middle block */ + p->align = alignment; + p->free = 0; + p->reserved = reserved; + return p; +} + +PMemBlock mmAllocMem( memHeap_t *heap, int size, int align2, int startSearch) +{ + int mask,startofs, endofs; + TMemBlock *p; + + if (heap == NULL || align2 < 0 || size <= 0) + return NULL; + + mask = (1 << align2)-1; + startofs = 0; + p = (TMemBlock *)heap; + while (p != NULL) { + if (ISFREE(p)) { + startofs = (p->ofs + mask) & ~mask; + if ( startofs < startSearch ) { + startofs = startSearch; + } + endofs = startofs+size; + if (endofs <= (p->ofs+p->size)) + break; + } + p = p->next; + } + if (p == NULL) + return NULL; + p = SliceBlock(p,startofs,size,0,mask+1); + p->heap = heap; + return p; +} + +static __inline__ int Join2Blocks(TMemBlock *p) +{ + if (p->free && p->next && p->next->free) { + TMemBlock *q = p->next; + p->size += q->size; + p->next = q->next; + drm_free(q, sizeof(TMemBlock), DRM_MEM_DRIVER); + return 1; + } + return 0; +} + +int mmFreeMem(PMemBlock b) +{ + TMemBlock *p, *prev; + + if (b == NULL) + return 0; + if (b->heap == NULL) + return -1; + + p = b->heap; + prev = NULL; + while (p != NULL && p != b) { + prev = p; + p = p->next; + } + if (p == NULL || p->free || p->reserved) + return -1; + + p->free = 1; + Join2Blocks(p); + if (prev) + Join2Blocks(prev); + return 0; +} + diff --git a/drivers/char/drm/sis_ds.h b/drivers/char/drm/sis_ds.h new file mode 100644 index 000000000000..171ee75afa57 --- /dev/null +++ b/drivers/char/drm/sis_ds.h @@ -0,0 +1,145 @@ +/* sis_ds.h -- Private header for Direct Rendering Manager -*- linux-c -*- + * Created: Mon Jan 4 10:05:05 1999 by sclin@sis.com.tw + * + * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Sung-Ching Lin + * + */ + +#ifndef __SIS_DS_H__ +#define __SIS_DS_H__ + +/* Set Data Structure */ + +#define SET_SIZE 5000 + +typedef unsigned int ITEM_TYPE; + +typedef struct { + ITEM_TYPE val; + int alloc_next, free_next; +} list_item_t; + +typedef struct { + int alloc; + int free; + int trace; + list_item_t list[SET_SIZE]; +} set_t; + +set_t *setInit(void); +int setAdd(set_t *set, ITEM_TYPE item); +int setDel(set_t *set, ITEM_TYPE item); +int setFirst(set_t *set, ITEM_TYPE *item); +int setNext(set_t *set, ITEM_TYPE *item); +int setDestroy(set_t *set); + +/* + * GLX Hardware Device Driver common code + * Copyright (C) 1999 Wittawat Yamwong + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +struct mem_block_t { + struct mem_block_t *next; + struct mem_block_t *heap; + int ofs,size; + int align; + unsigned int free:1; + unsigned int reserved:1; +}; +typedef struct mem_block_t TMemBlock; +typedef struct mem_block_t *PMemBlock; + +/* a heap is just the first block in a chain */ +typedef struct mem_block_t memHeap_t; + +static __inline__ int mmBlockSize(PMemBlock b) +{ + return b->size; +} + +static __inline__ int mmOffset(PMemBlock b) +{ + return b->ofs; +} + +static __inline__ void mmMarkReserved(PMemBlock b) +{ + b->reserved = 1; +} + +/* + * input: total size in bytes + * return: a heap pointer if OK, NULL if error + */ +memHeap_t *mmInit( int ofs, int size ); + +/* + * Allocate 'size' bytes with 2^align2 bytes alignment, + * restrict the search to free memory after 'startSearch' + * depth and back buffers should be in different 4mb banks + * to get better page hits if possible + * input: size = size of block + * align2 = 2^align2 bytes alignment + * startSearch = linear offset from start of heap to begin search + * return: pointer to the allocated block, 0 if error + */ +PMemBlock mmAllocMem( memHeap_t *heap, int size, int align2, int startSearch ); + +/* + * Returns 1 if the block 'b' is part of the heap 'heap' + */ +int mmBlockInHeap( PMemBlock heap, PMemBlock b ); + +/* + * Free block starts at offset + * input: pointer to a block + * return: 0 if OK, -1 if error + */ +int mmFreeMem( PMemBlock b ); + +/* For debuging purpose. */ +void mmDumpMemInfo( memHeap_t *mmInit ); + +#endif /* __SIS_DS_H__ */ diff --git a/drivers/char/drm/sis_mm.c b/drivers/char/drm/sis_mm.c new file mode 100644 index 000000000000..6610c5576d22 --- /dev/null +++ b/drivers/char/drm/sis_mm.c @@ -0,0 +1,417 @@ +/* sis_mm.c -- Private header for Direct Rendering Manager -*- linux-c -*- + * Created: Mon Jan 4 10:05:05 1999 by sclin@sis.com.tw + * + * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Sung-Ching Lin + * + */ + +#include "drmP.h" +#include "sis_drm.h" +#include "sis_drv.h" +#include "sis_ds.h" +#if defined(__linux__) && defined(CONFIG_FB_SIS) +#include