From 9fcb6be3b6c994f275761b22800e4244f610bdc5 Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Wed, 14 Nov 2018 13:01:47 +0000 Subject: clk: imx: add pfdv2 support The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pfdv2 can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd --- drivers/clk/imx/clk.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/clk/imx/clk.h') diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 3364e080ccdf..153d9a436ded 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -60,6 +60,9 @@ struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, struct clk *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx); +struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name, + void __iomem *reg, u8 idx); + struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift); -- cgit