From 1f737ffa13efd3da2c703d45894ea234e9290c89 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 28 Jul 2017 18:32:28 +0200 Subject: clk: meson: mpll: fix mpll0 fractional part ignored mpll0 clock is special compared to the other mplls. It needs another bit (ssen) to be set to activate the fractional part the mpll divider Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation") Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- drivers/clk/meson/clk-mpll.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/clk/meson/clk-mpll.c') diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index 39eab69fe51a..44a5a535ca63 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -161,6 +161,13 @@ static int mpll_set_rate(struct clk_hw *hw, reg = PARM_SET(p->width, p->shift, reg, 1); writel(reg, mpll->base + p->reg_off); + p = &mpll->ssen; + if (p->width != 0) { + reg = readl(mpll->base + p->reg_off); + reg = PARM_SET(p->width, p->shift, reg, 1); + writel(reg, mpll->base + p->reg_off); + } + p = &mpll->n2; reg = readl(mpll->base + p->reg_off); reg = PARM_SET(p->width, p->shift, reg, n2); -- cgit