From 7bed92460d910c75f0d722f1240d2dc1d466d884 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 29 Dec 2016 10:45:10 +0800 Subject: clk: rockchip: add new pll-type for rk3328 The rk3328's pll and clock are similar with rk3036's, it different with pll_mode_mask, the rk3328 soc pll mode only one bit(rk3036 soc have two bits) so these should be independent and separate from the series of rk3328s. Signed-off-by: Elaine Zhang Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/rockchip/clk.h') diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 58be202c55d9..8f83cde407c9 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -130,6 +130,7 @@ struct clk; enum rockchip_pll_type { pll_rk3036, pll_rk3066, + pll_rk3328, pll_rk3399, }; -- cgit