From 8432984732b59b333706fceb4cfb5123140be827 Mon Sep 17 00:00:00 2001
From: Pankaj Dubey <pankaj.dubey@samsung.com>
Date: Wed, 12 Mar 2014 20:26:45 +0530
Subject: clk/samsung: add support for pll2550xx

exynos5260 use pll2550xx and it has different bit fields
for P,M,S values as compared to pll2550. Support for
pll2550xx is added here.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
 drivers/clk/samsung/clk-pll.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'drivers/clk/samsung/clk-pll.h')

diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 6428bcc6df6f..ec4bc1d45e31 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -31,6 +31,7 @@ enum samsung_pll_type {
 	pll_s3c2410_mpll,
 	pll_s3c2410_upll,
 	pll_s3c2440_mpll,
+	pll_2550xx,
 };
 
 #define PLL_35XX_RATE(_rate, _m, _p, _s)			\
-- 
cgit