From b4054ac6a26ee94a3a0f18e9ea585545d69e29c2 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Mon, 26 Aug 2013 19:09:05 +0200 Subject: clk: samsung: pll: Add support for rate configuration of PLL45xx This patch implements round_rate and set_rate callbacks of PLL45xx driver to allow reconfiguration of PLL at runtime. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Reviewed-by: Sylwester Nawrocki Signed-off-by: Mike Turquette --- drivers/clk/samsung/clk-pll.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/clk/samsung/clk-pll.h') diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index fceb2cb00f2a..2c331291fe40 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -41,6 +41,15 @@ enum samsung_pll_type { .kdiv = (_k), \ } +#define PLL_45XX_RATE(_rate, _m, _p, _s, _afc) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + .afc = (_afc), \ + } + /* NOTE: Rate table should be kept sorted in descending order. */ struct samsung_pll_rate_table { @@ -49,6 +58,7 @@ struct samsung_pll_rate_table { unsigned int mdiv; unsigned int sdiv; unsigned int kdiv; + unsigned int afc; }; enum pll46xx_type { -- cgit