From 1318952514d5651c453d89989595a9df3b37267b Mon Sep 17 00:00:00 2001 From: Doug Thompson Date: Fri, 30 Jun 2006 01:56:08 -0700 Subject: [PATCH] EDAC: probe1 cleanup 1-of-2 - Add lower-level functions that handle various parts of the initialization done by the xxx_probe1() functions. Some of the xxx_probe1() functions are much too long and complicated (see "Chapter 5: Functions" in Documentation/CodingStyle). - Cleanup of probe1() functions in EDAC Signed-off-by: Doug Thompson Cc: Alan Cox Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/edac/e7xxx_edac.c | 158 ++++++++++++++++++++++++---------------------- 1 file changed, 82 insertions(+), 76 deletions(-) (limited to 'drivers/edac/e7xxx_edac.c') diff --git a/drivers/edac/e7xxx_edac.c b/drivers/edac/e7xxx_edac.c index 1e282c843e77..9878379b4993 100644 --- a/drivers/edac/e7xxx_edac.c +++ b/drivers/edac/e7xxx_edac.c @@ -335,99 +335,61 @@ static void e7xxx_check(struct mem_ctl_info *mci) e7xxx_process_error_info(mci, &info, 1); } -static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx) +/* Return 1 if dual channel mode is active. Else return 0. */ +static inline int dual_channel_active(u32 drc, int dev_idx) { - int rc = -ENODEV; - int index; - u16 pci_data; - struct mem_ctl_info *mci = NULL; - struct e7xxx_pvt *pvt = NULL; - u32 drc; - int drc_chan = 1; /* Number of channels 0=1chan,1=2chan */ - int drc_drbg = 1; /* DRB granularity 0=32mb,1=64mb */ - int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */ - u32 dra; - unsigned long last_cumul_size; - struct e7xxx_error_info discard; - - debugf0("%s(): mci\n", __func__); + return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1; +} - /* need to find out the number of channels */ - pci_read_config_dword(pdev, E7XXX_DRC, &drc); +/* Return DRB granularity (0=32mb, 1=64mb). */ +static inline int drb_granularity(u32 drc, int dev_idx) +{ /* only e7501 can be single channel */ - if (dev_idx == E7501) { - drc_chan = ((drc >> 22) & 0x1); - drc_drbg = (drc >> 18) & 0x3; - } - - drc_ddim = (drc >> 20) & 0x3; - mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1); - - if (mci == NULL) { - rc = -ENOMEM; - goto fail; - } - - debugf3("%s(): init mci\n", __func__); - mci->mtype_cap = MEM_FLAG_RDDR; - mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | - EDAC_FLAG_S4ECD4ED; - /* FIXME - what if different memory types are in different csrows? */ - mci->mod_name = EDAC_MOD_STR; - mci->mod_ver = E7XXX_REVISION; - mci->dev = &pdev->dev; - - debugf3("%s(): init pvt\n", __func__); - pvt = (struct e7xxx_pvt *) mci->pvt_info; - pvt->dev_info = &e7xxx_devs[dev_idx]; - pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, - pvt->dev_info->err_dev, - pvt->bridge_ck); + return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1; +} - if (!pvt->bridge_ck) { - e7xxx_printk(KERN_ERR, "error reporting device not found:" - "vendor %x device 0x%x (broken BIOS?)\n", - PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev); - goto fail; - } - debugf3("%s(): more mci init\n", __func__); - mci->ctl_name = pvt->dev_info->ctl_name; - mci->edac_check = e7xxx_check; - mci->ctl_page_to_phys = ctl_page_to_phys; +static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, + int dev_idx, u32 drc) +{ + unsigned long last_cumul_size; + int index; + u8 value; + u32 dra, cumul_size; + int drc_chan, drc_drbg, drc_ddim, mem_dev; + struct csrow_info *csrow; - /* find out the device types */ pci_read_config_dword(pdev, E7XXX_DRA, &dra); + drc_chan = dual_channel_active(drc, dev_idx); + drc_drbg = drb_granularity(drc, dev_idx); + drc_ddim = (drc >> 20) & 0x3; + last_cumul_size = 0; - /* - * The dram row boundary (DRB) reg values are boundary address + /* The dram row boundary (DRB) reg values are boundary address * for each DRAM row with a granularity of 32 or 64MB (single/dual * channel operation). DRB regs are cumulative; therefore DRB7 will * contain the total memory contained in all eight rows. */ - for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) { - u8 value; - u32 cumul_size; + for (index = 0; index < mci->nr_csrows; index++) { /* mem_dev 0=x8, 1=x4 */ - int mem_dev = (dra >> (index * 4 + 3)) & 0x1; - struct csrow_info *csrow = &mci->csrows[index]; + mem_dev = (dra >> (index * 4 + 3)) & 0x1; + csrow = &mci->csrows[index]; pci_read_config_byte(pdev, E7XXX_DRB + index, &value); /* convert a 64 or 32 MiB DRB to a page size. */ cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, cumul_size); - if (cumul_size == last_cumul_size) - continue; /* not populated */ + continue; /* not populated */ csrow->first_page = last_cumul_size; csrow->last_page = cumul_size - 1; csrow->nr_pages = cumul_size - last_cumul_size; last_cumul_size = cumul_size; - csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ - csrow->mtype = MEM_RDDR; /* only one type supported */ + csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ + csrow->mtype = MEM_RDDR; /* only one type supported */ csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; /* @@ -445,9 +407,54 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx) } else csrow->edac_mode = EDAC_NONE; } +} - mci->edac_cap |= EDAC_FLAG_NONE; +static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx) +{ + u16 pci_data; + struct mem_ctl_info *mci = NULL; + struct e7xxx_pvt *pvt = NULL; + u32 drc; + int drc_chan; + struct e7xxx_error_info discard; + + debugf0("%s(): mci\n", __func__); + pci_read_config_dword(pdev, E7XXX_DRC, &drc); + + drc_chan = dual_channel_active(drc, dev_idx); + mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1); + + if (mci == NULL) + return -ENOMEM; + debugf3("%s(): init mci\n", __func__); + mci->mtype_cap = MEM_FLAG_RDDR; + mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | + EDAC_FLAG_S4ECD4ED; + /* FIXME - what if different memory types are in different csrows? */ + mci->mod_name = EDAC_MOD_STR; + mci->mod_ver = E7XXX_REVISION; + mci->dev = &pdev->dev; + debugf3("%s(): init pvt\n", __func__); + pvt = (struct e7xxx_pvt *) mci->pvt_info; + pvt->dev_info = &e7xxx_devs[dev_idx]; + pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, + pvt->dev_info->err_dev, + pvt->bridge_ck); + + if (!pvt->bridge_ck) { + e7xxx_printk(KERN_ERR, "error reporting device not found:" + "vendor %x device 0x%x (broken BIOS?)\n", + PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev); + goto fail0; + } + + debugf3("%s(): more mci init\n", __func__); + mci->ctl_name = pvt->dev_info->ctl_name; + mci->edac_check = e7xxx_check; + mci->ctl_page_to_phys = ctl_page_to_phys; + e7xxx_init_csrows(mci, pdev, dev_idx, drc); + mci->edac_cap |= EDAC_FLAG_NONE; debugf3("%s(): tolm, remapbase, remaplimit\n", __func__); /* load the top of low memory, remap base, and remap limit vars */ pci_read_config_word(pdev, E7XXX_TOLM, &pci_data); @@ -468,21 +475,20 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx) */ if (edac_mc_add_mc(mci,0)) { debugf3("%s(): failed edac_mc_add_mc()\n", __func__); - goto fail; + goto fail1; } /* get this far and it's successful */ debugf3("%s(): success\n", __func__); return 0; -fail: - if (mci != NULL) { - if(pvt != NULL && pvt->bridge_ck) - pci_dev_put(pvt->bridge_ck); - edac_mc_free(mci); - } +fail1: + pci_dev_put(pvt->bridge_ck); + +fail0: + edac_mc_free(mci); - return rc; + return -ENODEV; } /* returns count (>= 0), or negative on error */ -- cgit