From ddb8a8a022b9733e50a353d1d09a95fcdb8d2b8f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 16 Oct 2024 16:31:13 -0400 Subject: EDAC/fsl_ddr: Add support for i.MX9 DDR controller Add support for the i.MX9 DDR controller, which has different register offsets and some function changes compared to the existing fsl_ddr controller. The ECC and error injection functions are almost the same, so update and reuse the driver for i.MX9. Add a special type 'TYPE_IMX9' specifically for the i.MX9 controller to distinguish the differences. Signed-off-by: Ye Li Signed-off-by: Frank Li Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Peng Fan Link: https://lore.kernel.org/r/20241016-imx95_edac-v3-5-86ae6fc2756a@nxp.com --- drivers/edac/fsl_ddr_edac.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/edac/fsl_ddr_edac.h') diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h index de66f9822fba..73618f79e587 100644 --- a/drivers/edac/fsl_ddr_edac.h +++ b/drivers/edac/fsl_ddr_edac.h @@ -39,6 +39,9 @@ #define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54 #define FSL_MC_ERR_SBE 0x0e58 +#define IMX9_MC_ERR_EN 0x1000 +#define IMX9_MC_DATA_ERR_INJECT_OFF 0x100 + #define DSC_MEM_EN 0x80000000 #define DSC_ECC_EN 0x20000000 #define DSC_RD_EN 0x10000000 @@ -46,6 +49,9 @@ #define DSC_DBW_32 0x00080000 #define DSC_DBW_64 0x00000000 +#define ERR_ECC_EN 0x80000000 +#define ERR_INLINE_ECC 0x40000000 + #define DSC_SDTYPE_MASK 0x07000000 #define DSC_X32_EN 0x00000020 @@ -65,14 +71,18 @@ #define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */ #define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */ +#define TYPE_IMX9 0x1 /* MC used by iMX9 having registers changed */ + struct fsl_mc_pdata { char *name; int edac_idx; void __iomem *mc_vbase; + void __iomem *inject_vbase; int irq; u32 orig_ddr_err_disable; u32 orig_ddr_err_sbe; bool little_endian; + unsigned long flag; }; int fsl_mc_err_probe(struct platform_device *op); void fsl_mc_err_remove(struct platform_device *op); -- cgit