From 5c7b0c4e7d5cd9850a93b8a1ea092baf4c8b3cd0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 20 Oct 2017 14:57:37 +0200 Subject: gpio: grgpio: Do not use gc->pin2mask() The pin2mask() accessor only shuffles BIT ORDER in big endian systems, i.e. the bitstuffing is swizzled big endian so "bit 0" is bit 7 or bit 15 or bit 31 or so. The grgpio only uses big endian BYTE ORDER which will be taken car of by the ->write_reg() callback. Just use BIT(offset) to assign the bit. Acked-by: Andreas Larsson Signed-off-by: Linus Walleij --- drivers/gpio/gpio-grgpio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpio') diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c index 6544a16ab02e..e2fc561f4315 100644 --- a/drivers/gpio/gpio-grgpio.c +++ b/drivers/gpio/gpio-grgpio.c @@ -35,6 +35,7 @@ #include #include #include +#include #define GRGPIO_MAX_NGPIO 32 @@ -96,12 +97,11 @@ static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset, int val) { struct gpio_chip *gc = &priv->gc; - unsigned long mask = gc->pin2mask(gc, offset); if (val) - priv->imask |= mask; + priv->imask |= BIT(offset); else - priv->imask &= ~mask; + priv->imask &= ~BIT(offset); gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask); } -- cgit