From d766e6a393383c60a55bdcc72586f21a1ff12509 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 29 Mar 2016 18:28:50 -0400 Subject: drm/amdgpu: switch ih handling to two levels (v3) Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by: Alex Deucher Signed-off-by: Ken Wang Reviewed-by: Ken Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h index ba38ae6a1463..d77c63940a3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -26,6 +26,10 @@ struct amdgpu_device; +#define AMDGPU_IH_CLIENTID_LEGACY 0 + +#define AMDGPU_IH_CLIENTID_MAX 0x1f + /* * R6xx+ IH ring */ @@ -47,10 +51,12 @@ struct amdgpu_ih_ring { }; struct amdgpu_iv_entry { + unsigned client_id; unsigned src_id; unsigned src_data; unsigned ring_id; unsigned vm_id; + unsigned vm_id_src; unsigned pas_id; const uint32_t *iv_entry; }; -- cgit