From 741deade2a704a434bd5939118c43d38e9ddac25 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 13 Sep 2018 15:41:57 -0500 Subject: drm/amdgpu: simplify Raven, Raven2, and Picasso handling Treat them all as Raven rather than adding a new picasso asic type. This simplifies a lot of code and also handles the case of rv2 chips with the 0x15d8 pci id. It also fixes dmcu fw handling for picasso. Acked-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c') diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index 2a126c6950c7..80698b5ffa4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -412,7 +412,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); - if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) { + if (adev->asic_type != CHIP_RAVEN) { def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); } else @@ -428,7 +428,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); - if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) + if (adev->asic_type != CHIP_RAVEN) data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | @@ -445,7 +445,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); - if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) + if (adev->asic_type != CHIP_RAVEN) data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | @@ -458,13 +458,13 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); if (def1 != data1) { - if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) + if (adev->asic_type != CHIP_RAVEN) WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); else WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); } - if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO && def2 != data2) + if (adev->asic_type != CHIP_RAVEN && def2 != data2) WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); } @@ -528,7 +528,6 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, case CHIP_VEGA12: case CHIP_VEGA20: case CHIP_RAVEN: - case CHIP_PICASSO: mmhub_v1_0_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); athub_update_medium_grain_clock_gating(adev, -- cgit