From 4d4d3ff16db2642ade8b2fd64cb1abd65bddcf49 Mon Sep 17 00:00:00 2001 From: Webb Chen Date: Tue, 27 Feb 2024 10:01:25 +0800 Subject: drm/amd/display: Keep VBios pixel rate div setting util next mode set [why] VBios & Driver may have differnet pixel rate div policy. If the policy is not same and fast boot is enabled, it would cause the pixel rate is too high after driver only performs stream blank & unblank. [how] We would keep pixel rate div setting by VBios until next mode set. Reviewed-by: Jun Lei Acked-by: Aurabindo Pillai Signed-off-by: Webb Chen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index d4c7885fc916..d6248a73c7c1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -176,6 +176,11 @@ struct dccg_funcs { enum pixel_rate_div k1, enum pixel_rate_div k2); + void (*get_pixel_rate_div)(struct dccg *dccg, + uint32_t otg_inst, + uint32_t *div_factor1, + uint32_t *div_factor2); + void (*set_valid_pixel_rate)( struct dccg *dccg, int ref_dtbclk_khz, -- cgit From 532a0d2ad2920bc18e73566a112feccfd55ff4de Mon Sep 17 00:00:00 2001 From: Webb Chen Date: Tue, 27 Feb 2024 10:01:25 +0800 Subject: drm/amd/display: Revert "dc: Keep VBios pixel rate div setting util next mode set" This reverts commit 4d4d3ff16db2 ("drm/amd/display: Keep VBios pixel rate div setting util next mode set") which causes issue. Reviewed-by: Charlene Liu Acked-by: Wayne Lin Signed-off-by: Webb Chen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index d6248a73c7c1..d4c7885fc916 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -176,11 +176,6 @@ struct dccg_funcs { enum pixel_rate_div k1, enum pixel_rate_div k2); - void (*get_pixel_rate_div)(struct dccg *dccg, - uint32_t otg_inst, - uint32_t *div_factor1, - uint32_t *div_factor2); - void (*set_valid_pixel_rate)( struct dccg *dccg, int ref_dtbclk_khz, -- cgit From 176278d8bff2c2be000b9c9509a7fc8120b5278d Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Mon, 8 Apr 2024 13:32:53 -0400 Subject: drm/amd/display: reset DSC clock in post unlock update [why] Switching between DSC clock or disable DSC block are not double buffered update. Corruption is observed if these updates happen before DSC double buffered disconnection. [how] Move DSC disable and refclk reset to post unlock update. Wait for DSC double buffered disconnection and all mpccs are disconnected before reset DSC clock. Reviewed-by: Samson Tam Acked-by: Tom Chung Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index d4c7885fc916..867bc67aabfa 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -208,7 +208,8 @@ struct dccg_funcs { uint32_t otg_inst); void (*set_dto_dscclk)( struct dccg *dccg, - uint32_t dsc_inst); + uint32_t dsc_inst, + bool enable); void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst); }; -- cgit From c49e44ede5cdfe650c2f769d8bd58cbe289e87cd Mon Sep 17 00:00:00 2001 From: Daniel Miess Date: Tue, 23 Apr 2024 15:45:59 -0400 Subject: drm/amd/display: Enable SYMCLK gating in DCCG [WHY & HOW] Enable root clock optimization for SYMCLK and only disable it when it's actively used. Reviewed-by: Charlene Liu Acked-by: Alex Hung Signed-off-by: Daniel Miess Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 867bc67aabfa..5b0924ea78af 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -199,6 +199,13 @@ struct dccg_funcs { struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst); + + void (*set_symclk_root_clock_gating)( + struct dccg *dccg, + uint32_t stream_enc_inst, + uint32_t link_enc_inst, + bool enable); + void (*set_dp_dto)( struct dccg *dccg, const struct dp_dto_params *params); -- cgit From 56116dc7a9fdd2ce2b0e01d16f772a766a0219e0 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Fri, 10 May 2024 15:19:05 -0600 Subject: Revert "drm/amd/display: Enable SYMCLK gating in DCCG" This reverts commit c49e44ede5cdfe650c2f769d8bd58cbe289e87cd. This causes regression on DP link layer test. Reported-by: Mark Broadworth Acked-by: Rodrigo Siqueira Signed-off-by: Alex Hung Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 5b0924ea78af..867bc67aabfa 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -199,13 +199,6 @@ struct dccg_funcs { struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst); - - void (*set_symclk_root_clock_gating)( - struct dccg *dccg, - uint32_t stream_enc_inst, - uint32_t link_enc_inst, - bool enable); - void (*set_dp_dto)( struct dccg *dccg, const struct dp_dto_params *params); -- cgit From 975507d73c44e9382478d6fd2d49c5e660cca4f4 Mon Sep 17 00:00:00 2001 From: yi-lchen Date: Mon, 29 Apr 2024 14:28:36 +0800 Subject: drm/amd/display: Keep VBios pixel rate div setting until next mode set [why] Vbios & Driver have difference pixel rate div policy. When enabling fast boot & performing blank & unblank w/o timing setting, pixel clock & pixel rate dividor are not match. It would cause too high pixel reate and eDP would be black screen. [How] We would keep pixel rate div setting by Vbios until next timing setting. Reviewed-by: Jun Lei Acked-by: Zaeem Mohamed Signed-off-by: yi-lchen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 867bc67aabfa..4fb1aacee894 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -176,6 +176,11 @@ struct dccg_funcs { enum pixel_rate_div k1, enum pixel_rate_div k2); + void (*get_pixel_rate_div)(struct dccg *dccg, + uint32_t otg_inst, + uint32_t *div_factor1, + uint32_t *div_factor2); + void (*set_valid_pixel_rate)( struct dccg *dccg, int ref_dtbclk_khz, -- cgit