From a51482458dafb836dbf7c8ae3200ca8db7348201 Mon Sep 17 00:00:00 2001 From: Zhan Liu Date: Mon, 14 Jun 2021 14:54:14 -0400 Subject: drm/amd/display: Enabling eDP no power sequencing with DAL feature mask [Why] Sometimes, DP receiver chip power-controlled externally by an Embedded Controller could be treated and used as eDP, if it drives mobile display. In this case, we shouldn't be doing power-sequencing, hence we can skip waiting for T7-ready and T9-ready." [How] Added a feature mask to enable eDP no power sequencing feature. To enable this, set 0x10 flag in amdgpu.dcfeaturemask on Linux command line. Signed-off-by: Zhan Liu Reviewed-by: Nikola Cornij Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/amd_shared.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/include') diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 332b0df53e52..ff1d3d4a6488 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -223,10 +223,12 @@ enum amd_harvest_ip_mask { }; enum DC_FEATURE_MASK { - DC_FBC_MASK = 0x1, - DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2, - DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4, - DC_PSR_MASK = 0x8, + //Default value can be found at "uint amdgpu_dc_feature_mask" + DC_FBC_MASK = (1 << 0), //0x1, disabled by default + DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1), //0x2, enabled by default + DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), //0x4, disabled by default + DC_PSR_MASK = (1 << 3), //0x8, disabled by default + DC_EDP_NO_POWER_SEQUENCING = (1 << 4), //0x10, disabled by default }; enum DC_DEBUG_MASK { -- cgit