From f141e251474d673f75e8c16dbdabeb4da3939d7e Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Fri, 11 Feb 2022 11:28:47 +0800 Subject: drm/amd/pm: validate SMU feature enable message for getting feature enabled mask There's always miss the SMU feature enabled checked in the NPI phase, so let validate the SMU feature enable message directly rather than add more and more MP1 version check. Signed-off-by: Prike Liang Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c') diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c index b3a0f3fb3e65..f1a4a720d426 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c @@ -552,6 +552,16 @@ static int cyan_skillfish_get_dpm_ultimate_freq(struct smu_context *smu, return 0; } +static int cyan_skillfish_get_enabled_mask(struct smu_context *smu, + uint64_t *feature_mask) +{ + if (!feature_mask) + return -EINVAL; + memset(feature_mask, 0xff, sizeof(*feature_mask)); + + return 0; +} + static const struct pptable_funcs cyan_skillfish_ppt_funcs = { .check_fw_status = smu_v11_0_check_fw_status, @@ -562,7 +572,7 @@ static const struct pptable_funcs cyan_skillfish_ppt_funcs = { .fini_smc_tables = smu_v11_0_fini_smc_tables, .read_sensor = cyan_skillfish_read_sensor, .print_clk_levels = cyan_skillfish_print_clk_levels, - .get_enabled_mask = smu_cmn_get_enabled_mask, + .get_enabled_mask = cyan_skillfish_get_enabled_mask, .is_dpm_running = cyan_skillfish_is_dpm_running, .get_gpu_metrics = cyan_skillfish_get_gpu_metrics, .od_edit_dpm_table = cyan_skillfish_od_edit_dpm_table, -- cgit