From d8e0b16d818ebd76386029fe098cddbae49bfaf5 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 8 Jul 2020 12:45:00 +0800 Subject: drm/amd/powerplay: tag swSMU code layers Per designs, the swSMU code is separated into four layers. And the typical calling flow should be like: amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c -> smu_cmn.c. Compile errors will come out for any violations. This can help to prevent cross callings(e.g. amdgpu_smu.c -> ${asic}_ppt.c -> amdgpu_smu.c -> ${asic}_ppt.c) which were common in our code. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 ++ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 3 +++ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 3 +++ 3 files changed, 8 insertions(+) (limited to 'drivers/gpu/drm/amd/powerplay/inc') diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index a152ea0cab74..896b443f1ce8 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -653,6 +653,7 @@ enum smu_cmn2asic_mapping_type { #define WORKLOAD_MAP(profile, workload) \ [profile] = {1, (workload)} +#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) int smu_load_microcode(struct smu_context *smu); int smu_check_fw_status(struct smu_context *smu); @@ -790,3 +791,4 @@ int smu_get_dpm_clock_table(struct smu_context *smu, int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value); #endif +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h index b695b8800b3b..b18ee5837f50 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h @@ -134,6 +134,8 @@ enum smu_v11_0_baco_seq { BACO_SEQ_COUNT, }; +#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) + int smu_v11_0_init_microcode(struct smu_context *smu); void smu_v11_0_fini_microcode(struct smu_context *smu); @@ -263,3 +265,4 @@ int smu_v11_0_get_dpm_level_range(struct smu_context *smu, uint32_t *max_value); #endif +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h index 52cdd6a0f99a..02de3b6199e5 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h @@ -31,6 +31,8 @@ #define MP1_Public 0x03b00000 #define MP1_SRAM 0x03c00004 +#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) + int smu_v12_0_check_fw_status(struct smu_context *smu); int smu_v12_0_check_fw_version(struct smu_context *smu); @@ -59,3 +61,4 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_ int smu_v12_0_set_driver_table_location(struct smu_context *smu); #endif +#endif -- cgit