From 6c339f37f1cd9b910f4c04b14079b1663b685c4d Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Mon, 6 Jul 2020 16:11:31 +0800 Subject: drm/amd/powerplay: unify swSMU index to asic specific index mapping By this we can drop redundant code. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 56 +++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/drm/amd/powerplay/navi10_ppt.c') diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 0c21e5de8997..aeca8a8730f5 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -42,6 +42,7 @@ #include "thm/thm_11_0_2_sh_mask.h" #include "asic_reg/mp/mp_11_0_sh_mask.h" +#include "smu_cmn.h" /* * DO NOT use these for err/warn/info/debug messages. @@ -64,10 +65,7 @@ FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) -#define MSG_MAP(msg, index, valid_in_vf) \ - [SMU_MSG_##msg] = {1, (index), (valid_in_vf)} - -static struct smu_11_0_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { +static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), @@ -138,7 +136,7 @@ static struct smu_11_0_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), }; -static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = { +static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = { CLK_MAP(GFXCLK, PPCLK_GFXCLK), CLK_MAP(SCLK, PPCLK_GFXCLK), CLK_MAP(SOCCLK, PPCLK_SOCCLK), @@ -153,7 +151,7 @@ static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = { CLK_MAP(PHYCLK, PPCLK_PHYCLK), }; -static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = { +static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = { FEA_MAP(DPM_PREFETCHER), FEA_MAP(DPM_GFXCLK), FEA_MAP(DPM_GFX_PACE), @@ -199,7 +197,7 @@ static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUN FEA_MAP(APCC_DFLL), }; -static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = { +static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = { TAB_MAP(PPTABLE), TAB_MAP(WATERMARKS), TAB_MAP(AVFS), @@ -214,12 +212,12 @@ static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = { TAB_MAP(PACE), }; -static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { +static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { PWR_MAP(AC), PWR_MAP(DC), }; -static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { +static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), @@ -231,6 +229,7 @@ static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index) { +#if 0 struct smu_11_0_msg_mapping mapping; if (index >= SMU_MSG_MAX_COUNT) @@ -245,10 +244,13 @@ static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index) return -EACCES; return mapping.map_to; +#endif + return 0; } static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index) { +#if 0 struct smu_11_0_cmn2aisc_mapping mapping; if (index >= SMU_CLK_COUNT) @@ -260,10 +262,13 @@ static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index) } return mapping.map_to; +#endif + return 0; } static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index) { +#if 0 struct smu_11_0_cmn2aisc_mapping mapping; if (index >= SMU_FEATURE_COUNT) @@ -275,10 +280,13 @@ static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index) } return mapping.map_to; +#endif + return 0; } static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index) { +#if 0 struct smu_11_0_cmn2aisc_mapping mapping; if (index >= SMU_TABLE_COUNT) @@ -290,10 +298,13 @@ static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index) } return mapping.map_to; +#endif + return 0; } static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index) { +#if 0 struct smu_11_0_cmn2aisc_mapping mapping; if (index >= SMU_POWER_SOURCE_COUNT) @@ -305,11 +316,14 @@ static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index) } return mapping.map_to; +#endif + return 0; } static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile) { +#if 0 struct smu_11_0_cmn2aisc_mapping mapping; if (profile > PP_SMC_POWER_PROFILE_CUSTOM) @@ -321,6 +335,8 @@ static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_P } return mapping.map_to; +#endif + return 0; } static bool is_asic_secure(struct smu_context *smu) @@ -918,7 +934,9 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, MetricsMember_t member_type; int clk_id = 0; - clk_id = smu_clk_get_index(smu, clk_type); + clk_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); if (clk_id < 0) return clk_id; @@ -956,7 +974,9 @@ static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu DpmDescriptor_t *dpm_desc = NULL; uint32_t clk_index = 0; - clk_index = smu_clk_get_index(smu, clk_type); + clk_index = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); dpm_desc = &pptable->DpmDescriptor[clk_index]; /* 0 - Fine grained DPM, 1 - Discrete DPM */ @@ -1484,7 +1504,9 @@ static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf) for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ - workload_type = smu_workload_get_type(smu, i); + workload_type = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_WORKLOAD, + i); if (workload_type < 0) return -EINVAL; @@ -1613,7 +1635,9 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u } /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ - workload_type = smu_workload_get_type(smu, smu->power_profile_mode); + workload_type = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_WORKLOAD, + smu->power_profile_mode); if (workload_type < 0) return -EINVAL; smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, @@ -2427,4 +2451,10 @@ static const struct pptable_funcs navi10_ppt_funcs = { void navi10_set_ppt_funcs(struct smu_context *smu) { smu->ppt_funcs = &navi10_ppt_funcs; + smu->message_map = navi10_message_map; + smu->clock_map = navi10_clk_map; + smu->feature_map = navi10_feature_mask_map; + smu->table_map = navi10_table_map; + smu->pwr_src_map = navi10_pwr_src_map; + smu->workload_map = navi10_workload_map; } -- cgit