From 13c0e836316a03ab859f616b85cfe25c3d69d5db Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 25 Sep 2023 17:07:33 -0400 Subject: drm/amd/display: Adjust code style for hw_sequencer.h [Why&How] * Rearrange some definitions for consistency * Drop legacy code Signed-off-by: Aurabindo Pillai Reviewed-by: Rodrigo Siqueira Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 17 ------- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 --- drivers/gpu/drm/amd/display/dc/dc_stream.h | 6 --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 27 ----------- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h | 6 --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 3 -- drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 3 -- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 56 +++++++++------------- 8 files changed, 23 insertions(+), 102 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 2e49b0ab91d7..ac493dd7fa68 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -288,23 +288,6 @@ static void program_cursor_attributes( } } -#ifndef TRIM_FSFT -/* - * dc_optimize_timing_for_fsft() - dc to optimize timing - */ -bool dc_optimize_timing_for_fsft( - struct dc_stream_state *pStream, - unsigned int max_input_rate_in_khz) -{ - struct dc *dc; - - dc = pStream->ctx->dc; - - return (dc->hwss.optimize_timing_for_fsft && - dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz)); -} -#endif - static bool is_subvp_high_refresh_candidate(struct dc_stream_state *stream) { uint32_t refresh_rate; diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 100d62162b71..9649934ea186 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -769,9 +769,6 @@ struct dc_crtc_timing_flags { uint32_t LTE_340MCSC_SCRAMBLE:1; uint32_t DSC : 1; /* Use DSC with this timing */ -#ifndef TRIM_FSFT - uint32_t FAST_TRANSPORT: 1; -#endif uint32_t VBLANK_SYNCHRONIZABLE: 1; }; @@ -950,10 +947,6 @@ struct dc_crtc_timing { enum dc_aspect_ratio aspect_ratio; enum scanning_type scan_type; -#ifndef TRIM_FSFT - uint32_t fast_transport_output_rate_100hz; -#endif - struct dc_crtc_timing_flags flags; uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ struct dc_dsc_config dsc_cfg; diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 889610a8b26b..4ac48c346a33 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -524,12 +524,6 @@ struct dc_stream_status *dc_stream_get_status_from_state( struct dc_stream_status *dc_stream_get_status( struct dc_stream_state *dc_stream); -#ifndef TRIM_FSFT -bool dc_optimize_timing_for_fsft( - struct dc_stream_state *pStream, - unsigned int max_input_rate_in_khz); -#endif - /******************************************************************************* * Cursor interfaces - To manages the cursor within a stream ******************************************************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 21b94adab575..f5a7002302f8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -2927,33 +2927,6 @@ void dcn20_fpga_init_hw(struct dc *dc) if (dc->res_pool->hubbub->funcs->init_crb) dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); } -#ifndef TRIM_FSFT -bool dcn20_optimize_timing_for_fsft(struct dc *dc, - struct dc_crtc_timing *timing, - unsigned int max_input_rate_in_khz) -{ - unsigned int old_v_front_porch; - unsigned int old_v_total; - unsigned int max_input_rate_in_100hz; - unsigned long long new_v_total; - - max_input_rate_in_100hz = max_input_rate_in_khz * 10; - if (max_input_rate_in_100hz < timing->pix_clk_100hz) - return false; - - old_v_total = timing->v_total; - old_v_front_porch = timing->v_front_porch; - - timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; - timing->pix_clk_100hz = max_input_rate_in_100hz; - - new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); - - timing->v_total = new_v_total; - timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); - return true; -} -#endif void dcn20_set_disp_pattern_generator(const struct dc *dc, struct pipe_ctx *pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h index 351b66e3f38b..ab02e4e9c8c2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h @@ -136,12 +136,6 @@ int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config); -#ifndef TRIM_FSFT -bool dcn20_optimize_timing_for_fsft(struct dc *dc, - struct dc_crtc_timing *timing, - unsigned int max_input_rate_in_khz); -#endif - void dcn20_set_disp_pattern_generator(const struct dc *dc, struct pipe_ctx *pipe_ctx, enum controller_dp_test_pattern test_pattern, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c index e4b44e691ce6..15b66ed66ad6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c @@ -93,9 +93,6 @@ static const struct hw_sequencer_funcs dcn20_funcs = { .set_backlight_level = dce110_set_backlight_level, .set_abm_immediate_disable = dce110_set_abm_immediate_disable, .set_pipe = dce110_set_pipe, -#ifndef TRIM_FSFT - .optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft, -#endif .enable_lvds_link_output = dce110_enable_lvds_link_output, .enable_tmds_link_output = dce110_enable_tmds_link_output, .enable_dp_link_output = dce110_enable_dp_link_output, diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c index f024157bd6eb..647e666f692a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c @@ -96,9 +96,6 @@ static const struct hw_sequencer_funcs dcn21_funcs = { .set_backlight_level = dcn21_set_backlight_level, .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, .set_pipe = dcn21_set_pipe, -#ifndef TRIM_FSFT - .optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft, -#endif .enable_lvds_link_output = dce110_enable_lvds_link_output, .enable_tmds_link_output = dce110_enable_tmds_link_output, .enable_dp_link_output = dce110_enable_dp_link_output, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index d4d59a916668..844ad5eb8e35 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -260,11 +260,6 @@ struct hw_sequencer_funcs { void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *events); -#ifndef TRIM_FSFT - bool (*optimize_timing_for_fsft)(struct dc *dc, - struct dc_crtc_timing *timing, - unsigned int max_input_rate_in_khz); -#endif /* Stream Related */ void (*enable_stream)(struct pipe_ctx *pipe_ctx); @@ -381,7 +376,18 @@ struct hw_sequencer_funcs { bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr); + void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); + void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); + void (*subvp_pipe_control_lock)(struct dc *dc, + struct dc_state *context, + bool lock, + bool should_lock_all_pipes, + struct pipe_ctx *top_pipe_to_program, + bool subvp_prev_use); + void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); + void (*z10_restore)(const struct dc *dc); + void (*z10_save_init)(struct dc *dc); bool (*is_abm_supported)(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream); @@ -392,27 +398,17 @@ struct hw_sequencer_funcs { enum dc_color_depth color_depth, const struct tg_color *solid_color, int width, int height, int offset); - - void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); - void (*z10_restore)(const struct dc *dc); - void (*z10_save_init)(struct dc *dc); - void (*blank_phantom)(struct dc *dc, struct timing_generator *tg, int width, int height); - void (*update_visual_confirm_color)(struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id); - void (*update_phantom_vp_position)(struct dc *dc, struct dc_state *context, struct pipe_ctx *phantom_pipe); void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); - bool (*is_pipe_topology_transition_seamless)(struct dc *dc, - const struct dc_state *cur_ctx, - const struct dc_state *new_ctx); void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context, struct pg_block_update *update_state); @@ -424,15 +420,9 @@ struct hw_sequencer_funcs { struct pg_block_update *update_state, bool power_on); void (*set_idle_state)(const struct dc *dc, bool allow_idle); uint32_t (*get_idle_state)(const struct dc *dc); - void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); - void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); - void (*subvp_pipe_control_lock)(struct dc *dc, - struct dc_state *context, - bool lock, - bool should_lock_all_pipes, - struct pipe_ctx *top_pipe_to_program, - bool subvp_prev_use); - + bool (*is_pipe_topology_transition_seamless)(struct dc *dc, + const struct dc_state *cur_ctx, + const struct dc_state *new_ctx); }; void color_space_to_black_color( @@ -447,25 +437,25 @@ const uint16_t *find_color_matrix( enum dc_color_space color_space, uint32_t *array_size); +void get_surface_tile_visual_confirm_color( + struct pipe_ctx *pipe_ctx, + struct tg_color *color); void get_surface_visual_confirm_color( const struct pipe_ctx *pipe_ctx, struct tg_color *color); -void get_subvp_visual_confirm_color( - struct dc *dc, - struct dc_state *context, - struct pipe_ctx *pipe_ctx, - struct tg_color *color); - void get_hdr_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color); void get_mpctree_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color); -void get_surface_tile_visual_confirm_color( - struct pipe_ctx *pipe_ctx, - struct tg_color *color); + +void get_subvp_visual_confirm_color( + struct dc *dc, + struct dc_state *context, + struct pipe_ctx *pipe_ctx, + struct tg_color *color); void get_mclk_switch_visual_confirm_color( struct dc *dc, -- cgit