From c816723b6b8a627c2edafc8bcc8062017323d031 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Sat, 5 Jun 2021 08:53:52 -0700 Subject: drm/i915/gt: replace IS_GEN and friends with GRAPHICS_VER This was done by the following semantic patch: @@ expression i915; @@ - INTEL_GEN(i915) + GRAPHICS_VER(i915) @@ expression i915; expression E; @@ - INTEL_GEN(i915) >= E + GRAPHICS_VER(i915) >= E @@ expression dev_priv; expression E; @@ - !IS_GEN(dev_priv, E) + GRAPHICS_VER(dev_priv) != E @@ expression dev_priv; expression E; @@ - IS_GEN(dev_priv, E) + GRAPHICS_VER(dev_priv) == E @@ expression dev_priv; expression from, until; @@ - IS_GEN_RANGE(dev_priv, from, until) + IS_GRAPHICS_VER(dev_priv, from, until) @def@ expression E; identifier id =~ "^gen$"; @@ - id = GRAPHICS_VER(E) + ver = GRAPHICS_VER(E) @@ identifier def.id; @@ - id + ver It also takes care of renaming the variable we assign to GRAPHICS_VER() so to use "ver" rather than "gen". Signed-off-by: Lucas De Marchi Reviewed-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20210605155356.4183026-2-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/gt/intel_sseu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/i915/gt/intel_sseu.c') diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 0d9f74aec8fe..367fd44b81c8 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -590,13 +590,13 @@ void intel_sseu_info_init(struct intel_gt *gt) cherryview_sseu_info_init(gt); else if (IS_BROADWELL(i915)) bdw_sseu_info_init(gt); - else if (IS_GEN(i915, 9)) + else if (GRAPHICS_VER(i915) == 9) gen9_sseu_info_init(gt); - else if (IS_GEN(i915, 10)) + else if (GRAPHICS_VER(i915) == 10) gen10_sseu_info_init(gt); - else if (IS_GEN(i915, 11)) + else if (GRAPHICS_VER(i915) == 11) gen11_sseu_info_init(gt); - else if (INTEL_GEN(i915) >= 12) + else if (GRAPHICS_VER(i915) >= 12) gen12_sseu_info_init(gt); } @@ -613,7 +613,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt, * No explicit RPCS request is needed to ensure full * slice/subslice/EU enablement prior to Gen9. */ - if (INTEL_GEN(i915) < 9) + if (GRAPHICS_VER(i915) < 9) return 0; /* @@ -651,7 +651,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt, * subslices are enabled, or a count between one and four on the first * slice. */ - if (IS_GEN(i915, 11) && + if (GRAPHICS_VER(i915) == 11 && slices == 1 && subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) { GEM_BUG_ON(subslices & 1); @@ -669,7 +669,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt, if (sseu->has_slice_pg) { u32 mask, val = slices; - if (INTEL_GEN(i915) >= 11) { + if (GRAPHICS_VER(i915) >= 11) { mask = GEN11_RPCS_S_CNT_MASK; val <<= GEN11_RPCS_S_CNT_SHIFT; } else { -- cgit