From 5e352e32aec23570ea948f039e25faf9b9ba362b Mon Sep 17 00:00:00 2001 From: Fei Yang Date: Tue, 9 May 2023 09:51:59 -0700 Subject: drm/i915: preparation for using PAT index This patch is a preparation for replacing enum i915_cache_level with PAT index. Caching policy for buffer objects is set through the PAT index in PTE, the old i915_cache_level is not sufficient to represent all caching modes supported by the hardware. Preparing the transition by adding some platform dependent data structures and helper functions to translate the cache_level to pat_index. cachelevel_to_pat: a platform dependent array mapping cache_level to pat_index. max_pat_index: the maximum PAT index recommended in hardware specification Needed for validating the PAT index passed in from user space. i915_gem_get_pat_index: function to convert cache_level to PAT index. obj_to_i915(obj): macro moved to header file for wider usage. I915_MAX_CACHE_LEVEL: upper bound of i915_cache_level for the convenience of coding. Cc: Chris Wilson Cc: Matt Roper Signed-off-by: Fei Yang Reviewed-by: Andi Shyti Reviewed-by: Andrzej Hajda Signed-off-by: Andi Shyti Link: https://patchwork.freedesktop.org/patch/msgid/20230509165200.1740-2-fei.yang@intel.com --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 ++++++ drivers/gpu/drm/i915/gt/intel_ggtt.c | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'drivers/gpu/drm/i915/gt') diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 22ec1566d2a7..bb6998d67133 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -78,6 +78,12 @@ static u64 mtl_pte_encode(dma_addr_t addr, case I915_CACHE_WT: pte |= GEN12_PPGTT_PTE_PAT0; break; + default: + /* This should never happen. Added to deal with the compile + * error due to the addition of I915_MAX_CACHE_LEVEL. Will + * be removed by the pat_index patch. + */ + break; } return pte; diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 20915edc8bd9..c8390d03fce2 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -242,6 +242,12 @@ static u64 mtl_ggtt_pte_encode(dma_addr_t addr, case I915_CACHE_WT: pte |= MTL_GGTT_PTE_PAT0; break; + default: + /* This should never happen. Added to deal with the compile + * error due to the addition of I915_MAX_CACHE_LEVEL. Will + * be removed by the pat_index patch. + */ + break; } return pte; -- cgit