From 2b4cebe4e165b0ef30a138e4cf602538dea15583 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 29 Mar 2011 09:56:14 +1000 Subject: drm/nv50: use "nv86" tlb flush method on everything except 0x50/0xac It has been reported that this greatly improves (and possibly fixes completely) the stability of NVA3+ chipsets. In traces of my NVA8, NVIDIA now appear to be doing this too. The most recent traces of 0x50 and 0xac I could find don't show NVIDIA checking PGRAPH status on these flushes, so for now, we won't either. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nv50_graph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau/nv50_graph.c') diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c index 8675b00caf18..b02a5b1e7d37 100644 --- a/drivers/gpu/drm/nouveau/nv50_graph.c +++ b/drivers/gpu/drm/nouveau/nv50_graph.c @@ -503,7 +503,7 @@ nv50_graph_tlb_flush(struct drm_device *dev) } void -nv86_graph_tlb_flush(struct drm_device *dev) +nv84_graph_tlb_flush(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; -- cgit