From f9e3dc786a585e1ec371c446c62dcc77d0548629 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 21 Oct 2015 17:22:43 +0300 Subject: drm/i915: add hotplug activation period to hotplug update mask commit 0706f17c307b056ff6f1848320ba82d76945a6ff Author: Egbert Eich Date: Wed Sep 23 16:15:27 2015 +0200 drm/i915: Avoid race of intel_crt_detect_hotplug() with HPD interrupt, v2 added a check with WARN to ensure only bits within the mask are enabled. Turns out that doesn't hold for G4X, which spits out: [ 2.641439] ------------[ cut here ]------------ [ 2.641444] WARNING: CPU: 0 PID: 1 at drivers/gpu/drm/i915/i915_irq.c:182 i915_hotplug_interrupt_update_locked+0x45/0x83() [ 2.641446] WARN_ON(bits & ~mask) etc. Add CRT_HOTPLUG_ACTIVATION_PERIOD_64 to the mask to fix the warning. Reported-and-tested-by: Oleksij Rempel References: https://bugzilla.kernel.org/show_bug.cgi?id=104991 Fixes: 0706f17c307b ("drm/i915: Avoid race of intel_crt_detect_hotplug() with HPD interrupt, v2") Cc: Egbert Eich Cc: Daniel Vetter Signed-off-by: Jani Nikula Reviewed-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/1445437363-3030-1-git-send-email-jani.nikula@intel.com --- drivers/gpu/drm/i915/i915_irq.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index e24378ee7eda..5d8ec7a81831 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -4236,9 +4236,10 @@ static void i915_hpd_irq_setup(struct drm_device *dev) /* Ignore TV since it's buggy */ i915_hotplug_interrupt_update_locked(dev_priv, - (HOTPLUG_INT_EN_MASK - | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK), - hotplug_en); + HOTPLUG_INT_EN_MASK | + CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | + CRT_HOTPLUG_ACTIVATION_PERIOD_64, + hotplug_en); } static irqreturn_t i965_irq_handler(int irq, void *arg) -- cgit From 5a37ed0a9eda5fd77a4cc92c6e46b6f6e8db873d Mon Sep 17 00:00:00 2001 From: Thomas Daniel Date: Fri, 23 Oct 2015 14:55:38 +0100 Subject: drm/i915: Fix maxfifo watermark calc on vlv cursor planes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A typo resulted in the watermarks for cursor planes not being calculated correctly. Fixed the typo. Cc: Ville Syrjälä Signed-off-by: Thomas Daniel Reviewed-by: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9dda3eaebd12..80175a38a875 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1135,7 +1135,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc) case DRM_PLANE_TYPE_CURSOR: for (level = 0; level < wm_state->num_levels; level++) wm_state->sr[level].cursor = - wm_state->sr[level].cursor; + wm_state->wm[level].cursor; break; case DRM_PLANE_TYPE_PRIMARY: for (level = 0; level < wm_state->num_levels; level++) -- cgit From 6675bce251b6ec20ec09c07e941d9f664be4ae58 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 28 Oct 2015 13:57:09 +0200 Subject: drm/i915: disable CPU PWM also on LPT/SPT backlight disable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Although we don't support or enable CPU PWM with LPT/SPT based systems, it may have been enabled prior to loading the driver. Disable the CPU PWM on LPT/SPT backlight disable to avoid warnings on LCPLL disable. The issue has been present on BDW since BDW enabling, but was recently introduced on HSW with commit 437b15b8017e0d946453c10794b0c5d4591cf180 Author: Jani Nikula Date: Fri Sep 4 16:55:13 2015 +0300 drm/i915: use pch backlight override on hsw too Cc: Paulo Zanoni Cc: Ville Syrjälä Reference: http://mid.gmane.org/87y4frhwsn.fsf@yhuang-dev.intel.com Reported-by: kernel test robot Tested-by: Ville Syrjälä Signed-off-by: Jani Nikula Link: http://patchwork.freedesktop.org/patch/msgid/1446033429-8006-1-git-send-email-jani.nikula@intel.com --- drivers/gpu/drm/i915/intel_panel.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index b05c6d9b3be7..a24df35e11e7 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -732,6 +732,20 @@ static void lpt_disable_backlight(struct intel_connector *connector) intel_panel_actually_set_backlight(connector, 0); + /* + * Although we don't support or enable CPU PWM with LPT/SPT based + * systems, it may have been enabled prior to loading the + * driver. Disable to avoid warnings on LCPLL disable. + * + * This needs rework if we need to add support for CPU PWM on PCH split + * platforms. + */ + tmp = I915_READ(BLC_PWM_CPU_CTL2); + if (tmp & BLM_PWM_ENABLE) { + DRM_DEBUG_KMS("cpu backlight was enabled, disabling\n"); + I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); + } + tmp = I915_READ(BLC_PWM_PCH_CTL1); I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); } -- cgit From b10f1b20171945b49988b2b1fe68cb312cc36d32 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Thu, 22 Oct 2015 13:56:34 +0200 Subject: drm/i915/skl: Prevent unclaimed register writes on skylake. I'm getting unclaimed register writes when checking the WM registers after the crtc is disabled. So I would imagine those are guarded by the crtc power well. Fix this by not reading out wm state when the power well is off. Cc: stable@vger.kernel.org # v4.3 Signed-off-by: Maarten Lankhorst Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181 Reviewed-by: Daniel Vetter Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_pm.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 80175a38a875..d52a15df6917 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2818,7 +2818,12 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, int plane; u32 val; + memset(ddb, 0, sizeof(*ddb)); + for_each_pipe(dev_priv, pipe) { + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) + continue; + for_each_plane(dev_priv, pipe, plane) { val = I915_READ(PLANE_BUF_CFG(pipe, plane)); skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], -- cgit From 9be64eee3a87dc03218ca9a12834d1150a57b8a8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 30 Oct 2015 14:50:24 +0200 Subject: drm/i915: add quirk to enable backlight on Dell Chromebook 11 (2015) Reported-by: Keith Webb Suggested-by: Keith Webb Cc: stable@vger.kernel.org Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=106671 Reviewed-by: Clint Taylor Signed-off-by: Jani Nikula Link: http://patchwork.freedesktop.org/patch/msgid/1446209424-28801-1-git-send-email-jani.nikula@intel.com --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 82128b95785c..81358ca2adfb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14695,6 +14695,9 @@ static struct intel_quirk intel_quirks[] = { /* Dell Chromebook 11 */ { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, + + /* Dell Chromebook 11 (2015 version) */ + { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, }; static void intel_init_quirks(struct drm_device *dev) -- cgit From 9807216f585fc69a6cad3668414a2936a84444c8 Mon Sep 17 00:00:00 2001 From: Vivek Kasireddy Date: Thu, 29 Oct 2015 18:54:38 -0700 Subject: drm/i915: Skip fence installation for objects with rotated views (v4) While pinning a fb object to the display plane, only install a fence if the object is using a normal view. This corresponds with the behavior found in i915_gem_object_do_pin() where the fencability criteria is determined only for objects with normal views. v2: Look at the object's map_and_fenceable flag to determine whether to install a fence or not (Chris). v3: Pin and unpin a fence only if the current view type is normal. v4: Extend the "view type is normal" check for pin_fence as well. Cc: Chris Wilson Cc: Tvrtko Ursulin Reviewed-by: Ville Syrjala Signed-off-by: Vivek Kasireddy Link: http://patchwork.freedesktop.org/patch/msgid/1446170078-20792-1-git-send-email-vivek.kasireddy@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 81358ca2adfb..6795df562341 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2389,22 +2389,24 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane, * framebuffer compression. For simplicity, we always install * a fence as the cost is not that onerous. */ - ret = i915_gem_object_get_fence(obj); - if (ret == -EDEADLK) { - /* - * -EDEADLK means there are no free fences - * no pending flips. - * - * This is propagated to atomic, but it uses - * -EDEADLK to force a locking recovery, so - * change the returned error to -EBUSY. - */ - ret = -EBUSY; - goto err_unpin; - } else if (ret) - goto err_unpin; + if (view.type == I915_GGTT_VIEW_NORMAL) { + ret = i915_gem_object_get_fence(obj); + if (ret == -EDEADLK) { + /* + * -EDEADLK means there are no free fences + * no pending flips. + * + * This is propagated to atomic, but it uses + * -EDEADLK to force a locking recovery, so + * change the returned error to -EBUSY. + */ + ret = -EBUSY; + goto err_unpin; + } else if (ret) + goto err_unpin; - i915_gem_object_pin_fence(obj); + i915_gem_object_pin_fence(obj); + } dev_priv->mm.interruptible = true; intel_runtime_pm_put(dev_priv); @@ -2430,7 +2432,9 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb, ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); WARN_ONCE(ret, "Couldn't get view from plane state!"); - i915_gem_object_unpin_fence(obj); + if (view.type == I915_GGTT_VIEW_NORMAL) + i915_gem_object_unpin_fence(obj); + i915_gem_object_unpin_from_display_plane(obj, &view); } -- cgit From 99106bc17e667989b4c0af0a6afcbd6ddbada8fb Mon Sep 17 00:00:00 2001 From: Mika Kuoppala Date: Thu, 5 Nov 2015 13:11:38 +0200 Subject: drm/i915: Do graphics device reset under forcewake We have a timed release of a forcewake when using I915_READ/WRITE macros. wait_for() macro will go to quite long sleep if the first read doesn't satisfy the condition for successful exit. With these two interacting, it is possible that we lose the forcewake during the wait_for() and the subsequent read will reaquire forcewake. Further experiments with skl shows that when we lose forcewake, we lose the reset request we submitted. So reset request register is not power context saved. Grab forcewakes for all engines before starting the reset/request dance so that all requests stay valid for the duration of reset requisition across all the engines. v2: Add comment on power well sleeps. Wrap the reset handling under forcewake instead of just reset requests (Chris) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92774 Cc: Chris Wilson Reviewed-by: Chris Wilson Tested-by: Tomi Sarvela (v1, v2) Signed-off-by: Mika Kuoppala Link: http://patchwork.freedesktop.org/patch/msgid/1446721898-1450-1-git-send-email-mika.kuoppala@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_uncore.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 1663ea55e37c..43cba129a0c0 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1531,13 +1531,22 @@ static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *) int intel_gpu_reset(struct drm_device *dev) { + struct drm_i915_private *dev_priv = to_i915(dev); int (*reset)(struct drm_device *); + int ret; reset = intel_get_gpu_reset(dev); if (reset == NULL) return -ENODEV; - return reset(dev); + /* If the power well sleeps during the reset, the reset + * request may be dropped and never completes (causing -EIO). + */ + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + ret = reset(dev); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + + return ret; } bool intel_has_gpu_reset(struct drm_device *dev) -- cgit From b291681926a142958112eedde62823230d6afb84 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 3 Nov 2015 08:31:41 +0100 Subject: drm/i915: Extend DSL readout fix to BDW and SKL. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Those platforms have the same bug as haswell, and the same fix applies to them. The original HSW fix that this extends is commit 41b578fb0e8b930f2470d3f673b0fa279e77a7b8 Author: Jesse Barnes Date: Tue Sep 22 12:15:54 2015 -0700 drm/i915: workaround bad DSL readout v3 Signed-off-by: Maarten Lankhorst Acked-by: Ville Syrjälä Cc: stable@vger.kernel.org # v4.3 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91579 Link: http://patchwork.freedesktop.org/patch/msgid/1446535913-31970-3-git-send-email-maarten.lankhorst@linux.intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 5d8ec7a81831..684a0d9909e7 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -749,7 +749,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) * problem. We may need to extend this to include other platforms, * but so far testing only shows the problem on HSW. */ - if (IS_HASWELL(dev) && !position) { + if (HAS_DDI(dev) && !position) { int i, temp; for (i = 0; i < 100; i++) { -- cgit From 1b0e3a049efe471c399674fd954500ce97438d30 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 5 Nov 2015 23:04:11 +0200 Subject: drm/i915/skl: disable display side power well support for now MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The display power well support on this platform is in a somewhat broken state atm, so disable it by default. This in effect will get rid of incorrect assert WARNs about the CSR/DMC firmware not being loaded during power well toggling. It also removes a problem during driver loading where a register is accessed while its backing power well is down, resulting in another WARN. Until we come up with the root cause of the second problem and the proper fix for both issues, keep all display side power wells on. Also clarify a bit the option description. Reported-by: Dave Airlie Reference: http://mid.gmane.org/CAPM=9tyjBQjSBTKa49cRr6SYkpNW7Pq-fUFznZZ8Y1snvvk7mA@mail.gmail.com Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Link: http://patchwork.freedesktop.org/patch/msgid/1446757451-2777-1-git-send-email-imre.deak@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_params.c | 5 +++-- drivers/gpu/drm/i915/intel_runtime_pm.c | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index ca9b8f644ffe..96bb23865eac 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -38,7 +38,7 @@ struct i915_params i915 __read_mostly = { .enable_ppgtt = -1, .enable_psr = 0, .preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT), - .disable_power_well = 1, + .disable_power_well = -1, .enable_ips = 1, .prefault_disable = 0, .load_detect_test = 0, @@ -127,7 +127,8 @@ MODULE_PARM_DESC(preliminary_hw_support, module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0600); MODULE_PARM_DESC(disable_power_well, - "Disable the power well when possible (default: true)"); + "Disable display power wells when possible " + "(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)"); module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600); MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)"); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 0cfe4c14866a..1aedf2762dff 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1810,6 +1810,21 @@ static struct i915_power_well bxt_power_wells[] = { } }; +static int +sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, + int disable_power_well) +{ + if (disable_power_well >= 0) + return !!disable_power_well; + + if (IS_SKYLAKE(dev_priv)) { + DRM_DEBUG_KMS("Disabling display power well support\n"); + return 0; + } + + return 1; +} + #define set_power_wells(power_domains, __power_wells) ({ \ (power_domains)->power_wells = (__power_wells); \ (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ @@ -1826,6 +1841,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) { struct i915_power_domains *power_domains = &dev_priv->power_domains; + i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, + i915.disable_power_well); + mutex_init(&power_domains->lock); /* -- cgit