From 88548710d2aed71677f7594a78219bf081d4297f Mon Sep 17 00:00:00 2001 From: Daniel Matyas Date: Tue, 31 Oct 2023 20:21:53 +0200 Subject: hwmon: (max31827) Handle new properties from the devicetree Used fwnode to retrieve data from the devicetree in the init_client function. If the uint32 properties are not present, the default values are used for max31827 chip. Signed-off-by: Daniel Matyas Link: https://lore.kernel.org/r/20231031182158.124608-1-daniel.matyas@analog.com Signed-off-by: Guenter Roeck --- drivers/hwmon/max31827.c | 75 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 69 insertions(+), 6 deletions(-) (limited to 'drivers/hwmon') diff --git a/drivers/hwmon/max31827.c b/drivers/hwmon/max31827.c index a1ce65145669..3f1312b555ab 100644 --- a/drivers/hwmon/max31827.c +++ b/drivers/hwmon/max31827.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -23,9 +24,17 @@ #define MAX31827_CONFIGURATION_1SHOT_MASK BIT(0) #define MAX31827_CONFIGURATION_CNV_RATE_MASK GENMASK(3, 1) +#define MAX31827_CONFIGURATION_TIMEOUT_MASK BIT(5) +#define MAX31827_CONFIGURATION_RESOLUTION_MASK GENMASK(7, 6) +#define MAX31827_CONFIGURATION_ALRM_POL_MASK BIT(8) +#define MAX31827_CONFIGURATION_COMP_INT_MASK BIT(9) +#define MAX31827_CONFIGURATION_FLT_Q_MASK GENMASK(11, 10) #define MAX31827_CONFIGURATION_U_TEMP_STAT_MASK BIT(14) #define MAX31827_CONFIGURATION_O_TEMP_STAT_MASK BIT(15) +#define MAX31827_ALRM_POL_LOW 0x0 +#define MAX31827_FLT_Q_1 0x0 + #define MAX31827_12_BIT_CNV_TIME 140 #define MAX31827_16_BIT_TO_M_DGR(x) (sign_extend32(x, 15) * 1000 / 16) @@ -362,14 +371,68 @@ static int max31827_write(struct device *dev, enum hwmon_sensor_types type, return -EOPNOTSUPP; } -static int max31827_init_client(struct max31827_state *st) +static int max31827_init_client(struct max31827_state *st, + struct device *dev) { + struct fwnode_handle *fwnode; + unsigned int res = 0; + u32 data, lsb_idx; + bool prop; + int ret; + + fwnode = dev_fwnode(dev); + st->enable = true; + res |= MAX31827_DEVICE_ENABLE(1); + + res |= MAX31827_CONFIGURATION_RESOLUTION_MASK; + + prop = fwnode_property_read_bool(fwnode, "adi,comp-int"); + res |= FIELD_PREP(MAX31827_CONFIGURATION_COMP_INT_MASK, prop); + + prop = fwnode_property_read_bool(fwnode, "adi,timeout-enable"); + res |= FIELD_PREP(MAX31827_CONFIGURATION_TIMEOUT_MASK, !prop); + + if (fwnode_property_present(fwnode, "adi,alarm-pol")) { + ret = fwnode_property_read_u32(fwnode, "adi,alarm-pol", &data); + if (ret) + return ret; + + res |= FIELD_PREP(MAX31827_CONFIGURATION_ALRM_POL_MASK, !!data); + } else { + /* + * Set default value. + */ + res |= FIELD_PREP(MAX31827_CONFIGURATION_ALRM_POL_MASK, + MAX31827_ALRM_POL_LOW); + } + + if (fwnode_property_present(fwnode, "adi,fault-q")) { + ret = fwnode_property_read_u32(fwnode, "adi,fault-q", &data); + if (ret) + return ret; + + /* + * Convert the desired fault queue into register bits. + */ + if (data != 0) + lsb_idx = __ffs(data); + + if (hweight32(data) != 1 || lsb_idx > 4) { + dev_err(dev, "Invalid data in adi,fault-q\n"); + return -EINVAL; + } + + res |= FIELD_PREP(MAX31827_CONFIGURATION_FLT_Q_MASK, lsb_idx); + } else { + /* + * Set default value. + */ + res |= FIELD_PREP(MAX31827_CONFIGURATION_FLT_Q_MASK, + MAX31827_FLT_Q_1); + } - return regmap_update_bits(st->regmap, MAX31827_CONFIGURATION_REG, - MAX31827_CONFIGURATION_1SHOT_MASK | - MAX31827_CONFIGURATION_CNV_RATE_MASK, - MAX31827_DEVICE_ENABLE(1)); + return regmap_write(st->regmap, MAX31827_CONFIGURATION_REG, res); } static const struct hwmon_channel_info *max31827_info[] = { @@ -417,7 +480,7 @@ static int max31827_probe(struct i2c_client *client) if (err) return dev_err_probe(dev, err, "failed to enable regulator\n"); - err = max31827_init_client(st); + err = max31827_init_client(st, dev); if (err) return err; -- cgit