From 59bdb43769f2c3995badcd930d799451f5a39f76 Mon Sep 17 00:00:00 2001 From: Zoltan Devai Date: Wed, 12 Nov 2008 23:05:40 -0500 Subject: Input: pcspkr - fix PIT lockup on some chipsets There've been reports [1] about the sysem bell causing a hard lockup. My machine was affected as well: any speaker output hung the machine completely, nothing in the logs, no magic sysrq, etc., looked like a hardware problem. Had a closer look on the issue, and it turned out that the pcspkr module is responsible. The cause is the bad setup of Timer 2 in the i8253 controller, which probably hangs the whole PIT controller. Intel datasheets [2] state that the timer registers are in an undefined state after reset and they need to be programmed before enabling the timer. (And enabling without programming the frequency first doesn't make sense anyway). I don't know which chipsets are affected (if not all), it also depends on the BIOS whether it initializes the timer (e.g. to beep when you start the machine). The following patch solved the issue on my ICH6 notebook, couldn't test it with any others, but should be safe to apply. [1] https://bugs.launchpad.net/ubuntu/+source/linux/+bug/146151 https://bugs.launchpad.net/ubuntu/+bug/270790 http://ubuntuforums.org/showthread.php?t=227693 http://bugs.gentoo.org/show_bug.cgi?id=222583 https://bugzilla.redhat.com/show_bug.cgi?id=454225 [2] http://www.intel.com/assets/pdf/datasheet/252516.pdf http://www.intel.com/assets/pdf/datasheet/301473.pdf http://www.intel.com/design/chipsets/datashts/29065503.pdf Signed-off-by: Zoltan Devai Signed-off-by: Dmitry Torokhov --- drivers/input/misc/pcspkr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/input/misc/pcspkr.c') diff --git a/drivers/input/misc/pcspkr.c b/drivers/input/misc/pcspkr.c index 43aaa5cebd12..d6a30cee7bc7 100644 --- a/drivers/input/misc/pcspkr.c +++ b/drivers/input/misc/pcspkr.c @@ -52,13 +52,13 @@ static int pcspkr_event(struct input_dev *dev, unsigned int type, unsigned int c spin_lock_irqsave(&i8253_lock, flags); if (count) { - /* enable counter 2 */ - outb_p(inb_p(0x61) | 3, 0x61); /* set command for counter 2, 2 byte write */ outb_p(0xB6, 0x43); /* select desired HZ */ outb_p(count & 0xff, 0x42); outb((count >> 8) & 0xff, 0x42); + /* enable counter 2 */ + outb_p(inb_p(0x61) | 3, 0x61); } else { /* disable counter 2 */ outb(inb_p(0x61) & 0xFC, 0x61); -- cgit