From a9d5fcc00e715354d3fec1e8009c5895b5ba65ba Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Wed, 12 Nov 2014 14:22:53 +0800 Subject: irqchip: dw-apb-ictl: Enable IRQ_GC_MASK_CACHE_PER_TYPE The irq_chip_type instances have separate mask registers, so we need to enable IRQ_GC_MASK_CACHE_PER_TYPE to actually handle separate mask registers. Signed-off-by: Jisheng Zhang Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1415773374-4629-3-git-send-email-jszhang@marvell.com Signed-off-by: Jason Cooper --- drivers/irqchip/irq-dw-apb-ictl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/irqchip/irq-dw-apb-ictl.c') diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c index fcc338584bda..c136b67740de 100644 --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -115,6 +115,7 @@ static int __init dw_apb_ictl_init(struct device_node *np, ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ? 2 : 1, np->name, handle_level_irq, clr, 0, + IRQ_GC_MASK_CACHE_PER_TYPE | IRQ_GC_INIT_MASK_CACHE); if (ret) { pr_err("%s: unable to alloc irq domain gc\n", np->full_name); -- cgit