From 900c33e86e4b53e96e6ea10e9737870e03911a66 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Tue, 25 Aug 2020 00:06:26 +0200 Subject: media: ccs-pll: Add support for DDR OP system and pixel clocks Add support for dual data rate operational system and pixel clocks. This is implemented using two PLL flags. Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/ccs-pll.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/media/i2c/ccs-pll.h') diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 517ee504f44a..b97d7ff50ea5 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -30,6 +30,8 @@ #define CCS_PLL_FLAG_FIFO_DERATING BIT(6) #define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7) #define CCS_PLL_FLAG_DUAL_PLL BIT(8) +#define CCS_PLL_FLAG_OP_SYS_DDR BIT(9) +#define CCS_PLL_FLAG_OP_PIX_DDR BIT(10) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front) -- cgit