From 7b678c69c0ca59ed4a1e65055b1e58918db38968 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 7 Nov 2019 08:42:05 +0000 Subject: mtd: spi-nor: Merge spansion Quad Enable methods Merge spansion_no_read_cr_quad_enable() spansion_read_cr_quad_enable() into spi_nor_sr2_bit1_quad_enable(). Reduce code duplication by introducing spi_nor_write_16bit_cr_and_check(). The Configuration Register contains bits that can be updated in future: FREEZE, CMP. Provide a generic method that allows updating all bits of the Configuration Register. Signed-off-by: Tudor Ambarus Reviewed-by: Vignesh Raghavendra --- drivers/mtd/spi-nor/spi-nor.c | 161 +++++++++++++++++------------------------- 1 file changed, 66 insertions(+), 95 deletions(-) (limited to 'drivers/mtd/spi-nor/spi-nor.c') diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 8c59b5220e2a..16fb3c7d0daf 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1054,6 +1054,59 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) return 0; } +/** + * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the + * Configuration Register in one shot. Ensure that the byte written in the + * Configuration Register match the received value, and that the 16-bit Write + * did not affect what was already in the Status Register 1. + * @nor: pointer to a 'struct spi_nor'. + * @cr: byte value to be written to the Configuration Register. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr) +{ + int ret; + u8 *sr_cr = nor->bouncebuf; + u8 sr_written; + + /* Keep the current value of the Status Register 1. */ + ret = spi_nor_read_sr(nor, sr_cr); + if (ret) + return ret; + + sr_cr[1] = cr; + + ret = spi_nor_write_sr(nor, sr_cr, 2); + if (ret) + return ret; + + sr_written = sr_cr[0]; + + ret = spi_nor_read_sr(nor, sr_cr); + if (ret) + return ret; + + if (sr_written != sr_cr[0]) { + dev_dbg(nor->dev, "SR: Read back test failed\n"); + return -EIO; + } + + if (nor->flags & SNOR_F_NO_READ_CR) + return 0; + + ret = spi_nor_read_cr(nor, &sr_cr[1]); + if (ret) + return ret; + + if (cr != sr_cr[1]) { + dev_dbg(nor->dev, "CR: read back test failed\n"); + return -EIO; + } + + return 0; +} + /** * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that * the byte written match the received value without affecting other bits in the @@ -2051,111 +2104,29 @@ static int macronix_quad_enable(struct spi_nor *nor) } /** - * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register. - * @nor: pointer to a 'struct spi_nor' + * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status + * Register 2. + * @nor: pointer to a 'struct spi_nor'. * - * Set the Quad Enable (QE) bit in the Configuration Register. - * This function should be used with QSPI memories not supporting the Read - * Configuration Register (35h) instruction. - * - * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI - * memories. + * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. * * Return: 0 on success, -errno otherwise. */ -static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) +static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) { - u8 *sr_cr = nor->bouncebuf; int ret; - u8 sr_written; - - /* Keep the current value of the Status Register. */ - ret = spi_nor_read_sr(nor, sr_cr); - if (ret) - return ret; - - sr_cr[1] = SR2_QUAD_EN_BIT1; - - ret = spi_nor_write_sr(nor, sr_cr, 2); - if (ret) - return ret; - sr_written = sr_cr[0]; - - ret = spi_nor_read_sr(nor, sr_cr); - if (ret) - return ret; - - if (sr_cr[0] != sr_written) { - dev_err(nor->dev, "SR: Read back test failed\n"); - return -EIO; - } - - return 0; -} - -/** - * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. - * @nor: pointer to a 'struct spi_nor' - * - * Set the Quad Enable (QE) bit in the Configuration Register. - * This function should be used with QSPI memories supporting the Read - * Configuration Register (35h) instruction. - * - * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI - * memories. - * - * Return: 0 on success, -errno otherwise. - */ -static int spansion_read_cr_quad_enable(struct spi_nor *nor) -{ - u8 *sr_cr = nor->bouncebuf; - int ret; - u8 sr_written; + if (nor->flags & SNOR_F_NO_READ_CR) + return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1); - /* Check current Quad Enable bit value. */ - ret = spi_nor_read_cr(nor, &sr_cr[1]); + ret = spi_nor_read_cr(nor, nor->bouncebuf); if (ret) return ret; - if (sr_cr[1] & SR2_QUAD_EN_BIT1) + if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) return 0; - sr_cr[1] |= SR2_QUAD_EN_BIT1; - - /* Keep the current value of the Status Register. */ - ret = spi_nor_read_sr(nor, sr_cr); - if (ret) - return ret; - - ret = spi_nor_write_sr(nor, sr_cr, 2); - if (ret) - return ret; - - sr_written = sr_cr[0]; - - ret = spi_nor_read_sr(nor, sr_cr); - if (ret) - return ret; - - if (sr_written != sr_cr[0]) { - dev_err(nor->dev, "SR: Read back test failed\n"); - return -EIO; - } - - sr_written = sr_cr[1]; - - /* Read back and check it. */ - ret = spi_nor_read_cr(nor, &sr_cr[1]); - if (ret) - return ret; - - if (sr_cr[1] != sr_written) { - dev_dbg(nor->dev, "CR: Read back test failed\n"); - return -EIO; - } - - return 0; + return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); } /** @@ -3685,7 +3656,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, * supported. */ nor->flags |= SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR; - params->quad_enable = spansion_no_read_cr_quad_enable; + params->quad_enable = spi_nor_sr2_bit1_quad_enable; break; case BFPT_DWORD15_QER_SR1_BIT6: @@ -3707,7 +3678,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, */ nor->flags |= SNOR_F_HAS_16BIT_SR; - params->quad_enable = spansion_read_cr_quad_enable; + params->quad_enable = spi_nor_sr2_bit1_quad_enable; break; default: @@ -4697,7 +4668,7 @@ static void spi_nor_info_init_params(struct spi_nor *nor) u8 i, erase_mask; /* Initialize legacy flash parameters and settings. */ - params->quad_enable = spansion_read_cr_quad_enable; + params->quad_enable = spi_nor_sr2_bit1_quad_enable; params->set_4byte = spansion_set_4byte; params->setup = spi_nor_default_setup; /* Default to 16-bit Write Status (01h) Command */ -- cgit