From 0c87f90b4c13586a00fbe63524c7be197609d8dc Mon Sep 17 00:00:00 2001 From: Srikanth Thokala Date: Fri, 6 Aug 2021 02:40:10 +0530 Subject: PCI: keembay: Add support for Intel Keem Bay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add driver for Intel Keem Bay SoC PCIe controller. This controller is based on DesignWare PCIe core. In Root Complex mode, only internal reference clock is possible for Keem Bay A0. For Keem Bay B0, external reference clock can be used and will be the default configuration. Currently, keembay_pcie_of_data structure has one member. It will be expanded later to handle this difference. Endpoint mode link initialization is handled by the boot firmware. Link: https://lore.kernel.org/r/20210805211010.29484-3-srikanth.thokala@intel.com Signed-off-by: Wan Ahmad Zainie Signed-off-by: Srikanth Thokala Signed-off-by: Lorenzo Pieralisi Reviewed-by: Krzysztof Wilczyński Reviewed-by: Rob Herring Acked-by: Andy Shevchenko --- drivers/pci/controller/dwc/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pci/controller/dwc/Makefile') diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 9e6ce0dc2f53..8b3e7176b4bf 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o +obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o obj-$(CONFIG_PCI_MESON) += pci-meson.o -- cgit