From 5586ee4191219f74632ad6e527c46d1c3d9cdf3e Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Fri, 19 May 2017 15:05:43 +0800 Subject: pinctrl: imx: add soc specific mux_mode mask and shift property MX7ULP MUX mode mask and shift bit is different from VF610. Let's make it a platform specific property for the later easy of adding MX7ULP support. One trick in exist code that Vybrid hardcoded the config part as 0xffff because its mux_config register BIT[15-0] are all configs part. But it's not true in ULP, so use mux_mask instead to address the difference. Cc: Stefan Agner Cc: Bai Ping Signed-off-by: Fugang Duan Signed-off-by: Dong Aisheng Acked-by: Shawn Guo Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/pinctrl/freescale/pinctrl-imx.h') diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index 38aa53c671ed..880bba7fd1ab 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -64,6 +64,10 @@ struct imx_pinctrl_soc_info { const char *gpr_compatible; struct mutex mutex; + /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */ + unsigned int mux_mask; + u8 mux_shift; + /* generic pinconf */ bool generic_pinconf; const struct pinconf_generic_params *custom_params; -- cgit