From e16a2c7aced8422cda2b7f13ea3f3daccb150db6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 29 Sep 2017 11:03:11 +0200 Subject: pinctrl: sh-pfc: Drop width parameter of sh_pfc_{read,write}_reg() On modern Renesas SoCs, all PFC registers are 32-bit, and all callers of sh_pfc_{read,write}_reg() already operate on 32-bit registers only. Hence make the 32-bit width implicit, and rename the functions to sh_pfc_{read,write}() to shorten lines. All accesses to 8-bit or 16-bit registers are still done using sh_pfc_{read,write}_raw_reg(). Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pinctrl.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/pinctrl/sh-pfc/pinctrl.c') diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 5c9d79981e6d..736634aee500 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -513,7 +513,7 @@ static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc, return -EINVAL; spin_lock_irqsave(&pfc->lock, flags); - val = sh_pfc_read_reg(pfc, reg, 32); + val = sh_pfc_read(pfc, reg); spin_unlock_irqrestore(&pfc->lock, flags); val = (val >> offset) & GENMASK(size - 1, 0); @@ -550,11 +550,11 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, spin_lock_irqsave(&pfc->lock, flags); - val = sh_pfc_read_reg(pfc, reg, 32); + val = sh_pfc_read(pfc, reg); val &= ~GENMASK(offset + size - 1, offset); val |= strength << offset; - sh_pfc_write_reg(pfc, reg, 32, val); + sh_pfc_write(pfc, reg, val); spin_unlock_irqrestore(&pfc->lock, flags); @@ -645,7 +645,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, return bit; spin_lock_irqsave(&pfc->lock, flags); - val = sh_pfc_read_reg(pfc, pocctrl, 32); + val = sh_pfc_read(pfc, pocctrl); spin_unlock_irqrestore(&pfc->lock, flags); arg = (val & BIT(bit)) ? 3300 : 1800; @@ -716,12 +716,12 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, return -EINVAL; spin_lock_irqsave(&pfc->lock, flags); - val = sh_pfc_read_reg(pfc, pocctrl, 32); + val = sh_pfc_read(pfc, pocctrl); if (mV == 3300) val |= BIT(bit); else val &= ~BIT(bit); - sh_pfc_write_reg(pfc, pocctrl, 32, val); + sh_pfc_write(pfc, pocctrl, val); spin_unlock_irqrestore(&pfc->lock, flags); break; -- cgit