From bc41f9f138bd93b82b08f84ca55b7da2acb847b3 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Nov 2013 13:46:17 +0100 Subject: sh-pfc: r8a7791: Fix DU pin groups organisation Rename the sync_1 group to sync as the device has a single sync pin group for the DU, move the cde_disp mux array right after the corresponding pins array, and split the clk_in pins in three separate groups as the pins can be used independently. Signed-off-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index bf76a654c02f..d26c16360161 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -1730,11 +1730,11 @@ static const unsigned int du_clk_out_1_pins[] = { static const unsigned int du_clk_out_1_mux[] = { DU1_DOTCLKOUT1_MARK }; -static const unsigned int du_sync_1_pins[] = { +static const unsigned int du_sync_pins[] = { /* EXVSYNC/VSYNC, EXHSYNC/HSYNC, EXDISP/EXODDF/EXCDE */ RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), }; -static const unsigned int du_sync_1_mux[] = { +static const unsigned int du_sync_mux[] = { DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK }; @@ -1742,6 +1742,9 @@ static const unsigned int du_cde_disp_pins[] = { /* CDE DISP */ RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30), }; +static const unsigned int du_cde_disp_mux[] = { + DU1_CDE_MARK, DU1_DISP_MARK +}; static const unsigned int du0_clk_in_pins[] = { /* CLKIN */ RCAR_GP_PIN(6, 31), @@ -1749,15 +1752,26 @@ static const unsigned int du0_clk_in_pins[] = { static const unsigned int du0_clk_in_mux[] = { DU0_DOTCLKIN_MARK }; -static const unsigned int du_cde_disp_mux[] = { - DU1_CDE_MARK, DU1_DISP_MARK -}; static const unsigned int du1_clk_in_pins[] = { /* CLKIN */ - RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19), RCAR_GP_PIN(3, 24), + RCAR_GP_PIN(3, 24), }; static const unsigned int du1_clk_in_mux[] = { - DU1_DOTCLKIN_C_MARK, DU1_DOTCLKIN_B_MARK, DU1_DOTCLKIN_MARK + DU1_DOTCLKIN_MARK +}; +static const unsigned int du1_clk_in_b_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(7, 19), +}; +static const unsigned int du1_clk_in_b_mux[] = { + DU1_DOTCLKIN_B_MARK, +}; +static const unsigned int du1_clk_in_c_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(7, 20), +}; +static const unsigned int du1_clk_in_c_mux[] = { + DU1_DOTCLKIN_C_MARK, }; /* - ETH -------------------------------------------------------------------- */ static const unsigned int eth_link_pins[] = { @@ -2670,10 +2684,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_out_0), SH_PFC_PIN_GROUP(du_clk_out_1), - SH_PFC_PIN_GROUP(du_sync_1), + SH_PFC_PIN_GROUP(du_sync), SH_PFC_PIN_GROUP(du_cde_disp), SH_PFC_PIN_GROUP(du0_clk_in), SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du1_clk_in_b), + SH_PFC_PIN_GROUP(du1_clk_in_c), SH_PFC_PIN_GROUP(eth_link), SH_PFC_PIN_GROUP(eth_magic), SH_PFC_PIN_GROUP(eth_mdio), @@ -2805,7 +2821,7 @@ static const char * const du_groups[] = { "du_rgb888", "du_clk_out_0", "du_clk_out_1", - "du_sync_1", + "du_sync", "du_cde_disp", }; @@ -2815,6 +2831,8 @@ static const char * const du0_groups[] = { static const char * const du1_groups[] = { "du1_clk_in", + "du1_clk_in_b", + "du1_clk_in_c", }; static const char * const eth_groups[] = { -- cgit From 3f9c1268159917932fcefe9b3abd5eabb4ed5a29 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 29 Oct 2013 13:02:18 +0100 Subject: sh-pfc: Share common PORTCR macro definition The macro is defined identically in four different locations. Share it. Signed-off-by: Laurent Pinchart Reviewed-by: Simon Horman Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 11 ----------- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 11 ----------- drivers/pinctrl/sh-pfc/pfc-sh7372.c | 11 ----------- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 10 ---------- drivers/pinctrl/sh-pfc/sh_pfc.h | 3 +-- 5 files changed, 1 insertion(+), 45 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index d25fd4ea0a1d..d76cc343a82a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -2061,17 +2061,6 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi2), }; -#undef PORTCR -#define PORTCR(nr, reg) \ - { \ - PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ - _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ - PORT##nr##_FN0, PORT##nr##_FN1, \ - PORT##nr##_FN2, PORT##nr##_FN3, \ - PORT##nr##_FN4, PORT##nr##_FN5, \ - PORT##nr##_FN6, PORT##nr##_FN7 } \ - } - static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), PORTCR(1, 0xe6050001), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 009174d07767..7ac006583558 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -3234,17 +3234,6 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(tpu0), }; -#undef PORTCR -#define PORTCR(nr, reg) \ - { \ - PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ - _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ - PORT##nr##_FN0, PORT##nr##_FN1, \ - PORT##nr##_FN2, PORT##nr##_FN3, \ - PORT##nr##_FN4, PORT##nr##_FN5, \ - PORT##nr##_FN6, PORT##nr##_FN7 } \ - } - static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), /* PORT0CR */ PORTCR(1, 0xe6050001), /* PORT1CR */ diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index 70b522d34821..4fea6ceb2dbf 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -2118,17 +2118,6 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(usb1), }; -#undef PORTCR -#define PORTCR(nr, reg) \ - { \ - PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ - _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ - PORT##nr##_FN0, PORT##nr##_FN1, \ - PORT##nr##_FN2, PORT##nr##_FN3, \ - PORT##nr##_FN4, PORT##nr##_FN5, \ - PORT##nr##_FN6, PORT##nr##_FN7 } \ - } - static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xE6051000), /* PORT0CR */ PORTCR(1, 0xE6051001), /* PORT1CR */ diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 7e278a97e411..b81b56eae0c9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3138,16 +3138,6 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(usb), }; -#undef PORTCR -#define PORTCR(nr, reg) \ - { \ - PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ - _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ - PORT##nr##_FN0, PORT##nr##_FN1, \ - PORT##nr##_FN2, PORT##nr##_FN3, \ - PORT##nr##_FN4, PORT##nr##_FN5, \ - PORT##nr##_FN6, PORT##nr##_FN7 } \ - } static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), /* PORT0CR */ PORTCR(1, 0xe6050001), /* PORT1CR */ diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 11bd0d970a52..8a494e557b43 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -304,8 +304,7 @@ struct sh_pfc_soc_info { #define PORTCR(nr, reg) \ { \ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ - _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ - PORT##nr##_IN_PU, PORT##nr##_OUT), \ + _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ PORT##nr##_FN0, PORT##nr##_FN1, \ PORT##nr##_FN2, PORT##nr##_FN3, \ PORT##nr##_FN4, PORT##nr##_FN5, \ -- cgit From 1d7b59a07740712b46dd0271abf7dd4013badf49 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 28 Nov 2013 19:01:27 -0800 Subject: sh-pfc: r8a7790: Add SSI pin support Signed-off-by: Kuninori Morimoto Signed-off-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 239 +++++++++++++++++++++++++++++++++++ 1 file changed, 239 insertions(+) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 72786fc93958..a6903de2eb12 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -2961,6 +2961,189 @@ static const unsigned int sdhi3_wp_pins[] = { static const unsigned int sdhi3_wp_mux[] = { SD3_WP_MARK, }; +/* - SSI -------------------------------------------------------------------- */ +static const unsigned int ssi0_data_pins[] = { + /* SDATA0 */ + RCAR_GP_PIN(4, 5), +}; +static const unsigned int ssi0_data_mux[] = { + SSI_SDATA0_MARK, +}; +static const unsigned int ssi0129_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), +}; +static const unsigned int ssi0129_ctrl_mux[] = { + SSI_SCK0129_MARK, SSI_WS0129_MARK, +}; +static const unsigned int ssi1_data_pins[] = { + /* SDATA1 */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int ssi1_data_mux[] = { + SSI_SDATA1_MARK, +}; +static const unsigned int ssi1_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24), +}; +static const unsigned int ssi1_ctrl_mux[] = { + SSI_SCK1_MARK, SSI_WS1_MARK, +}; +static const unsigned int ssi2_data_pins[] = { + /* SDATA2 */ + RCAR_GP_PIN(4, 7), +}; +static const unsigned int ssi2_data_mux[] = { + SSI_SDATA2_MARK, +}; +static const unsigned int ssi2_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17), +}; +static const unsigned int ssi2_ctrl_mux[] = { + SSI_SCK2_MARK, SSI_WS2_MARK, +}; +static const unsigned int ssi3_data_pins[] = { + /* SDATA3 */ + RCAR_GP_PIN(4, 10), +}; +static const unsigned int ssi3_data_mux[] = { + SSI_SDATA3_MARK +}; +static const unsigned int ssi34_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), +}; +static const unsigned int ssi34_ctrl_mux[] = { + SSI_SCK34_MARK, SSI_WS34_MARK, +}; +static const unsigned int ssi4_data_pins[] = { + /* SDATA4 */ + RCAR_GP_PIN(4, 13), +}; +static const unsigned int ssi4_data_mux[] = { + SSI_SDATA4_MARK, +}; +static const unsigned int ssi4_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), +}; +static const unsigned int ssi4_ctrl_mux[] = { + SSI_SCK4_MARK, SSI_WS4_MARK, +}; +static const unsigned int ssi5_pins[] = { + /* SDATA5, SCK, WS */ + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), +}; +static const unsigned int ssi5_mux[] = { + SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK, +}; +static const unsigned int ssi5_b_pins[] = { + /* SDATA5, SCK, WS */ + RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), +}; +static const unsigned int ssi5_b_mux[] = { + SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK +}; +static const unsigned int ssi5_c_pins[] = { + /* SDATA5, SCK, WS */ + RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), +}; +static const unsigned int ssi5_c_mux[] = { + SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK, +}; +static const unsigned int ssi6_pins[] = { + /* SDATA6, SCK, WS */ + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), +}; +static const unsigned int ssi6_mux[] = { + SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK, +}; +static const unsigned int ssi6_b_pins[] = { + /* SDATA6, SCK, WS */ + RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27), +}; +static const unsigned int ssi6_b_mux[] = { + SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK, +}; +static const unsigned int ssi7_data_pins[] = { + /* SDATA7 */ + RCAR_GP_PIN(4, 22), +}; +static const unsigned int ssi7_data_mux[] = { + SSI_SDATA7_MARK, +}; +static const unsigned int ssi7_b_data_pins[] = { + /* SDATA7 */ + RCAR_GP_PIN(4, 22), +}; +static const unsigned int ssi7_b_data_mux[] = { + SSI_SDATA7_B_MARK, +}; +static const unsigned int ssi7_c_data_pins[] = { + /* SDATA7 */ + RCAR_GP_PIN(1, 26), +}; +static const unsigned int ssi7_c_data_mux[] = { + SSI_SDATA7_C_MARK, +}; +static const unsigned int ssi78_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), +}; +static const unsigned int ssi78_ctrl_mux[] = { + SSI_SCK78_MARK, SSI_WS78_MARK, +}; +static const unsigned int ssi78_b_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24), +}; +static const unsigned int ssi78_b_ctrl_mux[] = { + SSI_SCK78_B_MARK, SSI_WS78_B_MARK, +}; +static const unsigned int ssi78_c_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), +}; +static const unsigned int ssi78_c_ctrl_mux[] = { + SSI_SCK78_C_MARK, SSI_WS78_C_MARK, +}; +static const unsigned int ssi8_data_pins[] = { + /* SDATA8 */ + RCAR_GP_PIN(4, 23), +}; +static const unsigned int ssi8_data_mux[] = { + SSI_SDATA8_MARK, +}; +static const unsigned int ssi8_b_data_pins[] = { + /* SDATA8 */ + RCAR_GP_PIN(4, 23), +}; +static const unsigned int ssi8_b_data_mux[] = { + SSI_SDATA8_B_MARK, +}; +static const unsigned int ssi8_c_data_pins[] = { + /* SDATA8 */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int ssi8_c_data_mux[] = { + SSI_SDATA8_C_MARK, +}; +static const unsigned int ssi9_data_pins[] = { + /* SDATA9 */ + RCAR_GP_PIN(4, 24), +}; +static const unsigned int ssi9_data_mux[] = { + SSI_SDATA9_MARK, +}; +static const unsigned int ssi9_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), +}; +static const unsigned int ssi9_ctrl_mux[] = { + SSI_SCK9_MARK, SSI_WS9_MARK, +}; /* - TPU0 ------------------------------------------------------------------- */ static const unsigned int tpu0_to0_pins[] = { /* TO */ @@ -3259,6 +3442,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi0129_ctrl), + SH_PFC_PIN_GROUP(ssi1_data), + SH_PFC_PIN_GROUP(ssi1_ctrl), + SH_PFC_PIN_GROUP(ssi2_data), + SH_PFC_PIN_GROUP(ssi2_ctrl), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5), + SH_PFC_PIN_GROUP(ssi5_b), + SH_PFC_PIN_GROUP(ssi5_c), + SH_PFC_PIN_GROUP(ssi6), + SH_PFC_PIN_GROUP(ssi6_b), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi7_b_data), + SH_PFC_PIN_GROUP(ssi7_c_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi78_b_ctrl), + SH_PFC_PIN_GROUP(ssi78_c_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi8_b_data), + SH_PFC_PIN_GROUP(ssi8_c_data), + SH_PFC_PIN_GROUP(ssi9_data), + SH_PFC_PIN_GROUP(ssi9_ctrl), SH_PFC_PIN_GROUP(tpu0_to0), SH_PFC_PIN_GROUP(tpu0_to1), SH_PFC_PIN_GROUP(tpu0_to2), @@ -3533,6 +3742,35 @@ static const char * const sdhi3_groups[] = { "sdhi3_wp", }; +static const char * const ssi_groups[] = { + "ssi0_data", + "ssi0129_ctrl", + "ssi1_data", + "ssi1_ctrl", + "ssi2_data", + "ssi2_ctrl", + "ssi3_data", + "ssi34_ctrl", + "ssi4_data", + "ssi4_ctrl", + "ssi5", + "ssi5_b", + "ssi5_c", + "ssi6", + "ssi6_b", + "ssi7_data", + "ssi7_b_data", + "ssi7_c_data", + "ssi78_ctrl", + "ssi78_b_ctrl", + "ssi78_c_ctrl", + "ssi8_data", + "ssi8_b_data", + "ssi8_c_data", + "ssi9_data", + "ssi9_ctrl", +}; + static const char * const tpu0_groups[] = { "tpu0_to0", "tpu0_to1", @@ -3599,6 +3837,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(tpu0), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), -- cgit From fcec5b2254c9b7c99d31afb4c390f301b7ad201e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 28 Nov 2013 19:01:37 -0800 Subject: sh-pfc: r8a7790: Add Audio pin support Signed-off-by: Kuninori Morimoto Signed-off-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 68 ++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index a6903de2eb12..1375709422c7 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -1739,6 +1739,56 @@ static struct sh_pfc_pin pinmux_pins[] = { SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15), }; +/* - AUDIO CLOCK ------------------------------------------------------------ */ +static const unsigned int audio_clk_a_pins[] = { + /* CLK A */ + RCAR_GP_PIN(4, 25), +}; +static const unsigned int audio_clk_a_mux[] = { + AUDIO_CLKA_MARK, +}; +static const unsigned int audio_clk_b_pins[] = { + /* CLK B */ + RCAR_GP_PIN(4, 26), +}; +static const unsigned int audio_clk_b_mux[] = { + AUDIO_CLKB_MARK, +}; +static const unsigned int audio_clk_c_pins[] = { + /* CLK C */ + RCAR_GP_PIN(5, 27), +}; +static const unsigned int audio_clk_c_mux[] = { + AUDIO_CLKC_MARK, +}; +static const unsigned int audio_clkout_pins[] = { + /* CLK OUT */ + RCAR_GP_PIN(5, 16), +}; +static const unsigned int audio_clkout_mux[] = { + AUDIO_CLKOUT_MARK, +}; +static const unsigned int audio_clkout_b_pins[] = { + /* CLK OUT B */ + RCAR_GP_PIN(0, 23), +}; +static const unsigned int audio_clkout_b_mux[] = { + AUDIO_CLKOUT_B_MARK, +}; +static const unsigned int audio_clkout_c_pins[] = { + /* CLK OUT C */ + RCAR_GP_PIN(5, 27), +}; +static const unsigned int audio_clkout_c_mux[] = { + AUDIO_CLKOUT_C_MARK, +}; +static const unsigned int audio_clkout_d_pins[] = { + /* CLK OUT D */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int audio_clkout_d_mux[] = { + AUDIO_CLKOUT_D_MARK, +}; /* - DU RGB ----------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -3277,6 +3327,13 @@ static const unsigned int vin1_clk_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clk_c), + SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_out_0), @@ -3487,6 +3544,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin1_clk), }; +static const char * const audio_clk_groups[] = { + "audio_clk_a", + "audio_clk_b", + "audio_clk_c", + "audio_clkout", + "audio_clkout_b", + "audio_clkout_c", + "audio_clkout_d", +}; + static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -3807,6 +3874,7 @@ static const char * const vin1_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), -- cgit From 2ef3967ef5b7e37af5b87beae67cdb24a318f324 Mon Sep 17 00:00:00 2001 From: Takashi Yoshii Date: Mon, 2 Dec 2013 03:19:12 +0900 Subject: sh-pfc: r8a7791: Fix msiof groups to follow GROUP SH_PFC_PIN_GROUP(), pins[], mux[], defines clk, sync, ss1, ss2, rx, tx But, msiof?_groups[] defines clk, ctrl, data Fix msiof[012]_groups members to be consistent to PIN_GROUP. Signed-off-by: Takashi Yoshii Signed-off-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index d26c16360161..ea02d37bab7c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -2858,20 +2858,29 @@ static const char * const mmc_groups[] = { static const char * const msiof0_groups[] = { "msiof0_clk", - "msiof0_ctrl", - "msiof0_data", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_rx", + "msiof0_tx", }; static const char * const msiof1_groups[] = { "msiof1_clk", - "msiof1_ctrl", - "msiof1_data", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_rx", + "msiof1_tx", }; static const char * const msiof2_groups[] = { "msiof2_clk", - "msiof2_ctrl", - "msiof2_data", + "msiof2_sync", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_rx", + "msiof2_tx", }; static const char * const scif0_groups[] = { -- cgit From 7a57be873ae02aa956f453450a6903c6c8970896 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 10 Dec 2013 22:20:22 +0400 Subject: pinctrl: sh-pfc: pfc-r8a7790: Rename VIN pin groups This drops superfluous "signal" word from the pin group names and renames data_enable group to clkenb as in the h/w manual. Signed-off-by: Valentine Barshak Signed-off-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 1375709422c7..5a45ab0877e5 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3278,28 +3278,28 @@ static const unsigned int vin0_data_b_mux[] = { VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, }; -static const unsigned int vin0_hsync_signal_pins[] = { +static const unsigned int vin0_hsync_pins[] = { RCAR_GP_PIN(0, 12), }; -static const unsigned int vin0_hsync_signal_mux[] = { +static const unsigned int vin0_hsync_mux[] = { VI0_HSYNC_N_MARK, }; -static const unsigned int vin0_vsync_signal_pins[] = { +static const unsigned int vin0_vsync_pins[] = { RCAR_GP_PIN(0, 13), }; -static const unsigned int vin0_vsync_signal_mux[] = { +static const unsigned int vin0_vsync_mux[] = { VI0_VSYNC_N_MARK, }; -static const unsigned int vin0_field_signal_pins[] = { +static const unsigned int vin0_field_pins[] = { RCAR_GP_PIN(0, 15), }; -static const unsigned int vin0_field_signal_mux[] = { +static const unsigned int vin0_field_mux[] = { VI0_FIELD_MARK, }; -static const unsigned int vin0_data_enable_pins[] = { +static const unsigned int vin0_clkenb_pins[] = { RCAR_GP_PIN(0, 14), }; -static const unsigned int vin0_data_enable_mux[] = { +static const unsigned int vin0_clkenb_mux[] = { VI0_CLKENB_MARK, }; static const unsigned int vin0_clk_pins[] = { @@ -3535,10 +3535,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin0_data_g), SH_PFC_PIN_GROUP(vin0_data_r), SH_PFC_PIN_GROUP(vin0_data_b), - SH_PFC_PIN_GROUP(vin0_hsync_signal), - SH_PFC_PIN_GROUP(vin0_vsync_signal), - SH_PFC_PIN_GROUP(vin0_field_signal), - SH_PFC_PIN_GROUP(vin0_data_enable), + SH_PFC_PIN_GROUP(vin0_hsync), + SH_PFC_PIN_GROUP(vin0_vsync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), SH_PFC_PIN_GROUP(vin1_data), SH_PFC_PIN_GROUP(vin1_clk), @@ -3861,10 +3861,10 @@ static const char * const vin0_groups[] = { "vin0_data_g", "vin0_data_r", "vin0_data_b", - "vin0_hsync_signal", - "vin0_vsync_signal", - "vin0_field_signal", - "vin0_data_enable", + "vin0_hsync", + "vin0_vsync", + "vin0_field", + "vin0_clkenb", "vin0_clk", }; -- cgit From a9e4c7bb466b34b19ca71ee7383ca23bd37a88c5 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 10 Dec 2013 22:20:23 +0400 Subject: pinctrl: sh-pfc: pfc-r8a7790: Group VIN0 HSYNC and VSYNC together This groups VIN0 HSYNC and VSYNC pins together since one cannot be used without another. Signed-off-by: Valentine Barshak Signed-off-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 5a45ab0877e5..81ff4bf72264 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3278,16 +3278,12 @@ static const unsigned int vin0_data_b_mux[] = { VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, }; -static const unsigned int vin0_hsync_pins[] = { - RCAR_GP_PIN(0, 12), +static const unsigned int vin0_sync_pins[] = { + RCAR_GP_PIN(0, 12), /* HSYNC */ + RCAR_GP_PIN(0, 13), /* VSYNC */ }; -static const unsigned int vin0_hsync_mux[] = { +static const unsigned int vin0_sync_mux[] = { VI0_HSYNC_N_MARK, -}; -static const unsigned int vin0_vsync_pins[] = { - RCAR_GP_PIN(0, 13), -}; -static const unsigned int vin0_vsync_mux[] = { VI0_VSYNC_N_MARK, }; static const unsigned int vin0_field_pins[] = { @@ -3535,8 +3531,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin0_data_g), SH_PFC_PIN_GROUP(vin0_data_r), SH_PFC_PIN_GROUP(vin0_data_b), - SH_PFC_PIN_GROUP(vin0_hsync), - SH_PFC_PIN_GROUP(vin0_vsync), + SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), @@ -3861,8 +3856,7 @@ static const char * const vin0_groups[] = { "vin0_data_g", "vin0_data_r", "vin0_data_b", - "vin0_hsync", - "vin0_vsync", + "vin0_sync", "vin0_field", "vin0_clkenb", "vin0_clk", -- cgit From 64fe8abc7336e17f977bb38c4c261d24bfc5da17 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 10 Dec 2013 22:20:24 +0400 Subject: pinctrl: sh-pfc: pfc-r8a7790: Reorganize VIN0 data pins This reorganizes and renames VIN0 data pin groups to cover all possible configurations. There's total of eight data pin groups, one per each configuration. Most of the groups share the same pin/mux array. Only the 18-bit configuration needs a separate pin/mux array since in combines interleaved data pins. Signed-off-by: Valentine Barshak Signed-off-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 125 ++++++++++++++++++++++++++--------- 1 file changed, 95 insertions(+), 30 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 81ff4bf72264..11e12d61de9b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3247,36 +3247,91 @@ static const unsigned int usb2_pins[] = { static const unsigned int usb2_mux[] = { USB2_PWEN_MARK, USB2_OVC_MARK, }; -/* - VIN0 ------------------------------------------------------------------- */ -static const unsigned int vin0_data_g_pins[] = { - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), - RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), -}; -static const unsigned int vin0_data_g_mux[] = { - VI0_G0_MARK, VI0_G1_MARK, VI0_G2_MARK, - VI0_G3_MARK, VI0_G4_MARK, VI0_G5_MARK, - VI0_G6_MARK, VI0_G7_MARK, + +union vin_data { + unsigned int data24[24]; + unsigned int data20[20]; + unsigned int data16[16]; + unsigned int data12[12]; + unsigned int data10[10]; + unsigned int data8[8]; + unsigned int data4[4]; }; -static const unsigned int vin0_data_r_pins[] = { - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), - RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), - RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), + +#define VIN_DATA_PIN_GROUP(n, s) \ + { \ + .name = #n#s, \ + .pins = n##_pins.data##s, \ + .mux = n##_mux.data##s, \ + .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ + } + +/* - VIN0 ------------------------------------------------------------------- */ +static const union vin_data vin0_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + /* G */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + /* R */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), + RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), + }, }; -static const unsigned int vin0_data_r_mux[] = { - VI0_R0_MARK, VI0_R1_MARK, VI0_R2_MARK, - VI0_R3_MARK, VI0_R4_MARK, VI0_R5_MARK, - VI0_R6_MARK, VI0_R7_MARK, +static const union vin_data vin0_data_mux = { + .data24 = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, + }, }; -static const unsigned int vin0_data_b_pins[] = { - RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), +static const unsigned int vin0_data18_pins[] = { + /* B */ + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + /* G */ + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + /* R */ + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), + RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), }; -static const unsigned int vin0_data_b_mux[] = { - VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK, - VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, +static const unsigned int vin0_data18_mux[] = { + /* B */ + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, }; static const unsigned int vin0_sync_pins[] = { RCAR_GP_PIN(0, 12), /* HSYNC */ @@ -3528,9 +3583,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), - SH_PFC_PIN_GROUP(vin0_data_g), - SH_PFC_PIN_GROUP(vin0_data_r), - SH_PFC_PIN_GROUP(vin0_data_b), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + VIN_DATA_PIN_GROUP(vin0_data, 4), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), @@ -3853,9 +3913,14 @@ static const char * const usb2_groups[] = { }; static const char * const vin0_groups[] = { - "vin0_data_g", - "vin0_data_r", - "vin0_data_b", + "vin0_data24", + "vin0_data20", + "vin0_data18", + "vin0_data16", + "vin0_data12", + "vin0_data10", + "vin0_data8", + "vin0_data4", "vin0_sync", "vin0_field", "vin0_clkenb", -- cgit From 317a03a9cb925a5566b852dff85f6aaa4aff7e3e Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 10 Dec 2013 22:20:25 +0400 Subject: pinctrl: sh-pfc: pfc-r8a7790: Add missing VIN1 pins Both VIN0 and VIN1 channels support identical input interfaces. Add missing VIN1 pins here and organize them in the same pin groups as VIN0. Signed-off-by: Valentine Barshak Signed-off-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 112 ++++++++++++++++++++++++++++++++--- 1 file changed, 104 insertions(+), 8 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 11e12d61de9b..2194ea6374ca 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3360,15 +3360,91 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const unsigned int vin1_data_pins[] = { - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), - RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), +static const union vin_data vin1_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), + /* G */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), + }, +}; +static const union vin_data vin1_data_mux = { + .data24 = { + /* B */ + VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, + VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, + VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, + VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, + /* G */ + VI1_G0_MARK, VI1_G1_MARK, + VI1_G2_MARK, VI1_G3_MARK, + VI1_G4_MARK, VI1_G5_MARK, + VI1_G6_MARK, VI1_G7_MARK, + /* R */ + VI1_R0_MARK, VI1_R1_MARK, + VI1_R2_MARK, VI1_R3_MARK, + VI1_R4_MARK, VI1_R5_MARK, + VI1_R6_MARK, VI1_R7_MARK, + }, +}; +static const unsigned int vin1_data18_pins[] = { + /* B */ + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), + /* G */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), }; -static const unsigned int vin1_data_mux[] = { - VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK, - VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, +static const unsigned int vin1_data18_mux[] = { + /* B */ + VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, + VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, + /* G */ + VI1_G2_MARK, VI1_G3_MARK, + VI1_G4_MARK, VI1_G5_MARK, + VI1_G6_MARK, VI1_G7_MARK, + /* R */ + VI1_R2_MARK, VI1_R3_MARK, + VI1_R4_MARK, VI1_R5_MARK, + VI1_R6_MARK, VI1_R7_MARK, +}; +static const unsigned int vin1_sync_pins[] = { + RCAR_GP_PIN(1, 24), /* HSYNC */ + RCAR_GP_PIN(1, 25), /* VSYNC */ +}; +static const unsigned int vin1_sync_mux[] = { + VI1_HSYNC_N_MARK, + VI1_VSYNC_N_MARK, +}; +static const unsigned int vin1_field_pins[] = { + RCAR_GP_PIN(1, 13), +}; +static const unsigned int vin1_field_mux[] = { + VI1_FIELD_MARK, +}; +static const unsigned int vin1_clkenb_pins[] = { + RCAR_GP_PIN(1, 26), +}; +static const unsigned int vin1_clkenb_mux[] = { + VI1_CLKENB_MARK, }; static const unsigned int vin1_clk_pins[] = { RCAR_GP_PIN(2, 9), @@ -3595,7 +3671,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - SH_PFC_PIN_GROUP(vin1_data), + VIN_DATA_PIN_GROUP(vin1_data, 24), + VIN_DATA_PIN_GROUP(vin1_data, 20), + SH_PFC_PIN_GROUP(vin1_data18), + VIN_DATA_PIN_GROUP(vin1_data, 16), + VIN_DATA_PIN_GROUP(vin1_data, 12), + VIN_DATA_PIN_GROUP(vin1_data, 10), + VIN_DATA_PIN_GROUP(vin1_data, 8), + VIN_DATA_PIN_GROUP(vin1_data, 4), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), }; @@ -3928,7 +4014,17 @@ static const char * const vin0_groups[] = { }; static const char * const vin1_groups[] = { - "vin1_data", + "vin1_data24", + "vin1_data20", + "vin1_data18", + "vin1_data16", + "vin1_data12", + "vin1_data10", + "vin1_data8", + "vin1_data4", + "vin1_sync", + "vin1_field", + "vin1_clkenb", "vin1_clk", }; -- cgit From 054d4259091a52be0d8ed3e3febf07cf263d294d Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 10 Dec 2013 22:20:26 +0400 Subject: pinctrl: sh-pfc: pfc-r8a7790: Add VIN2 and VIN3 pins There are VIN2 and VIN3 channels available on the R8A7790 SoC. VIN2 supports 4/8/16/18/24-bit data, while VIN3 supports 8-bit. Add both here, covering all possible data pin configurations. Signed-off-by: Valentine Barshak Signed-off-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 168 +++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 2194ea6374ca..293a51a7434e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3452,6 +3452,138 @@ static const unsigned int vin1_clk_pins[] = { static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; +/* - VIN2 ----------------------------------------------------------------- */ +static const union vin_data vin2_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + /* G */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), + }, +}; +static const union vin_data vin2_data_mux = { + .data24 = { + /* B */ + VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, + VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, + VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, + VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, + /* G */ + VI2_G0_MARK, VI2_G1_MARK, + VI2_G2_MARK, VI2_G3_MARK, + VI2_G4_MARK, VI2_G5_MARK, + VI2_G6_MARK, VI2_G7_MARK, + /* R */ + VI2_R0_MARK, VI2_R1_MARK, + VI2_R2_MARK, VI2_R3_MARK, + VI2_R4_MARK, VI2_R5_MARK, + VI2_R6_MARK, VI2_R7_MARK, + }, +}; +static const unsigned int vin2_data18_pins[] = { + /* B */ + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + /* G */ + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), +}; +static const unsigned int vin2_data18_mux[] = { + /* B */ + VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, + VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, + VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, + /* G */ + VI2_G2_MARK, VI2_G3_MARK, + VI2_G4_MARK, VI2_G5_MARK, + VI2_G6_MARK, VI2_G7_MARK, + /* R */ + VI2_R2_MARK, VI2_R3_MARK, + VI2_R4_MARK, VI2_R5_MARK, + VI2_R6_MARK, VI2_R7_MARK, +}; +static const unsigned int vin2_sync_pins[] = { + RCAR_GP_PIN(1, 16), /* HSYNC */ + RCAR_GP_PIN(1, 21), /* VSYNC */ +}; +static const unsigned int vin2_sync_mux[] = { + VI2_HSYNC_N_MARK, + VI2_VSYNC_N_MARK, +}; +static const unsigned int vin2_field_pins[] = { + RCAR_GP_PIN(1, 9), +}; +static const unsigned int vin2_field_mux[] = { + VI2_FIELD_MARK, +}; +static const unsigned int vin2_clkenb_pins[] = { + RCAR_GP_PIN(1, 8), +}; +static const unsigned int vin2_clkenb_mux[] = { + VI2_CLKENB_MARK, +}; +static const unsigned int vin2_clk_pins[] = { + RCAR_GP_PIN(1, 11), +}; +static const unsigned int vin2_clk_mux[] = { + VI2_CLK_MARK, +}; +/* - VIN3 ----------------------------------------------------------------- */ +static const unsigned int vin3_data8_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin3_data8_mux[] = { + VI3_DATA0_MARK, VI3_DATA1_MARK, + VI3_DATA2_MARK, VI3_DATA3_MARK, + VI3_DATA4_MARK, VI3_DATA5_MARK, + VI3_DATA6_MARK, VI3_DATA7_MARK, +}; +static const unsigned int vin3_sync_pins[] = { + RCAR_GP_PIN(1, 16), /* HSYNC */ + RCAR_GP_PIN(1, 17), /* VSYNC */ +}; +static const unsigned int vin3_sync_mux[] = { + VI3_HSYNC_N_MARK, + VI2_VSYNC_N_MARK, +}; +static const unsigned int vin3_field_pins[] = { + RCAR_GP_PIN(1, 15), +}; +static const unsigned int vin3_field_mux[] = { + VI3_FIELD_MARK, +}; +static const unsigned int vin3_clkenb_pins[] = { + RCAR_GP_PIN(1, 14), +}; +static const unsigned int vin3_clkenb_mux[] = { + VI3_CLKENB_MARK, +}; +static const unsigned int vin3_clk_pins[] = { + RCAR_GP_PIN(1, 23), +}; +static const unsigned int vin3_clk_mux[] = { + VI3_CLK_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clk_a), @@ -3683,6 +3815,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), + VIN_DATA_PIN_GROUP(vin2_data, 24), + SH_PFC_PIN_GROUP(vin2_data18), + VIN_DATA_PIN_GROUP(vin2_data, 16), + VIN_DATA_PIN_GROUP(vin2_data, 8), + VIN_DATA_PIN_GROUP(vin2_data, 4), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin2_field), + SH_PFC_PIN_GROUP(vin2_clkenb), + SH_PFC_PIN_GROUP(vin2_clk), + SH_PFC_PIN_GROUP(vin3_data8), + SH_PFC_PIN_GROUP(vin3_sync), + SH_PFC_PIN_GROUP(vin3_field), + SH_PFC_PIN_GROUP(vin3_clkenb), + SH_PFC_PIN_GROUP(vin3_clk), }; static const char * const audio_clk_groups[] = { @@ -4028,6 +4174,26 @@ static const char * const vin1_groups[] = { "vin1_clk", }; +static const char * const vin2_groups[] = { + "vin2_data24", + "vin2_data18", + "vin2_data16", + "vin2_data8", + "vin2_data4", + "vin2_sync", + "vin2_field", + "vin2_clkenb", + "vin2_clk", +}; + +static const char * const vin3_groups[] = { + "vin3_data8", + "vin3_sync", + "vin3_field", + "vin3_clkenb", + "vin3_clk", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(du), @@ -4067,6 +4233,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(usb2), SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), + SH_PFC_FUNCTION(vin3), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { -- cgit From 8d72a7fc8dd74d41ec5f37b70797679e910007e0 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 04:26:21 +0100 Subject: sh-pfc: Turn unsigned indices into unsigned int Some indices take positive values only, make them unsigned. Signed-off-by: Laurent Pinchart Acked-by: Magnus Damm Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 8 ++++---- drivers/pinctrl/sh-pfc/gpio.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index d77ece5217f0..06e648bf3a1b 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -29,7 +29,7 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) { struct resource *res; - int k; + unsigned int k; if (pdev->num_resources == 0) return -EINVAL; @@ -147,7 +147,7 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, unsigned long *maskp, unsigned long *posp) { - int k; + unsigned int k; *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); @@ -196,7 +196,7 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, { const struct pinmux_cfg_reg *config_reg; unsigned long r_width, f_width, curr_width, ncomb; - int k, m, n, pos, bit_pos; + unsigned int k, m, n, pos, bit_pos; k = 0; while (1) { @@ -238,7 +238,7 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, u16 *enum_idp) { const u16 *data = pfc->info->gpio_data; - int k; + unsigned int k; if (pos) { *enum_idp = data[pos + 1]; diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 04bf52b64fb3..3d30e6ecdf4a 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -204,7 +204,7 @@ static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value) static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) { struct sh_pfc *pfc = gpio_to_pfc(gc); - int i, k; + unsigned int i, k; for (i = 0; i < pfc->info->gpio_irq_size; i++) { unsigned short *gpios = pfc->info->gpio_irq[i].gpios; -- cgit From 316b2550015dc8d26fb1395826533e9ef3434da9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 04:26:22 +0100 Subject: sh-pfc: Terminate gpios array by -1 0 is a valid GPIO value, use -1 to terminate the gpios array in IRQ lists. Signed-off-by: Laurent Pinchart Acked-by: Magnus Damm Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/gpio.c | 4 ++-- drivers/pinctrl/sh-pfc/sh_pfc.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 3d30e6ecdf4a..c24be810f56c 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -207,9 +207,9 @@ static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) unsigned int i, k; for (i = 0; i < pfc->info->gpio_irq_size; i++) { - unsigned short *gpios = pfc->info->gpio_irq[i].gpios; + short *gpios = pfc->info->gpio_irq[i].gpios; - for (k = 0; gpios[k]; k++) { + for (k = 0; gpios[k] >= 0; k++) { if (gpios[k] == offset) return pfc->info->gpio_irq[i].irq; } diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 8a494e557b43..e17ccab54f2d 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -94,11 +94,11 @@ struct pinmux_data_reg { struct pinmux_irq { int irq; - unsigned short *gpios; + short *gpios; }; #define PINMUX_IRQ(irq_nr, ids...) \ - { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \ + { .irq = irq_nr, .gpios = (short []) { ids, -1 } } struct pinmux_range { u16 begin; -- cgit From c48ca30341011fabb0c8bb88b58fce5b7ae9ebd9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 04:26:23 +0100 Subject: sh-pfc: sh73a0: Add missing IRQ15 The external IRQ15 input multiplexed on GPIO 0 is missing. Add it. Signed-off-by: Laurent Pinchart Acked-by: Magnus Damm Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index b81b56eae0c9..a6bd1e772345 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3651,6 +3651,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { }; static const struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(irq_pin(15), 0), PINMUX_IRQ(irq_pin(19), 9), PINMUX_IRQ(irq_pin(1), 10), PINMUX_IRQ(irq_pin(0), 11), -- cgit From de55c71feb312baa7cf18d3eb966e3bf932d455a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 04:26:24 +0100 Subject: sh-pfc: sh73a0: Sort IRQ entries by IRQ number This makes catching duplicate entries easier. Merge the two IRQ9 entries found after sorting. Signed-off-by: Laurent Pinchart Acked-by: Magnus Damm Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 47 ++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 24 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index a6bd1e772345..a8d472210e32 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3651,39 +3651,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { }; static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(irq_pin(15), 0), - PINMUX_IRQ(irq_pin(19), 9), - PINMUX_IRQ(irq_pin(1), 10), PINMUX_IRQ(irq_pin(0), 11), + PINMUX_IRQ(irq_pin(1), 10), + PINMUX_IRQ(irq_pin(2), 149), + PINMUX_IRQ(irq_pin(3), 224), + PINMUX_IRQ(irq_pin(4), 159), + PINMUX_IRQ(irq_pin(5), 227), + PINMUX_IRQ(irq_pin(6), 147), + PINMUX_IRQ(irq_pin(7), 150), + PINMUX_IRQ(irq_pin(8), 223), + PINMUX_IRQ(irq_pin(9), 56, 308), + PINMUX_IRQ(irq_pin(10), 54), + PINMUX_IRQ(irq_pin(11), 238), + PINMUX_IRQ(irq_pin(12), 156), + PINMUX_IRQ(irq_pin(13), 239), + PINMUX_IRQ(irq_pin(14), 251), + PINMUX_IRQ(irq_pin(15), 0), + PINMUX_IRQ(irq_pin(16), 249), + PINMUX_IRQ(irq_pin(17), 234), PINMUX_IRQ(irq_pin(18), 13), + PINMUX_IRQ(irq_pin(19), 9), PINMUX_IRQ(irq_pin(20), 14), PINMUX_IRQ(irq_pin(21), 15), - PINMUX_IRQ(irq_pin(31), 26), - PINMUX_IRQ(irq_pin(30), 27), - PINMUX_IRQ(irq_pin(29), 28), PINMUX_IRQ(irq_pin(22), 40), PINMUX_IRQ(irq_pin(23), 53), - PINMUX_IRQ(irq_pin(10), 54), - PINMUX_IRQ(irq_pin(9), 56), + PINMUX_IRQ(irq_pin(24), 118), + PINMUX_IRQ(irq_pin(25), 164), PINMUX_IRQ(irq_pin(26), 115), PINMUX_IRQ(irq_pin(27), 116), PINMUX_IRQ(irq_pin(28), 117), - PINMUX_IRQ(irq_pin(24), 118), - PINMUX_IRQ(irq_pin(6), 147), - PINMUX_IRQ(irq_pin(2), 149), - PINMUX_IRQ(irq_pin(7), 150), - PINMUX_IRQ(irq_pin(12), 156), - PINMUX_IRQ(irq_pin(4), 159), - PINMUX_IRQ(irq_pin(25), 164), - PINMUX_IRQ(irq_pin(8), 223), - PINMUX_IRQ(irq_pin(3), 224), - PINMUX_IRQ(irq_pin(5), 227), - PINMUX_IRQ(irq_pin(17), 234), - PINMUX_IRQ(irq_pin(11), 238), - PINMUX_IRQ(irq_pin(13), 239), - PINMUX_IRQ(irq_pin(16), 249), - PINMUX_IRQ(irq_pin(14), 251), - PINMUX_IRQ(irq_pin(9), 308), + PINMUX_IRQ(irq_pin(29), 28), + PINMUX_IRQ(irq_pin(30), 27), + PINMUX_IRQ(irq_pin(31), 26), }; /* ----------------------------------------------------------------------------- -- cgit From 5b46ac3a7723636082ec6234289517ca5b9c65af Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 04:26:25 +0100 Subject: sh-pfc: Rename sh_pfc window field to windows There's more than one window, name the field windows. Signed-off-by: Laurent Pinchart Acked-by: Magnus Damm Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 19 ++++++++++--------- drivers/pinctrl/sh-pfc/core.h | 2 +- drivers/pinctrl/sh-pfc/gpio.c | 4 ++-- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 4 ++-- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7372.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 8 ++++---- 7 files changed, 21 insertions(+), 20 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 06e648bf3a1b..7831f078a5ef 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -34,20 +34,21 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) if (pdev->num_resources == 0) return -EINVAL; - pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources * - sizeof(*pfc->window), GFP_NOWAIT); - if (!pfc->window) + pfc->windows = devm_kzalloc(pfc->dev, pdev->num_resources * + sizeof(*pfc->windows), GFP_NOWAIT); + if (!pfc->windows) return -ENOMEM; pfc->num_windows = pdev->num_resources; for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) { WARN_ON(resource_type(res) != IORESOURCE_MEM); - pfc->window[k].phys = res->start; - pfc->window[k].size = resource_size(res); - pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start, - resource_size(res)); - if (!pfc->window[k].virt) + pfc->windows[k].phys = res->start; + pfc->windows[k].size = resource_size(res); + pfc->windows[k].virt = + devm_ioremap_nocache(pfc->dev, res->start, + resource_size(res)); + if (!pfc->windows[k].virt) return -ENOMEM; } @@ -62,7 +63,7 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, /* scan through physical windows and convert address */ for (i = 0; i < pfc->num_windows; i++) { - window = pfc->window + i; + window = pfc->windows + i; if (address < window->phys) continue; diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 11ea87268658..a83b7472e674 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -37,7 +37,7 @@ struct sh_pfc { spinlock_t lock; unsigned int num_windows; - struct sh_pfc_window *window; + struct sh_pfc_window *windows; struct sh_pfc_pin_range *ranges; unsigned int nr_ranges; diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index c24be810f56c..6a21349fb116 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -347,7 +347,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) * GPIOs. */ for (i = 0; i < pfc->num_windows; ++i) { - struct sh_pfc_window *window = &pfc->window[i]; + struct sh_pfc_window *window = &pfc->windows[i]; if (pfc->info->data_regs[0].reg >= window->phys && pfc->info->data_regs[0].reg < window->phys + window->size) @@ -358,7 +358,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) return 0; /* Register the real GPIOs chip. */ - chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->window[i]); + chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]); if (IS_ERR(chip)) return PTR_ERR(chip); diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index d76cc343a82a..32dd478f28e3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -2680,7 +2680,7 @@ static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc, { void __iomem *addr; - addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; + addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; switch (ioread8(addr) & PORTCR_PULMD_MASK) { case PORTCR_PULMD_UP: @@ -2699,7 +2699,7 @@ static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, void __iomem *addr; u32 value; - addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; + addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; value = ioread8(addr) & ~PORTCR_PULMD_MASK; switch (bias) { diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 7ac006583558..a189b962a1eb 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -3710,7 +3710,7 @@ static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) &r8a7740_portcr_offsets[i]; if (i <= group->end_pin) - return pfc->window->virt + group->offset + pin; + return pfc->windows->virt + group->offset + pin; } return NULL; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index 4fea6ceb2dbf..bcdd5c3cdcf0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -2574,7 +2574,7 @@ static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) &sh7372_portcr_offsets[i]; if (i <= group->end_pin) - return pfc->window->virt + group->offset + pin; + return pfc->windows->virt + group->offset + pin; } return NULL; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index a8d472210e32..dc7c7fb33805 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3692,7 +3692,7 @@ static const struct pinmux_irq pinmux_irqs[] = { static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable) { struct sh_pfc *pfc = reg->reg_data; - void __iomem *addr = pfc->window[1].virt + 4; + void __iomem *addr = pfc->windows[1].virt + 4; unsigned long flags; u32 value; @@ -3725,7 +3725,7 @@ static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg) static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg) { struct sh_pfc *pfc = reg->reg_data; - void __iomem *addr = pfc->window[1].virt + 4; + void __iomem *addr = pfc->windows[1].virt + 4; unsigned long flags; u32 value; @@ -3784,7 +3784,7 @@ static const unsigned int sh73a0_portcr_offsets[] = { static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { - void __iomem *addr = pfc->window->virt + void __iomem *addr = pfc->windows->virt + sh73a0_portcr_offsets[pin >> 5] + pin; u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; @@ -3802,7 +3802,7 @@ static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias) { - void __iomem *addr = pfc->window->virt + void __iomem *addr = pfc->windows->virt + sh73a0_portcr_offsets[pin >> 5] + pin; u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; -- cgit From 70c8f01a357ac74d223a632659787396fef1e649 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 04:26:26 +0100 Subject: sh-pfc: Support GPIO to IRQ mapping specified IRQ resources On non-DT platforms IRQ controllers associated with the GPIOs have a fixed IRQ base value known at compile time. The sh-pfc driver translates GPIO number to IRQ numbers using a hardcoded table. This mechanism breaks on DT platforms, as the IRQ base values are dynamic in that case. Fix this by specifying IRQs associated with GPIOs in IRQ resources, populated automatically from the device tree. When IRQ resources are specified the driver requires one IRQ resource per GPIO able to generate an interrupt, and uses the translation table to compute the IRQ resource offset instead of the IRQ number. Cc: devicetree@vger.kernel.org Signed-off-by: Laurent Pinchart Acked-by: Magnus Damm Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 69 +++++++++++++++++++++++++++++++++---------- drivers/pinctrl/sh-pfc/core.h | 2 ++ drivers/pinctrl/sh-pfc/gpio.c | 14 ++++++++- 3 files changed, 68 insertions(+), 17 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 7831f078a5ef..b9b464d0578c 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -26,30 +26,67 @@ #include "core.h" -static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) +static int sh_pfc_map_resources(struct sh_pfc *pfc, + struct platform_device *pdev) { + unsigned int num_windows = 0; + unsigned int num_irqs = 0; + struct sh_pfc_window *windows; + unsigned int *irqs = NULL; struct resource *res; - unsigned int k; + unsigned int i; + + /* Count the MEM and IRQ resources. */ + for (i = 0; i < pdev->num_resources; ++i) { + switch (resource_type(&pdev->resource[i])) { + case IORESOURCE_MEM: + num_windows++; + break; + + case IORESOURCE_IRQ: + num_irqs++; + break; + } + } - if (pdev->num_resources == 0) + if (num_windows == 0) return -EINVAL; - pfc->windows = devm_kzalloc(pfc->dev, pdev->num_resources * - sizeof(*pfc->windows), GFP_NOWAIT); - if (!pfc->windows) + /* Allocate memory windows and IRQs arrays. */ + windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows), + GFP_KERNEL); + if (windows == NULL) return -ENOMEM; - pfc->num_windows = pdev->num_resources; + pfc->num_windows = num_windows; + pfc->windows = windows; - for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) { - WARN_ON(resource_type(res) != IORESOURCE_MEM); - pfc->windows[k].phys = res->start; - pfc->windows[k].size = resource_size(res); - pfc->windows[k].virt = - devm_ioremap_nocache(pfc->dev, res->start, - resource_size(res)); - if (!pfc->windows[k].virt) + if (num_irqs) { + irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs), + GFP_KERNEL); + if (irqs == NULL) return -ENOMEM; + + pfc->num_irqs = num_irqs; + pfc->irqs = irqs; + } + + /* Fill them. */ + for (i = 0, res = pdev->resource; i < pdev->num_resources; i++, res++) { + switch (resource_type(res)) { + case IORESOURCE_MEM: + windows->phys = res->start; + windows->size = resource_size(res); + windows->virt = devm_ioremap_resource(pfc->dev, res); + if (IS_ERR(windows->virt)) + return -ENOMEM; + windows++; + break; + + case IORESOURCE_IRQ: + *irqs++ = res->start; + break; + } } return 0; @@ -482,7 +519,7 @@ static int sh_pfc_probe(struct platform_device *pdev) pfc->info = info; pfc->dev = &pdev->dev; - ret = sh_pfc_ioremap(pfc, pdev); + ret = sh_pfc_map_resources(pfc, pdev); if (unlikely(ret < 0)) return ret; diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index a83b7472e674..b7b0e6ccf305 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -38,6 +38,8 @@ struct sh_pfc { unsigned int num_windows; struct sh_pfc_window *windows; + unsigned int num_irqs; + unsigned int *irqs; struct sh_pfc_pin_range *ranges; unsigned int nr_ranges; diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 6a21349fb116..63480815e1af 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -211,11 +211,17 @@ static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) for (k = 0; gpios[k] >= 0; k++) { if (gpios[k] == offset) - return pfc->info->gpio_irq[i].irq; + goto found; } } return -ENOSYS; + +found: + if (pfc->num_irqs) + return pfc->irqs[i]; + else + return pfc->info->gpio_irq[i].irq; } static int gpio_pin_setup(struct sh_pfc_chip *chip) @@ -357,6 +363,12 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) if (i == pfc->num_windows) return 0; + /* If we have IRQ resources make sure their number is correct. */ + if (pfc->num_irqs && pfc->num_irqs != pfc->info->gpio_irq_size) { + dev_err(pfc->dev, "invalid number of IRQ resources\n"); + return -EINVAL; + } + /* Register the real GPIOs chip. */ chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]); if (IS_ERR(chip)) -- cgit From 9aecff583e64a15b1f8f7fa739abb4a8701f7c67 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 16 Dec 2013 20:25:14 +0100 Subject: pinctrl: sh-pfc: Constify enum_ids and var_field_width compound literals The enum_ids and var_field_width fields of struct pinmux_data_reg and pinmux_cfg_reg are initialized using compound literals. Cast them to const to store them in .rodata. Signed-off-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/sh_pfc.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index e17ccab54f2d..cdd033851c21 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -76,12 +76,13 @@ struct pinmux_cfg_reg { #define PINMUX_CFG_REG(name, r, r_width, f_width) \ .reg = r, .reg_width = r_width, .field_width = f_width, \ - .enum_ids = (u16 [(r_width / f_width) * (1 << f_width)]) + .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ .reg = r, .reg_width = r_width, \ - .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ - .enum_ids = (u16 []) + .var_field_width = (const unsigned long [r_width]) \ + { var_fw0, var_fwn, 0 }, \ + .enum_ids = (const u16 []) struct pinmux_data_reg { unsigned long reg, reg_width; @@ -90,7 +91,7 @@ struct pinmux_data_reg { #define PINMUX_DATA_REG(name, r, r_width) \ .reg = r, .reg_width = r_width, \ - .enum_ids = (u16 [r_width]) \ + .enum_ids = (const u16 [r_width]) \ struct pinmux_irq { int irq; -- cgit From 6d5bddd5258c11f58cc6a6d17cd97ce5ad39a270 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 16 Dec 2013 20:25:15 +0100 Subject: pinctrl: sh-pfc: Constify IRQ GPIOs arrays The arrays are never modified, make them const. Signed-off-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/gpio.c | 2 +- drivers/pinctrl/sh-pfc/sh_pfc.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 63480815e1af..a9288ab01f7b 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -207,7 +207,7 @@ static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) unsigned int i, k; for (i = 0; i < pfc->info->gpio_irq_size; i++) { - short *gpios = pfc->info->gpio_irq[i].gpios; + const short *gpios = pfc->info->gpio_irq[i].gpios; for (k = 0; gpios[k] >= 0; k++) { if (gpios[k] == offset) diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index cdd033851c21..25496c416de0 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -95,11 +95,11 @@ struct pinmux_data_reg { struct pinmux_irq { int irq; - short *gpios; + const short *gpios; }; #define PINMUX_IRQ(irq_nr, ids...) \ - { .irq = irq_nr, .gpios = (short []) { ids, -1 } } + { .irq = irq_nr, .gpios = (const short []) { ids, -1 } } struct pinmux_range { u16 begin; -- cgit From f41a1efe63c6fc101b9c5b478c9dc22a43312b21 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 16 Dec 2013 20:25:16 +0100 Subject: pinctrl: sh-pfc: sh: Constify pins and cfg_regs arrays The arrays are never modified, declare them as const. Signed-off-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh7203.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7264.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7269.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7720.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7722.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7723.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7724.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7734.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7757.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7785.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7786.c | 2 +- drivers/pinctrl/sh-pfc/pfc-shx3.c | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c index bf3d8f28768d..3bda7bafd0ab 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c @@ -702,7 +702,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PA */ PINMUX_GPIO(PA7), PINMUX_GPIO(PA6), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index 673a59503223..e1cb6dc05028 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -1071,7 +1071,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(SD_D2_MARK, PK0MD_10), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* Port A */ PINMUX_GPIO(PA3), PINMUX_GPIO(PA2), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index a19b60f72b23..7a11320ad96d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -1451,7 +1451,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(PWM1A_MARK, PJ0MD_100), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* Port A */ PINMUX_GPIO(PA1), PINMUX_GPIO(PA0), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c index 7a26809eda15..13d05f88bc01 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c @@ -576,7 +576,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(PTA7), PINMUX_GPIO(PTA6), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c index add309347b05..914d872c37a4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c @@ -754,7 +754,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(PTA7), PINMUX_GPIO(PTA6), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c index 1cecc9101a52..4eb7eae2e6d0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c @@ -917,7 +917,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(PTA7), PINMUX_GPIO(PTA6), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c index 1085ab556b8e..74a1a7f1317c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c @@ -1146,7 +1146,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(PTA7), PINMUX_GPIO(PTA6), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index ec0c47c4f100..e53dd1cb1625 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -1357,7 +1357,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c index 33d75e510911..625661a88c52 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c @@ -1074,7 +1074,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PTA */ PINMUX_GPIO(PTA7), PINMUX_GPIO(PTA6), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c index 517eb49d76bd..b38dd7e3e375 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c @@ -671,7 +671,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PA */ PINMUX_GPIO(PA7), PINMUX_GPIO(PA6), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c index 623345fac936..6cb4e0aaf20b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c @@ -407,7 +407,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PA */ PINMUX_GPIO(PA7), PINMUX_GPIO(PA6), diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c index 55262bd869ed..a3fcb2284d91 100644 --- a/drivers/pinctrl/sh-pfc/pfc-shx3.c +++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c @@ -285,7 +285,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(IRQOUT_MARK, PH0_FN), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PA */ PINMUX_GPIO(PA7), PINMUX_GPIO(PA6), -- cgit From 44a45b55a72754e5c9ed047179fb269b530f45fc Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 16 Dec 2013 20:25:17 +0100 Subject: pinctrl: sh-pfc: ARM: Constify pins and cfg_regs arrays The arrays are never modified, declare them as const. Signed-off-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 2 +- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 2 +- drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 4 ++-- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 2 +- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 4 ++-- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 4 ++-- drivers/pinctrl/sh-pfc/pfc-sh7372.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 2 +- 8 files changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 32dd478f28e3..d39ca87353e4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -1272,7 +1272,7 @@ static const u16 pinmux_data[] = { #define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) #define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1), R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3), R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index a189b962a1eb..f4d30246460f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -1543,7 +1543,7 @@ static const u16 pinmux_data[] = { #define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) #define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD) -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* Table 56-1 (I/O and Pull U/D) */ R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1), R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index 8b1881c20598..c7d610d1f3ef 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -1260,7 +1260,7 @@ static const u16 pinmux_data[] = { */ #define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), /* Pins not associated with a GPIO port */ @@ -2104,7 +2104,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(vin1), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { GP_0_31_FN, FN_IP1_14_11, GP_0_30_FN, FN_IP1_10_8, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index d3e94e307d7f..f5c01e1e2615 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1410,7 +1410,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 293a51a7434e..a8ba2575a453 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -1731,7 +1731,7 @@ static const u16 pinmux_data[] = { #define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200) #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), /* Pins not associated with a GPIO port */ @@ -4237,7 +4237,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(vin3), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { GP_0_31_FN, FN_IP3_17_15, GP_0_30_FN, FN_IP3_14_12, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index ea02d37bab7c..d73a5f312777 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -1674,7 +1674,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), }; -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; @@ -3056,7 +3056,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(usb1), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { GP_0_31_FN, FN_IP1_22_20, GP_0_30_FN, FN_IP1_19_17, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index bcdd5c3cdcf0..e9c522bfb3df 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -844,7 +844,7 @@ static const u16 pinmux_data[] = { #define SH7372_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) #define SH7372_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD) -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* Table 57-1 (I/O and Pull U/D) */ SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1), SH7372_PIN_O(2), SH7372_PIN_I_PD(3), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index dc7c7fb33805..6f6ba100994d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -1179,7 +1179,7 @@ static const u16 pinmux_data[] = { */ #define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1) -static struct sh_pfc_pin pinmux_pins[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* Table 25-1 (I/O and Pull U/D) */ SH73A0_PIN_I_PD(0), SH73A0_PIN_I_PU(1), -- cgit From 646ae3ef7eaa8199aea38d042954a6f911477528 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 24 Dec 2013 00:28:28 +0400 Subject: pinctrl: sh-pfc: r8a7790: Fix vsync value in the vin3_sync_mux array This fixes a typo in the vin3_sync_mux array (s/VI2/VI3/). Signed-off-by: Valentine Barshak Signed-off-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index a8ba2575a453..c381ae63c508 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3564,7 +3564,7 @@ static const unsigned int vin3_sync_pins[] = { }; static const unsigned int vin3_sync_mux[] = { VI3_HSYNC_N_MARK, - VI2_VSYNC_N_MARK, + VI3_VSYNC_N_MARK, }; static const unsigned int vin3_field_pins[] = { RCAR_GP_PIN(1, 15), -- cgit From 5e5a298cdb7c7e2eeb3d5d74e1b0a638d14cdd14 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Fri, 20 Dec 2013 18:14:24 +0400 Subject: pinctrl: sh-pfc: r8a7791: Group USB PWEN and OVC pins together This groups USB PWEN and OVC pins together on R8A7791 SoC, the same way it's done on R8A7790, since both are needed for a USB device. Signed-off-by: Valentine Barshak Signed-off-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 40 +++++++++++------------------------- 1 file changed, 12 insertions(+), 28 deletions(-) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index d73a5f312777..70a74da35379 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -2649,33 +2649,21 @@ static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, }; /* - USB0 ------------------------------------------------------------------- */ -static const unsigned int usb0_pwen_pins[] = { - /* PWEN */ - RCAR_GP_PIN(7, 23), +static const unsigned int usb0_pins[] = { + RCAR_GP_PIN(7, 23), /* PWEN */ + RCAR_GP_PIN(7, 24), /* OVC */ }; -static const unsigned int usb0_pwen_mux[] = { +static const unsigned int usb0_mux[] = { USB0_PWEN_MARK, -}; -static const unsigned int usb0_ovc_pins[] = { - /* OVC */ - RCAR_GP_PIN(7, 24), -}; -static const unsigned int usb0_ovc_mux[] = { USB0_OVC_MARK, }; /* - USB1 ------------------------------------------------------------------- */ -static const unsigned int usb1_pwen_pins[] = { - /* PWEN */ - RCAR_GP_PIN(7, 25), +static const unsigned int usb1_pins[] = { + RCAR_GP_PIN(7, 25), /* PWEN */ + RCAR_GP_PIN(6, 30), /* OVC */ }; -static const unsigned int usb1_pwen_mux[] = { +static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, -}; -static const unsigned int usb1_ovc_pins[] = { - /* OVC */ - RCAR_GP_PIN(6, 30), -}; -static const unsigned int usb1_ovc_mux[] = { USB1_OVC_MARK, }; @@ -2810,10 +2798,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(usb0_pwen), - SH_PFC_PIN_GROUP(usb0_ovc), - SH_PFC_PIN_GROUP(usb1_pwen), - SH_PFC_PIN_GROUP(usb1_ovc), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), }; static const char * const du_groups[] = { @@ -3016,12 +3002,10 @@ static const char * const sdhi2_groups[] = { }; static const char * const usb0_groups[] = { - "usb0_pwen", - "usb0_ovc", + "usb0", }; static const char * const usb1_groups[] = { - "usb1_pwen", - "usb1_ovc", + "usb1", }; static const struct sh_pfc_function pinmux_functions[] = { -- cgit From 8e32c9671f84acd89d868659b86834e2f1b29f25 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Wed, 25 Dec 2013 23:36:01 +0400 Subject: pinctrl: sh-pfc: r8a7791: Add VIN pins This adds VIN[0-2] pinmux support to r8a7791 SoC. VIN1 B mirror is also added along with the primary configuration since it's the only one that provides access to all 24 data bits on VIN1. Signed-off-by: Valentine Barshak Signed-off-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 360 +++++++++++++++++++++++++++++++++++ 1 file changed, 360 insertions(+) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 70a74da35379..c3a336a9157d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -2667,6 +2667,290 @@ static const unsigned int usb1_mux[] = { USB1_OVC_MARK, }; +union vin_data { + unsigned int data24[24]; + unsigned int data20[20]; + unsigned int data16[16]; + unsigned int data12[12]; + unsigned int data10[10]; + unsigned int data8[8]; +}; + +#define VIN_DATA_PIN_GROUP(n, s) \ + { \ + .name = #n#s, \ + .pins = n##_pins.data##s, \ + .mux = n##_mux.data##s, \ + .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ + } + +/* - VIN0 ------------------------------------------------------------------- */ +static const union vin_data vin0_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), + /* G */ + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), + /* R */ + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), + RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), + }, +}; +static const union vin_data vin0_data_mux = { + .data24 = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, + }, +}; +static const unsigned int vin0_data18_pins[] = { + /* B */ + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), + /* G */ + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), + /* R */ + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), + RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), +}; +static const unsigned int vin0_data18_mux[] = { + /* B */ + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, +}; +static const unsigned int vin0_sync_pins[] = { + RCAR_GP_PIN(4, 3), /* HSYNC */ + RCAR_GP_PIN(4, 4), /* VSYNC */ +}; +static const unsigned int vin0_sync_mux[] = { + VI0_HSYNC_N_MARK, + VI0_VSYNC_N_MARK, +}; +static const unsigned int vin0_field_pins[] = { + RCAR_GP_PIN(4, 2), +}; +static const unsigned int vin0_field_mux[] = { + VI0_FIELD_MARK, +}; +static const unsigned int vin0_clkenb_pins[] = { + RCAR_GP_PIN(4, 1), +}; +static const unsigned int vin0_clkenb_mux[] = { + VI0_CLKENB_MARK, +}; +static const unsigned int vin0_clk_pins[] = { + RCAR_GP_PIN(4, 0), +}; +static const unsigned int vin0_clk_mux[] = { + VI0_CLK_MARK, +}; +/* - VIN1 ----------------------------------------------------------------- */ +static const unsigned int vin1_data8_pins[] = { + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), +}; +static const unsigned int vin1_data8_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, +}; +static const unsigned int vin1_sync_pins[] = { + RCAR_GP_PIN(5, 0), /* HSYNC */ + RCAR_GP_PIN(5, 1), /* VSYNC */ +}; +static const unsigned int vin1_sync_mux[] = { + VI1_HSYNC_N_MARK, + VI1_VSYNC_N_MARK, +}; +static const unsigned int vin1_field_pins[] = { + RCAR_GP_PIN(5, 3), +}; +static const unsigned int vin1_field_mux[] = { + VI1_FIELD_MARK, +}; +static const unsigned int vin1_clkenb_pins[] = { + RCAR_GP_PIN(5, 2), +}; +static const unsigned int vin1_clkenb_mux[] = { + VI1_CLKENB_MARK, +}; +static const unsigned int vin1_clk_pins[] = { + RCAR_GP_PIN(5, 4), +}; +static const unsigned int vin1_clk_mux[] = { + VI1_CLK_MARK, +}; +static const union vin_data vin1_b_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + /* G */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), + RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), + /* R */ + RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), + }, +}; +static const union vin_data vin1_b_data_mux = { + .data24 = { + /* B */ + VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, + VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, + VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, + VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, + /* G */ + VI1_G0_B_MARK, VI1_G1_B_MARK, + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R0_B_MARK, VI1_R1_B_MARK, + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, + }, +}; +static const unsigned int vin1_b_data18_pins[] = { + /* B */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + /* G */ + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), + RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), + /* R */ + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), +}; +static const unsigned int vin1_b_data18_mux[] = { + /* B */ + VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, + VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, + VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, + VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, + /* G */ + VI1_G0_B_MARK, VI1_G1_B_MARK, + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R0_B_MARK, VI1_R1_B_MARK, + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, +}; +static const unsigned int vin1_b_sync_pins[] = { + RCAR_GP_PIN(3, 17), /* HSYNC */ + RCAR_GP_PIN(3, 18), /* VSYNC */ +}; +static const unsigned int vin1_b_sync_mux[] = { + VI1_HSYNC_N_B_MARK, + VI1_VSYNC_N_B_MARK, +}; +static const unsigned int vin1_b_field_pins[] = { + RCAR_GP_PIN(3, 20), +}; +static const unsigned int vin1_b_field_mux[] = { + VI1_FIELD_B_MARK, +}; +static const unsigned int vin1_b_clkenb_pins[] = { + RCAR_GP_PIN(3, 19), +}; +static const unsigned int vin1_b_clkenb_mux[] = { + VI1_CLKENB_B_MARK, +}; +static const unsigned int vin1_b_clk_pins[] = { + RCAR_GP_PIN(3, 16), +}; +static const unsigned int vin1_b_clk_mux[] = { + VI1_CLK_B_MARK, +}; +/* - VIN2 ----------------------------------------------------------------- */ +static const unsigned int vin2_data8_pins[] = { + RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), + RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25), + RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27), +}; +static const unsigned int vin2_data8_mux[] = { + VI2_DATA0_MARK, VI2_DATA1_MARK, + VI2_DATA2_MARK, VI2_DATA3_MARK, + VI2_DATA4_MARK, VI2_DATA5_MARK, + VI2_DATA6_MARK, VI2_DATA7_MARK, +}; +static const unsigned int vin2_sync_pins[] = { + RCAR_GP_PIN(4, 15), /* HSYNC */ + RCAR_GP_PIN(4, 16), /* VSYNC */ +}; +static const unsigned int vin2_sync_mux[] = { + VI2_HSYNC_N_MARK, + VI2_VSYNC_N_MARK, +}; +static const unsigned int vin2_field_pins[] = { + RCAR_GP_PIN(4, 18), +}; +static const unsigned int vin2_field_mux[] = { + VI2_FIELD_MARK, +}; +static const unsigned int vin2_clkenb_pins[] = { + RCAR_GP_PIN(4, 17), +}; +static const unsigned int vin2_clkenb_mux[] = { + VI2_CLKENB_MARK, +}; +static const unsigned int vin2_clk_pins[] = { + RCAR_GP_PIN(4, 19), +}; +static const unsigned int vin2_clk_mux[] = { + VI2_CLK_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), @@ -2800,6 +3084,38 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_wp), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + SH_PFC_PIN_GROUP(vin1_data8), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), + VIN_DATA_PIN_GROUP(vin1_b_data, 24), + VIN_DATA_PIN_GROUP(vin1_b_data, 20), + SH_PFC_PIN_GROUP(vin1_b_data18), + VIN_DATA_PIN_GROUP(vin1_b_data, 16), + VIN_DATA_PIN_GROUP(vin1_b_data, 12), + VIN_DATA_PIN_GROUP(vin1_b_data, 10), + VIN_DATA_PIN_GROUP(vin1_b_data, 8), + SH_PFC_PIN_GROUP(vin1_b_sync), + SH_PFC_PIN_GROUP(vin1_b_field), + SH_PFC_PIN_GROUP(vin1_b_clkenb), + SH_PFC_PIN_GROUP(vin1_b_clk), + SH_PFC_PIN_GROUP(vin2_data8), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin2_field), + SH_PFC_PIN_GROUP(vin2_clkenb), + SH_PFC_PIN_GROUP(vin2_clk), }; static const char * const du_groups[] = { @@ -3008,6 +3324,47 @@ static const char * const usb1_groups[] = { "usb1", }; +static const char * const vin0_groups[] = { + "vin0_data24", + "vin0_data20", + "vin0_data18", + "vin0_data16", + "vin0_data12", + "vin0_data10", + "vin0_data8", + "vin0_sync", + "vin0_field", + "vin0_clkenb", + "vin0_clk", +}; + +static const char * const vin1_groups[] = { + "vin1_data8", + "vin1_sync", + "vin1_field", + "vin1_clkenb", + "vin1_clk", + "vin1_b_data24", + "vin1_b_data20", + "vin1_b_data18", + "vin1_b_data16", + "vin1_b_data12", + "vin1_b_data10", + "vin1_b_data8", + "vin1_b_sync", + "vin1_b_field", + "vin1_b_clkenb", + "vin1_b_clk", +}; + +static const char * const vin2_groups[] = { + "vin2_data8", + "vin2_sync", + "vin2_field", + "vin2_clkenb", + "vin2_clk", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(du0), @@ -3038,6 +3395,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { -- cgit From a5ffaf644550d8120399abd62c543afe61ca628f Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Fri, 27 Dec 2013 15:27:37 +0400 Subject: pinctrl: sh-pfc: r8a7791: Add I2C pins This adds I2C[0-4] pinmux support to R8A7791 SoC. Signed-off-by: Valentine Barshak Signed-off-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 196 +++++++++++++++++++++++++++++++++++ 1 file changed, 196 insertions(+) (limited to 'drivers/pinctrl/sh-pfc') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index c3a336a9157d..77d103fe39d9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -1805,6 +1805,144 @@ static const unsigned int eth_rmii_mux[] = { ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, }; +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), +}; +static const unsigned int i2c0_mux[] = { + SCL0_MARK, SDA0_MARK, +}; +static const unsigned int i2c0_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), +}; +static const unsigned int i2c0_b_mux[] = { + SCL0_B_MARK, SDA0_B_MARK, +}; +static const unsigned int i2c0_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1), +}; +static const unsigned int i2c0_c_mux[] = { + SCL0_C_MARK, SDA0_C_MARK, +}; +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), +}; +static const unsigned int i2c1_mux[] = { + SCL1_MARK, SDA1_MARK, +}; +static const unsigned int i2c1_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), +}; +static const unsigned int i2c1_b_mux[] = { + SCL1_B_MARK, SDA1_B_MARK, +}; +static const unsigned int i2c1_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), +}; +static const unsigned int i2c1_c_mux[] = { + SCL1_C_MARK, SDA1_C_MARK, +}; +static const unsigned int i2c1_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), +}; +static const unsigned int i2c1_d_mux[] = { + SCL1_D_MARK, SDA1_D_MARK, +}; +static const unsigned int i2c1_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16), +}; +static const unsigned int i2c1_e_mux[] = { + SCL1_E_MARK, SDA1_E_MARK, +}; +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), +}; +static const unsigned int i2c2_mux[] = { + SCL2_MARK, SDA2_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29), +}; +static const unsigned int i2c2_b_mux[] = { + SCL2_B_MARK, SDA2_B_MARK, +}; +static const unsigned int i2c2_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), +}; +static const unsigned int i2c2_c_mux[] = { + SCL2_C_MARK, SDA2_C_MARK, +}; +static const unsigned int i2c2_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), +}; +static const unsigned int i2c2_d_mux[] = { + SCL2_D_MARK, SDA2_D_MARK, +}; +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; +static const unsigned int i2c3_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), +}; +static const unsigned int i2c3_b_mux[] = { + SCL3_B_MARK, SDA3_B_MARK, +}; +static const unsigned int i2c3_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), +}; +static const unsigned int i2c3_c_mux[] = { + SCL3_C_MARK, SDA3_C_MARK, +}; +static const unsigned int i2c3_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), +}; +static const unsigned int i2c3_d_mux[] = { + SCL3_D_MARK, SDA3_D_MARK, +}; +/* - I2C4 ------------------------------------------------------------------- */ +static const unsigned int i2c4_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), +}; +static const unsigned int i2c4_mux[] = { + SCL4_MARK, SDA4_MARK, +}; +static const unsigned int i2c4_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), +}; +static const unsigned int i2c4_b_mux[] = { + SCL4_B_MARK, SDA4_B_MARK, +}; +static const unsigned int i2c4_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14), +}; +static const unsigned int i2c4_c_mux[] = { + SCL4_C_MARK, SDA4_C_MARK, +}; /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ */ @@ -2966,6 +3104,25 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(eth_magic), SH_PFC_PIN_GROUP(eth_mdio), SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c0_b), + SH_PFC_PIN_GROUP(i2c0_c), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c1_d), + SH_PFC_PIN_GROUP(i2c1_e), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(i2c3_c), + SH_PFC_PIN_GROUP(i2c3_d), + SH_PFC_PIN_GROUP(i2c4), + SH_PFC_PIN_GROUP(i2c4_b), + SH_PFC_PIN_GROUP(i2c4_c), SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), @@ -3144,6 +3301,40 @@ static const char * const eth_groups[] = { "eth_rmii", }; +static const char * const i2c0_groups[] = { + "i2c0", + "i2c0_b", + "i2c0_c", +}; + +static const char * const i2c1_groups[] = { + "i2c1", + "i2c1_b", + "i2c1_c", + "i2c1_d", + "i2c1_e", +}; + +static const char * const i2c2_groups[] = { + "i2c2", + "i2c2_b", + "i2c2_c", + "i2c2_d", +}; + +static const char * const i2c3_groups[] = { + "i2c3", + "i2c3_b", + "i2c3_c", + "i2c3_d", +}; + +static const char * const i2c4_groups[] = { + "i2c4", + "i2c4_b", + "i2c4_c", +}; + static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", @@ -3370,6 +3561,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), -- cgit